1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Marvell Xenon SDHCI Controller
8
9description: |
10  This file documents differences between the core MMC properties described by
11  mmc-controller.yaml and the properties used by the Xenon implementation.
12
13  Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
14  Each SDHC is independent and owns independent resources, such as register
15  sets, clock and PHY.
16
17  Each SDHC should have an independent device tree node.
18
19maintainers:
20  - Ulf Hansson <ulf.hansson@linaro.org>
21
22properties:
23  compatible:
24    oneOf:
25      - enum:
26          - marvell,armada-cp110-sdhci
27          - marvell,armada-ap806-sdhci
28
29      - items:
30          - enum:
31              - marvell,armada-ap807-sdhci
32              - marvell,ac5-sdhci
33          - const: marvell,armada-ap806-sdhci
34
35      - items:
36          - const: marvell,armada-3700-sdhci
37          - const: marvell,sdhci-xenon
38
39  reg:
40    minItems: 1
41    maxItems: 2
42    description: |
43      For "marvell,armada-3700-sdhci", two register areas.  The first one
44      for Xenon IP register. The second one for the Armada 3700 SoC PHY PAD
45      Voltage Control register.  Please follow the examples with compatible
46      "marvell,armada-3700-sdhci" in below.
47      Please also check property marvell,pad-type in below.
48
49      For other compatible strings, one register area for Xenon IP.
50
51  clocks:
52    minItems: 1
53    maxItems: 2
54
55  clock-names:
56    minItems: 1
57    items:
58      - const: core
59      - const: axi
60
61  interrupts:
62    maxItems: 1
63
64  marvell,xenon-sdhc-id:
65    $ref: /schemas/types.yaml#/definitions/uint32
66    minimum: 0
67    maximum: 7
68    description: |
69      Indicate the corresponding bit index of current SDHC in SDHC System
70      Operation Control Register Bit[7:0].  Set/clear the corresponding bit to
71      enable/disable current SDHC.
72
73  marvell,xenon-phy-type:
74    $ref: /schemas/types.yaml#/definitions/string
75    enum:
76      - emmc 5.1 phy
77      - emmc 5.0 phy
78    description: |
79      Xenon support multiple types of PHYs. To select eMMC 5.1 PHY, set:
80      marvell,xenon-phy-type = "emmc 5.1 phy" eMMC 5.1 PHY is the default
81      choice if this property is not provided.  To select eMMC 5.0 PHY, set:
82      marvell,xenon-phy-type = "emmc 5.0 phy"
83
84      All those types of PHYs can support eMMC, SD and SDIO. Please note that
85      this property only presents the type of PHY.  It doesn't stand for the
86      entire SDHC type or property.  For example, "emmc 5.1 phy" doesn't mean
87      that this Xenon SDHC only supports eMMC 5.1.
88
89  marvell,xenon-phy-znr:
90    $ref: /schemas/types.yaml#/definitions/uint32
91    minimum: 0
92    maximum: 0x1f
93    default: 0xf
94    description: |
95      Set PHY ZNR value.
96      Only available for eMMC PHY.
97
98  marvell,xenon-phy-zpr:
99    $ref: /schemas/types.yaml#/definitions/uint32
100    minimum: 0
101    maximum: 0x1f
102    default: 0xf
103    description: |
104      Set PHY ZPR value.
105      Only available for eMMC PHY.
106
107  marvell,xenon-phy-nr-success-tun:
108    $ref: /schemas/types.yaml#/definitions/uint32
109    minimum: 1
110    maximum: 7
111    default: 0x4
112    description: |
113      Set the number of required consecutive successful sampling points
114      used to identify a valid sampling window, in tuning process.
115
116  marvell,xenon-phy-tun-step-divider:
117    $ref: /schemas/types.yaml#/definitions/uint32
118    default: 64
119    description: |
120      Set the divider for calculating TUN_STEP.
121
122  marvell,xenon-phy-slow-mode:
123    type: boolean
124    description: |
125      If this property is selected, transfers will bypass PHY.
126      Only available when bus frequency lower than 55MHz in SDR mode.
127      Disabled by default. Please only try this property if timing issues
128      always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25,
129      SD Default Speed and HS mode and eMMC legacy speed mode.
130
131  marvell,xenon-tun-count:
132    $ref: /schemas/types.yaml#/definitions/uint32
133    default: 0x9
134    description: |
135      Xenon SDHC SoC usually doesn't provide re-tuning counter in
136      Capabilities Register 3 Bit[11:8].
137      This property provides the re-tuning counter.
138
139allOf:
140  - $ref: mmc-controller.yaml#
141  - if:
142      properties:
143        compatible:
144          contains:
145            const: marvell,armada-3700-sdhci
146
147    then:
148      properties:
149        reg:
150          items:
151            - description: Xenon IP registers
152            - description: Armada 3700 SoC PHY PAD Voltage Control register
153
154        marvell,pad-type:
155          $ref: /schemas/types.yaml#/definitions/string
156          enum:
157            - sd
158            - fixed-1-8v
159          description: |
160            Type of Armada 3700 SoC PHY PAD Voltage Controller register.
161            If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning
162            and is switched to 1.8V when later in higher speed mode.
163            If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for
164            eMMC.
165            Please follow the examples with compatible
166            "marvell,armada-3700-sdhci" in below.
167
168      required:
169        - marvell,pad-type
170
171  - if:
172      properties:
173        compatible:
174          contains:
175            enum:
176              - marvell,armada-cp110-sdhci
177              - marvell,armada-ap807-sdhci
178              - marvell,armada-ap806-sdhci
179
180    then:
181      properties:
182        clocks:
183          minItems: 2
184
185        clock-names:
186          items:
187            - const: core
188            - const: axi
189
190
191required:
192  - compatible
193  - reg
194  - clocks
195  - clock-names
196
197unevaluatedProperties: false
198
199examples:
200  - |
201    // For eMMC
202    #include <dt-bindings/interrupt-controller/arm-gic.h>
203    #include <dt-bindings/interrupt-controller/irq.h>
204
205    mmc@aa0000 {
206      compatible = "marvell,armada-ap807-sdhci", "marvell,armada-ap806-sdhci";
207      reg = <0xaa0000 0x1000>;
208      interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
209      clocks = <&emmc_clk 0>, <&axi_clk 0>;
210      clock-names = "core", "axi";
211      bus-width = <4>;
212      marvell,xenon-phy-slow-mode;
213      marvell,xenon-tun-count = <11>;
214      non-removable;
215      no-sd;
216      no-sdio;
217
218      /* Vmmc and Vqmmc are both fixed */
219    };
220
221  - |
222    // For SD/SDIO
223    #include <dt-bindings/interrupt-controller/arm-gic.h>
224    #include <dt-bindings/interrupt-controller/irq.h>
225
226    mmc@ab0000 {
227      compatible = "marvell,armada-cp110-sdhci";
228      reg = <0xab0000 0x1000>;
229      interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
230      vqmmc-supply = <&sd_vqmmc_regulator>;
231      vmmc-supply = <&sd_vmmc_regulator>;
232      clocks = <&sdclk 0>, <&axi_clk 0>;
233      clock-names = "core", "axi";
234      bus-width = <4>;
235      marvell,xenon-tun-count = <9>;
236    };
237
238  - |
239    // For eMMC with compatible "marvell,armada-3700-sdhci":
240    #include <dt-bindings/interrupt-controller/arm-gic.h>
241    #include <dt-bindings/interrupt-controller/irq.h>
242
243    mmc@aa0000 {
244      compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
245      reg = <0xaa0000 0x1000>,
246            <0x17808 0x4>;
247      interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
248      clocks = <&emmcclk 0>;
249      clock-names = "core";
250      bus-width = <8>;
251      mmc-ddr-1_8v;
252      mmc-hs400-1_8v;
253      non-removable;
254      no-sd;
255      no-sdio;
256
257      /* Vmmc and Vqmmc are both fixed */
258
259      marvell,pad-type = "fixed-1-8v";
260    };
261
262  - |
263    // For SD/SDIO with compatible "marvell,armada-3700-sdhci":
264    #include <dt-bindings/interrupt-controller/arm-gic.h>
265    #include <dt-bindings/interrupt-controller/irq.h>
266
267    mmc@ab0000 {
268      compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
269      reg = <0xab0000 0x1000>,
270            <0x17808 0x4>;
271      interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
272      vqmmc-supply = <&sd_regulator>;
273      /* Vmmc is fixed */
274      clocks = <&sdclk 0>;
275      clock-names = "core";
276      bus-width = <4>;
277
278      marvell,pad-type = "sd";
279    };
280