1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM System MMU Architecture Implementation
8
9maintainers:
10  - Will Deacon <will@kernel.org>
11  - Robin Murphy <Robin.Murphy@arm.com>
12
13description: |+
14  ARM SoCs may contain an implementation of the ARM System Memory
15  Management Unit Architecture, which can be used to provide 1 or 2 stages
16  of address translation to bus masters external to the CPU.
17
18  The SMMU may also raise interrupts in response to various fault
19  conditions.
20
21properties:
22  $nodename:
23    pattern: "^iommu@[0-9a-f]*"
24  compatible:
25    oneOf:
26      - description: Qcom SoCs implementing "arm,smmu-v2"
27        items:
28          - enum:
29              - qcom,msm8996-smmu-v2
30              - qcom,msm8998-smmu-v2
31              - qcom,sdm630-smmu-v2
32              - qcom,sm6375-smmu-v2
33          - const: qcom,smmu-v2
34
35      - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
36        items:
37          - enum:
38              - qcom,qcm2290-smmu-500
39              - qcom,qdu1000-smmu-500
40              - qcom,sa8775p-smmu-500
41              - qcom,sc7180-smmu-500
42              - qcom,sc7280-smmu-500
43              - qcom,sc8180x-smmu-500
44              - qcom,sc8280xp-smmu-500
45              - qcom,sdm670-smmu-500
46              - qcom,sdm845-smmu-500
47              - qcom,sdx55-smmu-500
48              - qcom,sdx65-smmu-500
49              - qcom,sdx75-smmu-500
50              - qcom,sm6115-smmu-500
51              - qcom,sm6125-smmu-500
52              - qcom,sm6350-smmu-500
53              - qcom,sm6375-smmu-500
54              - qcom,sm8150-smmu-500
55              - qcom,sm8250-smmu-500
56              - qcom,sm8350-smmu-500
57              - qcom,sm8450-smmu-500
58              - qcom,sm8550-smmu-500
59              - qcom,sm8650-smmu-500
60              - qcom,x1e80100-smmu-500
61          - const: qcom,smmu-500
62          - const: arm,mmu-500
63
64      - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
65        deprecated: true
66        items:
67          # Do not add additional SoC to this list. Instead use two previous lists.
68          - enum:
69              - qcom,qcm2290-smmu-500
70              - qcom,sc7180-smmu-500
71              - qcom,sc7280-smmu-500
72              - qcom,sc8180x-smmu-500
73              - qcom,sc8280xp-smmu-500
74              - qcom,sdm845-smmu-500
75              - qcom,sm6115-smmu-500
76              - qcom,sm6350-smmu-500
77              - qcom,sm6375-smmu-500
78              - qcom,sm8150-smmu-500
79              - qcom,sm8250-smmu-500
80              - qcom,sm8350-smmu-500
81              - qcom,sm8450-smmu-500
82          - const: arm,mmu-500
83      - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
84        items:
85          - enum:
86              - qcom,qcm2290-smmu-500
87              - qcom,sa8775p-smmu-500
88              - qcom,sc7280-smmu-500
89              - qcom,sc8280xp-smmu-500
90              - qcom,sm6115-smmu-500
91              - qcom,sm6125-smmu-500
92              - qcom,sm8150-smmu-500
93              - qcom,sm8250-smmu-500
94              - qcom,sm8350-smmu-500
95              - qcom,sm8450-smmu-500
96              - qcom,sm8550-smmu-500
97              - qcom,sm8650-smmu-500
98          - const: qcom,adreno-smmu
99          - const: qcom,smmu-500
100          - const: arm,mmu-500
101      - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)
102        deprecated: true
103        items:
104          # Do not add additional SoC to this list. Instead use previous list.
105          - enum:
106              - qcom,sc7280-smmu-500
107              - qcom,sm8150-smmu-500
108              - qcom,sm8250-smmu-500
109          - const: qcom,adreno-smmu
110          - const: arm,mmu-500
111      - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
112        items:
113          - enum:
114              - qcom,msm8996-smmu-v2
115              - qcom,sc7180-smmu-v2
116              - qcom,sdm630-smmu-v2
117              - qcom,sdm845-smmu-v2
118              - qcom,sm6350-smmu-v2
119              - qcom,sm7150-smmu-v2
120          - const: qcom,adreno-smmu
121          - const: qcom,smmu-v2
122      - description: Qcom Adreno GPUs on Google Cheza platform
123        items:
124          - const: qcom,sdm845-smmu-v2
125          - const: qcom,smmu-v2
126      - description: Marvell SoCs implementing "arm,mmu-500"
127        items:
128          - const: marvell,ap806-smmu-500
129          - const: arm,mmu-500
130      - description: NVIDIA SoCs that require memory controller interaction
131          and may program multiple ARM MMU-500s identically with the memory
132          controller interleaving translations between multiple instances
133          for improved performance.
134        items:
135          - enum:
136              - nvidia,tegra186-smmu
137              - nvidia,tegra194-smmu
138              - nvidia,tegra234-smmu
139          - const: nvidia,smmu-500
140      - items:
141          - const: arm,mmu-500
142          - const: arm,smmu-v2
143      - items:
144          - enum:
145              - arm,mmu-400
146              - arm,mmu-401
147          - const: arm,smmu-v1
148      - enum:
149          - arm,smmu-v1
150          - arm,smmu-v2
151          - arm,mmu-400
152          - arm,mmu-401
153          - arm,mmu-500
154          - cavium,smmu-v2
155
156  reg:
157    minItems: 1
158    maxItems: 2
159
160  '#global-interrupts':
161    description: The number of global interrupts exposed by the device.
162    $ref: /schemas/types.yaml#/definitions/uint32
163    minimum: 0
164    maximum: 260   # 2 secure, 2 non-secure, and up to 256 perf counters
165
166  '#iommu-cells':
167    enum: [ 1, 2 ]
168    description: |
169      See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
170      value of 1, each IOMMU specifier represents a distinct stream ID emitted
171      by that device into the relevant SMMU.
172
173      SMMUs with stream matching support and complex masters may use a value of
174      2, where the second cell of the IOMMU specifier represents an SMR mask to
175      combine with the ID in the first cell.  Care must be taken to ensure the
176      set of matched IDs does not result in conflicts.
177
178  interrupts:
179    minItems: 1
180    maxItems: 388   # 260 plus 128 contexts
181    description: |
182      Interrupt list, with the first #global-interrupts entries corresponding to
183      the global interrupts and any following entries corresponding to context
184      interrupts, specified in order of their indexing by the SMMU.
185
186      For SMMUv2 implementations, there must be exactly one interrupt per
187      context bank. In the case of a single, combined interrupt, it must be
188      listed multiple times.
189
190  dma-coherent:
191    description: |
192      Present if page table walks made by the SMMU are cache coherent with the
193      CPU.
194
195      NOTE: this only applies to the SMMU itself, not masters connected
196      upstream of the SMMU.
197
198  calxeda,smmu-secure-config-access:
199    type: boolean
200    description:
201      Enable proper handling of buggy implementations that always use secure
202      access to SMMU configuration registers. In this case non-secure aliases of
203      secure registers have to be used during SMMU configuration.
204
205  stream-match-mask:
206    $ref: /schemas/types.yaml#/definitions/uint32
207    description: |
208      For SMMUs supporting stream matching and using #iommu-cells = <1>,
209      specifies a mask of bits to ignore when matching stream IDs (e.g. this may
210      be programmed into the SMRn.MASK field of every stream match register
211      used). For cases where it is desirable to ignore some portion of every
212      Stream ID (e.g. for certain MMU-500 configurations given globally unique
213      input IDs). This property is not valid for SMMUs using stream indexing, or
214      using stream matching with #iommu-cells = <2>, and may be ignored if
215      present in such cases.
216
217  clock-names:
218    minItems: 1
219    maxItems: 7
220
221  clocks:
222    minItems: 1
223    maxItems: 7
224
225  power-domains:
226    minItems: 1
227    maxItems: 3
228
229  nvidia,memory-controller:
230    description: |
231      A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
232      The memory controller needs to be programmed with a mapping of memory
233      client IDs to ARM SMMU stream IDs.
234
235      If this property is absent, the mapping programmed by early firmware
236      will be used and it is not guaranteed that IOMMU translations will be
237      enabled for any given device.
238    $ref: /schemas/types.yaml#/definitions/phandle
239
240required:
241  - compatible
242  - reg
243  - '#global-interrupts'
244  - '#iommu-cells'
245  - interrupts
246
247additionalProperties: false
248
249allOf:
250  - if:
251      properties:
252        compatible:
253          contains:
254            enum:
255              - nvidia,tegra186-smmu
256              - nvidia,tegra194-smmu
257              - nvidia,tegra234-smmu
258    then:
259      properties:
260        reg:
261          minItems: 1
262          maxItems: 2
263
264      # The reference to the memory controller is required to ensure that the
265      # memory client to stream ID mapping can be done synchronously with the
266      # IOMMU attachment.
267      required:
268        - nvidia,memory-controller
269    else:
270      properties:
271        reg:
272          maxItems: 1
273
274  - if:
275      properties:
276        compatible:
277          contains:
278            enum:
279              - qcom,msm8998-smmu-v2
280              - qcom,sdm630-smmu-v2
281    then:
282      anyOf:
283        - properties:
284            clock-names:
285              items:
286                - const: bus
287            clocks:
288              items:
289                - description: bus clock required for downstream bus access and for
290                    the smmu ptw
291        - properties:
292            clock-names:
293              items:
294                - const: iface
295                - const: mem
296                - const: mem_iface
297            clocks:
298              items:
299                - description: interface clock required to access smmu's registers
300                    through the TCU's programming interface.
301                - description: bus clock required for memory access
302                - description: bus clock required for GPU memory access
303        - properties:
304            clock-names:
305              items:
306                - const: iface-mm
307                - const: iface-smmu
308                - const: bus-smmu
309            clocks:
310              items:
311                - description: interface clock required to access mnoc's registers
312                    through the TCU's programming interface.
313                - description: interface clock required to access smmu's registers
314                    through the TCU's programming interface.
315                - description: bus clock required for the smmu ptw
316
317  - if:
318      properties:
319        compatible:
320          contains:
321            enum:
322              - qcom,sm6375-smmu-v2
323    then:
324      anyOf:
325        - properties:
326            clock-names:
327              items:
328                - const: bus
329            clocks:
330              items:
331                - description: bus clock required for downstream bus access and for
332                    the smmu ptw
333        - properties:
334            clock-names:
335              items:
336                - const: iface
337                - const: mem
338                - const: mem_iface
339            clocks:
340              items:
341                - description: interface clock required to access smmu's registers
342                    through the TCU's programming interface.
343                - description: bus clock required for memory access
344                - description: bus clock required for GPU memory access
345        - properties:
346            clock-names:
347              items:
348                - const: iface-mm
349                - const: iface-smmu
350                - const: bus-mm
351                - const: bus-smmu
352            clocks:
353              items:
354                - description: interface clock required to access mnoc's registers
355                    through the TCU's programming interface.
356                - description: interface clock required to access smmu's registers
357                    through the TCU's programming interface.
358                - description: bus clock required for downstream bus access
359                - description: bus clock required for the smmu ptw
360
361  - if:
362      properties:
363        compatible:
364          contains:
365            enum:
366              - qcom,msm8996-smmu-v2
367              - qcom,sc7180-smmu-v2
368              - qcom,sdm845-smmu-v2
369    then:
370      properties:
371        clock-names:
372          items:
373            - const: bus
374            - const: iface
375
376        clocks:
377          items:
378            - description: bus clock required for downstream bus access and for
379                the smmu ptw
380            - description: interface clock required to access smmu's registers
381                through the TCU's programming interface.
382
383  - if:
384      properties:
385        compatible:
386          contains:
387            enum:
388              - qcom,sa8775p-smmu-500
389              - qcom,sc7280-smmu-500
390              - qcom,sc8280xp-smmu-500
391    then:
392      properties:
393        clock-names:
394          items:
395            - const: gcc_gpu_memnoc_gfx_clk
396            - const: gcc_gpu_snoc_dvm_gfx_clk
397            - const: gpu_cc_ahb_clk
398            - const: gpu_cc_hlos1_vote_gpu_smmu_clk
399            - const: gpu_cc_cx_gmu_clk
400            - const: gpu_cc_hub_cx_int_clk
401            - const: gpu_cc_hub_aon_clk
402
403        clocks:
404          items:
405            - description: GPU memnoc_gfx clock
406            - description: GPU snoc_dvm_gfx clock
407            - description: GPU ahb clock
408            - description: GPU hlos1_vote_GPU smmu clock
409            - description: GPU cx_gmu clock
410            - description: GPU hub_cx_int clock
411            - description: GPU hub_aon clock
412
413  - if:
414      properties:
415        compatible:
416          contains:
417            enum:
418              - qcom,sm6350-smmu-v2
419              - qcom,sm7150-smmu-v2
420              - qcom,sm8150-smmu-500
421              - qcom,sm8250-smmu-500
422    then:
423      properties:
424        clock-names:
425          items:
426            - const: ahb
427            - const: bus
428            - const: iface
429
430        clocks:
431          items:
432            - description: bus clock required for AHB bus access
433            - description: bus clock required for downstream bus access and for
434                the smmu ptw
435            - description: interface clock required to access smmu's registers
436                through the TCU's programming interface.
437
438  - if:
439      properties:
440        compatible:
441          items:
442            - enum:
443                - qcom,sm8350-smmu-500
444            - const: qcom,adreno-smmu
445            - const: qcom,smmu-500
446            - const: arm,mmu-500
447    then:
448      properties:
449        clock-names:
450          items:
451            - const: bus
452            - const: iface
453            - const: ahb
454            - const: hlos1_vote_gpu_smmu
455            - const: cx_gmu
456            - const: hub_cx_int
457            - const: hub_aon
458        clocks:
459          minItems: 7
460          maxItems: 7
461
462  - if:
463      properties:
464        compatible:
465          items:
466            - enum:
467                - qcom,qcm2290-smmu-500
468                - qcom,sm6115-smmu-500
469                - qcom,sm6125-smmu-500
470            - const: qcom,adreno-smmu
471            - const: qcom,smmu-500
472            - const: arm,mmu-500
473    then:
474      properties:
475        clock-names:
476          items:
477            - const: mem
478            - const: hlos
479            - const: iface
480
481        clocks:
482          items:
483            - description: GPU memory bus clock
484            - description: Voter clock required for HLOS SMMU access
485            - description: Interface clock required for register access
486
487  - if:
488      properties:
489        compatible:
490          items:
491            - const: qcom,sm8450-smmu-500
492            - const: qcom,adreno-smmu
493            - const: qcom,smmu-500
494            - const: arm,mmu-500
495
496    then:
497      properties:
498        clock-names:
499          items:
500            - const: gmu
501            - const: hub
502            - const: hlos
503            - const: bus
504            - const: iface
505            - const: ahb
506
507        clocks:
508          items:
509            - description: GMU clock
510            - description: GPU HUB clock
511            - description: HLOS vote clock
512            - description: GPU memory bus clock
513            - description: GPU SNoC bus clock
514            - description: GPU AHB clock
515
516  - if:
517      properties:
518        compatible:
519          items:
520            - enum:
521                - qcom,sm8550-smmu-500
522                - qcom,sm8650-smmu-500
523            - const: qcom,adreno-smmu
524            - const: qcom,smmu-500
525            - const: arm,mmu-500
526    then:
527      properties:
528        clock-names:
529          items:
530            - const: hlos
531            - const: bus
532            - const: iface
533            - const: ahb
534
535        clocks:
536          items:
537            - description: HLOS vote clock
538            - description: GPU memory bus clock
539            - description: GPU SNoC bus clock
540            - description: GPU AHB clock
541
542  # Disallow clocks for all other platforms with specific compatibles
543  - if:
544      properties:
545        compatible:
546          contains:
547            enum:
548              - cavium,smmu-v2
549              - marvell,ap806-smmu-500
550              - nvidia,smmu-500
551              - qcom,qdu1000-smmu-500
552              - qcom,sc7180-smmu-500
553              - qcom,sc8180x-smmu-500
554              - qcom,sdm670-smmu-500
555              - qcom,sdm845-smmu-500
556              - qcom,sdx55-smmu-500
557              - qcom,sdx65-smmu-500
558              - qcom,sm6350-smmu-500
559              - qcom,sm6375-smmu-500
560              - qcom,x1e80100-smmu-500
561    then:
562      properties:
563        clock-names: false
564        clocks: false
565
566  - if:
567      properties:
568        compatible:
569          contains:
570            const: qcom,sm6375-smmu-500
571    then:
572      properties:
573        power-domains:
574          items:
575            - description: SNoC MMU TBU RT GDSC
576            - description: SNoC MMU TBU NRT GDSC
577            - description: SNoC TURING MMU TBU0 GDSC
578
579      required:
580        - power-domains
581    else:
582      properties:
583        power-domains:
584          maxItems: 1
585
586examples:
587  - |+
588    /* SMMU with stream matching or stream indexing */
589    smmu1: iommu@ba5e0000 {
590            compatible = "arm,smmu-v1";
591            reg = <0xba5e0000 0x10000>;
592            #global-interrupts = <2>;
593            interrupts = <0 32 4>,
594                         <0 33 4>,
595                         <0 34 4>, /* This is the first context interrupt */
596                         <0 35 4>,
597                         <0 36 4>,
598                         <0 37 4>;
599            #iommu-cells = <1>;
600    };
601
602    /* device with two stream IDs, 0 and 7 */
603    master1 {
604            iommus = <&smmu1 0>,
605                     <&smmu1 7>;
606    };
607
608
609    /* SMMU with stream matching */
610    smmu2: iommu@ba5f0000 {
611            compatible = "arm,smmu-v1";
612            reg = <0xba5f0000 0x10000>;
613            #global-interrupts = <2>;
614            interrupts = <0 38 4>,
615                         <0 39 4>,
616                         <0 40 4>, /* This is the first context interrupt */
617                         <0 41 4>,
618                         <0 42 4>,
619                         <0 43 4>;
620            #iommu-cells = <2>;
621    };
622
623    /* device with stream IDs 0 and 7 */
624    master2 {
625            iommus = <&smmu2 0 0>,
626                     <&smmu2 7 0>;
627    };
628
629    /* device with stream IDs 1, 17, 33 and 49 */
630    master3 {
631            iommus = <&smmu2 1 0x30>;
632    };
633
634
635    /* ARM MMU-500 with 10-bit stream ID input configuration */
636    smmu3: iommu@ba600000 {
637            compatible = "arm,mmu-500", "arm,smmu-v2";
638            reg = <0xba600000 0x10000>;
639            #global-interrupts = <2>;
640            interrupts = <0 44 4>,
641                         <0 45 4>,
642                         <0 46 4>, /* This is the first context interrupt */
643                         <0 47 4>,
644                         <0 48 4>,
645                         <0 49 4>;
646            #iommu-cells = <1>;
647            /* always ignore appended 5-bit TBU number */
648            stream-match-mask = <0x7c00>;
649    };
650
651    bus {
652            /* bus whose child devices emit one unique 10-bit stream
653               ID each, but may master through multiple SMMU TBUs */
654            iommu-map = <0 &smmu3 0 0x400>;
655
656
657    };
658
659  - |+
660    /* Qcom's arm,smmu-v2 implementation */
661    #include <dt-bindings/interrupt-controller/arm-gic.h>
662    #include <dt-bindings/interrupt-controller/irq.h>
663    smmu4: iommu@d00000 {
664      compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
665      reg = <0xd00000 0x10000>;
666
667      #global-interrupts = <1>;
668      interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
669             <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
670             <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
671      #iommu-cells = <1>;
672      power-domains = <&mmcc 0>;
673
674      clocks = <&mmcc 123>,
675        <&mmcc 124>;
676      clock-names = "bus", "iface";
677    };
678