1158979Snetchild# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2166322Sjoel# Copyright 2019 Texas Instruments Incorporated 3166322Sjoel%YAML 1.2 4166322Sjoel--- 5158979Snetchild$id: http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml# 6158979Snetchild$schema: http://devicetree.org/meta-schemas/core.yaml# 7158979Snetchild 8158979Snetchildtitle: Texas Instruments J721E Display Subsystem 9158979Snetchild 10158979Snetchildmaintainers: 11158979Snetchild - Jyri Sarha <jsarha@ti.com> 12158979Snetchild - Tomi Valkeinen <tomi.valkeinen@ti.com> 13158979Snetchild 14158979Snetchilddescription: | 15158979Snetchild The J721E TI Keystone Display SubSystem with four output ports and 16158979Snetchild four video planes. There is two full video planes and two "lite 17158979Snetchild planes" without scaling support. The video ports can be connected to 18158979Snetchild the SoC's DPI pins or to integrated display bridges on the SoC. 19158979Snetchild 20158979Snetchildproperties: 21158979Snetchild compatible: 22158979Snetchild const: ti,j721e-dss 23158979Snetchild 24158979Snetchild reg: 25158979Snetchild items: 26158979Snetchild - description: common_m DSS Master common 27158979Snetchild - description: common_s0 DSS Shared common 0 28158979Snetchild - description: common_s1 DSS Shared common 1 29158979Snetchild - description: common_s2 DSS Shared common 2 30166322Sjoel - description: VIDL1 light video plane 1 31166322Sjoel - description: VIDL2 light video plane 2 32166322Sjoel - description: VID1 video plane 1 33166322Sjoel - description: VID1 video plane 2 34158979Snetchild - description: OVR1 overlay manager for vp1 35158979Snetchild - description: OVR2 overlay manager for vp2 36158979Snetchild - description: OVR3 overlay manager for vp3 37158979Snetchild - description: OVR4 overlay manager for vp4 38158979Snetchild - description: VP1 video port 1 39158979Snetchild - description: VP2 video port 2 40158979Snetchild - description: VP3 video port 3 41158979Snetchild - description: VP4 video port 4 42158979Snetchild - description: WB Write Back 43158979Snetchild 44158979Snetchild reg-names: 45158979Snetchild items: 46158979Snetchild - const: common_m 47158979Snetchild - const: common_s0 48158979Snetchild - const: common_s1 49158979Snetchild - const: common_s2 50158979Snetchild - const: vidl1 51158979Snetchild - const: vidl2 52158979Snetchild - const: vid1 53166971Snetchild - const: vid2 54166971Snetchild - const: ovr1 55158979Snetchild - const: ovr2 56158979Snetchild - const: ovr3 57158979Snetchild - const: ovr4 58158979Snetchild - const: vp1 59158979Snetchild - const: vp2 60193640Sariff - const: vp3 61158979Snetchild - const: vp4 62158979Snetchild - const: wb 63158979Snetchild 64166971Snetchild clocks: 65158979Snetchild items: 66158979Snetchild - description: fck DSS functional clock 67158979Snetchild - description: vp1 Video Port 1 pixel clock 68158979Snetchild - description: vp2 Video Port 2 pixel clock 69158979Snetchild - description: vp3 Video Port 3 pixel clock 70158979Snetchild - description: vp4 Video Port 4 pixel clock 71158979Snetchild 72166971Snetchild clock-names: 73166971Snetchild items: 74158979Snetchild - const: fck 75166971Snetchild - const: vp1 76158979Snetchild - const: vp2 77158979Snetchild - const: vp3 78158979Snetchild - const: vp4 79158979Snetchild 80158979Snetchild assigned-clocks: 81158979Snetchild minItems: 1 82166971Snetchild maxItems: 5 83158979Snetchild 84158979Snetchild assigned-clock-parents: 85158979Snetchild minItems: 1 86158979Snetchild maxItems: 5 87158979Snetchild 88158979Snetchild interrupts: 89158979Snetchild items: 90158979Snetchild - description: common_m DSS Master common 91 - description: common_s0 DSS Shared common 0 92 - description: common_s1 DSS Shared common 1 93 - description: common_s2 DSS Shared common 2 94 95 interrupt-names: 96 items: 97 - const: common_m 98 - const: common_s0 99 - const: common_s1 100 - const: common_s2 101 102 power-domains: 103 maxItems: 1 104 description: phandle to the associated power domain 105 106 dma-coherent: 107 type: boolean 108 109 ports: 110 $ref: /schemas/graph.yaml#/properties/ports 111 112 properties: 113 port@0: 114 $ref: /schemas/graph.yaml#/properties/port 115 description: 116 The output port node form video port 1 117 118 port@1: 119 $ref: /schemas/graph.yaml#/properties/port 120 description: 121 The output port node from video port 2 122 123 port@2: 124 $ref: /schemas/graph.yaml#/properties/port 125 description: 126 The output port node from video port 3 127 128 port@3: 129 $ref: /schemas/graph.yaml#/properties/port 130 description: 131 The output port node from video port 4 132 133 max-memory-bandwidth: 134 $ref: /schemas/types.yaml#/definitions/uint32 135 description: 136 Input memory (from main memory to dispc) bandwidth limit in 137 bytes per second 138 139required: 140 - compatible 141 - reg 142 - reg-names 143 - clocks 144 - clock-names 145 - interrupts 146 - interrupt-names 147 - ports 148 149additionalProperties: false 150 151examples: 152 - | 153 #include <dt-bindings/interrupt-controller/arm-gic.h> 154 #include <dt-bindings/interrupt-controller/irq.h> 155 #include <dt-bindings/soc/ti,sci_pm_domain.h> 156 157 dss: dss@4a00000 { 158 compatible = "ti,j721e-dss"; 159 reg = <0x04a00000 0x10000>, /* common_m */ 160 <0x04a10000 0x10000>, /* common_s0*/ 161 <0x04b00000 0x10000>, /* common_s1*/ 162 <0x04b10000 0x10000>, /* common_s2*/ 163 <0x04a20000 0x10000>, /* vidl1 */ 164 <0x04a30000 0x10000>, /* vidl2 */ 165 <0x04a50000 0x10000>, /* vid1 */ 166 <0x04a60000 0x10000>, /* vid2 */ 167 <0x04a70000 0x10000>, /* ovr1 */ 168 <0x04a90000 0x10000>, /* ovr2 */ 169 <0x04ab0000 0x10000>, /* ovr3 */ 170 <0x04ad0000 0x10000>, /* ovr4 */ 171 <0x04a80000 0x10000>, /* vp1 */ 172 <0x04aa0000 0x10000>, /* vp2 */ 173 <0x04ac0000 0x10000>, /* vp3 */ 174 <0x04ae0000 0x10000>, /* vp4 */ 175 <0x04af0000 0x10000>; /* wb */ 176 reg-names = "common_m", "common_s0", 177 "common_s1", "common_s2", 178 "vidl1", "vidl2","vid1","vid2", 179 "ovr1", "ovr2", "ovr3", "ovr4", 180 "vp1", "vp2", "vp3", "vp4", 181 "wb"; 182 clocks = <&k3_clks 152 0>, 183 <&k3_clks 152 1>, 184 <&k3_clks 152 4>, 185 <&k3_clks 152 9>, 186 <&k3_clks 152 13>; 187 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 188 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 189 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 193 interrupt-names = "common_m", 194 "common_s0", 195 "common_s1", 196 "common_s2"; 197 ports { 198 #address-cells = <1>; 199 #size-cells = <0>; 200 port@0 { 201 reg = <0>; 202 203 dpi_out_0: endpoint { 204 remote-endpoint = <&dp_bridge_input>; 205 }; 206 }; 207 }; 208 }; 209