10SN/A# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
20SN/A%YAML 1.2
30SN/A---
40SN/A$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
50SN/A$schema: http://devicetree.org/meta-schemas/core.yaml#
62362SN/A
70SN/Atitle: Qualcomm Global Clock & Reset Controller on IPQ5332
82362SN/A
90SN/Amaintainers:
100SN/A  - Bjorn Andersson <andersson@kernel.org>
110SN/A
120SN/Adescription: |
130SN/A  Qualcomm global clock control module provides the clocks, resets and power
140SN/A  domains on IPQ5332.
150SN/A
160SN/A  See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h
170SN/A
180SN/AallOf:
190SN/A  - $ref: qcom,gcc.yaml#
202362SN/A
212362SN/Aproperties:
222362SN/A  compatible:
230SN/A    const: qcom,ipq5332-gcc
240SN/A
250SN/A  clocks:
260SN/A    items:
270SN/A      - description: Board XO clock source
280SN/A      - description: Sleep clock source
290SN/A      - description: PCIE 2lane PHY pipe clock source
300SN/A      - description: PCIE 2lane x1 PHY pipe clock source (For second lane)
310SN/A      - description: USB PCIE wrapper pipe clock source
320SN/A
330SN/Arequired:
340SN/A  - compatible
350SN/A  - clocks
360SN/A
370SN/AunevaluatedProperties: false
380SN/A
390SN/Aexamples:
400SN/A  - |
410SN/A    clock-controller@1800000 {
420SN/A      compatible = "qcom,ipq5332-gcc";
431693SN/A      reg = <0x01800000 0x80000>;
441693SN/A      clocks = <&xo_board>,
456936SN/A               <&sleep_clk>,
466936SN/A               <&pcie_2lane_phy_pipe_clk>,
473171SN/A               <&pcie_2lane_phy_pipe_clk_x1>,
483171SN/A               <&usb_pcie_wrapper_pipe_clk>;
493171SN/A      #clock-cells = <1>;
506936SN/A      #power-domain-cells = <1>;
513171SN/A      #reset-cells = <1>;
523171SN/A    };
533171SN/A...
543171SN/A