1/* longlong.h -- definitions for mixed size 32/64 bit arithmetic. 2 Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000 3 Free Software Foundation, Inc. 4 5 This file is part of the GNU C Library. 6 7 The GNU C Library is free software; you can redistribute it and/or 8 modify it under the terms of the GNU Lesser General Public 9 License as published by the Free Software Foundation; either 10 version 2.1 of the License, or (at your option) any later version. 11 12 The GNU C Library is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 Lesser General Public License for more details. 16 17 You should have received a copy of the GNU Lesser General Public 18 License along with the GNU C Library; if not, write to the Free 19 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 20 02111-1307 USA. */ 21 22/* You have to define the following before including this file: 23 24 UWtype -- An unsigned type, default type for operations (typically a "word") 25 UHWtype -- An unsigned type, at least half the size of UWtype. 26 UDWtype -- An unsigned type, at least twice as large a UWtype 27 W_TYPE_SIZE -- size in bits of UWtype 28 29 UQItype -- Unsigned 8 bit type. 30 SItype, USItype -- Signed and unsigned 32 bit types. 31 DItype, UDItype -- Signed and unsigned 64 bit types. 32 33 On a 32 bit machine UWtype should typically be USItype; 34 on a 64 bit machine, UWtype should typically be UDItype. 35*/ 36 37#define __BITS4 (W_TYPE_SIZE / 4) 38#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2)) 39#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1)) 40#define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2)) 41 42#ifndef W_TYPE_SIZE 43#define W_TYPE_SIZE 32 44#define UWtype USItype 45#define UHWtype USItype 46#define UDWtype UDItype 47#endif 48 49/* Define auxiliary asm macros. 50 51 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) multiplies two 52 UWtype integers MULTIPLER and MULTIPLICAND, and generates a two UWtype 53 word product in HIGH_PROD and LOW_PROD. 54 55 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a 56 UDWtype product. This is just a variant of umul_ppmm. 57 58 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator, 59 denominator) divides a UDWtype, composed by the UWtype integers 60 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient 61 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less 62 than DENOMINATOR for correct operation. If, in addition, the most 63 significant bit of DENOMINATOR must be 1, then the pre-processor symbol 64 UDIV_NEEDS_NORMALIZATION is defined to 1. 65 66 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator, 67 denominator). Like udiv_qrnnd but the numbers are signed. The quotient 68 is rounded towards 0. 69 70 5) count_leading_zeros(count, x) counts the number of zero-bits from the 71 msb to the first nonzero bit in the UWtype X. This is the number of 72 steps X needs to be shifted left to set the msb. Undefined for X == 0, 73 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value. 74 75 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts 76 from the least significant end. 77 78 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1, 79 high_addend_2, low_addend_2) adds two UWtype integers, composed by 80 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2 81 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow 82 (i.e. carry out) is not stored anywhere, and is lost. 83 84 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend, 85 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers, 86 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and 87 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE 88 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere, 89 and is lost. 90 91 If any of these macros are left undefined for a particular CPU, 92 C macros are used. */ 93 94/* The CPUs come in alphabetical order below. 95 96 Please add support for more CPUs here, or improve the current support 97 for the CPUs below! 98 (E.g. WE32100, IBM360.) */ 99 100#if defined (__GNUC__) && !defined (NO_ASM) 101 102/* We sometimes need to clobber "cc" with gcc2, but that would not be 103 understood by gcc1. Use cpp to avoid major code duplication. */ 104#if __GNUC__ < 2 105#define __CLOBBER_CC 106#define __AND_CLOBBER_CC 107#else /* __GNUC__ >= 2 */ 108#define __CLOBBER_CC : "cc" 109#define __AND_CLOBBER_CC , "cc" 110#endif /* __GNUC__ < 2 */ 111 112#if defined (__alpha) && W_TYPE_SIZE == 64 113#define umul_ppmm(ph, pl, m0, m1) \ 114 do { \ 115 UDItype __m0 = (m0), __m1 = (m1); \ 116 __asm__ ("umulh %r1,%2,%0" \ 117 : "=r" ((UDItype) ph) \ 118 : "%rJ" (__m0), \ 119 "rI" (__m1)); \ 120 (pl) = __m0 * __m1; \ 121 } while (0) 122#define UMUL_TIME 46 123#ifndef LONGLONG_STANDALONE 124#define udiv_qrnnd(q, r, n1, n0, d) \ 125 do { UDItype __r; \ 126 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \ 127 (r) = __r; \ 128 } while (0) 129extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype); 130#define UDIV_TIME 220 131#endif /* LONGLONG_STANDALONE */ 132#ifdef __alpha_cix__ 133#define count_leading_zeros(COUNT,X) \ 134 __asm__("ctlz %1,%0" : "=r"(COUNT) : "r"(X)) 135#define count_trailing_zeros(COUNT,X) \ 136 __asm__("cttz %1,%0" : "=r"(COUNT) : "r"(X)) 137#define COUNT_LEADING_ZEROS_0 64 138#else 139extern const UQItype __clz_tab[]; 140#define count_leading_zeros(COUNT,X) \ 141 do { \ 142 UDItype __xr = (X), __t, __a; \ 143 __asm__("cmpbge $31,%1,%0" : "=r"(__t) : "r"(__xr)); \ 144 __a = __clz_tab[__t ^ 0xff] - 1; \ 145 __asm__("extbl %1,%2,%0" : "=r"(__t) : "r"(__xr), "r"(__a)); \ 146 (COUNT) = 64 - (__clz_tab[__t] + __a*8); \ 147 } while (0) 148#define count_trailing_zeros(COUNT,X) \ 149 do { \ 150 UDItype __xr = (X), __t, __a; \ 151 __asm__("cmpbge $31,%1,%0" : "=r"(__t) : "r"(__xr)); \ 152 __t = ~__t & -~__t; \ 153 __a = ((__t & 0xCC) != 0) * 2; \ 154 __a += ((__t & 0xF0) != 0) * 4; \ 155 __a += ((__t & 0xAA) != 0); \ 156 __asm__("extbl %1,%2,%0" : "=r"(__t) : "r"(__xr), "r"(__a)); \ 157 __a <<= 3; \ 158 __t &= -__t; \ 159 __a += ((__t & 0xCC) != 0) * 2; \ 160 __a += ((__t & 0xF0) != 0) * 4; \ 161 __a += ((__t & 0xAA) != 0); \ 162 (COUNT) = __a; \ 163 } while (0) 164#endif /* __alpha_cix__ */ 165#endif /* __alpha */ 166 167#if defined (__arc__) && W_TYPE_SIZE == 32 168#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 169 __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \ 170 : "=r" ((USItype) (sh)), \ 171 "=&r" ((USItype) (sl)) \ 172 : "%r" ((USItype) (ah)), \ 173 "rIJ" ((USItype) (bh)), \ 174 "%r" ((USItype) (al)), \ 175 "rIJ" ((USItype) (bl))) 176#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 177 __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \ 178 : "=r" ((USItype) (sh)), \ 179 "=&r" ((USItype) (sl)) \ 180 : "r" ((USItype) (ah)), \ 181 "rIJ" ((USItype) (bh)), \ 182 "r" ((USItype) (al)), \ 183 "rIJ" ((USItype) (bl))) 184/* Call libgcc routine. */ 185#define umul_ppmm(w1, w0, u, v) \ 186do { \ 187 DWunion __w; \ 188 __w.ll = __umulsidi3 (u, v); \ 189 w1 = __w.s.high; \ 190 w0 = __w.s.low; \ 191} while (0) 192#define __umulsidi3 __umulsidi3 193UDItype __umulsidi3 (USItype, USItype); 194#endif 195 196#if defined (__arm__) && (defined (__thumb2__) || !defined (__thumb__)) \ 197 && W_TYPE_SIZE == 32 198#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 199 __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \ 200 : "=r" ((USItype) (sh)), \ 201 "=&r" ((USItype) (sl)) \ 202 : "%r" ((USItype) (ah)), \ 203 "rI" ((USItype) (bh)), \ 204 "%r" ((USItype) (al)), \ 205 "rI" ((USItype) (bl)) __CLOBBER_CC) 206#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 207 __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \ 208 : "=r" ((USItype) (sh)), \ 209 "=&r" ((USItype) (sl)) \ 210 : "r" ((USItype) (ah)), \ 211 "rI" ((USItype) (bh)), \ 212 "r" ((USItype) (al)), \ 213 "rI" ((USItype) (bl)) __CLOBBER_CC) 214# if defined(__ARM_ARCH_2__) || defined(__ARM_ARCH_2A__) \ 215 || defined(__ARM_ARCH_3__) 216# define umul_ppmm(xh, xl, a, b) \ 217 do { \ 218 register USItype __t0, __t1, __t2; \ 219 __asm__ ("%@ Inlined umul_ppmm\n" \ 220 " mov %2, %5, lsr #16\n" \ 221 " mov %0, %6, lsr #16\n" \ 222 " bic %3, %5, %2, lsl #16\n" \ 223 " bic %4, %6, %0, lsl #16\n" \ 224 " mul %1, %3, %4\n" \ 225 " mul %4, %2, %4\n" \ 226 " mul %3, %0, %3\n" \ 227 " mul %0, %2, %0\n" \ 228 " adds %3, %4, %3\n" \ 229 " addcs %0, %0, #65536\n" \ 230 " adds %1, %1, %3, lsl #16\n" \ 231 " adc %0, %0, %3, lsr #16" \ 232 : "=&r" ((USItype) (xh)), \ 233 "=r" ((USItype) (xl)), \ 234 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \ 235 : "r" ((USItype) (a)), \ 236 "r" ((USItype) (b)) __CLOBBER_CC ); \ 237 } while (0) 238# define UMUL_TIME 20 239# else 240# define umul_ppmm(xh, xl, a, b) \ 241 do { \ 242 /* Generate umull, under compiler control. */ \ 243 register UDItype __t0 = (UDItype)(USItype)(a) * (USItype)(b); \ 244 (xl) = (USItype)__t0; \ 245 (xh) = (USItype)(__t0 >> 32); \ 246 } while (0) 247# define UMUL_TIME 3 248# endif 249# define UDIV_TIME 100 250#endif /* __arm__ */ 251 252#if defined (__hppa) && W_TYPE_SIZE == 32 253#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 254 __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \ 255 : "=r" ((USItype) (sh)), \ 256 "=&r" ((USItype) (sl)) \ 257 : "%rM" ((USItype) (ah)), \ 258 "rM" ((USItype) (bh)), \ 259 "%rM" ((USItype) (al)), \ 260 "rM" ((USItype) (bl))) 261#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 262 __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \ 263 : "=r" ((USItype) (sh)), \ 264 "=&r" ((USItype) (sl)) \ 265 : "rM" ((USItype) (ah)), \ 266 "rM" ((USItype) (bh)), \ 267 "rM" ((USItype) (al)), \ 268 "rM" ((USItype) (bl))) 269#if defined (_PA_RISC1_1) 270#define umul_ppmm(w1, w0, u, v) \ 271 do { \ 272 union \ 273 { \ 274 UDItype __f; \ 275 struct {USItype __w1, __w0;} __w1w0; \ 276 } __t; \ 277 __asm__ ("xmpyu %1,%2,%0" \ 278 : "=x" (__t.__f) \ 279 : "x" ((USItype) (u)), \ 280 "x" ((USItype) (v))); \ 281 (w1) = __t.__w1w0.__w1; \ 282 (w0) = __t.__w1w0.__w0; \ 283 } while (0) 284#define UMUL_TIME 8 285#else 286#define UMUL_TIME 30 287#endif 288#define UDIV_TIME 40 289#define count_leading_zeros(count, x) \ 290 do { \ 291 USItype __tmp; \ 292 __asm__ ( \ 293 "ldi 1,%0\n" \ 294" extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \ 295" extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\ 296" ldo 16(%0),%0 ; Yes. Perform add.\n" \ 297" extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \ 298" extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\ 299" ldo 8(%0),%0 ; Yes. Perform add.\n" \ 300" extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \ 301" extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\ 302" ldo 4(%0),%0 ; Yes. Perform add.\n" \ 303" extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \ 304" extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\ 305" ldo 2(%0),%0 ; Yes. Perform add.\n" \ 306" extru %1,30,1,%1 ; Extract bit 1.\n" \ 307" sub %0,%1,%0 ; Subtract it.\n" \ 308 : "=r" (count), "=r" (__tmp) : "1" (x)); \ 309 } while (0) 310#endif 311 312#if (defined (__i370__) || defined (__mvs__)) && W_TYPE_SIZE == 32 313#define umul_ppmm(xh, xl, m0, m1) \ 314 do { \ 315 union {UDItype __ll; \ 316 struct {USItype __h, __l;} __i; \ 317 } __xx; \ 318 USItype __m0 = (m0), __m1 = (m1); \ 319 __asm__ ("mr %0,%3" \ 320 : "=r" (__xx.__i.__h), \ 321 "=r" (__xx.__i.__l) \ 322 : "%1" (__m0), \ 323 "r" (__m1)); \ 324 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \ 325 (xh) += ((((SItype) __m0 >> 31) & __m1) \ 326 + (((SItype) __m1 >> 31) & __m0)); \ 327 } while (0) 328#define smul_ppmm(xh, xl, m0, m1) \ 329 do { \ 330 union {DItype __ll; \ 331 struct {USItype __h, __l;} __i; \ 332 } __xx; \ 333 __asm__ ("mr %0,%3" \ 334 : "=r" (__xx.__i.__h), \ 335 "=r" (__xx.__i.__l) \ 336 : "%1" (m0), \ 337 "r" (m1)); \ 338 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \ 339 } while (0) 340#define sdiv_qrnnd(q, r, n1, n0, d) \ 341 do { \ 342 union {DItype __ll; \ 343 struct {USItype __h, __l;} __i; \ 344 } __xx; \ 345 __xx.__i.__h = n1; __xx.__i.__l = n0; \ 346 __asm__ ("dr %0,%2" \ 347 : "=r" (__xx.__ll) \ 348 : "0" (__xx.__ll), "r" (d)); \ 349 (q) = __xx.__i.__l; (r) = __xx.__i.__h; \ 350 } while (0) 351#endif 352 353#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32 354#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 355 __asm__ ("addl %5,%1\n\tadcl %3,%0" \ 356 : "=r" ((USItype) (sh)), \ 357 "=&r" ((USItype) (sl)) \ 358 : "%0" ((USItype) (ah)), \ 359 "g" ((USItype) (bh)), \ 360 "%1" ((USItype) (al)), \ 361 "g" ((USItype) (bl))) 362#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 363 __asm__ ("subl %5,%1\n\tsbbl %3,%0" \ 364 : "=r" ((USItype) (sh)), \ 365 "=&r" ((USItype) (sl)) \ 366 : "0" ((USItype) (ah)), \ 367 "g" ((USItype) (bh)), \ 368 "1" ((USItype) (al)), \ 369 "g" ((USItype) (bl))) 370#define umul_ppmm(w1, w0, u, v) \ 371 __asm__ ("mull %3" \ 372 : "=a" ((USItype) (w0)), \ 373 "=d" ((USItype) (w1)) \ 374 : "%0" ((USItype) (u)), \ 375 "rm" ((USItype) (v))) 376#define udiv_qrnnd(q, r, n1, n0, dv) \ 377 __asm__ ("divl %4" \ 378 : "=a" ((USItype) (q)), \ 379 "=d" ((USItype) (r)) \ 380 : "0" ((USItype) (n0)), \ 381 "1" ((USItype) (n1)), \ 382 "rm" ((USItype) (dv))) 383#define count_leading_zeros(count, x) \ 384 do { \ 385 USItype __cbtmp; \ 386 __asm__ ("bsrl %1,%0" \ 387 : "=r" (__cbtmp) : "rm" ((USItype) (x))); \ 388 (count) = __cbtmp ^ 31; \ 389 } while (0) 390#define count_trailing_zeros(count, x) \ 391 __asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x))) 392#define UMUL_TIME 40 393#define UDIV_TIME 40 394#endif /* 80x86 */ 395 396#if defined (__i960__) && W_TYPE_SIZE == 32 397#define umul_ppmm(w1, w0, u, v) \ 398 ({union {UDItype __ll; \ 399 struct {USItype __l, __h;} __i; \ 400 } __xx; \ 401 __asm__ ("emul %2,%1,%0" \ 402 : "=d" (__xx.__ll) \ 403 : "%dI" ((USItype) (u)), \ 404 "dI" ((USItype) (v))); \ 405 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;}) 406#define __umulsidi3(u, v) \ 407 ({UDItype __w; \ 408 __asm__ ("emul %2,%1,%0" \ 409 : "=d" (__w) \ 410 : "%dI" ((USItype) (u)), \ 411 "dI" ((USItype) (v))); \ 412 __w; }) 413#endif /* __i960__ */ 414 415#if defined (__M32R__) && W_TYPE_SIZE == 32 416#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 417 /* The cmp clears the condition bit. */ \ 418 __asm__ ("cmp %0,%0\n\taddx %%5,%1\n\taddx %%3,%0" \ 419 : "=r" ((USItype) (sh)), \ 420 "=&r" ((USItype) (sl)) \ 421 : "%0" ((USItype) (ah)), \ 422 "r" ((USItype) (bh)), \ 423 "%1" ((USItype) (al)), \ 424 "r" ((USItype) (bl)) \ 425 : "cbit") 426#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 427 /* The cmp clears the condition bit. */ \ 428 __asm__ ("cmp %0,%0\n\tsubx %5,%1\n\tsubx %3,%0" \ 429 : "=r" ((USItype) (sh)), \ 430 "=&r" ((USItype) (sl)) \ 431 : "0" ((USItype) (ah)), \ 432 "r" ((USItype) (bh)), \ 433 "1" ((USItype) (al)), \ 434 "r" ((USItype) (bl)) \ 435 : "cbit") 436#endif /* __M32R__ */ 437 438#if defined (__mc68000__) && W_TYPE_SIZE == 32 439#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 440 __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \ 441 : "=d" ((USItype) (sh)), \ 442 "=&d" ((USItype) (sl)) \ 443 : "%0" ((USItype) (ah)), \ 444 "d" ((USItype) (bh)), \ 445 "%1" ((USItype) (al)), \ 446 "g" ((USItype) (bl))) 447#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 448 __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \ 449 : "=d" ((USItype) (sh)), \ 450 "=&d" ((USItype) (sl)) \ 451 : "0" ((USItype) (ah)), \ 452 "d" ((USItype) (bh)), \ 453 "1" ((USItype) (al)), \ 454 "g" ((USItype) (bl))) 455 456/* The '020, '030, '040 and CPU32 have 32x32->64 and 64/32->32q-32r. */ 457#if defined (__mc68020__) || defined(mc68020) \ 458 || defined(__mc68030__) || defined(mc68030) \ 459 || defined(__mc68040__) || defined(mc68040) \ 460 || defined(__mcpu32__) || defined(mcpu32) 461#define umul_ppmm(w1, w0, u, v) \ 462 __asm__ ("mulu%.l %3,%1:%0" \ 463 : "=d" ((USItype) (w0)), \ 464 "=d" ((USItype) (w1)) \ 465 : "%0" ((USItype) (u)), \ 466 "dmi" ((USItype) (v))) 467#define UMUL_TIME 45 468#define udiv_qrnnd(q, r, n1, n0, d) \ 469 __asm__ ("divu%.l %4,%1:%0" \ 470 : "=d" ((USItype) (q)), \ 471 "=d" ((USItype) (r)) \ 472 : "0" ((USItype) (n0)), \ 473 "1" ((USItype) (n1)), \ 474 "dmi" ((USItype) (d))) 475#define UDIV_TIME 90 476#define sdiv_qrnnd(q, r, n1, n0, d) \ 477 __asm__ ("divs%.l %4,%1:%0" \ 478 : "=d" ((USItype) (q)), \ 479 "=d" ((USItype) (r)) \ 480 : "0" ((USItype) (n0)), \ 481 "1" ((USItype) (n1)), \ 482 "dmi" ((USItype) (d))) 483 484#else /* not mc68020 */ 485#if !defined(__mcf5200__) 486/* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */ 487#define umul_ppmm(xh, xl, a, b) \ 488 __asm__ ("| Inlined umul_ppmm\n" \ 489 " move%.l %2,%/d0\n" \ 490 " move%.l %3,%/d1\n" \ 491 " move%.l %/d0,%/d2\n" \ 492 " swap %/d0\n" \ 493 " move%.l %/d1,%/d3\n" \ 494 " swap %/d1\n" \ 495 " move%.w %/d2,%/d4\n" \ 496 " mulu %/d3,%/d4\n" \ 497 " mulu %/d1,%/d2\n" \ 498 " mulu %/d0,%/d3\n" \ 499 " mulu %/d0,%/d1\n" \ 500 " move%.l %/d4,%/d0\n" \ 501 " eor%.w %/d0,%/d0\n" \ 502 " swap %/d0\n" \ 503 " add%.l %/d0,%/d2\n" \ 504 " add%.l %/d3,%/d2\n" \ 505 " jcc 1f\n" \ 506 " add%.l %#65536,%/d1\n" \ 507 "1: swap %/d2\n" \ 508 " moveq %#0,%/d0\n" \ 509 " move%.w %/d2,%/d0\n" \ 510 " move%.w %/d4,%/d2\n" \ 511 " move%.l %/d2,%1\n" \ 512 " add%.l %/d1,%/d0\n" \ 513 " move%.l %/d0,%0" \ 514 : "=g" ((USItype) (xh)), \ 515 "=g" ((USItype) (xl)) \ 516 : "g" ((USItype) (a)), \ 517 "g" ((USItype) (b)) \ 518 : "d0", "d1", "d2", "d3", "d4") 519#define UMUL_TIME 100 520#define UDIV_TIME 400 521#endif /* not mcf5200 */ 522#endif /* not mc68020 */ 523 524/* The '020, '030, '040 and '060 have bitfield insns. */ 525#if defined (__mc68020__) || defined(mc68020) \ 526 || defined(__mc68030__) || defined(mc68030) \ 527 || defined(__mc68040__) || defined(mc68040) \ 528 || defined(__mc68060__) || defined(mc68060) 529#define count_leading_zeros(count, x) \ 530 __asm__ ("bfffo %1{%b2:%b2},%0" \ 531 : "=d" ((USItype) (count)) \ 532 : "od" ((USItype) (x)), "n" (0)) 533#endif 534#endif /* mc68000 */ 535 536#if defined (__m88000__) && W_TYPE_SIZE == 32 537#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 538 __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \ 539 : "=r" ((USItype) (sh)), \ 540 "=&r" ((USItype) (sl)) \ 541 : "%rJ" ((USItype) (ah)), \ 542 "rJ" ((USItype) (bh)), \ 543 "%rJ" ((USItype) (al)), \ 544 "rJ" ((USItype) (bl))) 545#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 546 __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \ 547 : "=r" ((USItype) (sh)), \ 548 "=&r" ((USItype) (sl)) \ 549 : "rJ" ((USItype) (ah)), \ 550 "rJ" ((USItype) (bh)), \ 551 "rJ" ((USItype) (al)), \ 552 "rJ" ((USItype) (bl))) 553#define count_leading_zeros(count, x) \ 554 do { \ 555 USItype __cbtmp; \ 556 __asm__ ("ff1 %0,%1" \ 557 : "=r" (__cbtmp) \ 558 : "r" ((USItype) (x))); \ 559 (count) = __cbtmp ^ 31; \ 560 } while (0) 561#define COUNT_LEADING_ZEROS_0 63 /* sic */ 562#if defined (__mc88110__) 563#define umul_ppmm(wh, wl, u, v) \ 564 do { \ 565 union {UDItype __ll; \ 566 struct {USItype __h, __l;} __i; \ 567 } __xx; \ 568 __asm__ ("mulu.d %0,%1,%2" \ 569 : "=r" (__xx.__ll) \ 570 : "r" ((USItype) (u)), \ 571 "r" ((USItype) (v))); \ 572 (wh) = __xx.__i.__h; \ 573 (wl) = __xx.__i.__l; \ 574 } while (0) 575#define udiv_qrnnd(q, r, n1, n0, d) \ 576 ({union {UDItype __ll; \ 577 struct {USItype __h, __l;} __i; \ 578 } __xx; \ 579 USItype __q; \ 580 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \ 581 __asm__ ("divu.d %0,%1,%2" \ 582 : "=r" (__q) \ 583 : "r" (__xx.__ll), \ 584 "r" ((USItype) (d))); \ 585 (r) = (n0) - __q * (d); (q) = __q; }) 586#define UMUL_TIME 5 587#define UDIV_TIME 25 588#else 589#define UMUL_TIME 17 590#define UDIV_TIME 150 591#endif /* __mc88110__ */ 592#endif /* __m88000__ */ 593 594#if defined (__mips__) && W_TYPE_SIZE == 32 595#define umul_ppmm(w1, w0, u, v) \ 596 __asm__ ("multu %2,%3" \ 597 : "=l" ((USItype) (w0)), \ 598 "=h" ((USItype) (w1)) \ 599 : "d" ((USItype) (u)), \ 600 "d" ((USItype) (v))) 601#define UMUL_TIME 10 602#define UDIV_TIME 100 603#endif /* __mips__ */ 604 605#if defined (__ns32000__) && W_TYPE_SIZE == 32 606#define umul_ppmm(w1, w0, u, v) \ 607 ({union {UDItype __ll; \ 608 struct {USItype __l, __h;} __i; \ 609 } __xx; \ 610 __asm__ ("meid %2,%0" \ 611 : "=g" (__xx.__ll) \ 612 : "%0" ((USItype) (u)), \ 613 "g" ((USItype) (v))); \ 614 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;}) 615#define __umulsidi3(u, v) \ 616 ({UDItype __w; \ 617 __asm__ ("meid %2,%0" \ 618 : "=g" (__w) \ 619 : "%0" ((USItype) (u)), \ 620 "g" ((USItype) (v))); \ 621 __w; }) 622#define udiv_qrnnd(q, r, n1, n0, d) \ 623 ({union {UDItype __ll; \ 624 struct {USItype __l, __h;} __i; \ 625 } __xx; \ 626 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \ 627 __asm__ ("deid %2,%0" \ 628 : "=g" (__xx.__ll) \ 629 : "0" (__xx.__ll), \ 630 "g" ((USItype) (d))); \ 631 (r) = __xx.__i.__l; (q) = __xx.__i.__h; }) 632#define count_trailing_zeros(count,x) \ 633 do { \ 634 __asm__ ("ffsd %2,%0" \ 635 : "=r" ((USItype) (count)) \ 636 : "0" ((USItype) 0), \ 637 "r" ((USItype) (x))); \ 638 } while (0) 639#endif /* __ns32000__ */ 640 641/* FIXME: We should test _IBMR2 here when we add assembly support for the 642 system vendor compilers. 643 FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good 644 enough, since that hits ARM and m68k too. */ 645#if (defined (_ARCH_PPC) /* AIX */ \ 646 || defined (_ARCH_PWR) /* AIX */ \ 647 || defined (_ARCH_COM) /* AIX */ \ 648 || defined (__powerpc__) /* gcc */ \ 649 || defined (__POWERPC__) /* BEOS */ \ 650 || defined (__ppc__) /* Darwin */ \ 651 || defined (PPC) /* GNU/Linux, SysV */ \ 652 ) && W_TYPE_SIZE == 32 653#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 654 do { \ 655 if (__builtin_constant_p (bh) && (bh) == 0) \ 656 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \ 657 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ 658 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \ 659 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \ 660 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ 661 else \ 662 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \ 663 : "=r" (sh), "=&r" (sl) \ 664 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \ 665 } while (0) 666#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 667 do { \ 668 if (__builtin_constant_p (ah) && (ah) == 0) \ 669 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \ 670 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ 671 else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \ 672 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \ 673 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ 674 else if (__builtin_constant_p (bh) && (bh) == 0) \ 675 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \ 676 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ 677 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \ 678 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \ 679 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ 680 else \ 681 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \ 682 : "=r" (sh), "=&r" (sl) \ 683 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \ 684 } while (0) 685#define count_leading_zeros(count, x) \ 686 __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x)) 687#define COUNT_LEADING_ZEROS_0 32 688#if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \ 689 || defined (__ppc__) || defined (PPC) || defined (__vxworks__) 690#define umul_ppmm(ph, pl, m0, m1) \ 691 do { \ 692 USItype __m0 = (m0), __m1 = (m1); \ 693 __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \ 694 (pl) = __m0 * __m1; \ 695 } while (0) 696#define UMUL_TIME 15 697#define smul_ppmm(ph, pl, m0, m1) \ 698 do { \ 699 SItype __m0 = (m0), __m1 = (m1); \ 700 __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \ 701 (pl) = __m0 * __m1; \ 702 } while (0) 703#define SMUL_TIME 14 704#define UDIV_TIME 120 705#elif defined (_ARCH_PWR) 706#define UMUL_TIME 8 707#define smul_ppmm(xh, xl, m0, m1) \ 708 __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1)) 709#define SMUL_TIME 4 710#define sdiv_qrnnd(q, r, nh, nl, d) \ 711 __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d)) 712#define UDIV_TIME 100 713#endif 714#endif /* 32-bit POWER architecture variants. */ 715 716/* We should test _IBMR2 here when we add assembly support for the system 717 vendor compilers. */ 718#if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64 719#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 720 do { \ 721 if (__builtin_constant_p (bh) && (bh) == 0) \ 722 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \ 723 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ 724 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \ 725 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \ 726 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ 727 else \ 728 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \ 729 : "=r" (sh), "=&r" (sl) \ 730 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \ 731 } while (0) 732#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 733 do { \ 734 if (__builtin_constant_p (ah) && (ah) == 0) \ 735 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \ 736 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ 737 else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \ 738 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \ 739 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ 740 else if (__builtin_constant_p (bh) && (bh) == 0) \ 741 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \ 742 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ 743 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \ 744 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \ 745 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ 746 else \ 747 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \ 748 : "=r" (sh), "=&r" (sl) \ 749 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \ 750 } while (0) 751#define count_leading_zeros(count, x) \ 752 __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x)) 753#define COUNT_LEADING_ZEROS_0 64 754#define umul_ppmm(ph, pl, m0, m1) \ 755 do { \ 756 UDItype __m0 = (m0), __m1 = (m1); \ 757 __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \ 758 (pl) = __m0 * __m1; \ 759 } while (0) 760#define UMUL_TIME 15 761#define smul_ppmm(ph, pl, m0, m1) \ 762 do { \ 763 DItype __m0 = (m0), __m1 = (m1); \ 764 __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \ 765 (pl) = __m0 * __m1; \ 766 } while (0) 767#define SMUL_TIME 14 /* ??? */ 768#define UDIV_TIME 120 /* ??? */ 769#endif /* 64-bit PowerPC. */ 770 771#if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32 772#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 773 __asm__ ("a %1,%5\n\tae %0,%3" \ 774 : "=r" ((USItype) (sh)), \ 775 "=&r" ((USItype) (sl)) \ 776 : "%0" ((USItype) (ah)), \ 777 "r" ((USItype) (bh)), \ 778 "%1" ((USItype) (al)), \ 779 "r" ((USItype) (bl))) 780#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 781 __asm__ ("s %1,%5\n\tse %0,%3" \ 782 : "=r" ((USItype) (sh)), \ 783 "=&r" ((USItype) (sl)) \ 784 : "0" ((USItype) (ah)), \ 785 "r" ((USItype) (bh)), \ 786 "1" ((USItype) (al)), \ 787 "r" ((USItype) (bl))) 788#define umul_ppmm(ph, pl, m0, m1) \ 789 do { \ 790 USItype __m0 = (m0), __m1 = (m1); \ 791 __asm__ ( \ 792 "s r2,r2\n" \ 793" mts r10,%2\n" \ 794" m r2,%3\n" \ 795" m r2,%3\n" \ 796" m r2,%3\n" \ 797" m r2,%3\n" \ 798" m r2,%3\n" \ 799" m r2,%3\n" \ 800" m r2,%3\n" \ 801" m r2,%3\n" \ 802" m r2,%3\n" \ 803" m r2,%3\n" \ 804" m r2,%3\n" \ 805" m r2,%3\n" \ 806" m r2,%3\n" \ 807" m r2,%3\n" \ 808" m r2,%3\n" \ 809" m r2,%3\n" \ 810" cas %0,r2,r0\n" \ 811" mfs r10,%1" \ 812 : "=r" ((USItype) (ph)), \ 813 "=r" ((USItype) (pl)) \ 814 : "%r" (__m0), \ 815 "r" (__m1) \ 816 : "r2"); \ 817 (ph) += ((((SItype) __m0 >> 31) & __m1) \ 818 + (((SItype) __m1 >> 31) & __m0)); \ 819 } while (0) 820#define UMUL_TIME 20 821#define UDIV_TIME 200 822#define count_leading_zeros(count, x) \ 823 do { \ 824 if ((x) >= 0x10000) \ 825 __asm__ ("clz %0,%1" \ 826 : "=r" ((USItype) (count)) \ 827 : "r" ((USItype) (x) >> 16)); \ 828 else \ 829 { \ 830 __asm__ ("clz %0,%1" \ 831 : "=r" ((USItype) (count)) \ 832 : "r" ((USItype) (x))); \ 833 (count) += 16; \ 834 } \ 835 } while (0) 836#endif 837 838#if defined (__sh2__) && W_TYPE_SIZE == 32 839#define umul_ppmm(w1, w0, u, v) \ 840 __asm__ ( \ 841 "dmulu.l %2,%3\n\tsts macl,%1\n\tsts mach,%0" \ 842 : "=r" ((USItype)(w1)), \ 843 "=r" ((USItype)(w0)) \ 844 : "r" ((USItype)(u)), \ 845 "r" ((USItype)(v)) \ 846 : "macl", "mach") 847#define UMUL_TIME 5 848#endif 849 850#if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32 851#define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v) 852#define count_leading_zeros(count, x) \ 853 do \ 854 { \ 855 UDItype x_ = (USItype)(x); \ 856 SItype c_; \ 857 \ 858 __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \ 859 (count) = c_ - 31; \ 860 } \ 861 while (0) 862#define COUNT_LEADING_ZEROS_0 32 863#endif 864 865#if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \ 866 && W_TYPE_SIZE == 32 867#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 868 __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \ 869 : "=r" ((USItype) (sh)), \ 870 "=&r" ((USItype) (sl)) \ 871 : "%rJ" ((USItype) (ah)), \ 872 "rI" ((USItype) (bh)), \ 873 "%rJ" ((USItype) (al)), \ 874 "rI" ((USItype) (bl)) \ 875 __CLOBBER_CC) 876#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 877 __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \ 878 : "=r" ((USItype) (sh)), \ 879 "=&r" ((USItype) (sl)) \ 880 : "rJ" ((USItype) (ah)), \ 881 "rI" ((USItype) (bh)), \ 882 "rJ" ((USItype) (al)), \ 883 "rI" ((USItype) (bl)) \ 884 __CLOBBER_CC) 885#if defined (__sparc_v8__) 886#define umul_ppmm(w1, w0, u, v) \ 887 __asm__ ("umul %2,%3,%1;rd %%y,%0" \ 888 : "=r" ((USItype) (w1)), \ 889 "=r" ((USItype) (w0)) \ 890 : "r" ((USItype) (u)), \ 891 "r" ((USItype) (v))) 892#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \ 893 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\ 894 : "=&r" ((USItype) (__q)), \ 895 "=&r" ((USItype) (__r)) \ 896 : "r" ((USItype) (__n1)), \ 897 "r" ((USItype) (__n0)), \ 898 "r" ((USItype) (__d))) 899#else 900#if defined (__sparclite__) 901/* This has hardware multiply but not divide. It also has two additional 902 instructions scan (ffs from high bit) and divscc. */ 903#define umul_ppmm(w1, w0, u, v) \ 904 __asm__ ("umul %2,%3,%1;rd %%y,%0" \ 905 : "=r" ((USItype) (w1)), \ 906 "=r" ((USItype) (w0)) \ 907 : "r" ((USItype) (u)), \ 908 "r" ((USItype) (v))) 909#define udiv_qrnnd(q, r, n1, n0, d) \ 910 __asm__ ("! Inlined udiv_qrnnd\n" \ 911" wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \ 912" tst %%g0\n" \ 913" divscc %3,%4,%%g1\n" \ 914" divscc %%g1,%4,%%g1\n" \ 915" divscc %%g1,%4,%%g1\n" \ 916" divscc %%g1,%4,%%g1\n" \ 917" divscc %%g1,%4,%%g1\n" \ 918" divscc %%g1,%4,%%g1\n" \ 919" divscc %%g1,%4,%%g1\n" \ 920" divscc %%g1,%4,%%g1\n" \ 921" divscc %%g1,%4,%%g1\n" \ 922" divscc %%g1,%4,%%g1\n" \ 923" divscc %%g1,%4,%%g1\n" \ 924" divscc %%g1,%4,%%g1\n" \ 925" divscc %%g1,%4,%%g1\n" \ 926" divscc %%g1,%4,%%g1\n" \ 927" divscc %%g1,%4,%%g1\n" \ 928" divscc %%g1,%4,%%g1\n" \ 929" divscc %%g1,%4,%%g1\n" \ 930" divscc %%g1,%4,%%g1\n" \ 931" divscc %%g1,%4,%%g1\n" \ 932" divscc %%g1,%4,%%g1\n" \ 933" divscc %%g1,%4,%%g1\n" \ 934" divscc %%g1,%4,%%g1\n" \ 935" divscc %%g1,%4,%%g1\n" \ 936" divscc %%g1,%4,%%g1\n" \ 937" divscc %%g1,%4,%%g1\n" \ 938" divscc %%g1,%4,%%g1\n" \ 939" divscc %%g1,%4,%%g1\n" \ 940" divscc %%g1,%4,%%g1\n" \ 941" divscc %%g1,%4,%%g1\n" \ 942" divscc %%g1,%4,%%g1\n" \ 943" divscc %%g1,%4,%%g1\n" \ 944" divscc %%g1,%4,%0\n" \ 945" rd %%y,%1\n" \ 946" bl,a 1f\n" \ 947" add %1,%4,%1\n" \ 948"1: ! End of inline udiv_qrnnd" \ 949 : "=r" ((USItype) (q)), \ 950 "=r" ((USItype) (r)) \ 951 : "r" ((USItype) (n1)), \ 952 "r" ((USItype) (n0)), \ 953 "rI" ((USItype) (d)) \ 954 : "g1" __AND_CLOBBER_CC) 955#define UDIV_TIME 37 956#define count_leading_zeros(count, x) \ 957 do { \ 958 __asm__ ("scan %1,1,%0" \ 959 : "=r" ((USItype) (count)) \ 960 : "r" ((USItype) (x))); \ 961 } while (0) 962/* Early sparclites return 63 for an argument of 0, but they warn that future 963 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0 964 undefined. */ 965#else 966/* SPARC without integer multiplication and divide instructions. 967 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */ 968#define umul_ppmm(w1, w0, u, v) \ 969 __asm__ ("! Inlined umul_ppmm\n" \ 970" wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\ 971" sra %3,31,%%o5 ! Don't move this insn\n" \ 972" and %2,%%o5,%%o5 ! Don't move this insn\n" \ 973" andcc %%g0,0,%%g1 ! Don't move this insn\n" \ 974" mulscc %%g1,%3,%%g1\n" \ 975" mulscc %%g1,%3,%%g1\n" \ 976" mulscc %%g1,%3,%%g1\n" \ 977" mulscc %%g1,%3,%%g1\n" \ 978" mulscc %%g1,%3,%%g1\n" \ 979" mulscc %%g1,%3,%%g1\n" \ 980" mulscc %%g1,%3,%%g1\n" \ 981" mulscc %%g1,%3,%%g1\n" \ 982" mulscc %%g1,%3,%%g1\n" \ 983" mulscc %%g1,%3,%%g1\n" \ 984" mulscc %%g1,%3,%%g1\n" \ 985" mulscc %%g1,%3,%%g1\n" \ 986" mulscc %%g1,%3,%%g1\n" \ 987" mulscc %%g1,%3,%%g1\n" \ 988" mulscc %%g1,%3,%%g1\n" \ 989" mulscc %%g1,%3,%%g1\n" \ 990" mulscc %%g1,%3,%%g1\n" \ 991" mulscc %%g1,%3,%%g1\n" \ 992" mulscc %%g1,%3,%%g1\n" \ 993" mulscc %%g1,%3,%%g1\n" \ 994" mulscc %%g1,%3,%%g1\n" \ 995" mulscc %%g1,%3,%%g1\n" \ 996" mulscc %%g1,%3,%%g1\n" \ 997" mulscc %%g1,%3,%%g1\n" \ 998" mulscc %%g1,%3,%%g1\n" \ 999" mulscc %%g1,%3,%%g1\n" \ 1000" mulscc %%g1,%3,%%g1\n" \ 1001" mulscc %%g1,%3,%%g1\n" \ 1002" mulscc %%g1,%3,%%g1\n" \ 1003" mulscc %%g1,%3,%%g1\n" \ 1004" mulscc %%g1,%3,%%g1\n" \ 1005" mulscc %%g1,%3,%%g1\n" \ 1006" mulscc %%g1,0,%%g1\n" \ 1007" add %%g1,%%o5,%0\n" \ 1008" rd %%y,%1" \ 1009 : "=r" ((USItype) (w1)), \ 1010 "=r" ((USItype) (w0)) \ 1011 : "%rI" ((USItype) (u)), \ 1012 "r" ((USItype) (v)) \ 1013 : "g1", "o5" __AND_CLOBBER_CC) 1014#define UMUL_TIME 39 /* 39 instructions */ 1015/* It's quite necessary to add this much assembler for the sparc. 1016 The default udiv_qrnnd (in C) is more than 10 times slower! */ 1017#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \ 1018 __asm__ ("! Inlined udiv_qrnnd\n" \ 1019" mov 32,%%g1\n" \ 1020" subcc %1,%2,%%g0\n" \ 1021"1: bcs 5f\n" \ 1022" addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \ 1023" sub %1,%2,%1 ! this kills msb of n\n" \ 1024" addx %1,%1,%1 ! so this can't give carry\n" \ 1025" subcc %%g1,1,%%g1\n" \ 1026"2: bne 1b\n" \ 1027" subcc %1,%2,%%g0\n" \ 1028" bcs 3f\n" \ 1029" addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \ 1030" b 3f\n" \ 1031" sub %1,%2,%1 ! this kills msb of n\n" \ 1032"4: sub %1,%2,%1\n" \ 1033"5: addxcc %1,%1,%1\n" \ 1034" bcc 2b\n" \ 1035" subcc %%g1,1,%%g1\n" \ 1036"! Got carry from n. Subtract next step to cancel this carry.\n" \ 1037" bne 4b\n" \ 1038" addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \ 1039" sub %1,%2,%1\n" \ 1040"3: xnor %0,0,%0\n" \ 1041" ! End of inline udiv_qrnnd" \ 1042 : "=&r" ((USItype) (__q)), \ 1043 "=&r" ((USItype) (__r)) \ 1044 : "r" ((USItype) (__d)), \ 1045 "1" ((USItype) (__n1)), \ 1046 "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC) 1047#define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */ 1048#endif /* __sparclite__ */ 1049#endif /* __sparc_v8__ */ 1050#endif /* sparc32 */ 1051 1052#if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \ 1053 && W_TYPE_SIZE == 64 1054#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 1055 __asm__ ("addcc %r4,%5,%1\n\t" \ 1056 "add %r2,%3,%0\n\t" \ 1057 "bcs,a,pn %%xcc, 1f\n\t" \ 1058 "add %0, 1, %0\n" \ 1059 "1:" \ 1060 : "=r" ((UDItype)(sh)), \ 1061 "=&r" ((UDItype)(sl)) \ 1062 : "%rJ" ((UDItype)(ah)), \ 1063 "rI" ((UDItype)(bh)), \ 1064 "%rJ" ((UDItype)(al)), \ 1065 "rI" ((UDItype)(bl)) \ 1066 __CLOBBER_CC) 1067 1068#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 1069 __asm__ ("subcc %r4,%5,%1\n\t" \ 1070 "sub %r2,%3,%0\n\t" \ 1071 "bcs,a,pn %%xcc, 1f\n\t" \ 1072 "sub %0, 1, %0\n\t" \ 1073 "1:" \ 1074 : "=r" ((UDItype)(sh)), \ 1075 "=&r" ((UDItype)(sl)) \ 1076 : "rJ" ((UDItype)(ah)), \ 1077 "rI" ((UDItype)(bh)), \ 1078 "rJ" ((UDItype)(al)), \ 1079 "rI" ((UDItype)(bl)) \ 1080 __CLOBBER_CC) 1081 1082#define umul_ppmm(wh, wl, u, v) \ 1083 do { \ 1084 UDItype tmp1, tmp2, tmp3, tmp4; \ 1085 __asm__ __volatile__ ( \ 1086 "srl %7,0,%3\n\t" \ 1087 "mulx %3,%6,%1\n\t" \ 1088 "srlx %6,32,%2\n\t" \ 1089 "mulx %2,%3,%4\n\t" \ 1090 "sllx %4,32,%5\n\t" \ 1091 "srl %6,0,%3\n\t" \ 1092 "sub %1,%5,%5\n\t" \ 1093 "srlx %5,32,%5\n\t" \ 1094 "addcc %4,%5,%4\n\t" \ 1095 "srlx %7,32,%5\n\t" \ 1096 "mulx %3,%5,%3\n\t" \ 1097 "mulx %2,%5,%5\n\t" \ 1098 "sethi %%hi(0x80000000),%2\n\t" \ 1099 "addcc %4,%3,%4\n\t" \ 1100 "srlx %4,32,%4\n\t" \ 1101 "add %2,%2,%2\n\t" \ 1102 "movcc %%xcc,%%g0,%2\n\t" \ 1103 "addcc %5,%4,%5\n\t" \ 1104 "sllx %3,32,%3\n\t" \ 1105 "add %1,%3,%1\n\t" \ 1106 "add %5,%2,%0" \ 1107 : "=r" ((UDItype)(wh)), \ 1108 "=&r" ((UDItype)(wl)), \ 1109 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \ 1110 : "r" ((UDItype)(u)), \ 1111 "r" ((UDItype)(v)) \ 1112 __CLOBBER_CC); \ 1113 } while (0) 1114#define UMUL_TIME 96 1115#define UDIV_TIME 230 1116#endif /* sparc64 */ 1117 1118#if defined (__vax__) && W_TYPE_SIZE == 32 1119#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 1120 __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \ 1121 : "=g" ((USItype) (sh)), \ 1122 "=&g" ((USItype) (sl)) \ 1123 : "%0" ((USItype) (ah)), \ 1124 "g" ((USItype) (bh)), \ 1125 "%1" ((USItype) (al)), \ 1126 "g" ((USItype) (bl))) 1127#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 1128 __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \ 1129 : "=g" ((USItype) (sh)), \ 1130 "=&g" ((USItype) (sl)) \ 1131 : "0" ((USItype) (ah)), \ 1132 "g" ((USItype) (bh)), \ 1133 "1" ((USItype) (al)), \ 1134 "g" ((USItype) (bl))) 1135#define umul_ppmm(xh, xl, m0, m1) \ 1136 do { \ 1137 union { \ 1138 UDItype __ll; \ 1139 struct {USItype __l, __h;} __i; \ 1140 } __xx; \ 1141 USItype __m0 = (m0), __m1 = (m1); \ 1142 __asm__ ("emul %1,%2,$0,%0" \ 1143 : "=r" (__xx.__ll) \ 1144 : "g" (__m0), \ 1145 "g" (__m1)); \ 1146 (xh) = __xx.__i.__h; \ 1147 (xl) = __xx.__i.__l; \ 1148 (xh) += ((((SItype) __m0 >> 31) & __m1) \ 1149 + (((SItype) __m1 >> 31) & __m0)); \ 1150 } while (0) 1151#define sdiv_qrnnd(q, r, n1, n0, d) \ 1152 do { \ 1153 union {DItype __ll; \ 1154 struct {SItype __l, __h;} __i; \ 1155 } __xx; \ 1156 __xx.__i.__h = n1; __xx.__i.__l = n0; \ 1157 __asm__ ("ediv %3,%2,%0,%1" \ 1158 : "=g" (q), "=g" (r) \ 1159 : "g" (__xx.__ll), "g" (d)); \ 1160 } while (0) 1161#endif /* __vax__ */ 1162 1163#if defined (__z8000__) && W_TYPE_SIZE == 16 1164#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 1165 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \ 1166 : "=r" ((unsigned int)(sh)), \ 1167 "=&r" ((unsigned int)(sl)) \ 1168 : "%0" ((unsigned int)(ah)), \ 1169 "r" ((unsigned int)(bh)), \ 1170 "%1" ((unsigned int)(al)), \ 1171 "rQR" ((unsigned int)(bl))) 1172#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 1173 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \ 1174 : "=r" ((unsigned int)(sh)), \ 1175 "=&r" ((unsigned int)(sl)) \ 1176 : "0" ((unsigned int)(ah)), \ 1177 "r" ((unsigned int)(bh)), \ 1178 "1" ((unsigned int)(al)), \ 1179 "rQR" ((unsigned int)(bl))) 1180#define umul_ppmm(xh, xl, m0, m1) \ 1181 do { \ 1182 union {long int __ll; \ 1183 struct {unsigned int __h, __l;} __i; \ 1184 } __xx; \ 1185 unsigned int __m0 = (m0), __m1 = (m1); \ 1186 __asm__ ("mult %S0,%H3" \ 1187 : "=r" (__xx.__i.__h), \ 1188 "=r" (__xx.__i.__l) \ 1189 : "%1" (__m0), \ 1190 "rQR" (__m1)); \ 1191 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \ 1192 (xh) += ((((signed int) __m0 >> 15) & __m1) \ 1193 + (((signed int) __m1 >> 15) & __m0)); \ 1194 } while (0) 1195#endif /* __z8000__ */ 1196 1197#endif /* __GNUC__ */ 1198 1199/* If this machine has no inline assembler, use C macros. */ 1200 1201#if !defined (add_ssaaaa) 1202#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 1203 do { \ 1204 UWtype __x; \ 1205 __x = (al) + (bl); \ 1206 (sh) = (ah) + (bh) + (__x < (al)); \ 1207 (sl) = __x; \ 1208 } while (0) 1209#endif 1210 1211#if !defined (sub_ddmmss) 1212#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 1213 do { \ 1214 UWtype __x; \ 1215 __x = (al) - (bl); \ 1216 (sh) = (ah) - (bh) - (__x > (al)); \ 1217 (sl) = __x; \ 1218 } while (0) 1219#endif 1220 1221#if !defined (umul_ppmm) 1222#define umul_ppmm(w1, w0, u, v) \ 1223 do { \ 1224 UWtype __x0, __x1, __x2, __x3; \ 1225 UHWtype __ul, __vl, __uh, __vh; \ 1226 \ 1227 __ul = __ll_lowpart (u); \ 1228 __uh = __ll_highpart (u); \ 1229 __vl = __ll_lowpart (v); \ 1230 __vh = __ll_highpart (v); \ 1231 \ 1232 __x0 = (UWtype) __ul * __vl; \ 1233 __x1 = (UWtype) __ul * __vh; \ 1234 __x2 = (UWtype) __uh * __vl; \ 1235 __x3 = (UWtype) __uh * __vh; \ 1236 \ 1237 __x1 += __ll_highpart (__x0);/* this can't give carry */ \ 1238 __x1 += __x2; /* but this indeed can */ \ 1239 if (__x1 < __x2) /* did we get it? */ \ 1240 __x3 += __ll_B; /* yes, add it in the proper pos. */ \ 1241 \ 1242 (w1) = __x3 + __ll_highpart (__x1); \ 1243 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \ 1244 } while (0) 1245#endif 1246 1247#if !defined (__umulsidi3) 1248#define __umulsidi3(u, v) \ 1249 ({DWunion __w; \ 1250 umul_ppmm (__w.s.high, __w.s.low, u, v); \ 1251 __w.ll; }) 1252#endif 1253 1254/* Define this unconditionally, so it can be used for debugging. */ 1255#define __udiv_qrnnd_c(q, r, n1, n0, d) \ 1256 do { \ 1257 UWtype __d1, __d0, __q1, __q0; \ 1258 UWtype __r1, __r0, __m; \ 1259 __d1 = __ll_highpart (d); \ 1260 __d0 = __ll_lowpart (d); \ 1261 \ 1262 __r1 = (n1) % __d1; \ 1263 __q1 = (n1) / __d1; \ 1264 __m = (UWtype) __q1 * __d0; \ 1265 __r1 = __r1 * __ll_B | __ll_highpart (n0); \ 1266 if (__r1 < __m) \ 1267 { \ 1268 __q1--, __r1 += (d); \ 1269 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\ 1270 if (__r1 < __m) \ 1271 __q1--, __r1 += (d); \ 1272 } \ 1273 __r1 -= __m; \ 1274 \ 1275 __r0 = __r1 % __d1; \ 1276 __q0 = __r1 / __d1; \ 1277 __m = (UWtype) __q0 * __d0; \ 1278 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \ 1279 if (__r0 < __m) \ 1280 { \ 1281 __q0--, __r0 += (d); \ 1282 if (__r0 >= (d)) \ 1283 if (__r0 < __m) \ 1284 __q0--, __r0 += (d); \ 1285 } \ 1286 __r0 -= __m; \ 1287 \ 1288 (q) = (UWtype) __q1 * __ll_B | __q0; \ 1289 (r) = __r0; \ 1290 } while (0) 1291 1292/* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through 1293 __udiv_w_sdiv (defined in libgcc or elsewhere). */ 1294#if !defined (udiv_qrnnd) && defined (sdiv_qrnnd) 1295#define udiv_qrnnd(q, r, nh, nl, d) \ 1296 do { \ 1297 USItype __r; \ 1298 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \ 1299 (r) = __r; \ 1300 } while (0) 1301#endif 1302 1303/* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */ 1304#if !defined (udiv_qrnnd) 1305#define UDIV_NEEDS_NORMALIZATION 1 1306#define udiv_qrnnd __udiv_qrnnd_c 1307#endif 1308 1309#if !defined (count_leading_zeros) 1310extern const UQItype __clz_tab[]; 1311#define count_leading_zeros(count, x) \ 1312 do { \ 1313 UWtype __xr = (x); \ 1314 UWtype __a; \ 1315 \ 1316 if (W_TYPE_SIZE <= 32) \ 1317 { \ 1318 __a = __xr < ((UWtype)1<<2*__BITS4) \ 1319 ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \ 1320 : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \ 1321 } \ 1322 else \ 1323 { \ 1324 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \ 1325 if (((__xr >> __a) & 0xff) != 0) \ 1326 break; \ 1327 } \ 1328 \ 1329 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \ 1330 } while (0) 1331#define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE 1332#endif 1333 1334#if !defined (count_trailing_zeros) 1335/* Define count_trailing_zeros using count_leading_zeros. The latter might be 1336 defined in asm, but if it is not, the C version above is good enough. */ 1337#define count_trailing_zeros(count, x) \ 1338 do { \ 1339 UWtype __ctz_x = (x); \ 1340 UWtype __ctz_c; \ 1341 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \ 1342 (count) = W_TYPE_SIZE - 1 - __ctz_c; \ 1343 } while (0) 1344#endif 1345 1346#ifndef UDIV_NEEDS_NORMALIZATION 1347#define UDIV_NEEDS_NORMALIZATION 0 1348#endif 1349