1/*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * @(#)fpu_emu.h 8.1 (Berkeley) 6/11/93 36 * $NetBSD: fpu_emu.h,v 1.4 2000/08/03 18:32:07 eeh Exp $ 37 * $FreeBSD: head/lib/libc/sparc64/fpu/fpu_emu.h 326025 2017-11-20 19:49:47Z pfg $ 38 */ 39 40/* 41 * Floating point emulator (tailored for SPARC, but structurally 42 * machine-independent). 43 * 44 * Floating point numbers are carried around internally in an `expanded' 45 * or `unpacked' form consisting of: 46 * - sign 47 * - unbiased exponent 48 * - mantissa (`1.' + 112-bit fraction + guard + round) 49 * - sticky bit 50 * Any implied `1' bit is inserted, giving a 113-bit mantissa that is 51 * always nonzero. Additional low-order `guard' and `round' bits are 52 * scrunched in, making the entire mantissa 115 bits long. This is divided 53 * into four 32-bit words, with `spare' bits left over in the upper part 54 * of the top word (the high bits of fp_mant[0]). An internal `exploded' 55 * number is thus kept within the half-open interval [1.0,2.0) (but see 56 * the `number classes' below). This holds even for denormalized numbers: 57 * when we explode an external denorm, we normalize it, introducing low-order 58 * zero bits, so that the rest of the code always sees normalized values. 59 * 60 * Note that a number of our algorithms use the `spare' bits at the top. 61 * The most demanding algorithm---the one for sqrt---depends on two such 62 * bits, so that it can represent values up to (but not including) 8.0, 63 * and then it needs a carry on top of that, so that we need three `spares'. 64 * 65 * The sticky-word is 32 bits so that we can use `OR' operators to goosh 66 * whole words from the mantissa into it. 67 * 68 * All operations are done in this internal extended precision. According 69 * to Hennesey & Patterson, Appendix A, rounding can be repeated---that is, 70 * it is OK to do a+b in extended precision and then round the result to 71 * single precision---provided single, double, and extended precisions are 72 * `far enough apart' (they always are), but we will try to avoid any such 73 * extra work where possible. 74 */ 75 76#ifndef _SPARC64_FPU_FPU_EMU_H_ 77#define _SPARC64_FPU_FPU_EMU_H_ 78 79#include <stdint.h> 80 81#include "fpu_reg.h" 82 83struct fpn { 84 int fp_class; /* see below */ 85 int fp_sign; /* 0 => positive, 1 => negative */ 86 int fp_exp; /* exponent (unbiased) */ 87 int fp_sticky; /* nonzero bits lost at right end */ 88 uint32_t fp_mant[4]; /* 115-bit mantissa */ 89}; 90 91#define FP_NMANT 115 /* total bits in mantissa (incl g,r) */ 92#define FP_NG 2 /* number of low-order guard bits */ 93#define FP_LG ((FP_NMANT - 1) & 31) /* log2(1.0) for fp_mant[0] */ 94#define FP_LG2 ((FP_NMANT - 1) & 63) /* log2(1.0) for fp_mant[0] and fp_mant[1] */ 95#define FP_QUIETBIT (1 << (FP_LG - 1)) /* Quiet bit in NaNs (0.5) */ 96#define FP_1 (1 << FP_LG) /* 1.0 in fp_mant[0] */ 97#define FP_2 (1 << (FP_LG + 1)) /* 2.0 in fp_mant[0] */ 98 99/* 100 * Number classes. Since zero, Inf, and NaN cannot be represented using 101 * the above layout, we distinguish these from other numbers via a class. 102 * In addition, to make computation easier and to follow Appendix N of 103 * the SPARC Version 8 standard, we give each kind of NaN a separate class. 104 */ 105#define FPC_SNAN -2 /* signalling NaN (sign irrelevant) */ 106#define FPC_QNAN -1 /* quiet NaN (sign irrelevant) */ 107#define FPC_ZERO 0 /* zero (sign matters) */ 108#define FPC_NUM 1 /* number (sign matters) */ 109#define FPC_INF 2 /* infinity (sign matters) */ 110 111#define ISNAN(fp) ((fp)->fp_class < 0) 112#define ISZERO(fp) ((fp)->fp_class == 0) 113#define ISINF(fp) ((fp)->fp_class == FPC_INF) 114 115/* 116 * ORDER(x,y) `sorts' a pair of `fpn *'s so that the right operand (y) points 117 * to the `more significant' operand for our purposes. Appendix N says that 118 * the result of a computation involving two numbers are: 119 * 120 * If both are SNaN: operand 2, converted to Quiet 121 * If only one is SNaN: the SNaN operand, converted to Quiet 122 * If both are QNaN: operand 2 123 * If only one is QNaN: the QNaN operand 124 * 125 * In addition, in operations with an Inf operand, the result is usually 126 * Inf. The class numbers are carefully arranged so that if 127 * (unsigned)class(op1) > (unsigned)class(op2) 128 * then op1 is the one we want; otherwise op2 is the one we want. 129 */ 130#define ORDER(x, y) { \ 131 if ((uint32_t)(x)->fp_class > (uint32_t)(y)->fp_class) \ 132 SWAP(x, y); \ 133} 134#define SWAP(x, y) { \ 135 register struct fpn *swap; \ 136 swap = (x), (x) = (y), (y) = swap; \ 137} 138 139/* 140 * Floating point operand types. FTYPE_LNG is syntethic (it does not occur in 141 * instructions). 142 */ 143#define FTYPE_INT INSFP_i 144#define FTYPE_SNG INSFP_s 145#define FTYPE_DBL INSFP_d 146#define FTYPE_EXT INSFP_q 147#define FTYPE_LNG 4 148 149/* 150 * Emulator state. 151 */ 152struct fpemu { 153 uint64_t fe_fsr; /* fsr copy (modified during op) */ 154 int fe_cx; /* exceptions */ 155 int pad; /* align access to following fields */ 156 struct fpn fe_f1; /* operand 1 */ 157 struct fpn fe_f2; /* operand 2, if required */ 158 struct fpn fe_f3; /* available storage for result */ 159}; 160 161/* 162 * Arithmetic functions. 163 * Each of these may modify its inputs (f1,f2) and/or the temporary. 164 * Each returns a pointer to the result and/or sets exceptions. 165 */ 166#define __fpu_sub(fe) (ISNAN(&(fe)->fe_f2) ? 0 : ((fe)->fe_f2.fp_sign ^= 1), \ 167 __fpu_add(fe)) 168 169#ifdef FPU_DEBUG 170#define FPE_INSN 0x1 171#define FPE_REG 0x2 172extern int __fpe_debug; 173void __fpu_dumpfpn(struct fpn *); 174#define DPRINTF(x, y) if (__fpe_debug & (x)) printf y 175#define DUMPFPN(x, f) if (__fpe_debug & (x)) __fpu_dumpfpn((f)) 176#else 177#define DPRINTF(x, y) 178#define DUMPFPN(x, f) 179#endif 180 181#endif /* !_SPARC64_FPU_FPU_EXTERN_H_ */ 182