1/* 2 * Copyright 2010, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT license. 4 * 5 * Author: 6 * Fran��ois Revol, revol@free.fr. 7 * 8 */ 9#ifndef _AMICALLS_H 10#define _AMICALLS_H 11 12 13#ifdef __cplusplus 14extern "C" { 15#endif 16 17#ifndef __ASSEMBLER__ 18#include <OS.h> 19#include <SupportDefs.h> 20 21/* 22 General macros for Amiga function calls. Not all the possibilities have 23 been created - only the ones which exist in OS 3.1. Third party libraries 24 and future versions of AmigaOS will maybe need some new ones... 25 26 LPX - functions that take X arguments. 27 28 Modifiers (variations are possible): 29 NR - no return (void), 30 A4, A5 - "a4" or "a5" is used as one of the arguments, 31 UB - base will be given explicitly by user (see cia.resource). 32 FP - one of the parameters has type "pointer to function". 33 34 "bt" arguments are not used - they are provided for backward compatibility 35 only. 36*/ 37/* those were taken from fd2pragma, but no copyright seems to be claimed on them */ 38 39#define LP0(offs, rt, name, bt, bn) \ 40({ \ 41 ({ \ 42 register int _d1 __asm("d1"); \ 43 register int _a0 __asm("a0"); \ 44 register int _a1 __asm("a1"); \ 45 register rt _##name##_re __asm("d0"); \ 46 void *const _##name##_bn = (bn); \ 47 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 48 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 49 : [libbase] "a" (_##name##_bn) \ 50 : "fp0", "fp1", "cc", "memory"); \ 51 _##name##_re; \ 52 }); \ 53}) 54 55#define LP0NR(offs, name, bt, bn) \ 56({ \ 57 { \ 58 register int _d0 __asm("d0"); \ 59 register int _d1 __asm("d1"); \ 60 register int _a0 __asm("a0"); \ 61 register int _a1 __asm("a1"); \ 62 void *const _##name##_bn = (bn); \ 63 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 64 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 65 : [libbase] "a" (_##name##_bn) \ 66 : "fp0", "fp1", "cc", "memory"); \ 67 } \ 68}) 69 70#define LP1(offs, rt, name, t1, v1, r1, bt, bn) \ 71({ \ 72 t1 _##name##_v1 = (v1); \ 73 ({ \ 74 register int _d1 __asm("d1"); \ 75 register int _a0 __asm("a0"); \ 76 register int _a1 __asm("a1"); \ 77 register rt _##name##_re __asm("d0"); \ 78 void *const _##name##_bn = (bn); \ 79 register t1 _n1 __asm(#r1) = _##name##_v1; \ 80 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 81 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 82 : [libbase] "a" (_##name##_bn), "rf"(_n1) \ 83 : "fp0", "fp1", "cc", "memory"); \ 84 _##name##_re; \ 85 }); \ 86}) 87 88#define LP1NR(offs, name, t1, v1, r1, bt, bn) \ 89({ \ 90 t1 _##name##_v1 = (v1); \ 91 { \ 92 register int _d0 __asm("d0"); \ 93 register int _d1 __asm("d1"); \ 94 register int _a0 __asm("a0"); \ 95 register int _a1 __asm("a1"); \ 96 void *const _##name##_bn = (bn); \ 97 register t1 _n1 __asm(#r1) = _##name##_v1; \ 98 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 99 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 100 : [libbase] "a" (_##name##_bn), "rf"(_n1) \ 101 : "fp0", "fp1", "cc", "memory"); \ 102 } \ 103}) 104 105/* Only graphics.library/AttemptLockLayerRom() */ 106#define LP1A5(offs, rt, name, t1, v1, r1, bt, bn) \ 107({ \ 108 t1 _##name##_v1 = (v1); \ 109 ({ \ 110 register int _d1 __asm("d1"); \ 111 register int _a0 __asm("a0"); \ 112 register int _a1 __asm("a1"); \ 113 register rt _##name##_re __asm("d0"); \ 114 void *const _##name##_bn = (bn); \ 115 register t1 _n1 __asm(#r1) = _##name##_v1; \ 116 __asm volatile ("exg d7,a5\n\tmove.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6\n\texg d7,a5" \ 117 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 118 : [libbase] "a" (_##name##_bn), "rf"(_n1) \ 119 : "fp0", "fp1", "cc", "memory"); \ 120 _##name##_re; \ 121 }); \ 122}) 123 124/* Only graphics.library/LockLayerRom() and graphics.library/UnlockLayerRom() */ 125#define LP1NRA5(offs, name, t1, v1, r1, bt, bn) \ 126({ \ 127 t1 _##name##_v1 = (v1); \ 128 { \ 129 register int _d0 __asm("d0"); \ 130 register int _d1 __asm("d1"); \ 131 register int _a0 __asm("a0"); \ 132 register int _a1 __asm("a1"); \ 133 void *const _##name##_bn = (bn); \ 134 register t1 _n1 __asm(#r1) = _##name##_v1; \ 135 __asm volatile ("exg d7,a5\n\tmove.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6\n\texg d7,a5" \ 136 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 137 : [libbase] "a" (_##name##_bn), "rf"(_n1) \ 138 : "fp0", "fp1", "cc", "memory"); \ 139 } \ 140}) 141 142/* Only exec.library/Supervisor() */ 143#define LP1A5FP(offs, rt, name, t1, v1, r1, bt, bn, fpt) \ 144({ \ 145 typedef fpt; \ 146 t1 _##name##_v1 = (v1); \ 147 ({ \ 148 register int _d1 __asm("d1"); \ 149 register int _a0 __asm("a0"); \ 150 register int _a1 __asm("a1"); \ 151 register rt _##name##_re __asm("d0"); \ 152 void *const _##name##_bn = (bn); \ 153 register t1 _n1 __asm(#r1) = _##name##_v1; \ 154 __asm volatile ("exg d7,a5\n\tmove.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6\n\texg d7,a5" \ 155 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 156 : [libbase] "a" (_##name##_bn), "rf"(_n1) \ 157 : "fp0", "fp1", "cc", "memory"); \ 158 _##name##_re; \ 159 }); \ 160}) 161 162#define LP2(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn) \ 163({ \ 164 t1 _##name##_v1 = (v1); \ 165 t2 _##name##_v2 = (v2); \ 166 ({ \ 167 register int _d1 __asm("d1"); \ 168 register int _a0 __asm("a0"); \ 169 register int _a1 __asm("a1"); \ 170 register rt _##name##_re __asm("d0"); \ 171 void *const _##name##_bn = (bn); \ 172 register t1 _n1 __asm(#r1) = _##name##_v1; \ 173 register t2 _n2 __asm(#r2) = _##name##_v2; \ 174 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 175 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 176 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2) \ 177 : "fp0", "fp1", "cc", "memory"); \ 178 _##name##_re; \ 179 }); \ 180}) 181 182#define LP2NR(offs, name, t1, v1, r1, t2, v2, r2, bt, bn) \ 183({ \ 184 t1 _##name##_v1 = (v1); \ 185 t2 _##name##_v2 = (v2); \ 186 { \ 187 register int _d0 __asm("d0"); \ 188 register int _d1 __asm("d1"); \ 189 register int _a0 __asm("a0"); \ 190 register int _a1 __asm("a1"); \ 191 void *const _##name##_bn = (bn); \ 192 register t1 _n1 __asm(#r1) = _##name##_v1; \ 193 register t2 _n2 __asm(#r2) = _##name##_v2; \ 194 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 195 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 196 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2) \ 197 : "fp0", "fp1", "cc", "memory"); \ 198 } \ 199}) 200 201/* Only cia.resource/AbleICR() and cia.resource/SetICR() */ 202#define LP2UB(offs, rt, name, t1, v1, r1, t2, v2, r2) \ 203({ \ 204 t1 _##name##_v1 = (v1); \ 205 t2 _##name##_v2 = (v2); \ 206 ({ \ 207 register int _d1 __asm("d1"); \ 208 register int _a0 __asm("a0"); \ 209 register int _a1 __asm("a1"); \ 210 register rt _##name##_re __asm("d0"); \ 211 register t1 _n1 __asm(#r1) = _##name##_v1; \ 212 register t2 _n2 __asm(#r2) = _##name##_v2; \ 213 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 214 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 215 : "r"(_n1), "rf"(_n2) \ 216 : "fp0", "fp1", "cc", "memory"); \ 217 _##name##_re; \ 218 }); \ 219}) 220 221/* Only dos.library/InternalUnLoadSeg() */ 222#define LP2FP(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn, fpt) \ 223({ \ 224 typedef fpt; \ 225 t1 _##name##_v1 = (v1); \ 226 t2 _##name##_v2 = (v2); \ 227 ({ \ 228 register int _d1 __asm("d1"); \ 229 register int _a0 __asm("a0"); \ 230 register int _a1 __asm("a1"); \ 231 register rt _##name##_re __asm("d0"); \ 232 void *const _##name##_bn = (bn); \ 233 register t1 _n1 __asm(#r1) = _##name##_v1; \ 234 register t2 _n2 __asm(#r2) = _##name##_v2; \ 235 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 236 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 237 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2) \ 238 : "fp0", "fp1", "cc", "memory"); \ 239 _##name##_re; \ 240 }); \ 241}) 242 243#define LP3(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \ 244({ \ 245 t1 _##name##_v1 = (v1); \ 246 t2 _##name##_v2 = (v2); \ 247 t3 _##name##_v3 = (v3); \ 248 ({ \ 249 register int _d1 __asm("d1"); \ 250 register int _a0 __asm("a0"); \ 251 register int _a1 __asm("a1"); \ 252 register rt _##name##_re __asm("d0"); \ 253 void *const _##name##_bn = (bn); \ 254 register t1 _n1 __asm(#r1) = _##name##_v1; \ 255 register t2 _n2 __asm(#r2) = _##name##_v2; \ 256 register t3 _n3 __asm(#r3) = _##name##_v3; \ 257 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 258 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 259 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ 260 : "fp0", "fp1", "cc", "memory"); \ 261 _##name##_re; \ 262 }); \ 263}) 264 265#define LP3NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \ 266({ \ 267 t1 _##name##_v1 = (v1); \ 268 t2 _##name##_v2 = (v2); \ 269 t3 _##name##_v3 = (v3); \ 270 { \ 271 register int _d0 __asm("d0"); \ 272 register int _d1 __asm("d1"); \ 273 register int _a0 __asm("a0"); \ 274 register int _a1 __asm("a1"); \ 275 void *const _##name##_bn = (bn); \ 276 register t1 _n1 __asm(#r1) = _##name##_v1; \ 277 register t2 _n2 __asm(#r2) = _##name##_v2; \ 278 register t3 _n3 __asm(#r3) = _##name##_v3; \ 279 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 280 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 281 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ 282 : "fp0", "fp1", "cc", "memory"); \ 283 } \ 284}) 285 286/* Only cia.resource/AddICRVector() */ 287#define LP3UB(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3) \ 288({ \ 289 t1 _##name##_v1 = (v1); \ 290 t2 _##name##_v2 = (v2); \ 291 t3 _##name##_v3 = (v3); \ 292 ({ \ 293 register int _d1 __asm("d1"); \ 294 register int _a0 __asm("a0"); \ 295 register int _a1 __asm("a1"); \ 296 register rt _##name##_re __asm("d0"); \ 297 register t1 _n1 __asm(#r1) = _##name##_v1; \ 298 register t2 _n2 __asm(#r2) = _##name##_v2; \ 299 register t3 _n3 __asm(#r3) = _##name##_v3; \ 300 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 301 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 302 : "r"(_n1), "rf"(_n2), "rf"(_n3) \ 303 : "fp0", "fp1", "cc", "memory"); \ 304 _##name##_re; \ 305 }); \ 306}) 307 308/* Only cia.resource/RemICRVector() */ 309#define LP3NRUB(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3) \ 310({ \ 311 t1 _##name##_v1 = (v1); \ 312 t2 _##name##_v2 = (v2); \ 313 t3 _##name##_v3 = (v3); \ 314 { \ 315 register int _d0 __asm("d0"); \ 316 register int _d1 __asm("d1"); \ 317 register int _a0 __asm("a0"); \ 318 register int _a1 __asm("a1"); \ 319 register t1 _n1 __asm(#r1) = _##name##_v1; \ 320 register t2 _n2 __asm(#r2) = _##name##_v2; \ 321 register t3 _n3 __asm(#r3) = _##name##_v3; \ 322 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 323 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 324 : "r"(_n1), "rf"(_n2), "rf"(_n3) \ 325 : "fp0", "fp1", "cc", "memory"); \ 326 } \ 327}) 328 329/* Only exec.library/SetFunction() */ 330#define LP3FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt) \ 331({ \ 332 typedef fpt; \ 333 t1 _##name##_v1 = (v1); \ 334 t2 _##name##_v2 = (v2); \ 335 t3 _##name##_v3 = (v3); \ 336 ({ \ 337 register int _d1 __asm("d1"); \ 338 register int _a0 __asm("a0"); \ 339 register int _a1 __asm("a1"); \ 340 register rt _##name##_re __asm("d0"); \ 341 void *const _##name##_bn = (bn); \ 342 register t1 _n1 __asm(#r1) = _##name##_v1; \ 343 register t2 _n2 __asm(#r2) = _##name##_v2; \ 344 register t3 _n3 __asm(#r3) = _##name##_v3; \ 345 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 346 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 347 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ 348 : "fp0", "fp1", "cc", "memory"); \ 349 _##name##_re; \ 350 }); \ 351}) 352 353/* Only graphics.library/SetCollision() */ 354#define LP3NRFP(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt) \ 355({ \ 356 typedef fpt; \ 357 t1 _##name##_v1 = (v1); \ 358 t2 _##name##_v2 = (v2); \ 359 t3 _##name##_v3 = (v3); \ 360 { \ 361 register int _d0 __asm("d0"); \ 362 register int _d1 __asm("d1"); \ 363 register int _a0 __asm("a0"); \ 364 register int _a1 __asm("a1"); \ 365 void *const _##name##_bn = (bn); \ 366 register t1 _n1 __asm(#r1) = _##name##_v1; \ 367 register t2 _n2 __asm(#r2) = _##name##_v2; \ 368 register t3 _n3 __asm(#r3) = _##name##_v3; \ 369 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 370 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 371 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ 372 : "fp0", "fp1", "cc", "memory"); \ 373 } \ 374}) 375 376#define LP4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \ 377({ \ 378 t1 _##name##_v1 = (v1); \ 379 t2 _##name##_v2 = (v2); \ 380 t3 _##name##_v3 = (v3); \ 381 t4 _##name##_v4 = (v4); \ 382 ({ \ 383 register int _d1 __asm("d1"); \ 384 register int _a0 __asm("a0"); \ 385 register int _a1 __asm("a1"); \ 386 register rt _##name##_re __asm("d0"); \ 387 void *const _##name##_bn = (bn); \ 388 register t1 _n1 __asm(#r1) = _##name##_v1; \ 389 register t2 _n2 __asm(#r2) = _##name##_v2; \ 390 register t3 _n3 __asm(#r3) = _##name##_v3; \ 391 register t4 _n4 __asm(#r4) = _##name##_v4; \ 392 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 393 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 394 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \ 395 : "fp0", "fp1", "cc", "memory"); \ 396 _##name##_re; \ 397 }); \ 398}) 399 400#define LP4NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \ 401({ \ 402 t1 _##name##_v1 = (v1); \ 403 t2 _##name##_v2 = (v2); \ 404 t3 _##name##_v3 = (v3); \ 405 t4 _##name##_v4 = (v4); \ 406 { \ 407 register int _d0 __asm("d0"); \ 408 register int _d1 __asm("d1"); \ 409 register int _a0 __asm("a0"); \ 410 register int _a1 __asm("a1"); \ 411 void *const _##name##_bn = (bn); \ 412 register t1 _n1 __asm(#r1) = _##name##_v1; \ 413 register t2 _n2 __asm(#r2) = _##name##_v2; \ 414 register t3 _n3 __asm(#r3) = _##name##_v3; \ 415 register t4 _n4 __asm(#r4) = _##name##_v4; \ 416 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 417 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 418 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \ 419 : "fp0", "fp1", "cc", "memory"); \ 420 } \ 421}) 422 423/* Only exec.library/RawDoFmt() */ 424#define LP4FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn, fpt) \ 425({ \ 426 typedef fpt; \ 427 t1 _##name##_v1 = (v1); \ 428 t2 _##name##_v2 = (v2); \ 429 t3 _##name##_v3 = (v3); \ 430 t4 _##name##_v4 = (v4); \ 431 ({ \ 432 register int _d1 __asm("d1"); \ 433 register int _a0 __asm("a0"); \ 434 register int _a1 __asm("a1"); \ 435 register rt _##name##_re __asm("d0"); \ 436 void *const _##name##_bn = (bn); \ 437 register t1 _n1 __asm(#r1) = _##name##_v1; \ 438 register t2 _n2 __asm(#r2) = _##name##_v2; \ 439 register t3 _n3 __asm(#r3) = _##name##_v3; \ 440 register t4 _n4 __asm(#r4) = _##name##_v4; \ 441 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 442 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 443 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \ 444 : "fp0", "fp1", "cc", "memory"); \ 445 _##name##_re; \ 446 }); \ 447}) 448 449#define LP5(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \ 450({ \ 451 t1 _##name##_v1 = (v1); \ 452 t2 _##name##_v2 = (v2); \ 453 t3 _##name##_v3 = (v3); \ 454 t4 _##name##_v4 = (v4); \ 455 t5 _##name##_v5 = (v5); \ 456 ({ \ 457 register int _d1 __asm("d1"); \ 458 register int _a0 __asm("a0"); \ 459 register int _a1 __asm("a1"); \ 460 register rt _##name##_re __asm("d0"); \ 461 void *const _##name##_bn = (bn); \ 462 register t1 _n1 __asm(#r1) = _##name##_v1; \ 463 register t2 _n2 __asm(#r2) = _##name##_v2; \ 464 register t3 _n3 __asm(#r3) = _##name##_v3; \ 465 register t4 _n4 __asm(#r4) = _##name##_v4; \ 466 register t5 _n5 __asm(#r5) = _##name##_v5; \ 467 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 468 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 469 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ 470 : "fp0", "fp1", "cc", "memory"); \ 471 _##name##_re; \ 472 }); \ 473}) 474 475#define LP5NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \ 476({ \ 477 t1 _##name##_v1 = (v1); \ 478 t2 _##name##_v2 = (v2); \ 479 t3 _##name##_v3 = (v3); \ 480 t4 _##name##_v4 = (v4); \ 481 t5 _##name##_v5 = (v5); \ 482 { \ 483 register int _d0 __asm("d0"); \ 484 register int _d1 __asm("d1"); \ 485 register int _a0 __asm("a0"); \ 486 register int _a1 __asm("a1"); \ 487 void *const _##name##_bn = (bn); \ 488 register t1 _n1 __asm(#r1) = _##name##_v1; \ 489 register t2 _n2 __asm(#r2) = _##name##_v2; \ 490 register t3 _n3 __asm(#r3) = _##name##_v3; \ 491 register t4 _n4 __asm(#r4) = _##name##_v4; \ 492 register t5 _n5 __asm(#r5) = _##name##_v5; \ 493 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 494 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 495 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ 496 : "fp0", "fp1", "cc", "memory"); \ 497 } \ 498}) 499 500/* Only exec.library/MakeLibrary() */ 501#define LP5FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn, fpt) \ 502({ \ 503 typedef fpt; \ 504 t1 _##name##_v1 = (v1); \ 505 t2 _##name##_v2 = (v2); \ 506 t3 _##name##_v3 = (v3); \ 507 t4 _##name##_v4 = (v4); \ 508 t5 _##name##_v5 = (v5); \ 509 ({ \ 510 register int _d1 __asm("d1"); \ 511 register int _a0 __asm("a0"); \ 512 register int _a1 __asm("a1"); \ 513 register rt _##name##_re __asm("d0"); \ 514 void *const _##name##_bn = (bn); \ 515 register t1 _n1 __asm(#r1) = _##name##_v1; \ 516 register t2 _n2 __asm(#r2) = _##name##_v2; \ 517 register t3 _n3 __asm(#r3) = _##name##_v3; \ 518 register t4 _n4 __asm(#r4) = _##name##_v4; \ 519 register t5 _n5 __asm(#r5) = _##name##_v5; \ 520 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 521 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 522 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ 523 : "fp0", "fp1", "cc", "memory"); \ 524 _##name##_re; \ 525 }); \ 526}) 527 528/* Only reqtools.library/XXX() */ 529#define LP5A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \ 530({ \ 531 t1 _##name##_v1 = (v1); \ 532 t2 _##name##_v2 = (v2); \ 533 t3 _##name##_v3 = (v3); \ 534 t4 _##name##_v4 = (v4); \ 535 t5 _##name##_v5 = (v5); \ 536 ({ \ 537 register int _d1 __asm("d1"); \ 538 register int _a0 __asm("a0"); \ 539 register int _a1 __asm("a1"); \ 540 register rt _##name##_re __asm("d0"); \ 541 void *const _##name##_bn = (bn); \ 542 register t1 _n1 __asm(#r1) = _##name##_v1; \ 543 register t2 _n2 __asm(#r2) = _##name##_v2; \ 544 register t3 _n3 __asm(#r3) = _##name##_v3; \ 545 register t4 _n4 __asm(#r4) = _##name##_v4; \ 546 register t5 _n5 __asm(#r5) = _##name##_v5; \ 547 __asm volatile ("exg d7,a4\n\tmove.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6\n\texg d7,a4" \ 548 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 549 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ 550 : "fp0", "fp1", "cc", "memory"); \ 551 _##name##_re; \ 552 }); \ 553}) 554 555#define LP6(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \ 556({ \ 557 t1 _##name##_v1 = (v1); \ 558 t2 _##name##_v2 = (v2); \ 559 t3 _##name##_v3 = (v3); \ 560 t4 _##name##_v4 = (v4); \ 561 t5 _##name##_v5 = (v5); \ 562 t6 _##name##_v6 = (v6); \ 563 ({ \ 564 register int _d1 __asm("d1"); \ 565 register int _a0 __asm("a0"); \ 566 register int _a1 __asm("a1"); \ 567 register rt _##name##_re __asm("d0"); \ 568 void *const _##name##_bn = (bn); \ 569 register t1 _n1 __asm(#r1) = _##name##_v1; \ 570 register t2 _n2 __asm(#r2) = _##name##_v2; \ 571 register t3 _n3 __asm(#r3) = _##name##_v3; \ 572 register t4 _n4 __asm(#r4) = _##name##_v4; \ 573 register t5 _n5 __asm(#r5) = _##name##_v5; \ 574 register t6 _n6 __asm(#r6) = _##name##_v6; \ 575 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 576 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 577 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \ 578 : "fp0", "fp1", "cc", "memory"); \ 579 _##name##_re; \ 580 }); \ 581}) 582 583#define LP6NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \ 584({ \ 585 t1 _##name##_v1 = (v1); \ 586 t2 _##name##_v2 = (v2); \ 587 t3 _##name##_v3 = (v3); \ 588 t4 _##name##_v4 = (v4); \ 589 t5 _##name##_v5 = (v5); \ 590 t6 _##name##_v6 = (v6); \ 591 { \ 592 register int _d0 __asm("d0"); \ 593 register int _d1 __asm("d1"); \ 594 register int _a0 __asm("a0"); \ 595 register int _a1 __asm("a1"); \ 596 void *const _##name##_bn = (bn); \ 597 register t1 _n1 __asm(#r1) = _##name##_v1; \ 598 register t2 _n2 __asm(#r2) = _##name##_v2; \ 599 register t3 _n3 __asm(#r3) = _##name##_v3; \ 600 register t4 _n4 __asm(#r4) = _##name##_v4; \ 601 register t5 _n5 __asm(#r5) = _##name##_v5; \ 602 register t6 _n6 __asm(#r6) = _##name##_v6; \ 603 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 604 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 605 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \ 606 : "fp0", "fp1", "cc", "memory"); \ 607 } \ 608}) 609 610#define LP7(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \ 611({ \ 612 t1 _##name##_v1 = (v1); \ 613 t2 _##name##_v2 = (v2); \ 614 t3 _##name##_v3 = (v3); \ 615 t4 _##name##_v4 = (v4); \ 616 t5 _##name##_v5 = (v5); \ 617 t6 _##name##_v6 = (v6); \ 618 t7 _##name##_v7 = (v7); \ 619 ({ \ 620 register int _d1 __asm("d1"); \ 621 register int _a0 __asm("a0"); \ 622 register int _a1 __asm("a1"); \ 623 register rt _##name##_re __asm("d0"); \ 624 void *const _##name##_bn = (bn); \ 625 register t1 _n1 __asm(#r1) = _##name##_v1; \ 626 register t2 _n2 __asm(#r2) = _##name##_v2; \ 627 register t3 _n3 __asm(#r3) = _##name##_v3; \ 628 register t4 _n4 __asm(#r4) = _##name##_v4; \ 629 register t5 _n5 __asm(#r5) = _##name##_v5; \ 630 register t6 _n6 __asm(#r6) = _##name##_v6; \ 631 register t7 _n7 __asm(#r7) = _##name##_v7; \ 632 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 633 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 634 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \ 635 : "fp0", "fp1", "cc", "memory"); \ 636 _##name##_re; \ 637 }); \ 638}) 639 640#define LP7NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \ 641({ \ 642 t1 _##name##_v1 = (v1); \ 643 t2 _##name##_v2 = (v2); \ 644 t3 _##name##_v3 = (v3); \ 645 t4 _##name##_v4 = (v4); \ 646 t5 _##name##_v5 = (v5); \ 647 t6 _##name##_v6 = (v6); \ 648 t7 _##name##_v7 = (v7); \ 649 { \ 650 register int _d0 __asm("d0"); \ 651 register int _d1 __asm("d1"); \ 652 register int _a0 __asm("a0"); \ 653 register int _a1 __asm("a1"); \ 654 void *const _##name##_bn = (bn); \ 655 register t1 _n1 __asm(#r1) = _##name##_v1; \ 656 register t2 _n2 __asm(#r2) = _##name##_v2; \ 657 register t3 _n3 __asm(#r3) = _##name##_v3; \ 658 register t4 _n4 __asm(#r4) = _##name##_v4; \ 659 register t5 _n5 __asm(#r5) = _##name##_v5; \ 660 register t6 _n6 __asm(#r6) = _##name##_v6; \ 661 register t7 _n7 __asm(#r7) = _##name##_v7; \ 662 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 663 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 664 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \ 665 : "fp0", "fp1", "cc", "memory"); \ 666 } \ 667}) 668 669/* Only workbench.library/AddAppIconA() */ 670#define LP7A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \ 671({ \ 672 t1 _##name##_v1 = (v1); \ 673 t2 _##name##_v2 = (v2); \ 674 t3 _##name##_v3 = (v3); \ 675 t4 _##name##_v4 = (v4); \ 676 t5 _##name##_v5 = (v5); \ 677 t6 _##name##_v6 = (v6); \ 678 t7 _##name##_v7 = (v7); \ 679 ({ \ 680 register int _d1 __asm("d1"); \ 681 register int _a0 __asm("a0"); \ 682 register int _a1 __asm("a1"); \ 683 register rt _##name##_re __asm("d0"); \ 684 void *const _##name##_bn = (bn); \ 685 register t1 _n1 __asm(#r1) = _##name##_v1; \ 686 register t2 _n2 __asm(#r2) = _##name##_v2; \ 687 register t3 _n3 __asm(#r3) = _##name##_v3; \ 688 register t4 _n4 __asm(#r4) = _##name##_v4; \ 689 register t5 _n5 __asm(#r5) = _##name##_v5; \ 690 register t6 _n6 __asm(#r6) = _##name##_v6; \ 691 register t7 _n7 __asm(#r7) = _##name##_v7; \ 692 __asm volatile ("exg d7,a4\n\tmove.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6\n\texg d7,a4" \ 693 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 694 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \ 695 : "fp0", "fp1", "cc", "memory"); \ 696 _##name##_re; \ 697 }); \ 698}) 699 700/* Would you believe that there really are beasts that need more than 7 701 arguments? :-) */ 702 703/* For example intuition.library/AutoRequest() */ 704#define LP8(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \ 705({ \ 706 t1 _##name##_v1 = (v1); \ 707 t2 _##name##_v2 = (v2); \ 708 t3 _##name##_v3 = (v3); \ 709 t4 _##name##_v4 = (v4); \ 710 t5 _##name##_v5 = (v5); \ 711 t6 _##name##_v6 = (v6); \ 712 t7 _##name##_v7 = (v7); \ 713 t8 _##name##_v8 = (v8); \ 714 ({ \ 715 register int _d1 __asm("d1"); \ 716 register int _a0 __asm("a0"); \ 717 register int _a1 __asm("a1"); \ 718 register rt _##name##_re __asm("d0"); \ 719 void *const _##name##_bn = (bn); \ 720 register t1 _n1 __asm(#r1) = _##name##_v1; \ 721 register t2 _n2 __asm(#r2) = _##name##_v2; \ 722 register t3 _n3 __asm(#r3) = _##name##_v3; \ 723 register t4 _n4 __asm(#r4) = _##name##_v4; \ 724 register t5 _n5 __asm(#r5) = _##name##_v5; \ 725 register t6 _n6 __asm(#r6) = _##name##_v6; \ 726 register t7 _n7 __asm(#r7) = _##name##_v7; \ 727 register t8 _n8 __asm(#r8) = _##name##_v8; \ 728 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 729 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 730 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \ 731 : "fp0", "fp1", "cc", "memory"); \ 732 _##name##_re; \ 733 }); \ 734}) 735 736/* For example intuition.library/ModifyProp() */ 737#define LP8NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \ 738({ \ 739 t1 _##name##_v1 = (v1); \ 740 t2 _##name##_v2 = (v2); \ 741 t3 _##name##_v3 = (v3); \ 742 t4 _##name##_v4 = (v4); \ 743 t5 _##name##_v5 = (v5); \ 744 t6 _##name##_v6 = (v6); \ 745 t7 _##name##_v7 = (v7); \ 746 t8 _##name##_v8 = (v8); \ 747 { \ 748 register int _d0 __asm("d0"); \ 749 register int _d1 __asm("d1"); \ 750 register int _a0 __asm("a0"); \ 751 register int _a1 __asm("a1"); \ 752 void *const _##name##_bn = (bn); \ 753 register t1 _n1 __asm(#r1) = _##name##_v1; \ 754 register t2 _n2 __asm(#r2) = _##name##_v2; \ 755 register t3 _n3 __asm(#r3) = _##name##_v3; \ 756 register t4 _n4 __asm(#r4) = _##name##_v4; \ 757 register t5 _n5 __asm(#r5) = _##name##_v5; \ 758 register t6 _n6 __asm(#r6) = _##name##_v6; \ 759 register t7 _n7 __asm(#r7) = _##name##_v7; \ 760 register t8 _n8 __asm(#r8) = _##name##_v8; \ 761 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 762 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 763 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \ 764 : "fp0", "fp1", "cc", "memory"); \ 765 } \ 766}) 767 768/* For example layers.library/CreateUpfrontHookLayer() */ 769#define LP9(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \ 770({ \ 771 t1 _##name##_v1 = (v1); \ 772 t2 _##name##_v2 = (v2); \ 773 t3 _##name##_v3 = (v3); \ 774 t4 _##name##_v4 = (v4); \ 775 t5 _##name##_v5 = (v5); \ 776 t6 _##name##_v6 = (v6); \ 777 t7 _##name##_v7 = (v7); \ 778 t8 _##name##_v8 = (v8); \ 779 t9 _##name##_v9 = (v9); \ 780 ({ \ 781 register int _d1 __asm("d1"); \ 782 register int _a0 __asm("a0"); \ 783 register int _a1 __asm("a1"); \ 784 register rt _##name##_re __asm("d0"); \ 785 void *const _##name##_bn = (bn); \ 786 register t1 _n1 __asm(#r1) = _##name##_v1; \ 787 register t2 _n2 __asm(#r2) = _##name##_v2; \ 788 register t3 _n3 __asm(#r3) = _##name##_v3; \ 789 register t4 _n4 __asm(#r4) = _##name##_v4; \ 790 register t5 _n5 __asm(#r5) = _##name##_v5; \ 791 register t6 _n6 __asm(#r6) = _##name##_v6; \ 792 register t7 _n7 __asm(#r7) = _##name##_v7; \ 793 register t8 _n8 __asm(#r8) = _##name##_v8; \ 794 register t9 _n9 __asm(#r9) = _##name##_v9; \ 795 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 796 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 797 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \ 798 : "fp0", "fp1", "cc", "memory"); \ 799 _##name##_re; \ 800 }); \ 801}) 802 803/* For example intuition.library/NewModifyProp() */ 804#define LP9NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \ 805({ \ 806 t1 _##name##_v1 = (v1); \ 807 t2 _##name##_v2 = (v2); \ 808 t3 _##name##_v3 = (v3); \ 809 t4 _##name##_v4 = (v4); \ 810 t5 _##name##_v5 = (v5); \ 811 t6 _##name##_v6 = (v6); \ 812 t7 _##name##_v7 = (v7); \ 813 t8 _##name##_v8 = (v8); \ 814 t9 _##name##_v9 = (v9); \ 815 { \ 816 register int _d0 __asm("d0"); \ 817 register int _d1 __asm("d1"); \ 818 register int _a0 __asm("a0"); \ 819 register int _a1 __asm("a1"); \ 820 void *const _##name##_bn = (bn); \ 821 register t1 _n1 __asm(#r1) = _##name##_v1; \ 822 register t2 _n2 __asm(#r2) = _##name##_v2; \ 823 register t3 _n3 __asm(#r3) = _##name##_v3; \ 824 register t4 _n4 __asm(#r4) = _##name##_v4; \ 825 register t5 _n5 __asm(#r5) = _##name##_v5; \ 826 register t6 _n6 __asm(#r6) = _##name##_v6; \ 827 register t7 _n7 __asm(#r7) = _##name##_v7; \ 828 register t8 _n8 __asm(#r8) = _##name##_v8; \ 829 register t9 _n9 __asm(#r9) = _##name##_v9; \ 830 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 831 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 832 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \ 833 : "fp0", "fp1", "cc", "memory"); \ 834 } \ 835}) 836 837/* Kriton Kyrimis <kyrimis@cti.gr> says CyberGraphics needs the following */ 838#define LP10(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \ 839({ \ 840 t1 _##name##_v1 = (v1); \ 841 t2 _##name##_v2 = (v2); \ 842 t3 _##name##_v3 = (v3); \ 843 t4 _##name##_v4 = (v4); \ 844 t5 _##name##_v5 = (v5); \ 845 t6 _##name##_v6 = (v6); \ 846 t7 _##name##_v7 = (v7); \ 847 t8 _##name##_v8 = (v8); \ 848 t9 _##name##_v9 = (v9); \ 849 t10 _##name##_v10 = (v10); \ 850 ({ \ 851 register int _d1 __asm("d1"); \ 852 register int _a0 __asm("a0"); \ 853 register int _a1 __asm("a1"); \ 854 register rt _##name##_re __asm("d0"); \ 855 void *const _##name##_bn = (bn); \ 856 register t1 _n1 __asm(#r1) = _##name##_v1; \ 857 register t2 _n2 __asm(#r2) = _##name##_v2; \ 858 register t3 _n3 __asm(#r3) = _##name##_v3; \ 859 register t4 _n4 __asm(#r4) = _##name##_v4; \ 860 register t5 _n5 __asm(#r5) = _##name##_v5; \ 861 register t6 _n6 __asm(#r6) = _##name##_v6; \ 862 register t7 _n7 __asm(#r7) = _##name##_v7; \ 863 register t8 _n8 __asm(#r8) = _##name##_v8; \ 864 register t9 _n9 __asm(#r9) = _##name##_v9; \ 865 register t10 _n10 __asm(#r10) = _##name##_v10; \ 866 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 867 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 868 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10) \ 869 : "fp0", "fp1", "cc", "memory"); \ 870 _##name##_re; \ 871 }); \ 872}) 873 874/* Only graphics.library/BltMaskBitMapRastPort() */ 875#define LP10NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \ 876({ \ 877 t1 _##name##_v1 = (v1); \ 878 t2 _##name##_v2 = (v2); \ 879 t3 _##name##_v3 = (v3); \ 880 t4 _##name##_v4 = (v4); \ 881 t5 _##name##_v5 = (v5); \ 882 t6 _##name##_v6 = (v6); \ 883 t7 _##name##_v7 = (v7); \ 884 t8 _##name##_v8 = (v8); \ 885 t9 _##name##_v9 = (v9); \ 886 t10 _##name##_v10 = (v10); \ 887 { \ 888 register int _d0 __asm("d0"); \ 889 register int _d1 __asm("d1"); \ 890 register int _a0 __asm("a0"); \ 891 register int _a1 __asm("a1"); \ 892 void *const _##name##_bn = (bn); \ 893 register t1 _n1 __asm(#r1) = _##name##_v1; \ 894 register t2 _n2 __asm(#r2) = _##name##_v2; \ 895 register t3 _n3 __asm(#r3) = _##name##_v3; \ 896 register t4 _n4 __asm(#r4) = _##name##_v4; \ 897 register t5 _n5 __asm(#r5) = _##name##_v5; \ 898 register t6 _n6 __asm(#r6) = _##name##_v6; \ 899 register t7 _n7 __asm(#r7) = _##name##_v7; \ 900 register t8 _n8 __asm(#r8) = _##name##_v8; \ 901 register t9 _n9 __asm(#r9) = _##name##_v9; \ 902 register t10 _n10 __asm(#r10) = _##name##_v10; \ 903 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 904 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 905 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10) \ 906 : "fp0", "fp1", "cc", "memory"); \ 907 } \ 908}) 909 910/* Only graphics.library/BltBitMap() */ 911#define LP11(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, t11, v11, r11, bt, bn) \ 912({ \ 913 t1 _##name##_v1 = (v1); \ 914 t2 _##name##_v2 = (v2); \ 915 t3 _##name##_v3 = (v3); \ 916 t4 _##name##_v4 = (v4); \ 917 t5 _##name##_v5 = (v5); \ 918 t6 _##name##_v6 = (v6); \ 919 t7 _##name##_v7 = (v7); \ 920 t8 _##name##_v8 = (v8); \ 921 t9 _##name##_v9 = (v9); \ 922 t10 _##name##_v10 = (v10); \ 923 t11 _##name##_v11 = (v11); \ 924 ({ \ 925 register int _d1 __asm("d1"); \ 926 register int _a0 __asm("a0"); \ 927 register int _a1 __asm("a1"); \ 928 register rt _##name##_re __asm("d0"); \ 929 void *const _##name##_bn = (bn); \ 930 register t1 _n1 __asm(#r1) = _##name##_v1; \ 931 register t2 _n2 __asm(#r2) = _##name##_v2; \ 932 register t3 _n3 __asm(#r3) = _##name##_v3; \ 933 register t4 _n4 __asm(#r4) = _##name##_v4; \ 934 register t5 _n5 __asm(#r5) = _##name##_v5; \ 935 register t6 _n6 __asm(#r6) = _##name##_v6; \ 936 register t7 _n7 __asm(#r7) = _##name##_v7; \ 937 register t8 _n8 __asm(#r8) = _##name##_v8; \ 938 register t9 _n9 __asm(#r9) = _##name##_v9; \ 939 register t10 _n10 __asm(#r10) = _##name##_v10; \ 940 register t11 _n11 __asm(#r11) = _##name##_v11; \ 941 __asm volatile ("move.l %%a6,%%sp@-\n\tmove.l %[libbase],%%a6\n\tjsr %%a6@(-"#offs":W)\n\tmove.l %%sp@+,%%a6" \ 942 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 943 : [libbase] "a" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10), "rf"(_n11) \ 944 : "fp0", "fp1", "cc", "memory"); \ 945 _##name##_re; \ 946 }); \ 947}) 948 949typedef void *APTR; 950 951#endif /* __ASSEMBLER__ */ 952 953// #pragma mark - 954 955 956#ifndef __ASSEMBLER__ 957 958// <exec/types.h> 959 960 961// <exec/nodes.h> 962 963// our VFS also has a struct Node... 964struct ListNode { 965 struct ANode *ln_Succ; 966 struct ANode *ln_Pred; 967 uint8 ln_Type; 968 uint8 ln_Pri; 969 const char *ln_Name; 970}; 971 972struct List { 973 struct ListNode *lh_Head; 974 struct ListNode *lh_Tail; 975 struct ListNode *lh_TailPred; 976 uint8 lh_Type; 977 uint8 lh_pad; 978}; 979 980// <exec/lists.h> 981 982 983// <exec/interrupts.h> 984 985 986// <exec/library.h> 987 988// cf. 989// http://ftp.netbsd.org/pub/NetBSD/NetBSD-release-4-0/src/sys/arch/amiga/stand/bootblock/boot/amigatypes.h 990 991struct Library { 992 uint8 dummy1[10]; 993 uint16 Version, Revision; 994 uint8 dummy2[34-24]; 995} _PACKED; 996 997// <exec/execbase.h> 998 999struct MemHead { 1000 struct MemHead *next; 1001 uint8 dummy1[9-4]; 1002 uint8 Pri; 1003 uint8 dummy2[14-10]; 1004 uint16 Attribs; 1005 uint32 First, Lower, Upper, Free; 1006} _PACKED; 1007 1008struct ExecBase { 1009 struct Library LibNode; 1010 uint8 dummy1[296-34]; 1011 uint16 AttnFlags; 1012 uint8 dummy2[300-298]; 1013 void *ResModules; 1014 uint8 dummy3[322-304]; 1015 struct MemHead *MemList; 1016 uint8 dummy4[568-326]; 1017 uint32 EClockFreq; 1018 uint8 dummy5[632-334]; 1019} _PACKED; 1020 1021struct Message { 1022 struct ListNode mn_Node; 1023 struct MsgPort *mn_ReplyPort; 1024 uint16 mn_Length; 1025} _PACKED; 1026 1027struct MsgPort { 1028 struct ListNode mp_Node; 1029 uint8 mp_Flags; 1030 uint8 mp_SigBits; 1031 void *mp_SigTask; 1032 struct List mp_MsgList; 1033} _PACKED; 1034 1035#endif /* __ASSEMBLER__ */ 1036 1037 1038#define AFF_68010 (0x01) 1039#define AFF_68020 (0x02) 1040#define AFF_68030 (0x04) 1041#define AFF_68040 (0x08) 1042#define AFF_68881 (0x10) 1043#define AFF_68882 (0x20) 1044#define AFF_FPU40 (0x40) 1045 1046 1047#ifndef __ASSEMBLER__ 1048 1049// <exec/ports.h> 1050 1051 1052 1053// <exec/io.h> 1054 1055 1056struct IORequest { 1057 struct Message io_Message; 1058 struct Device *io_Device; 1059 struct Unit *io_Unit; 1060 uint16 io_Command; 1061 uint8 io_Flags; 1062 int8 io_Error; 1063} _PACKED; 1064 1065struct IOStdReq { 1066 struct Message io_Message; 1067 struct Device *io_Device; 1068 struct Unit *io_Unit; 1069 uint16 io_Command; 1070 uint8 io_Flags; 1071 int8 io_Error; 1072 uint32 io_Actual; 1073 uint32 io_Length; 1074 void *io_Data; 1075 uint32 io_Offset; 1076} _PACKED; 1077 1078 1079#endif /* __ASSEMBLER__ */ 1080 1081// io_Flags 1082#define IOB_QUICK 0 1083#define IOF_QUICK 0x01 1084 1085 1086#define CMD_INVALID 0 1087#define CMD_RESET 1 1088#define CMD_READ 2 1089#define CMD_WRITE 3 1090#define CMD_UPDATE 4 1091#define CMD_CLEAR 5 1092#define CMD_STOP 6 1093#define CMD_START 7 1094#define CMD_FLUSH 8 1095#define CMD_NONSTD 9 1096 1097 1098#ifndef __ASSEMBLER__ 1099 1100// <exec/devices.h> 1101 1102 1103#endif /* __ASSEMBLER__ */ 1104 1105 1106// <exec/errors.h> 1107 1108#define IOERR_OPENFAIL (-1) 1109#define IOERR_ABORTED (-2) 1110#define IOERR_NOCMD (-3) 1111#define IOERR_BADLENGTH (-4) 1112#define IOERR_BADADDRESS (-5) 1113#define IOERR_UNITBUSY (-6) 1114#define IOERR_SELFTEST (-7) 1115 1116 1117#define EXEC_BASE_NAME SysBase 1118 1119#define _LVOFindResident (-0x60) 1120#define _LVOAllocAbs (-0xcc) 1121#define _LVOOldOpenLibrary (-0x198) 1122#define _LVOCloseLibrary (-0x19e) 1123#define _LVODoIO (-0x1c8) 1124#define _LVOOpenLibrary (-0x228) 1125 1126 1127#ifndef __ASSEMBLER__ 1128 1129extern ExecBase *EXEC_BASE_NAME; 1130 1131#define AllocAbs(par1, last) \ 1132 LP2(0xcc, APTR, AllocAbs, unsigned long, par1, d0, APTR, last, a1, \ 1133 , EXEC_BASE_NAME) 1134 1135#define OldOpenLibrary(last) \ 1136 LP1(0x198, struct Library *, OldOpenLibrary, /*UBYTE*/const char *, last, a1, \ 1137 , EXEC_BASE_NAME) 1138 1139#define CloseLibrary(last) \ 1140 LP1NR(0x19e, CloseLibrary, struct Library *, last, a1, \ 1141 , EXEC_BASE_NAME) 1142 1143#define OpenDevice(par1, par2, par3, last) \ 1144 LP4(0x1bc, int8, OpenDevice, /*UBYTE*/uint8 *, par1, a0, unsigned long, par2, d0, struct IORequest *, par3, a1, unsigned long, last, d1, \ 1145 , EXEC_BASE_NAME) 1146 1147#define CloseDevice(last) \ 1148 LP1NR(0x1c2, CloseDevice, struct IORequest *, last, a1, \ 1149 , EXEC_BASE_NAME) 1150 1151#define DoIO(last) \ 1152 LP1(0x1c8, int8, DoIO, struct IORequest *, last, a1, \ 1153 , EXEC_BASE_NAME) 1154 1155#define OpenLibrary(par1, last) \ 1156 LP2(0x228, struct Library *, OpenLibrary, uint8 *, par1, a1, \ 1157 unsigned long, last, d0, \ 1158 , EXEC_BASE_NAME) 1159 1160#define CreateIORequest(par1, last) \ 1161 LP2(0x28e, APTR, CreateIORequest, struct MsgPort *, par1, a0, unsigned long, last, d0, \ 1162 , EXEC_BASE_NAME) 1163 1164#define DeleteIORequest(last) \ 1165 LP1NR(0x294, DeleteIORequest, APTR, last, a0, \ 1166 , EXEC_BASE_NAME) 1167 1168#define CreateMsgPort() \ 1169 LP0(0x29a, struct MsgPort *, CreateMsgPort, \ 1170 , EXEC_BASE_NAME) 1171 1172#define ColdReboot() \ 1173 LP0NR(0x2d6, ColdReboot, \ 1174 , EXEC_BASE_NAME) 1175 1176 1177 1178extern "C" status_t exec_error(int32 err); 1179 1180#endif /* __ASSEMBLER__ */ 1181 1182// #pragma mark - 1183 1184// <graphics/gfx.h> 1185 1186#ifndef __ASSEMBLER__ 1187 1188struct BitMap { 1189 uint16 BytesPerRow; 1190 uint16 Rows; 1191 uint8 Flags; 1192 uint8 Depth; 1193 uint16 pad; 1194 void *Planes[8]; 1195}; 1196 1197struct Rectangle { 1198 int16 MinX, MinY, MaxX, MaxY; 1199}; 1200 1201struct Point { 1202 int16 x, y; 1203}; 1204 1205#endif /* __ASSEMBLER__ */ 1206 1207// <graphics/graphics.h> 1208 1209#define GRAPHICSNAME "graphics.library" 1210#define GRAPHICS_BASE_NAME GraphicsBase 1211 1212#ifndef __ASSEMBLER__ 1213 1214struct GfxBase { 1215 struct Library LibNode; 1216 struct View *ActiView; 1217 struct copinit *copinit; 1218 int32 *cia; 1219 int32 *blitter; 1220 uint16 *LOFlist; 1221 uint16 *SHFlist; 1222 struct bltnode *blthd; 1223 struct bltnode *blttl; 1224 struct bltnode *bsblthd; 1225 struct bltnode *bsblttl; 1226 1227 //... 1228} _PACKED; 1229 1230struct ViewPort { 1231 struct ViewPort *Next; 1232 struct ColorMap *ColorMap; 1233 struct CopList *DspIns; 1234 struct CopList *SprIns; 1235 struct CopList *ClrIns; 1236 struct UCopList *UCopIns; 1237 int16 DWidth, DHeight; 1238 int16 DxOffset, DyOffset; 1239 uint16 Modes; 1240 uint8 SpritePriorities; 1241 uint8 ExtendedModes; 1242 struct RastInfo *RasInfo; 1243} _PACKED; 1244 1245struct RastPort { 1246 struct Layer *Layer; 1247 struct BitMap *BitMap; 1248 //... 1249} _PACKED; 1250 1251// <graphics/text.h> 1252 1253struct TextAttr { 1254 const char *taName; 1255 uint16 ta_YSize; 1256 uint8 ta_Style, ta_Flags; 1257} _PACKED; 1258 1259struct TextFont { 1260 struct Message tf_Message; 1261 uint16 tf_YSize; 1262 uint8 tf_Style; 1263 uint8 tf_Flags; 1264 uint16 tf_XSize; 1265 //... 1266} _PACKED; 1267 1268extern struct GfxBase *GRAPHICS_BASE_NAME; 1269 1270#define ClearScreen(last) \ 1271 LP1NR(0x30, ClearScreen, struct RastPort *, last, a1, \ 1272 , GRAPHICS_BASE_NAME) 1273 1274#define Text(par1, par2, last) \ 1275 LP3(0x3c, int32, Text, struct RastPort *, par1, a1, const char *, par2, a0, unsigned long, last, d0, \ 1276 , GRAPHICS_BASE_NAME) 1277 1278#define SetFont(par1, last) \ 1279 LP2(0x42, int32, SetFont, struct RastPort *, par1, a1, struct TextFont *, last, a0, \ 1280 , GRAPHICS_BASE_NAME) 1281 1282#define OpenFont(last) \ 1283 LP1(0x48, struct TextFont *, OpenFont, struct TextAttr *, last, a0, \ 1284 , GRAPHICS_BASE_NAME) 1285 1286#define LoadRGB4(par1, par2, last) \ 1287 LP3NR(0xc0, LoadRGB4, struct ViewPort *, par1, a0, const uint16 *, par2, a1, long, last, d0, \ 1288 , GRAPHICS_BASE_NAME) 1289 1290#define Move(par1, par2, last) \ 1291 LP3NR(0xf0, Move, struct RastPort *, par1, a1, long, par2, d0, long, last, d1, \ 1292 , GRAPHICS_BASE_NAME) 1293 1294#define SetAPen(par1, last) \ 1295 LP2NR(0x156, SetAPen, struct RastPort *, par1, a1, unsigned long, last, d0, \ 1296 , GRAPHICS_BASE_NAME) 1297 1298#define SetBPen(par1, last) \ 1299 LP2NR(0x15c, SetBPen, struct RastPort *, par1, a1, unsigned long, last, d0, \ 1300 , GRAPHICS_BASE_NAME) 1301 1302#define SetDrMd(par1, last) \ 1303 LP2NR(0x162, SetDrMd, struct RastPort *, par1, a1, unsigned long, last, d0, \ 1304 , GRAPHICS_BASE_NAME) 1305 1306#define FindDisplayInfo(last) \ 1307 LP1(0x2d6, DisplayInfoHandle, FindDisplayInfo, unsigned long, last, d0, \ 1308 , GRAPHICS_BASE_NAME) 1309 1310#define NextDisplayInfo(last) \ 1311 LP1(0x2dc, uint32, NextDisplayInfo, unsigned long, last, d0, \ 1312 , GRAPHICS_BASE_NAME) 1313 1314#define GetDisplayInfoData(par1, par2, par3, par4, last) \ 1315 LP5(0x2f4, uint32, GetDisplayInfoData, DisplayInfoHandle, par1, a0, uint8 *, par2, a1, unsigned long, par3, d0, unsigned long, par4, d1, unsigned long, last, d2, \ 1316 , GRAPHICS_BASE_NAME) 1317 1318 1319#endif /* __ASSEMBLER__ */ 1320 1321/* drawing modes */ 1322#define JAM1 0 // only draw foreground 1323#define JAM2 1 // draw both fg & bg 1324 1325// <graphics/modeid.h> 1326 1327#define INVALID_ID (~0) 1328 1329// <graphics/displayinfo.h> 1330 1331#ifndef __ASSEMBLER__ 1332 1333typedef void *DisplayInfoHandle; 1334 1335struct QueryHeader { 1336 uint32 StructID; 1337 uint32 DisplayID; 1338 uint32 SkipID; 1339 uint32 Length; 1340}; 1341 1342struct DisplayInfo { 1343 struct QueryHeader Header; 1344 uint16 NotAvailable; 1345 uint32 PropertyFlags; 1346 struct Point Resolution; 1347 uint16 PixelSpeed; 1348 uint16 NumStdSprites; 1349 uint16 PaletteRange; 1350 struct Point SpriteResolution; 1351 uint8 pad[4]; 1352 uint8 RedBits; 1353 uint8 GreenBits; 1354 uint8 BlueBits; 1355 uint8 pad2[5]; 1356 uint32 reserved[2]; 1357}; 1358 1359struct DimensionInfo { 1360 struct QueryHeader Header; 1361 uint16 MaxDepth; 1362 uint16 MinRasterWidth; 1363 uint16 MinRasterHeight; 1364 uint16 MaxRasterWidth; 1365 uint16 MaxRasterHeight; 1366 struct Rectangle Nominal; 1367 //... overscan stuff 1368 struct Rectangle overscanStuff[4]; 1369 uint8 pad[14]; 1370 uint32 reserved[2]; 1371}; 1372 1373#define DISPLAYNAMELEN 32 1374 1375struct NameInfo { 1376 struct QueryHeader Header; 1377 uchar Name[DISPLAYNAMELEN]; 1378 uint32 reserved[2]; 1379}; 1380 1381#endif /* __ASSEMBLER__ */ 1382 1383#define DTAG_DISP 0x80000000 1384#define DTAG_DIMS 0x80001000 1385#define DTAG_MNTR 0x80002000 1386#define DTAG_NAME 0x80003000 1387 1388#define DIPF_IS_LACE 0x00000001 1389#define DIPF_IS_DUALPF 0x00000002 1390#define DIPF_IS_PF2PRI 0x00000004 1391#define DIPF_IS_HAM 0x00000008 1392#define DIPF_IS_ECS 0x00000010 1393#define DIPF_IS_AA 0x00010000 1394#define DIPF_IS_PAL 0x00000020 1395#define DIPF_IS_SPRITES 0x00000040 1396#define DIPF_IS_GENLOCK 0x00000080 1397#define DIPF_IS_WB 0x00000100 1398#define DIPF_IS_DRAGGABLE 0x00000200 1399#define DIPF_IS_PANELLED 0x00000400 1400#define DIPF_IS_BEAMSYNC 0x00000800 1401#define DIPF_IS_EXTRAHALDBRITE 0x00001000 1402// 1403#define DIPF_IS_FOREIGN 0x80000000 1404 1405// #pragma mark - 1406 1407 1408// <intuition/intuition.h> 1409 1410 1411#define ALERT_TYPE 0x80000000 1412#define RECOVERY_ALERT 0x00000000 1413#define DEADEND_ALERT 0x80000000 1414 1415#define INTUITION_BASE_NAME IntuitionBase 1416 1417#define _LVODisplayAlert (-0x5a) 1418 1419#ifndef __ASSEMBLER__ 1420 1421struct Window { 1422 uint8 dummy1[136]; 1423}; 1424 1425struct NewWindow { 1426 int16 LeftEdge, TopEdge; 1427 int16 Width, Height; 1428 uint8 DetailPen, BlockPen; 1429 uint32 IDCMPFlags; 1430 uint32 Flags; 1431 struct Gadget *FirstGadget; 1432 struct Image *CheckMark; 1433 const char *Title; 1434 struct Screen *Screen; 1435 struct BitMap *BitMap; 1436 int16 MinWidth, MinHeight; 1437 uint16 MaxWidth, MaxHeight; 1438 uint16 Type; 1439}; 1440 1441#endif /* __ASSEMBLER__ */ 1442 1443#define CUSTOMSCREEN 0x000f 1444 1445#define IDCMP_CLOSEWINDOW 0x00000200 1446 1447#define WFLG_SIZEGADGET 0x00000001 1448#define WFLG_DRAGBAR 0x00000002 1449#define WFLG_DEPTHGADGET 0x00000004 1450#define WFLG_CLOSEGADGET 0x00000008 1451 1452#define WFLG_SMART_REFRESH 0x00000000 1453#define WFLG_SIMPLE_REFRESH 0x00000040 1454 1455#define WFLG_ACTIVATE 0x00001000 1456 1457#ifndef __ASSEMBLER__ 1458 1459// <intuition/screen.h> 1460 1461struct NewScreen { 1462 int16 LeftEdge, TopEdge, Width, Height, Depth; 1463 uint8 DetailPen, BlockPen; 1464 uint16 ViewModes; 1465 uint16 Type; 1466 struct TextAttr *Font; 1467 /*UBYTE*/const char *DefaultTitle; 1468 struct Gadget *Gadgets; 1469 struct BitMap *CustomBitMap; 1470}; 1471 1472 1473struct Screen { 1474 struct Screen *NextScreen; 1475 struct Window *FirstWindow; 1476 int16 LeftEdge, TopEdge; 1477 int16 Width, Height; 1478 int16 MouseX, MouseY; 1479 uint16 Flags; 1480 const char *Title; 1481 const char *DefaultTitle; 1482 int8 BarHeight, BarVBorder, BarHBorder, MenuVBorder, MenuHBorder; 1483 int8 WBorTop, WBorLeft, WBorRight, WBorBottom; 1484 struct TextAttr *Font; 1485 struct ViewPort ViewPort; 1486 struct RastPort RastPort; 1487 //... 1488}; 1489 1490extern struct Library *INTUITION_BASE_NAME; 1491 1492#define CloseScreen(last) \ 1493 LP1(0x42, bool, CloseScreen, struct Screen *, last, a0, \ 1494 , INTUITION_BASE_NAME) 1495 1496#define DisplayAlert(par1, par2, last) \ 1497 LP3(0x5a, bool, DisplayAlert, unsigned long, par1, d0, void *, \ 1498 par2, a0, unsigned long, last, d1, \ 1499 , INTUITION_BASE_NAME) 1500 1501#define OpenScreen(last) \ 1502 LP1(0xc6, struct Screen *, OpenScreen, struct NewScreen *, last, a0, \ 1503 , INTUITION_BASE_NAME) 1504 1505#define OpenWindow(last) \ 1506 LP1(0xcc, struct Window *, OpenWindow, struct NewWindow *, last, a0, \ 1507 , INTUITION_BASE_NAME) 1508 1509#define RemakeDisplay() \ 1510 LP0(0x180, int32, RemakeDisplay, \ 1511 , INTUITION_BASE_NAME) 1512 1513 1514#endif /* __ASSEMBLER__ */ 1515 1516 1517// <devices/conunit.h> 1518 1519#define CONU_LIBRARY -1 1520#define CONU_STANDARD 0 1521#define CONU_CHARMAP 1 1522 1523#ifndef __ASSEMBLER__ 1524 1525struct ConUnit { 1526 struct MsgPort cu_MP; 1527 struct Window *cu_Window; 1528 int16 cu_XCP, cu_YCP; 1529 int16 cu_XMax, cu_YMax; 1530}; 1531 1532#endif /* __ASSEMBLER__ */ 1533 1534// <devices/console.h> 1535 1536#define CONSOLENAME "console.device" 1537 1538// <devices/keymap.h> 1539 1540#ifndef KEYMAP_BASE_NAME 1541#define KEYMAP_BASE_NAME KeymapBase 1542#endif 1543 1544#define KEYMAPNAME "keymap.library" 1545 1546#ifndef __ASSEMBLER__ 1547#define MapRawKey(par1, par2, par3, last) \ 1548 LP4(0x2a, int16, MapRawKey, struct InputEvent *, par1, a0, char *, par2, a1, long, par3, d1, struct KeyMap *, last, a2, \ 1549 , KEYMAP_BASE_NAME) 1550 1551extern struct Library *KEYMAP_BASE_NAME; 1552 1553#endif /* __ASSEMBLER__ */ 1554 1555// <libraries/lowlevel.h> 1556 1557#ifndef LOWLEVEL_BASE_NAME 1558#define LOWLEVEL_BASE_NAME LowLevelBase 1559#endif 1560 1561#define LOWLEVELNAME "lowlevel.library" 1562 1563#ifndef __ASSEMBLER__ 1564 1565#define GetKey() \ 1566 LP0(0x30, uint32, GetKey, \ 1567 , LOWLEVEL_BASE_NAME) 1568 1569#define QueryKeys(par1, last) \ 1570 LP2NR(0x36, QueryKeys, struct KeyQuery *, par1, a0, unsigned long, last, d1, \ 1571 , LOWLEVEL_BASE_NAME) 1572 1573extern struct Library *LOWLEVEL_BASE_NAME; 1574 1575#endif /* __ASSEMBLER__ */ 1576 1577 1578// <devices/keyboard.h> 1579 1580#define KBD_READEVENT (CMD_NONSTD+0) 1581 1582// <devices/inputevent.h> 1583 1584#ifndef __ASSEMBLER__ 1585 1586struct InputEvent { 1587 struct InputEvent *ie_NextEvent; 1588 uint8 ie_Class; 1589 uint8 ie_SubClass; 1590 uint16 ie_Code; 1591 uint16 ie_Qualifier; 1592 union { 1593 struct { 1594 int16 ie_x; 1595 int16 ie_y; 1596 } ie_xy; 1597 APTR ie_addr; 1598 struct { 1599 uint8 ie_prev1DownCode; 1600 uint8 ie_prev1DownQual; 1601 uint8 ie_prev2DownCode; 1602 uint8 ie_prev2DownQual; 1603 } ie_dead; 1604 } ie_position; 1605 /*struct timeval*/ 1606 struct { uint32 tv_secs, tv_micro; } ie_TimeStamp; 1607}; 1608 1609#endif /* __ASSEMBLER__ */ 1610 1611#define IECLASS_RAWKEY 0x01 1612#define IESUBCLASS_RAWKEY 0x01 1613 1614#define IECODE_UP_PREFIX 0x80 1615 1616#define IECODE_KEY_UP 0x4c 1617#define IECODE_KEY_DOWN 0x4d 1618#define IECODE_KEY_LEFT 0x4f 1619#define IECODE_KEY_RIGHT 0x4e 1620#define IECODE_KEY_PAGE_UP 0x67 1621#define IECODE_KEY_PAGE_DOWN 0x66 1622 1623#ifdef __cplusplus 1624} 1625#endif 1626 1627#endif /* _AMICALLS_H */ 1628