1/* 2 * Copyright 2009, Haiku, Inc. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Fran��ois Revol <revol@free.fr> 7 */ 8#ifndef _UART_H_ 9#define _UART_H_ 10 11// References: 12// http://www.beyondlogic.org/serial/serial.htm 13 14 15// 8250 UART registers 16#define THB 0 17#define RBR 0 18#define DLLB 0 19#define IER 1 20#define DLHB 1 21#define IIR 2 22#define FCR 2 23#define LCR 3 24#define MCR 4 25#define LSR 5 26#define MSR 6 27#define SR 7 28 29// bits 30#define IER_RDA (1 << 0) 31#define IER_THRE (1 << 1) 32#define IER_RLS (1 << 2) 33#define IER_MS (1 << 3) 34#define IER_SM (1 << 4) // 16750 35#define IER_LPM (1 << 5) // 16750 36 37#define IIR_PENDING (1 << 0) 38#define IIR_IMASK (0x03 << 1) 39#define IIR_MS (0 << 1) 40#define IIR_THRE (1 << 1) 41#define IIR_RDA (2 << 1) 42#define IIR_RLS (3 << 1) 43#define IIR_TO (1 << 3) // 16550 44#define IIR_F64EN (1 << 5) // 16750 45#define IIR_FMASK (3 << 6) 46 47#define FCR_ENABLE (1 << 0) 48#define FCR_RX_RST (1 << 1) 49#define FCR_TX_RST (1 << 2) 50#define FCR_DMA_EN (1 << 3) 51#define FCR_F64EN (1 << 5) 52#define FCR_FMASK (0x03 << 6) 53#define FCR_F_1 (0 << 6) 54#define FCR_F_4 (1 << 6) 55#define FCR_F_8 (2 << 6) 56#define FCR_F_14 (3 << 6) 57 58#define LCR_5BIT 0 59#define LCR_6BIT 1 60#define LCR_7BIT 2 61#define LCR_8BIT 3 62#define LCR_2STOP (1 << 2) 63#define LCR_P_EN (1 << 3) 64#define LCR_P_EVEN (1 << 4) 65#define LCR_P_MARK (1 << 5) 66#define LCR_BREAK (1 << 6) 67#define LCR_DLAB (1 << 7) 68 69#define MCR_DTR (1 << 0) 70#define MCR_RTS (1 << 1) 71#define MCR_AUX1 (1 << 2) 72#define MCR_AUX2 (1 << 3) 73#define MCR_IRQ_EN (1 << 3) // ? 74#define MCR_LOOP (1 << 4) 75#define MCR_AUTOFLOW (1 << 5) // 16750 76 77#define LSR_DR (1 << 0) 78#define LSR_OVERRUN (1 << 1) 79#define LSR_PARITY (1 << 2) 80#define LSR_FRAMING (1 << 3) 81#define LSR_BREAK (1 << 4) 82#define LSR_THRE (1 << 5) 83#define LSR_TSRE (1 << 6) 84#define LSR_FIFO (1 << 7) 85 86#define MSR_DCTS (1 << 0) 87#define MSR_DDSR (1 << 1) 88#define MSR_TERI (1 << 2) 89#define MSR_DDCD (1 << 3) 90#define MSR_CTS (1 << 4) 91#define MSR_DSR (1 << 5) 92#define MSR_RI (1 << 6) 93#define MSR_DCD (1 << 7) 94 95// speeds 96//#define BPS_50 97 98 99#endif // _UART_H_ 100