1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2007-2009 Marvell Semiconductor, Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 16 * redistribution must be conditioned upon including a substantially 17 * similar Disclaimer requirement for further binary redistribution. 18 * 19 * NO WARRANTY 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 23 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 24 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 28 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGES. 31 * 32 * $FreeBSD: releng/12.0/sys/dev/mwl/mwlreg.h 326255 2017-11-27 14:52:40Z pfg $ 33 */ 34 35/* 36 * Definitions for the Marvell Wireless LAN controller Hardware Access Layer. 37 */ 38#ifndef _MWL_HALREG_H_ 39#define _MWL_HALREG_H_ 40 41#define MWL_ANT_INFO_SUPPORT /* per-antenna data in rx descriptor */ 42 43#define MACREG_REG_TSF_LOW 0xa600 /* TSF lo */ 44#define MACREG_REG_TSF_HIGH 0xa604 /* TSF hi */ 45#define MACREG_REG_CHIP_REV 0xa814 /* chip rev */ 46 47// Map to 0x80000000 (Bus control) on BAR0 48#define MACREG_REG_H2A_INTERRUPT_EVENTS 0x00000C18 // (From host to ARM) 49#define MACREG_REG_H2A_INTERRUPT_CAUSE 0x00000C1C // (From host to ARM) 50#define MACREG_REG_H2A_INTERRUPT_MASK 0x00000C20 // (From host to ARM) 51#define MACREG_REG_H2A_INTERRUPT_CLEAR_SEL 0x00000C24 // (From host to ARM) 52#define MACREG_REG_H2A_INTERRUPT_STATUS_MASK 0x00000C28 // (From host to ARM) 53 54#define MACREG_REG_A2H_INTERRUPT_EVENTS 0x00000C2C // (From ARM to host) 55#define MACREG_REG_A2H_INTERRUPT_CAUSE 0x00000C30 // (From ARM to host) 56#define MACREG_REG_A2H_INTERRUPT_MASK 0x00000C34 // (From ARM to host) 57#define MACREG_REG_A2H_INTERRUPT_CLEAR_SEL 0x00000C38 // (From ARM to host) 58#define MACREG_REG_A2H_INTERRUPT_STATUS_MASK 0x00000C3C // (From ARM to host) 59 60// Map to 0x80000000 on BAR1 61#define MACREG_REG_GEN_PTR 0x00000C10 62#define MACREG_REG_INT_CODE 0x00000C14 63#define MACREG_REG_SCRATCH 0x00000C40 64#define MACREG_REG_FW_PRESENT 0x0000BFFC 65 66#define MACREG_REG_PROMISCUOUS 0xA300 67 68// Bit definitio for MACREG_REG_A2H_INTERRUPT_CAUSE (A2HRIC) 69#define MACREG_A2HRIC_BIT_TX_DONE 0x00000001 // bit 0 70#define MACREG_A2HRIC_BIT_RX_RDY 0x00000002 // bit 1 71#define MACREG_A2HRIC_BIT_OPC_DONE 0x00000004 // bit 2 72#define MACREG_A2HRIC_BIT_MAC_EVENT 0x00000008 // bit 3 73#define MACREG_A2HRIC_BIT_RX_PROBLEM 0x00000010 // bit 4 74 75#define MACREG_A2HRIC_BIT_RADIO_OFF 0x00000020 // bit 5 76#define MACREG_A2HRIC_BIT_RADIO_ON 0x00000040 // bit 6 77 78#define MACREG_A2HRIC_BIT_RADAR_DETECT 0x00000080 // bit 7 79 80#define MACREG_A2HRIC_BIT_ICV_ERROR 0x00000100 // bit 8 81#define MACREG_A2HRIC_BIT_MIC_ERROR 0x00000200 // bit 9 82#define MACREG_A2HRIC_BIT_QUEUE_EMPTY 0x00004000 83#define MACREG_A2HRIC_BIT_QUEUE_FULL 0x00000800 84#define MACREG_A2HRIC_BIT_CHAN_SWITCH 0x00001000 85#define MACREG_A2HRIC_BIT_TX_WATCHDOG 0x00002000 86#define MACREG_A2HRIC_BIT_BA_WATCHDOG 0x00000400 87#define MACREQ_A2HRIC_BIT_TX_ACK 0x00008000 88#define ISR_SRC_BITS ((MACREG_A2HRIC_BIT_RX_RDY) | \ 89 (MACREG_A2HRIC_BIT_TX_DONE) | \ 90 (MACREG_A2HRIC_BIT_OPC_DONE) | \ 91 (MACREG_A2HRIC_BIT_MAC_EVENT)| \ 92 (MACREG_A2HRIC_BIT_MIC_ERROR)| \ 93 (MACREG_A2HRIC_BIT_ICV_ERROR)| \ 94 (MACREG_A2HRIC_BIT_RADAR_DETECT)| \ 95 (MACREG_A2HRIC_BIT_CHAN_SWITCH)| \ 96 (MACREG_A2HRIC_BIT_TX_WATCHDOG)| \ 97 (MACREG_A2HRIC_BIT_QUEUE_EMPTY)| \ 98 (MACREG_A2HRIC_BIT_BA_WATCHDOG)| \ 99 (MACREQ_A2HRIC_BIT_TX_ACK)) 100 101#define MACREG_A2HRIC_BIT_MASK ISR_SRC_BITS 102 103// Bit definitio for MACREG_REG_H2A_INTERRUPT_CAUSE (H2ARIC) 104#define MACREG_H2ARIC_BIT_PPA_READY 0x00000001 // bit 0 105#define MACREG_H2ARIC_BIT_DOOR_BELL 0x00000002 // bit 1 106#define ISR_RESET (1<<15) 107 108// INT code register event definition 109#define MACREG_INT_CODE_CMD_FINISHED 0x00000005 110 111/* 112 * Host/Firmware Interface definitions. 113 */ 114 115/** 116 * Define total number of TX queues in the shared memory. 117 * This count includes the EDCA queues, Block Ack queues, and HCCA queues 118 * In addition to this, there could be a management packet queue some 119 * time in the future 120 */ 121#define NUM_EDCA_QUEUES 4 122#define NUM_HCCA_QUEUES 0 123#define NUM_BA_QUEUES 0 124#define NUM_MGMT_QUEUES 0 125#define NUM_ACK_EVENT_QUEUE 1 126#define TOTAL_TX_QUEUES \ 127 (NUM_EDCA_QUEUES + NUM_HCCA_QUEUES + NUM_BA_QUEUES + NUM_MGMT_QUEUES + NUM_ACK_EVENT_QUEUE) 128#define MAX_TXWCB_QUEUES TOTAL_TX_QUEUES - NUM_ACK_EVENT_QUEUE 129#define MAX_RXWCB_QUEUES 1 130 131//============================================================================= 132// PUBLIC DEFINITIONS 133//============================================================================= 134 135#define RATE_INDEX_MAX_ARRAY 14 136#define WOW_MAX_STATION 32 137 138/* 139 * Hardware tx/rx descriptors. 140 * 141 * NB: tx descriptor size must match f/w expected size 142 * because f/w prefetch's the next descriptor linearly 143 * and doesn't chase the next pointer. 144 */ 145struct mwl_txdesc { 146 uint32_t Status; 147#define EAGLE_TXD_STATUS_IDLE 0x00000000 148#define EAGLE_TXD_STATUS_USED 0x00000001 149#define EAGLE_TXD_STATUS_OK 0x00000001 150#define EAGLE_TXD_STATUS_OK_RETRY 0x00000002 151#define EAGLE_TXD_STATUS_OK_MORE_RETRY 0x00000004 152#define EAGLE_TXD_STATUS_MULTICAST_TX 0x00000008 153#define EAGLE_TXD_STATUS_BROADCAST_TX 0x00000010 154#define EAGLE_TXD_STATUS_FAILED_LINK_ERROR 0x00000020 155#define EAGLE_TXD_STATUS_FAILED_EXCEED_LIMIT 0x00000040 156#define EAGLE_TXD_STATUS_FAILED_XRETRY EAGLE_TXD_STATUS_FAILED_EXCEED_LIMIT 157#define EAGLE_TXD_STATUS_FAILED_AGING 0x00000080 158#define EAGLE_TXD_STATUS_FW_OWNED 0x80000000 159 uint8_t DataRate; 160 uint8_t TxPriority; 161 uint16_t QosCtrl; 162 uint32_t PktPtr; 163 uint16_t PktLen; 164 uint8_t DestAddr[6]; 165 uint32_t pPhysNext; 166 uint32_t SapPktInfo; 167#define EAGLE_TXD_MODE_BONLY 1 168#define EAGLE_TXD_MODE_GONLY 2 169#define EAGLE_TXD_MODE_BG 3 170#define EAGLE_TXD_MODE_NONLY 4 171#define EAGLE_TXD_MODE_BN 5 172#define EAGLE_TXD_MODE_GN 6 173#define EAGLE_TXD_MODE_BGN 7 174#define EAGLE_TXD_MODE_AONLY 8 175#define EAGLE_TXD_MODE_AG 10 176#define EAGLE_TXD_MODE_AN 12 177 uint16_t Format; 178#define EAGLE_TXD_FORMAT 0x0001 /* frame format/rate */ 179#define EAGLE_TXD_FORMAT_LEGACY 0x0000 /* legacy rate frame */ 180#define EAGLE_TXD_FORMAT_HT 0x0001 /* HT rate frame */ 181#define EAGLE_TXD_GI 0x0002 /* guard interval */ 182#define EAGLE_TXD_GI_SHORT 0x0002 /* short guard interval */ 183#define EAGLE_TXD_GI_LONG 0x0000 /* long guard interval */ 184#define EAGLE_TXD_CHW 0x0004 /* channel width */ 185#define EAGLE_TXD_CHW_20 0x0000 /* 20MHz channel width */ 186#define EAGLE_TXD_CHW_40 0x0004 /* 40MHz channel width */ 187#define EAGLE_TXD_RATE 0x01f8 /* tx rate (legacy)/ MCS */ 188#define EAGLE_TXD_RATE_S 3 189#define EAGLE_TXD_ADV 0x0600 /* advanced coding */ 190#define EAGLE_TXD_ADV_S 9 191#define EAGLE_TXD_ADV_NONE 0x0000 192#define EAGLE_TXD_ADV_LDPC 0x0200 193#define EAGLE_TXD_ADV_RS 0x0400 194/* NB: 3 is reserved */ 195#define EAGLE_TXD_ANTENNA 0x1800 /* antenna select */ 196#define EAGLE_TXD_ANTENNA_S 11 197#define EAGLE_TXD_EXTCHAN 0x6000 /* extension channel */ 198#define EAGLE_TXD_EXTCHAN_S 13 199#define EAGLE_TXD_EXTCHAN_HI 0x0000 /* above */ 200#define EAGLE_TXD_EXTCHAN_LO 0x2000 /* below */ 201#define EAGLE_TXD_PREAMBLE 0x8000 202#define EAGLE_TXD_PREAMBLE_SHORT 0x8000 /* short preamble */ 203#define EAGLE_TXD_PREAMBLE_LONG 0x0000 /* long preamble */ 204 uint16_t pad; /* align to 4-byte boundary */ 205#define EAGLE_TXD_FIXED_RATE 0x0100 /* get tx rate from Format */ 206#define EAGLE_TXD_DONT_AGGR 0x0200 /* don't aggregate frame */ 207 uint32_t ack_wcb_addr; 208} __packed; 209 210struct mwl_ant_info { 211 uint8_t rssi_a; /* RSSI for antenna A */ 212 uint8_t rssi_b; /* RSSI for antenna B */ 213 uint8_t rssi_c; /* RSSI for antenna C */ 214 uint8_t rsvd1; /* Reserved */ 215 uint8_t nf_a; /* Noise floor for antenna A */ 216 uint8_t nf_b; /* Noise floor for antenna B */ 217 uint8_t nf_c; /* Noise floor for antenna C */ 218 uint8_t rsvd2; /* Reserved */ 219 uint8_t nf; /* Noise floor */ 220 uint8_t rsvd3[3]; /* Reserved - To make word aligned */ 221} __packed; 222 223struct mwl_rxdesc { 224 uint8_t RxControl; /* control element */ 225#define EAGLE_RXD_CTRL_DRIVER_OWN 0x00 226#define EAGLE_RXD_CTRL_OS_OWN 0x04 227#define EAGLE_RXD_CTRL_DMA_OWN 0x80 228 uint8_t RSSI; /* received signal strengt indication */ 229 uint8_t Status; /* status field w/ USED bit */ 230#define EAGLE_RXD_STATUS_IDLE 0x00 231#define EAGLE_RXD_STATUS_OK 0x01 232#define EAGLE_RXD_STATUS_MULTICAST_RX 0x02 233#define EAGLE_RXD_STATUS_BROADCAST_RX 0x04 234#define EAGLE_RXD_STATUS_FRAGMENT_RX 0x08 235#define EAGLE_RXD_STATUS_GENERAL_DECRYPT_ERR 0xff 236#define EAGLE_RXD_STATUS_DECRYPT_ERR_MASK 0x80 237#define EAGLE_RXD_STATUS_TKIP_MIC_DECRYPT_ERR 0x02 238#define EAGLE_RXD_STATUS_WEP_ICV_DECRYPT_ERR 0x04 239#define EAGLE_RXD_STATUS_TKIP_ICV_DECRYPT_ERR 0x08 240 uint8_t Channel; /* channel # pkt received on */ 241 uint16_t PktLen; /* total length of received data */ 242 uint8_t SQ2; /* not used */ 243 uint8_t Rate; /* received data rate */ 244 uint32_t pPhysBuffData; /* physical address of payload data */ 245 uint32_t pPhysNext; /* physical address of next RX desc */ 246 uint16_t QosCtrl; /* received QosCtrl field variable */ 247 uint16_t HtSig2; /* like name states */ 248#ifdef MWL_ANT_INFO_SUPPORT 249 struct mwl_ant_info ai; /* antenna info */ 250#endif 251} __packed; 252 253/* 254// Define OpMode for SoftAP/Station mode 255// 256// The following mode signature has to be written to PCI scratch register#0 257// right after successfully downloading the last block of firmware and 258// before waiting for firmware ready signature 259 */ 260#define HostCmd_STA_MODE 0x5A 261#define HostCmd_SOFTAP_MODE 0xA5 262 263#define HostCmd_STA_FWRDY_SIGNATURE 0xF0F1F2F4 264#define HostCmd_SOFTAP_FWRDY_SIGNATURE 0xF1F2F4A5 265 266//*************************************************************************** 267//*************************************************************************** 268 269//*************************************************************************** 270 271#define HostCmd_CMD_CODE_DNLD 0x0001 272#define HostCmd_CMD_GET_HW_SPEC 0x0003 273#define HostCmd_CMD_SET_HW_SPEC 0x0004 274#define HostCmd_CMD_MAC_MULTICAST_ADR 0x0010 275#define HostCmd_CMD_802_11_GET_STAT 0x0014 276#define HostCmd_CMD_MAC_REG_ACCESS 0x0019 277#define HostCmd_CMD_BBP_REG_ACCESS 0x001a 278#define HostCmd_CMD_RF_REG_ACCESS 0x001b 279#define HostCmd_CMD_802_11_RADIO_CONTROL 0x001c 280#define HostCmd_CMD_802_11_RF_TX_POWER 0x001e 281#define HostCmd_CMD_802_11_RF_ANTENNA 0x0020 282#define HostCmd_CMD_SET_BEACON 0x0100 283#define HostCmd_CMD_SET_AID 0x010d 284#define HostCmd_CMD_SET_RF_CHANNEL 0x010a 285#define HostCmd_CMD_SET_INFRA_MODE 0x010e 286#define HostCmd_CMD_SET_G_PROTECT_FLAG 0x010f 287#define HostCmd_CMD_802_11_RTS_THSD 0x0113 288#define HostCmd_CMD_802_11_SET_SLOT 0x0114 289 290#define HostCmd_CMD_802_11H_DETECT_RADAR 0x0120 291#define HostCmd_CMD_SET_WMM_MODE 0x0123 292#define HostCmd_CMD_HT_GUARD_INTERVAL 0x0124 293#define HostCmd_CMD_SET_FIXED_RATE 0x0126 294#define HostCmd_CMD_SET_LINKADAPT_CS_MODE 0x0129 295#define HostCmd_CMD_SET_MAC_ADDR 0x0202 296#define HostCmd_CMD_SET_RATE_ADAPT_MODE 0x0203 297#define HostCmd_CMD_GET_WATCHDOG_BITMAP 0x0205 298 299//SoftAP command code 300#define HostCmd_CMD_BSS_START 0x1100 301#define HostCmd_CMD_SET_NEW_STN 0x1111 302#define HostCmd_CMD_SET_KEEP_ALIVE 0x1112 303#define HostCmd_CMD_SET_APMODE 0x1114 304#define HostCmd_CMD_SET_SWITCH_CHANNEL 0x1121 305 306/* 307 @HWENCR@ 308 Command to update firmware encryption keys. 309*/ 310#define HostCmd_CMD_UPDATE_ENCRYPTION 0x1122 311/* 312 @11E-BA@ 313 Command to create/destroy block ACK 314*/ 315#define HostCmd_CMD_BASTREAM 0x1125 316#define HostCmd_CMD_SET_RIFS 0x1126 317#define HostCmd_CMD_SET_N_PROTECT_FLAG 0x1131 318#define HostCmd_CMD_SET_N_PROTECT_OPMODE 0x1132 319#define HostCmd_CMD_SET_OPTIMIZATION_LEVEL 0x1133 320#define HostCmd_CMD_GET_CALTABLE 0x1134 321#define HostCmd_CMD_SET_MIMOPSHT 0x1135 322#define HostCmd_CMD_GET_BEACON 0x1138 323#define HostCmd_CMD_SET_REGION_CODE 0x1139 324#define HostCmd_CMD_SET_POWERSAVESTATION 0x1140 325#define HostCmd_CMD_SET_TIM 0x1141 326#define HostCmd_CMD_GET_TIM 0x1142 327#define HostCmd_CMD_GET_SEQNO 0x1143 328#define HostCmd_CMD_DWDS_ENABLE 0x1144 329#define HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE 0x1145 330#define HostCmd_CMD_CFEND_ENABLE 0x1146 331 332/* 333// Define general result code for each command 334 */ 335#define HostCmd_RESULT_OK 0x0000 // OK 336#define HostCmd_RESULT_ERROR 0x0001 // Genenral error 337#define HostCmd_RESULT_NOT_SUPPORT 0x0002 // Command is not valid 338#define HostCmd_RESULT_PENDING 0x0003 // Command is pending (will be processed) 339#define HostCmd_RESULT_BUSY 0x0004 // System is busy (command ignored) 340#define HostCmd_RESULT_PARTIAL_DATA 0x0005 // Data buffer is not big enough 341 342/* 343// Definition of action or option for each command 344// 345// Define general purpose action 346 */ 347#define HostCmd_ACT_GEN_READ 0x0000 348#define HostCmd_ACT_GEN_WRITE 0x0001 349#define HostCmd_ACT_GEN_GET 0x0000 350#define HostCmd_ACT_GEN_SET 0x0001 351#define HostCmd_ACT_GEN_OFF 0x0000 352#define HostCmd_ACT_GEN_ON 0x0001 353 354#define HostCmd_ACT_DIFF_CHANNEL 0x0002 355#define HostCmd_ACT_GEN_SET_LIST 0x0002 356 357// Define action or option for HostCmd_FW_USE_FIXED_RATE 358#define HostCmd_ACT_USE_FIXED_RATE 0x0001 359#define HostCmd_ACT_NOT_USE_FIXED_RATE 0x0002 360 361// Define action or option for HostCmd_CMD_802_11_SET_WEP 362//#define HostCmd_ACT_ENABLE 0x0001 // Use MAC control for WEP on/off 363//#define HostCmd_ACT_DISABLE 0x0000 364#define HostCmd_ACT_ADD 0x0002 365#define HostCmd_ACT_REMOVE 0x0004 366#define HostCmd_ACT_USE_DEFAULT 0x0008 367 368#define HostCmd_TYPE_WEP_40_BIT 0x0001 // 40 bit 369#define HostCmd_TYPE_WEP_104_BIT 0x0002 // 104 bit 370#define HostCmd_TYPE_WEP_128_BIT 0x0003 // 128 bit 371#define HostCmd_TYPE_WEP_TX_KEY 0x0004 // TX WEP 372 373#define HostCmd_NUM_OF_WEP_KEYS 4 374 375#define HostCmd_WEP_KEY_INDEX_MASK 0x3fffffff 376 377// Define action or option for HostCmd_CMD_802_11_RESET 378#define HostCmd_ACT_HALT 0x0001 379#define HostCmd_ACT_RESTART 0x0002 380 381// Define action or option for HostCmd_CMD_802_11_RADIO_CONTROL 382#define HostCmd_TYPE_AUTO_PREAMBLE 0x0001 383#define HostCmd_TYPE_SHORT_PREAMBLE 0x0002 384#define HostCmd_TYPE_LONG_PREAMBLE 0x0003 385 386// Define action or option for CMD_802_11_RF_CHANNEL 387#define HostCmd_TYPE_802_11A 0x0001 388#define HostCmd_TYPE_802_11B 0x0002 389 390// Define action or option for HostCmd_CMD_802_11_RF_TX_POWER 391#define HostCmd_ACT_TX_POWER_OPT_SET_HIGH 0x0003 392#define HostCmd_ACT_TX_POWER_OPT_SET_MID 0x0002 393#define HostCmd_ACT_TX_POWER_OPT_SET_LOW 0x0001 394#define HostCmd_ACT_TX_POWER_OPT_SET_AUTO 0x0000 395 396#define HostCmd_ACT_TX_POWER_LEVEL_MIN 0x000e // in dbm 397#define HostCmd_ACT_TX_POWER_LEVEL_GAP 0x0001 // in dbm 398// Define action or option for HostCmd_CMD_802_11_DATA_RATE 399#define HostCmd_ACT_SET_TX_AUTO 0x0000 400#define HostCmd_ACT_SET_TX_FIX_RATE 0x0001 401#define HostCmd_ACT_GET_TX_RATE 0x0002 402 403#define HostCmd_ACT_SET_RX 0x0001 404#define HostCmd_ACT_SET_TX 0x0002 405#define HostCmd_ACT_SET_BOTH 0x0003 406#define HostCmd_ACT_GET_RX 0x0004 407#define HostCmd_ACT_GET_TX 0x0008 408#define HostCmd_ACT_GET_BOTH 0x000c 409 410#define TYPE_ANTENNA_DIVERSITY 0xffff 411 412// Define action or option for HostCmd_CMD_802_11_PS_MODE 413#define HostCmd_TYPE_CAM 0x0000 414#define HostCmd_TYPE_MAX_PSP 0x0001 415#define HostCmd_TYPE_FAST_PSP 0x0002 416 417#define HostCmd_CMD_SET_EDCA_PARAMS 0x0115 418 419//============================================================================= 420// HOST COMMAND DEFINITIONS 421//============================================================================= 422 423// 424// Definition of data structure for each command 425// 426// Define general data structure 427typedef struct { 428 uint16_t Cmd; 429 uint16_t Length; 430#ifdef MWL_MBSS_SUPPORT 431 uint8_t SeqNum; 432 uint8_t MacId; 433#else 434 uint16_t SeqNum; 435#endif 436 uint16_t Result; 437} __packed FWCmdHdr; 438 439typedef struct { 440 FWCmdHdr CmdHdr; 441 uint8_t Version; // HW revision 442 uint8_t HostIf; // Host interface 443 uint16_t NumOfMCastAdr; // Max. number of Multicast address FW can handle 444 uint8_t PermanentAddr[6]; // MAC address 445 uint16_t RegionCode; // Region Code 446 uint32_t FWReleaseNumber; // 4 byte of FW release number 447 uint32_t ulFwAwakeCookie; // Firmware awake cookie 448 uint32_t DeviceCaps; // Device capabilities (see above) 449 uint32_t RxPdWrPtr; // Rx shared memory queue 450 uint32_t NumTxQueues; // # TX queues in WcbBase array 451 uint32_t WcbBase[MAX_TXWCB_QUEUES]; // TX WCB Rings 452 uint32_t Flags; 453#define SET_HW_SPEC_DISABLEMBSS 0x08 454#define SET_HW_SPEC_HOSTFORM_BEACON 0x10 455#define SET_HW_SPEC_HOSTFORM_PROBERESP 0x20 456#define SET_HW_SPEC_HOST_POWERSAVE 0x40 457#define SET_HW_SPEC_HOSTENCRDECR_MGMT 0x80 458 uint32_t TxWcbNumPerQueue; 459 uint32_t TotalRxWcb; 460} __packed HostCmd_DS_SET_HW_SPEC; 461 462typedef struct { 463 FWCmdHdr CmdHdr; 464 u_int8_t Version; /* version of the HW */ 465 u_int8_t HostIf; /* host interface */ 466 u_int16_t NumOfWCB; /* Max. number of WCB FW can handle */ 467 u_int16_t NumOfMCastAddr; /* MaxNbr of MC addresses FW can handle */ 468 u_int8_t PermanentAddr[6]; /* MAC address programmed in HW */ 469 u_int16_t RegionCode; 470 u_int16_t NumberOfAntenna; /* Number of antenna used */ 471 u_int32_t FWReleaseNumber; /* 4 byte of FW release number */ 472 u_int32_t WcbBase0; 473 u_int32_t RxPdWrPtr; 474 u_int32_t RxPdRdPtr; 475 u_int32_t ulFwAwakeCookie; 476 u_int32_t WcbBase1[TOTAL_TX_QUEUES-1]; 477} __packed HostCmd_DS_GET_HW_SPEC; 478 479typedef struct { 480 FWCmdHdr CmdHdr; 481 u_int32_t Enable; /* FALSE: Disable or TRUE: Enable */ 482} __packed HostCmd_DS_BSS_START; 483 484typedef struct { 485 u_int8_t ElemId; 486 u_int8_t Len; 487 u_int8_t OuiType[4]; /* 00:50:f2:01 */ 488 u_int8_t Ver[2]; 489 u_int8_t GrpKeyCipher[4]; 490 u_int8_t PwsKeyCnt[2]; 491 u_int8_t PwsKeyCipherList[4]; 492 u_int8_t AuthKeyCnt[2]; 493 u_int8_t AuthKeyList[4]; 494} __packed RsnIE_t; 495 496typedef struct { 497 u_int8_t ElemId; 498 u_int8_t Len; 499 u_int8_t Ver[2]; 500 u_int8_t GrpKeyCipher[4]; 501 u_int8_t PwsKeyCnt[2]; 502 u_int8_t PwsKeyCipherList[4]; 503 u_int8_t AuthKeyCnt[2]; 504 u_int8_t AuthKeyList[4]; 505 u_int8_t RsnCap[2]; 506} __packed Rsn48IE_t; 507 508typedef struct { 509 u_int8_t ElementId; 510 u_int8_t Len; 511 u_int8_t CfpCnt; 512 u_int8_t CfpPeriod; 513 u_int16_t CfpMaxDuration; 514 u_int16_t CfpDurationRemaining; 515} __packed CfParams_t; 516 517typedef struct { 518 u_int8_t ElementId; 519 u_int8_t Len; 520 u_int16_t AtimWindow; 521} __packed IbssParams_t; 522 523typedef union { 524 CfParams_t CfParamSet; 525 IbssParams_t IbssParamSet; 526} __packed SsParams_t; 527 528typedef struct { 529 u_int8_t ElementId; 530 u_int8_t Len; 531 u_int16_t DwellTime; 532 u_int8_t HopSet; 533 u_int8_t HopPattern; 534 u_int8_t HopIndex; 535} __packed FhParams_t; 536 537typedef struct { 538 u_int8_t ElementId; 539 u_int8_t Len; 540 u_int8_t CurrentChan; 541} __packed DsParams_t; 542 543typedef union { 544 FhParams_t FhParamSet; 545 DsParams_t DsParamSet; 546} __packed PhyParams_t; 547 548typedef struct { 549 u_int8_t FirstChannelNum; 550 u_int8_t NumOfChannels; 551 u_int8_t MaxTxPwrLevel; 552} __packed ChannelInfo_t; 553 554typedef struct { 555 u_int8_t ElementId; 556 u_int8_t Len; 557 u_int8_t CountryStr[3]; 558 ChannelInfo_t ChannelInfo[40]; 559} __packed Country_t; 560 561typedef struct { 562 u_int8_t AIFSN : 4; 563 u_int8_t ACM : 1; 564 u_int8_t ACI : 2; 565 u_int8_t rsvd : 1; 566 567}__packed ACIAIFSN_field_t; 568 569typedef struct { 570 u_int8_t ECW_min : 4; 571 u_int8_t ECW_max : 4; 572}__packed ECWmin_max_field_t; 573 574typedef struct { 575 ACIAIFSN_field_t ACI_AIFSN; 576 ECWmin_max_field_t ECW_min_max; 577 u_int16_t TXOP_lim; 578}__packed ACparam_rcd_t; 579 580typedef struct { 581 u_int8_t ElementId; 582 u_int8_t Len; 583 u_int8_t OUI[3]; 584 u_int8_t Type; 585 u_int8_t Subtype; 586 u_int8_t version; 587 u_int8_t rsvd; 588 ACparam_rcd_t AC_BE; 589 ACparam_rcd_t AC_BK; 590 ACparam_rcd_t AC_VI; 591 ACparam_rcd_t AC_VO; 592} __packed WMM_param_elem_t ; 593 594typedef struct { 595#ifdef MWL_MBSS_SUPPORT 596 u_int8_t StaMacAddr[6]; 597#endif 598 u_int8_t SsId[32]; 599 u_int8_t BssType; 600 u_int16_t BcnPeriod; 601 u_int8_t DtimPeriod; 602 SsParams_t SsParamSet; 603 PhyParams_t PhyParamSet; 604 u_int16_t ProbeDelay; 605 u_int16_t CapInfo; /* see below */ 606 u_int8_t BssBasicRateSet[14]; 607 u_int8_t OpRateSet[14]; 608 RsnIE_t RsnIE; 609 Rsn48IE_t Rsn48IE; 610 WMM_param_elem_t WMMParam; 611 Country_t Country; 612 u_int32_t ApRFType; /* 0->B, 1->G, 2->Mixed, 3->A, 4->11J */ 613} __packed StartCmd_t; 614 615#define HostCmd_CAPINFO_DEFAULT 0x0000 616#define HostCmd_CAPINFO_ESS 0x0001 617#define HostCmd_CAPINFO_IBSS 0x0002 618#define HostCmd_CAPINFO_CF_POLLABLE 0x0004 619#define HostCmd_CAPINFO_CF_REQUEST 0x0008 620#define HostCmd_CAPINFO_PRIVACY 0x0010 621#define HostCmd_CAPINFO_SHORT_PREAMBLE 0x0020 622#define HostCmd_CAPINFO_PBCC 0x0040 623#define HostCmd_CAPINFO_CHANNEL_AGILITY 0x0080 624#define HostCmd_CAPINFO_SHORT_SLOT 0x0400 625#define HostCmd_CAPINFO_DSSS_OFDM 0x2000 626 627typedef struct { 628 FWCmdHdr CmdHdr; 629 StartCmd_t StartCmd; 630} __packed HostCmd_DS_AP_BEACON; 631 632typedef struct { 633 FWCmdHdr CmdHdr; 634 uint16_t FrmBodyLen; 635 uint8_t FrmBody[1]; /* NB: variable length */ 636} __packed HostCmd_DS_SET_BEACON; 637 638// Define data structure for HostCmd_CMD_MAC_MULTICAST_ADR 639typedef struct { 640 FWCmdHdr CmdHdr; 641 uint16_t Action; 642 uint16_t NumOfAdrs; 643#define MWL_HAL_MCAST_MAX 32 644 uint8_t MACList[6*32]; 645} __packed HostCmd_DS_MAC_MULTICAST_ADR; 646 647// Indicate to FW the current state of AP ERP info 648typedef struct { 649 FWCmdHdr CmdHdr; 650 uint32_t GProtectFlag; 651} __packed HostCmd_FW_SET_G_PROTECT_FLAG; 652 653typedef struct { 654 FWCmdHdr CmdHdr; 655} __packed HostCmd_FW_SET_INFRA_MODE; 656 657// Define data structure for HostCmd_CMD_802_11_RF_CHANNEL 658typedef struct { 659 FWCmdHdr CmdHdr; 660 uint16_t Action; 661 uint8_t CurrentChannel; /* channel # */ 662 uint32_t ChannelFlags; /* see below */ 663} __packed HostCmd_FW_SET_RF_CHANNEL; 664 665/* bits 0-5 specify frequency band */ 666#define FREQ_BAND_2DOT4GHZ 0x0001 667#define FREQ_BAND_4DOT9GHZ 0x0002 /* XXX not implemented */ 668#define FREQ_BAND_5GHZ 0x0004 669#define FREQ_BAND_5DOT2GHZ 0x0008 /* XXX not implemented */ 670/* bits 6-10 specify channel width */ 671#define CH_AUTO_WIDTH 0x0000 /* XXX not used? */ 672#define CH_10_MHz_WIDTH 0x0040 673#define CH_20_MHz_WIDTH 0x0080 674#define CH_40_MHz_WIDTH 0x0100 675/* bits 11-12 specify extension channel */ 676#define EXT_CH_NONE 0x0000 /* no extension channel */ 677#define EXT_CH_ABOVE_CTRL_CH 0x0800 /* extension channel above */ 678#define EXT_CH_AUTO 0x1000 /* XXX not used? */ 679#define EXT_CH_BELOW_CTRL_CH 0x1800 /* extension channel below */ 680/* bits 13-31 are reserved */ 681 682#define FIXED_RATE_WITH_AUTO_RATE_DROP 0 683#define FIXED_RATE_WITHOUT_AUTORATE_DROP 1 684 685#define LEGACY_RATE_TYPE 0 686#define HT_RATE_TYPE 1 687 688#define RETRY_COUNT_VALID 0 689#define RETRY_COUNT_INVALID 1 690 691typedef struct { 692 // lower rate after the retry count 693 uint32_t FixRateType; //0: legacy, 1: HT 694 uint32_t RetryCountValid; //0: retry count is not valid, 1: use retry count specified 695} __packed FIX_RATE_FLAG; 696 697typedef struct { 698 FIX_RATE_FLAG FixRateTypeFlags; 699 uint32_t FixedRate; // legacy rate(not index) or an MCS code. 700 uint32_t RetryCount; 701} __packed FIXED_RATE_ENTRY; 702 703typedef struct { 704 FWCmdHdr CmdHdr; 705 uint32_t Action; //HostCmd_ACT_GEN_GET 0x0000 706 //HostCmd_ACT_GEN_SET 0x0001 707 //HostCmd_ACT_NOT_USE_FIXED_RATE 0x0002 708 uint32_t AllowRateDrop; // use fixed rate specified but firmware can drop to 709 uint32_t EntryCount; 710 FIXED_RATE_ENTRY FixedRateTable[4]; 711 uint8_t MulticastRate; 712 uint8_t MultiRateTxType; 713 uint8_t ManagementRate; 714} __packed HostCmd_FW_USE_FIXED_RATE; 715 716typedef struct { 717 uint32_t AllowRateDrop; 718 uint32_t EntryCount; 719 FIXED_RATE_ENTRY FixedRateTable[4]; 720} __packed USE_FIXED_RATE_INFO; 721 722typedef struct { 723 FWCmdHdr CmdHdr; 724 uint32_t Action; 725 uint32_t GIType; 726#define GI_TYPE_LONG 0x0001 727#define GI_TYPE_SHORT 0x0002 728} __packed HostCmd_FW_HT_GUARD_INTERVAL; 729 730typedef struct { 731 FWCmdHdr CmdHdr; 732 uint32_t Action; 733 uint8_t RxAntennaMap; 734 uint8_t TxAntennaMap; 735} __packed HostCmd_FW_HT_MIMO_CONFIG; 736 737typedef struct { 738 FWCmdHdr CmdHdr; 739 uint16_t Action; 740 uint8_t Slot; // Slot=0 if regular, Slot=1 if short. 741} __packed HostCmd_FW_SET_SLOT; 742 743// Define data structure for HostCmd_CMD_802_11_GET_STAT 744typedef struct { 745 FWCmdHdr CmdHdr; 746 uint32_t TxRetrySuccesses; 747 uint32_t TxMultipleRetrySuccesses; 748 uint32_t TxFailures; 749 uint32_t RTSSuccesses; 750 uint32_t RTSFailures; 751 uint32_t AckFailures; 752 uint32_t RxDuplicateFrames; 753 uint32_t FCSErrorCount; 754 uint32_t TxWatchDogTimeouts; 755 uint32_t RxOverflows; //used 756 uint32_t RxFragErrors; //used 757 uint32_t RxMemErrors; //used 758 uint32_t PointerErrors; //used 759 uint32_t TxUnderflows; //used 760 uint32_t TxDone; 761 uint32_t TxDoneBufTryPut; 762 uint32_t TxDoneBufPut; 763 uint32_t Wait4TxBuf; // Put size of requested buffer in here 764 uint32_t TxAttempts; 765 uint32_t TxSuccesses; 766 uint32_t TxFragments; 767 uint32_t TxMulticasts; 768 uint32_t RxNonCtlPkts; 769 uint32_t RxMulticasts; 770 uint32_t RxUndecryptableFrames; 771 uint32_t RxICVErrors; 772 uint32_t RxExcludedFrames; 773} __packed HostCmd_DS_802_11_GET_STAT; 774 775// Define data structure for HostCmd_CMD_MAC_REG_ACCESS 776typedef struct { 777 FWCmdHdr CmdHdr; 778 uint16_t Action; 779 uint16_t Offset; 780 uint32_t Value; 781 uint16_t Reserved; 782} __packed HostCmd_DS_MAC_REG_ACCESS; 783 784// Define data structure for HostCmd_CMD_BBP_REG_ACCESS 785typedef struct { 786 FWCmdHdr CmdHdr; 787 uint16_t Action; 788 uint16_t Offset; 789 uint8_t Value; 790 uint8_t Reserverd[3]; 791} __packed HostCmd_DS_BBP_REG_ACCESS; 792 793// Define data structure for HostCmd_CMD_RF_REG_ACCESS 794typedef struct { 795 FWCmdHdr CmdHdr; 796 uint16_t Action; 797 uint16_t Offset; 798 uint8_t Value; 799 uint8_t Reserverd[3]; 800} __packed HostCmd_DS_RF_REG_ACCESS; 801 802// Define data structure for HostCmd_CMD_802_11_RADIO_CONTROL 803typedef struct { 804 FWCmdHdr CmdHdr; 805 uint16_t Action; 806 uint16_t Control; // @bit0: 1/0,on/off, @bit1: 1/0, long/short @bit2: 1/0,auto/fix 807 uint16_t RadioOn; 808} __packed HostCmd_DS_802_11_RADIO_CONTROL; 809 810#define TX_POWER_LEVEL_TOTAL 8 811// Define data structure for HostCmd_CMD_802_11_RF_TX_POWER 812typedef struct { 813 FWCmdHdr CmdHdr; 814 uint16_t Action; 815 uint16_t SupportTxPowerLevel; 816 uint16_t CurrentTxPowerLevel; 817 uint16_t Reserved; 818 uint16_t PowerLevelList[TX_POWER_LEVEL_TOTAL]; 819} __packed HostCmd_DS_802_11_RF_TX_POWER; 820 821// Define data structure for HostCmd_CMD_802_11_RF_ANTENNA 822typedef struct _HostCmd_DS_802_11_RF_ANTENNA { 823 FWCmdHdr CmdHdr; 824 uint16_t Action; 825 uint16_t AntennaMode; // Number of antennas or 0xffff(diversity) 826} __packed HostCmd_DS_802_11_RF_ANTENNA; 827 828// Define data structure for HostCmd_CMD_802_11_PS_MODE 829typedef struct { 830 FWCmdHdr CmdHdr; 831 uint16_t Action; 832 uint16_t PowerMode; // CAM, Max.PSP or Fast PSP 833} __packed HostCmd_DS_802_11_PS_MODE; 834 835typedef struct { 836 FWCmdHdr CmdHdr; 837 uint16_t Action; 838 uint16_t Threshold; 839} __packed HostCmd_DS_802_11_RTS_THSD; 840 841// used for stand alone bssid sets/clears 842typedef struct { 843 FWCmdHdr CmdHdr; 844#ifdef MWL_MBSS_SUPPORT 845 uint16_t MacType; 846#define WL_MAC_TYPE_PRIMARY_CLIENT 0 847#define WL_MAC_TYPE_SECONDARY_CLIENT 1 848#define WL_MAC_TYPE_PRIMARY_AP 2 849#define WL_MAC_TYPE_SECONDARY_AP 3 850#endif 851 uint8_t MacAddr[6]; 852} __packed HostCmd_DS_SET_MAC, 853 HostCmd_FW_SET_BSSID, 854 HostCmd_FW_SET_MAC; 855 856// Indicate to FW to send out PS Poll 857typedef struct { 858 FWCmdHdr CmdHdr; 859 uint32_t PSPoll; 860} __packed HostCmd_FW_TX_POLL; 861 862// used for AID sets/clears 863typedef struct { 864 FWCmdHdr CmdHdr; 865 uint16_t AssocID; 866 uint8_t MacAddr[6]; //AP's Mac Address(BSSID) 867 uint32_t GProtection; 868 uint8_t ApRates[ RATE_INDEX_MAX_ARRAY]; 869} __packed HostCmd_FW_SET_AID; 870 871typedef struct { 872 uint32_t LegacyRateBitMap; 873 uint32_t HTRateBitMap; 874 uint16_t CapInfo; 875 uint16_t HTCapabilitiesInfo; 876 uint8_t MacHTParamInfo; 877 uint8_t Rev; 878 struct { 879 uint8_t ControlChan; 880 uint8_t AddChan; 881 uint16_t OpMode; 882 uint16_t stbc; 883 } __packed AddHtInfo; 884} __packed PeerInfo_t; 885 886typedef struct { 887 FWCmdHdr CmdHdr; 888 uint16_t AID; 889 uint8_t MacAddr[6]; 890 uint16_t StnId; 891 uint16_t Action; 892 uint16_t Reserved; 893 PeerInfo_t PeerInfo; 894 uint8_t Qosinfo; 895 uint8_t isQosSta; 896 uint32_t FwStaPtr; 897} __packed HostCmd_FW_SET_NEW_STN; 898 899typedef struct { 900 FWCmdHdr CmdHdr; 901 uint8_t tick; 902} __packed HostCmd_FW_SET_KEEP_ALIVE_TICK; 903 904typedef struct { 905 FWCmdHdr CmdHdr; 906 uint8_t QNum; 907} __packed HostCmd_FW_SET_RIFS; 908 909typedef struct { 910 FWCmdHdr CmdHdr; 911 uint8_t ApMode; 912} __packed HostCmd_FW_SET_APMODE; 913 914typedef struct { 915 FWCmdHdr CmdHdr; 916 uint16_t Action; // see following 917 uint16_t RadarTypeCode; 918} __packed HostCmd_802_11h_Detect_Radar; 919 920#define DR_DFS_DISABLE 0 921#define DR_CHK_CHANNEL_AVAILABLE_START 1 922#define DR_CHK_CHANNEL_AVAILABLE_STOP 2 923#define DR_IN_SERVICE_MONITOR_START 3 924 925//New Structure for Update Tim 30/9/2003 926typedef struct { 927 FWCmdHdr CmdHdr; 928 uint16_t Aid; 929 uint32_t Set; 930} __packed HostCmd_UpdateTIM; 931 932typedef struct { 933 FWCmdHdr CmdHdr; 934 uint32_t SsidBroadcastEnable; 935} __packed HostCmd_SSID_BROADCAST; 936 937typedef struct { 938 FWCmdHdr CmdHdr; 939 uint32_t WdsEnable; 940} __packed HostCmd_WDS; 941 942typedef struct { 943 FWCmdHdr CmdHdr; 944 uint32_t Next11hChannel; 945 uint32_t Mode; 946 uint32_t InitialCount; 947 uint32_t ChannelFlags ; 948} __packed HostCmd_SET_SWITCH_CHANNEL; 949 950typedef struct { 951 FWCmdHdr CmdHdr; 952 uint32_t SpectrumMgmt; 953} __packed HostCmd_SET_SPECTRUM_MGMT; 954 955typedef struct { 956 FWCmdHdr CmdHdr; 957 int32_t PowerConstraint; 958} __packed HostCmd_SET_POWER_CONSTRAINT; 959 960typedef struct { 961 uint8_t FirstChannelNo; 962 uint8_t NoofChannel; 963 uint8_t MaxTransmitPw; 964} __packed DomainChannelEntry; 965 966typedef struct { 967 uint8_t CountryString[3]; 968 uint8_t GChannelLen; 969 DomainChannelEntry DomainEntryG[1]; /** Assume only 1 G zone **/ 970 uint8_t AChannelLen; 971 DomainChannelEntry DomainEntryA[20]; /** Assume max of 5 A zone **/ 972} __packed DomainCountryInfo; 973 974typedef struct { 975 FWCmdHdr CmdHdr; 976 uint32_t Action ; // 0 -> unset, 1 ->set 977 DomainCountryInfo DomainInfo ; 978} __packed HostCmd_SET_COUNTRY_INFO; 979 980typedef struct { 981 FWCmdHdr CmdHdr; 982 uint16_t regionCode ; 983} __packed HostCmd_SET_REGIONCODE_INFO; 984 985// for HostCmd_CMD_SET_WMM_MODE 986typedef struct { 987 FWCmdHdr CmdHdr; 988 uint16_t Action; // 0->unset, 1->set 989} __packed HostCmd_FW_SetWMMMode; 990 991typedef struct { 992 FWCmdHdr CmdHdr; 993 uint16_t Action; // 0->unset, 1->set 994 uint16_t IeListLen; 995 uint8_t IeList[200]; 996} __packed HostCmd_FW_SetIEs; 997 998#define EDCA_PARAM_SIZE 18 999#define BA_PARAM_SIZE 2 1000 1001typedef struct { 1002 FWCmdHdr CmdHdr; 1003 uint16_t Action; //0 = get all, 0x1 =set CWMin/Max, 0x2 = set TXOP , 0x4 =set AIFSN 1004 uint16_t TxOP; // in unit of 32 us 1005 uint32_t CWMax; // 0~15 1006 uint32_t CWMin; // 0~15 1007 uint8_t AIFSN; 1008 uint8_t TxQNum; // Tx Queue number. 1009} __packed HostCmd_FW_SET_EDCA_PARAMS; 1010 1011/****************************************************************************** 1012 @HWENCR@ 1013 Hardware Encryption related data structures and constant definitions. 1014 Note that all related changes are marked with the @HWENCR@ tag. 1015*******************************************************************************/ 1016 1017#define MAX_ENCR_KEY_LENGTH 16 /* max 128 bits - depends on type */ 1018#define MIC_KEY_LENGTH 8 /* size of Tx/Rx MIC key - 8 bytes*/ 1019 1020#define ENCR_KEY_TYPE_ID_WEP 0x00 /* Key type is WEP */ 1021#define ENCR_KEY_TYPE_ID_TKIP 0x01 /* Key type is TKIP */ 1022#define ENCR_KEY_TYPE_ID_AES 0x02 /* Key type is AES-CCMP */ 1023 1024/* flags used in structure - same as driver EKF_XXX flags */ 1025#define ENCR_KEY_FLAG_INUSE 0x00000001 /* indicate key is in use */ 1026#define ENCR_KEY_FLAG_RXGROUPKEY 0x00000002 /* Group key for RX only */ 1027#define ENCR_KEY_FLAG_TXGROUPKEY 0x00000004 /* Group key for TX */ 1028#define ENCR_KEY_FLAG_PAIRWISE 0x00000008 /* pairwise */ 1029#define ENCR_KEY_FLAG_RXONLY 0x00000010 /* only used for RX */ 1030// These flags are new additions - for hardware encryption commands only. 1031#define ENCR_KEY_FLAG_AUTHENTICATOR 0x00000020 /* Key is for Authenticator */ 1032#define ENCR_KEY_FLAG_TSC_VALID 0x00000040 /* Sequence counters valid */ 1033#define ENCR_KEY_FLAG_WEP_TXKEY 0x01000000 /* Tx key for WEP */ 1034#define ENCR_KEY_FLAG_MICKEY_VALID 0x02000000 /* Tx/Rx MIC keys are valid */ 1035 1036/* 1037 UPDATE_ENCRYPTION command action type. 1038*/ 1039typedef enum { 1040 // request to enable/disable HW encryption 1041 EncrActionEnableHWEncryption, 1042 // request to set encryption key 1043 EncrActionTypeSetKey, 1044 // request to remove one or more keys 1045 EncrActionTypeRemoveKey, 1046 EncrActionTypeSetGroupKey 1047} ENCR_ACTION_TYPE; 1048 1049/* 1050 Key material definitions (for WEP, TKIP, & AES-CCMP) 1051*/ 1052 1053/* 1054 WEP Key material definition 1055 ---------------------------- 1056 WEPKey --> An array of 'MAX_ENCR_KEY_LENGTH' bytes. 1057 Note that we do not support 152bit WEP keys 1058*/ 1059typedef struct { 1060 // WEP key material (max 128bit) 1061 uint8_t KeyMaterial[ MAX_ENCR_KEY_LENGTH ]; 1062} __packed WEP_TYPE_KEY; 1063 1064/* 1065 TKIP Key material definition 1066 ---------------------------- 1067 This structure defines TKIP key material. Note that 1068 the TxMicKey and RxMicKey may or may not be valid. 1069*/ 1070/* TKIP Sequence counter - 24 bits */ 1071/* Incremented on each fragment MPDU */ 1072typedef struct { 1073 uint16_t low; 1074 uint32_t high; 1075} __packed ENCR_TKIPSEQCNT; 1076 1077typedef struct { 1078 // TKIP Key material. Key type (group or pairwise key) is 1079 // determined by flags in KEY_PARAM_SET structure. 1080 uint8_t KeyMaterial[ MAX_ENCR_KEY_LENGTH ]; 1081 uint8_t TkipTxMicKey[ MIC_KEY_LENGTH ]; 1082 uint8_t TkipRxMicKey[ MIC_KEY_LENGTH ]; 1083 ENCR_TKIPSEQCNT TkipRsc; 1084 ENCR_TKIPSEQCNT TkipTsc; 1085} __packed TKIP_TYPE_KEY; 1086 1087/* 1088 AES-CCMP Key material definition 1089 -------------------------------- 1090 This structure defines AES-CCMP key material. 1091*/ 1092typedef struct { 1093 // AES Key material 1094 uint8_t KeyMaterial[ MAX_ENCR_KEY_LENGTH ]; 1095} __packed AES_TYPE_KEY; 1096 1097/* 1098 Encryption key definition. 1099 -------------------------- 1100 This structure provides all required/essential 1101 information about the key being set/removed. 1102*/ 1103typedef struct { 1104 uint16_t Length; // Total length of this structure 1105 uint16_t KeyTypeId; // Key type - WEP, TKIP or AES-CCMP. 1106 uint32_t KeyInfo; // key flags (ENCR_KEY_FLAG_XXX_ 1107 uint32_t KeyIndex; // For WEP only - actual key index 1108 uint16_t KeyLen; // Size of the key 1109 union { // Key material (variable size array) 1110 WEP_TYPE_KEY WepKey; 1111 TKIP_TYPE_KEY TkipKey; 1112 AES_TYPE_KEY AesKey; 1113 }__packed Key; 1114#ifdef MWL_MBSS_SUPPORT 1115 uint8_t Macaddr[6]; 1116#endif 1117} __packed KEY_PARAM_SET; 1118 1119/* 1120 HostCmd_FW_UPDATE_ENCRYPTION 1121 ---------------------------- 1122 Define data structure for updating firmware encryption keys. 1123 1124*/ 1125typedef struct { 1126 FWCmdHdr CmdHdr; 1127 uint32_t ActionType; // ENCR_ACTION_TYPE 1128 uint32_t DataLength; // size of the data buffer attached. 1129#ifdef MWL_MBSS_SUPPORT 1130 uint8_t macaddr[6]; 1131#endif 1132 uint8_t ActionData[1]; 1133} __packed HostCmd_FW_UPDATE_ENCRYPTION; 1134 1135typedef struct { 1136 FWCmdHdr CmdHdr; 1137 uint32_t ActionType; // ENCR_ACTION_TYPE 1138 uint32_t DataLength; // size of the data buffer attached. 1139 KEY_PARAM_SET KeyParam; 1140#ifndef MWL_MBSS_SUPPORT 1141 uint8_t Macaddr[8]; /* XXX? */ 1142#endif 1143} __packed HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY; 1144 1145typedef struct { 1146 // Rate flags - see above. 1147 uint32_t Flags; 1148 // Rate in 500Kbps units. 1149 uint8_t RateKbps; 1150 // 802.11 rate to conversion table index value. 1151 // This is the value required by the firmware/hardware. 1152 uint16_t RateCodeToIndex; 1153}__packed RATE_INFO; 1154 1155/* 1156 UPDATE_STADB command action type. 1157*/ 1158typedef enum { 1159 // request to add entry to stainfo db 1160 StaInfoDbActionAddEntry, 1161 // request to modify peer entry 1162 StaInfoDbActionModifyEntry, 1163 // request to remove peer from stainfo db 1164 StaInfoDbActionRemoveEntry 1165}__packed STADB_ACTION_TYPE; 1166 1167/* 1168 @11E-BA@ 1169 802.11e/WMM Related command(s)/data structures 1170*/ 1171 1172// Flag to indicate if the stream is an immediate block ack stream. 1173// if this bit is not set, the stream is delayed block ack stream. 1174#define BASTREAM_FLAG_DELAYED_TYPE 0x00 1175#define BASTREAM_FLAG_IMMEDIATE_TYPE 0x01 1176 1177// Flag to indicate the direction of the stream (upstream/downstream). 1178// If this bit is not set, the direction is downstream. 1179#define BASTREAM_FLAG_DIRECTION_UPSTREAM 0x00 1180#define BASTREAM_FLAG_DIRECTION_DOWNSTREAM 0x02 1181#define BASTREAM_FLAG_DIRECTION_DLP 0x04 1182#define BASTREAM_FLAG_DIRECTION_BOTH 0x06 1183 1184typedef enum { 1185 BaCreateStream, 1186 BaUpdateStream, 1187 BaDestroyStream, 1188 BaFlushStream, 1189 BaCheckCreateStream 1190} BASTREAM_ACTION_TYPE; 1191 1192typedef struct { 1193 uint32_t Context; 1194} __packed BASTREAM_CONTEXT; 1195 1196// parameters for block ack creation 1197typedef struct { 1198 // BA Creation flags - see above 1199 uint32_t Flags; 1200 // idle threshold 1201 uint32_t IdleThrs; 1202 // block ack transmit threshold (after how many pkts should we send BAR?) 1203 uint32_t BarThrs; 1204 // receiver window size 1205 uint32_t WindowSize; 1206 // MAC Address of the BA partner 1207 uint8_t PeerMacAddr[6]; 1208 // Dialog Token 1209 uint8_t DialogToken; 1210 //TID for the traffic stream in this BA 1211 uint8_t Tid; 1212 // shared memory queue ID (not sure if this is required) 1213 uint8_t QueueId; 1214 uint8_t ParamInfo; 1215 // returned by firmware - firmware context pointer. 1216 // this context pointer will be passed to firmware for all future commands. 1217 BASTREAM_CONTEXT FwBaContext; 1218 uint8_t ResetSeqNo; /** 0 or 1**/ 1219 uint16_t StartSeqNo; 1220 1221 // proxy sta MAC Address 1222 uint8_t StaSrcMacAddr[6]; 1223}__packed BASTREAM_CREATE_STREAM; 1224 1225// new transmit sequence number information 1226typedef struct { 1227 // BA flags - see above 1228 uint32_t Flags; 1229 // returned by firmware in the create ba stream response 1230 BASTREAM_CONTEXT FwBaContext; 1231 // new sequence number for this block ack stream 1232 uint16_t BaSeqNum; 1233}__packed BASTREAM_UPDATE_STREAM; 1234 1235typedef struct { 1236 // BA Stream flags 1237 uint32_t Flags; 1238 // returned by firmware in the create ba stream response 1239 BASTREAM_CONTEXT FwBaContext; 1240}__packed BASTREAM_STREAM_INFO; 1241 1242//Command to create/destroy block ACK 1243typedef struct { 1244 FWCmdHdr CmdHdr; 1245 uint32_t ActionType; 1246 union 1247 { 1248 // information required to create BA Stream... 1249 BASTREAM_CREATE_STREAM CreateParams; 1250 // update starting/new sequence number etc. 1251 BASTREAM_UPDATE_STREAM UpdtSeqNum; 1252 // destroy an existing stream... 1253 BASTREAM_STREAM_INFO DestroyParams; 1254 // destroy an existing stream... 1255 BASTREAM_STREAM_INFO FlushParams; 1256 }__packed BaInfo; 1257}__packed HostCmd_FW_BASTREAM; 1258 1259// Define data structure for HostCmd_CMD_GET_WATCHDOG_BITMAP 1260typedef struct { 1261 FWCmdHdr CmdHdr; 1262 uint8_t Watchdogbitmap; // for SW/BA 1263} __packed HostCmd_FW_GET_WATCHDOG_BITMAP; 1264 1265// Define data structure for HostCmd_CMD_SET_REGION_POWER 1266typedef struct { 1267 FWCmdHdr CmdHdr; 1268 uint16_t MaxPowerLevel; 1269 uint16_t Reserved; 1270} __packed HostCmd_DS_SET_REGION_POWER; 1271 1272// Define data structure for HostCmd_CMD_SET_RATE_ADAPT_MODE 1273typedef struct { 1274 FWCmdHdr CmdHdr; 1275 uint16_t Action; 1276 uint16_t RateAdaptMode; 1277} __packed HostCmd_DS_SET_RATE_ADAPT_MODE; 1278 1279// Define data structure for HostCmd_CMD_SET_LINKADAPT_CS_MODE 1280typedef struct { 1281 FWCmdHdr CmdHdr; 1282 uint16_t Action; 1283 uint16_t CSMode; 1284} __packed HostCmd_DS_SET_LINKADAPT_CS_MODE; 1285 1286typedef struct { 1287 FWCmdHdr CmdHdr; 1288 uint32_t NProtectFlag; 1289} __packed HostCmd_FW_SET_N_PROTECT_FLAG; 1290 1291typedef struct { 1292 FWCmdHdr CmdHdr; 1293 uint8_t NProtectOpMode; 1294} __packed HostCmd_FW_SET_N_PROTECT_OPMODE; 1295 1296typedef struct { 1297 FWCmdHdr CmdHdr; 1298 uint8_t OptLevel; 1299} __packed HostCmd_FW_SET_OPTIMIZATION_LEVEL; 1300 1301typedef struct { 1302 FWCmdHdr CmdHdr; 1303 uint8_t annex; 1304 uint8_t index; 1305 uint8_t len; 1306 uint8_t Reserverd; 1307#define CAL_TBL_SIZE 160 1308 uint8_t calTbl[CAL_TBL_SIZE]; 1309} __packed HostCmd_FW_GET_CALTABLE; 1310 1311typedef struct { 1312 FWCmdHdr CmdHdr; 1313 uint8_t Addr[6]; 1314 uint8_t Enable; 1315 uint8_t Mode; 1316} __packed HostCmd_FW_SET_MIMOPSHT; 1317 1318#define MAX_BEACON_SIZE 1024 1319typedef struct { 1320 FWCmdHdr CmdHdr; 1321 uint16_t Bcnlen; 1322 uint8_t Reserverd[2]; 1323 uint8_t Bcn[MAX_BEACON_SIZE]; 1324} __packed HostCmd_FW_GET_BEACON; 1325 1326typedef struct { 1327 FWCmdHdr CmdHdr; 1328 uint8_t NumberOfPowersave; 1329 uint8_t reserved; 1330} __packed HostCmd_SET_POWERSAVESTATION; 1331 1332typedef struct { 1333 FWCmdHdr CmdHdr; 1334 uint16_t Aid; 1335 uint32_t Set; 1336 uint8_t reserved; 1337} __packed HostCmd_SET_TIM; 1338 1339typedef struct { 1340 FWCmdHdr CmdHdr; 1341 uint8_t TrafficMap[251]; 1342 uint8_t reserved; 1343} __packed HostCmd_GET_TIM; 1344 1345typedef struct { 1346 FWCmdHdr CmdHdr; 1347 uint8_t MacAddr[6]; 1348 uint8_t TID; 1349 uint16_t SeqNo; 1350 uint8_t reserved; 1351} __packed HostCmd_GET_SEQNO; 1352 1353typedef struct { 1354 FWCmdHdr CmdHdr; 1355 uint32_t Enable; //0 -- Disbale. or 1 -- Enable. 1356} __packed HostCmd_DWDS_ENABLE; 1357 1358typedef struct { 1359 FWCmdHdr CmdHdr; 1360 uint16_t Action; /* 0: Get. 1:Set */ 1361 uint32_t Option; /* 0: default. 1:Aggressive */ 1362 uint32_t Threshold; /* Range 0-200, default 8 */ 1363}__packed HostCmd_FW_AMPDU_RETRY_RATEDROP_MODE; 1364 1365typedef struct { 1366 FWCmdHdr CmdHdr; 1367 uint32_t Enable; /* 0 -- Disable. or 1 -- Enable */ 1368}__packed HostCmd_CFEND_ENABLE; 1369#endif /* _MWL_HALREG_H_ */ 1370