1/*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Sepherosa Ziehau <sepherosa@gmail.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of The DragonFly Project nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific, prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $DragonFly: src/sys/dev/netif/bwi/if_bwireg.h,v 1.4 2007/10/19 14:27:04 sephe Exp $ 37 * $FreeBSD: releng/12.0/sys/dev/bwi/if_bwireg.h 326022 2017-11-20 19:36:21Z pfg $ 38 */ 39 40#ifndef _IF_BWIREG_H 41#define _IF_BWIREG_H 42 43/* 44 * Registers for all of the register windows 45 */ 46#define BWI_FLAGS 0xf18 47#define BWI_FLAGS_INTR_MASK __BITS(5, 0) 48 49#define BWI_IMSTATE 0xf90 50#define BWI_IMSTATE_INBAND_ERR __BIT(17) 51#define BWI_IMSTATE_TIMEOUT __BIT(18) 52 53#define BWI_INTRVEC 0xf94 54 55#define BWI_STATE_LO 0xf98 56#define BWI_STATE_LO_RESET __BIT(0) 57#define BWI_STATE_LO_DISABLE1 __BIT(1) 58#define BWI_STATE_LO_DISABLE2 __BIT(2) 59#define BWI_STATE_LO_CLOCK __BIT(16) 60#define BWI_STATE_LO_GATED_CLOCK __BIT(17) 61#define BWI_STATE_LO_FLAG_PHYCLKEN __BIT(0) 62#define BWI_STATE_LO_FLAG_PHYRST __BIT(1) 63#define BWI_STATE_LO_FLAG_PHYLNK __BIT(11) 64#define BWI_STATE_LO_FLAGS_MASK __BITS(29, 18) 65 66#define BWI_STATE_HI 0xf9c 67#define BWI_STATE_HI_SERROR __BIT(0) 68#define BWI_STATE_HI_BUSY __BIT(2) 69#define BWI_STATE_HI_FLAG_MAGIC1 0x1 70#define BWI_STATE_HI_FLAG_MAGIC2 0x2 71#define BWI_STATE_HI_FLAG_64BIT 0x1000 72#define BWI_STATE_HI_FLAGS_MASK __BITS(28, 16) 73 74#define BWI_CONF_LO 0xfa8 75#define BWI_CONF_LO_SERVTO_MASK __BITS(2, 0) /* service timeout */ 76#define BWI_CONF_LO_SERVTO 2 77#define BWI_CONF_LO_REQTO_MASK __BITS(6, 4) /* request timeout */ 78#define BWI_CONF_LO_REQTO 3 79 80#define BWI_ID_LO 0xff8 81#define BWI_ID_LO_BUSREV_MASK __BITS(31, 28) 82/* Bus revision */ 83#define BWI_BUSREV_0 0 84#define BWI_BUSREV_1 1 85 86#define BWI_ID_HI 0xffc 87#define BWI_ID_HI_REGWIN_REV(v) (((v) & 0xf) | (((v) & 0x7000) >> 8)) 88#define BWI_ID_HI_REGWIN_TYPE(v) (((v) & 0x8ff0) >> 4) 89#define BWI_ID_HI_REGWIN_VENDOR_MASK __BITS(31, 16) 90 91/* 92 * Registers for common register window 93 */ 94#define BWI_INFO 0x0 95#define BWI_INFO_BBPID_MASK __BITS(15, 0) 96#define BWI_INFO_BBPREV_MASK __BITS(19, 16) 97#define BWI_INFO_BBPPKG_MASK __BITS(23, 20) 98#define BWI_INFO_NREGWIN_MASK __BITS(27, 24) 99 100#define BWI_CAPABILITY 0x4 101#define BWI_CAP_CLKMODE __BIT(18) 102 103#define BWI_CONTROL 0x28 104#define BWI_CONTROL_MAGIC0 0x3a4 105#define BWI_CONTROL_MAGIC1 0xa4 106#define BWI_PLL_ON_DELAY 0xb0 107#define BWI_FREQ_SEL_DELAY 0xb4 108 109#define BWI_CLOCK_CTRL 0xb8 110#define BWI_CLOCK_CTRL_CLKSRC __BITS(2, 0) 111#define BWI_CLOCK_CTRL_SLOW __BIT(11) 112#define BWI_CLOCK_CTRL_IGNPLL __BIT(12) 113#define BWI_CLOCK_CTRL_NODYN __BIT(13) 114#define BWI_CLOCK_CTRL_FDIV __BITS(31, 16) /* freq divisor */ 115 116/* Possible values for BWI_CLOCK_CTRL_CLKSRC */ 117#define BWI_CLKSRC_LP_OSC 0 /* Low power oscillator */ 118#define BWI_CLKSRC_CS_OSC 1 /* Crystal oscillator */ 119#define BWI_CLKSRC_PCI 2 120#define BWI_CLKSRC_MAX 3 /* Maximum of clock source */ 121/* Min/Max frequency for given clock source */ 122#define BWI_CLKSRC_LP_OSC_FMIN 25000 123#define BWI_CLKSRC_LP_OSC_FMAX 43000 124#define BWI_CLKSRC_CS_OSC_FMIN 19800000 125#define BWI_CLKSRC_CS_OSC_FMAX 20200000 126#define BWI_CLKSRC_PCI_FMIN 25000000 127#define BWI_CLKSRC_PCI_FMAX 34000000 128 129#define BWI_CLOCK_INFO 0xc0 130#define BWI_CLOCK_INFO_FDIV __BITS(31, 16) /* freq divisor */ 131 132/* 133 * Registers for bus register window 134 */ 135#define BWI_BUS_ADDR 0x50 136#define BWI_BUS_ADDR_MAGIC 0xfd8 137 138#define BWI_BUS_DATA 0x54 139 140#define BWI_BUS_CONFIG 0x108 141#define BWI_BUS_CONFIG_PREFETCH __BIT(2) 142#define BWI_BUS_CONFIG_BURST __BIT(3) 143#define BWI_BUS_CONFIG_MRM __BIT(5) 144 145/* 146 * Register for MAC 147 */ 148#define BWI_TXRX_INTR_STATUS_BASE 0x20 149#define BWI_TXRX_INTR_MASK_BASE 0x24 150#define BWI_TXRX_INTR_STATUS(i) (BWI_TXRX_INTR_STATUS_BASE + ((i) * 8)) 151#define BWI_TXRX_INTR_MASK(i) (BWI_TXRX_INTR_MASK_BASE + ((i) * 8)) 152 153#define BWI_MAC_STATUS 0x120 154#define BWI_MAC_STATUS_ENABLE __BIT(0) 155#define BWI_MAC_STATUS_UCODE_START __BIT(1) 156#define BWI_MAC_STATUS_UCODE_JUMP0 __BIT(2) 157#define BWI_MAC_STATUS_IHREN __BIT(10) 158#define BWI_MAC_STATUS_GPOSEL_MASK __BITS(15, 14) 159#define BWI_MAC_STATUS_BSWAP __BIT(16) 160#define BWI_MAC_STATUS_INFRA __BIT(17) 161#define BWI_MAC_STATUS_OPMODE_HOSTAP __BIT(18) 162#define BWI_MAC_STATUS_RFLOCK __BIT(19) 163#define BWI_MAC_STATUS_PASS_BCN __BIT(20) 164#define BWI_MAC_STATUS_PASS_BADPLCP __BIT(21) 165#define BWI_MAC_STATUS_PASS_CTL __BIT(22) 166#define BWI_MAC_STATUS_PASS_BADFCS __BIT(23) 167#define BWI_MAC_STATUS_PROMISC __BIT(24) 168#define BWI_MAC_STATUS_HW_PS __BIT(25) 169#define BWI_MAC_STATUS_WAKEUP __BIT(26) 170#define BWI_MAC_STATUS_PHYLNK __BIT(31) 171 172#define BWI_MAC_INTR_STATUS 0x128 173#define BWI_MAC_INTR_MASK 0x12c 174 175#define BWI_MAC_TMPLT_CTRL 0x130 176#define BWI_MAC_TMPLT_DATA 0x134 177 178#define BWI_MAC_PS_STATUS 0x140 179 180#define BWI_MOBJ_CTRL 0x160 181#define BWI_MOBJ_CTRL_VAL(objid, ofs) ((objid) << 16 | (ofs)) 182#define BWI_MOBJ_DATA 0x164 183#define BWI_MOBJ_DATA_UNALIGN 0x166 184/* 185 * Memory object IDs 186 */ 187#define BWI_WR_MOBJ_AUTOINC 0x100 /* Auto-increment wr */ 188#define BWI_RD_MOBJ_AUTOINC 0x200 /* Auto-increment rd */ 189/* Firmware ucode object */ 190#define BWI_FW_UCODE_MOBJ 0x0 191/* Common object */ 192#define BWI_COMM_MOBJ 0x1 193#define BWI_COMM_MOBJ_FWREV 0x0 194#define BWI_COMM_MOBJ_FWPATCHLV 0x2 195#define BWI_COMM_MOBJ_SLOTTIME 0x10 196#define BWI_COMM_MOBJ_MACREV 0x16 197#define BWI_COMM_MOBJ_TX_ACK 0x22 198#define BWI_COMM_MOBJ_UCODE_STATE 0x40 199#define BWI_COMM_MOBJ_SHRETRY_FB 0x44 200#define BWI_COMM_MOBJ_LGRETEY_FB 0x46 201#define BWI_COMM_MOBJ_TX_BEACON 0x54 202#define BWI_COMM_MOBJ_KEYTABLE_OFS 0x56 203#define BWI_COMM_MOBJ_TSSI_DS 0x58 204#define BWI_COMM_MOBJ_HFLAGS_LO 0x5e 205#define BWI_COMM_MOBJ_HFLAGS_MI 0x60 206#define BWI_COMM_MOBJ_HFLAGS_HI 0x62 207#define BWI_COMM_MOBJ_RF_ATTEN 0x64 208#define BWI_COMM_MOBJ_RF_NOISE 0x6e 209#define BWI_COMM_MOBJ_TSSI_OFDM 0x70 210#define BWI_COMM_MOBJ_PROBE_RESP_TO 0x74 211#define BWI_COMM_MOBJ_CHAN 0xa0 212#define BWI_COMM_MOBJ_KEY_ALGO 0x100 213#define BWI_COMM_MOBJ_TX_PROBE_RESP 0x188 214#define BWI_HFLAG_AUTO_ANTDIV 0x1ULL 215#define BWI_HFLAG_SYM_WA 0x2ULL /* ??? SYM work around */ 216#define BWI_HFLAG_PWR_BOOST_DS 0x8ULL 217#define BWI_HFLAG_GDC_WA 0x20ULL /* ??? GDC work around */ 218#define BWI_HFLAG_OFDM_PA 0x40ULL 219#define BWI_HFLAG_NOT_JAPAN 0x80ULL 220#define BWI_HFLAG_MAGIC1 0x200ULL 221#define BWI_UCODE_STATE_PS 4 222#define BWI_LO_TSSI_MASK __BITS(7, 0) 223#define BWI_HI_TSSI_MASK __BITS(15, 8) 224#define BWI_INVALID_TSSI 0x7f 225/* 802.11 object */ 226#define BWI_80211_MOBJ 0x2 227#define BWI_80211_MOBJ_CWMIN 0xc 228#define BWI_80211_MOBJ_CWMAX 0x10 229#define BWI_80211_MOBJ_SHRETRY 0x18 230#define BWI_80211_MOBJ_LGRETRY 0x1c 231/* Firmware PCM object */ 232#define BWI_FW_PCM_MOBJ 0x3 233/* MAC address of pairwise keys */ 234#define BWI_PKEY_ADDR_MOBJ 0x4 235 236#define BWI_TXSTATUS0 0x170 237#define BWI_TXSTATUS0_VALID __BIT(0) 238#define BWI_TXSTATUS0_ACKED __BIT(1) 239#define BWI_TXSTATUS0_FREASON_MASK __BITS(4, 2) /* Failure reason */ 240#define BWI_TXSTATUS0_AMPDU __BIT(5) 241#define BWI_TXSTATUS0_PENDING __BIT(6) 242#define BWI_TXSTATUS0_PM __BIT(7) 243#define BWI_TXSTATUS0_RTS_TXCNT_MASK __BITS(11, 8) 244#define BWI_TXSTATUS0_DATA_TXCNT_MASK __BITS(15, 12) 245#define BWI_TXSTATUS0_TXID_MASK __BITS(31, 16) 246#define BWI_TXSTATUS1 0x174 247 248#define BWI_TXRX_CTRL_BASE 0x200 249#define BWI_TX32_CTRL 0x0 250#define BWI_TX32_RINGINFO 0x4 251#define BWI_TX32_INDEX 0x8 252#define BWI_TX32_STATUS 0xc 253#define BWI_TX32_STATUS_STATE_MASK __BITS(15, 12) 254#define BWI_TX32_STATUS_STATE_DISABLED 0 255#define BWI_TX32_STATUS_STATE_IDLE 2 256#define BWI_TX32_STATUS_STATE_STOPPED 3 257#define BWI_RX32_CTRL 0x10 258#define BWI_RX32_CTRL_HDRSZ_MASK __BITS(7, 1) 259#define BWI_RX32_RINGINFO 0x14 260#define BWI_RX32_INDEX 0x18 261#define BWI_RX32_STATUS 0x1c 262#define BWI_RX32_STATUS_INDEX_MASK __BITS(11, 0) 263#define BWI_RX32_STATUS_STATE_MASK __BITS(15, 12) 264#define BWI_RX32_STATUS_STATE_DISABLED 0 265/* Shared by 32bit TX/RX CTRL */ 266#define BWI_TXRX32_CTRL_ENABLE __BIT(0) 267#define BWI_TXRX32_CTRL_ADDRHI_MASK __BITS(17, 16) 268/* Shared by 32bit TX/RX RINGINFO */ 269#define BWI_TXRX32_RINGINFO_FUNC_TXRX 0x1 270#define BWI_TXRX32_RINGINFO_FUNC_MASK __BITS(31, 30) 271#define BWI_TXRX32_RINGINFO_ADDR_MASK __BITS(29, 0) 272 273#define BWI_PHYINFO 0x3e0 274#define BWI_PHYINFO_REV_MASK __BITS(3, 0) 275#define BWI_PHYINFO_TYPE_MASK __BITS(11, 8) 276#define BWI_PHYINFO_TYPE_11A 0 277#define BWI_PHYINFO_TYPE_11B 1 278#define BWI_PHYINFO_TYPE_11G 2 279#define BWI_PHYINFO_TYPE_11N 4 280#define BWI_PHYINFO_TYPE_11LP 5 281#define BWI_PHYINFO_VER_MASK __BITS(15, 12) 282 283#define BWI_RF_ANTDIV 0x3e2 /* Antenna Diversity?? */ 284 285#define BWI_PHY_MAGIC_REG1 0x3e4 286#define BWI_PHY_MAGIC_REG1_VAL1 0x3000 287#define BWI_PHY_MAGIC_REG1_VAL2 0x9 288 289#define BWI_BBP_ATTEN 0x3e6 290#define BWI_BBP_ATTEN_MAGIC 0xf4 291#define BWI_BBP_ATTEN_MAGIC2 0x8140 292 293#define BWI_BPHY_CTRL 0x3ec 294#define BWI_BPHY_CTRL_INIT 0x3f22 295 296#define BWI_RF_CHAN 0x3f0 297#define BWI_RF_CHAN_EX 0x3f4 298 299#define BWI_RF_CTRL 0x3f6 300/* Register values for BWI_RF_CTRL */ 301#define BWI_RF_CTRL_RFINFO 0x1 302/* XXX extra bits for reading from radio */ 303#define BWI_RF_CTRL_RD_11A 0x40 304#define BWI_RF_CTRL_RD_11BG 0x80 305#define BWI_RF_DATA_HI 0x3f8 306#define BWI_RF_DATA_LO 0x3fa 307/* Values read from BWI_RF_DATA_{HI,LO} after BWI_RF_CTRL_RFINFO */ 308#define BWI_RFINFO_MANUFACT_MASK __BITS(11, 0) 309#define BWI_RF_MANUFACT_BCM 0x17f /* XXX */ 310#define BWI_RFINFO_TYPE_MASK __BITS(27, 12) 311#define BWI_RF_T_BCM2050 0x2050 312#define BWI_RF_T_BCM2053 0x2053 313#define BWI_RF_T_BCM2060 0x2060 314#define BWI_RFINFO_REV_MASK __BITS(31, 28) 315 316#define BWI_PHY_CTRL 0x3fc 317#define BWI_PHY_DATA 0x3fe 318 319#define BWI_ADDR_FILTER_CTRL 0x420 320#define BWI_ADDR_FILTER_CTRL_SET 0x20 321#define BWI_ADDR_FILTER_MYADDR 0 322#define BWI_ADDR_FILTER_BSSID 3 323#define BWI_ADDR_FILTER_DATA 0x422 324 325#define BWI_MAC_GPIO_CTRL 0x49c 326#define BWI_MAC_GPIO_MASK 0x49e 327#define BWI_MAC_PRE_TBTT 0x612 328#define BWI_MAC_SLOTTIME 0x684 329#define BWI_MAC_SLOTTIME_ADJUST 510 330#define BWI_MAC_POWERUP_DELAY 0x6a8 331 332/* 333 * Special registers 334 */ 335/* 336 * GPIO control 337 * If common regwin exists, then it is within common regwin, 338 * else it is in bus regwin. 339 */ 340#define BWI_GPIO_CTRL 0x6c 341 342#define PCI_VENDOR_BROADCOM 0x14e4 /* Broadcom */ 343#define PCI_PRODUCT_BROADCOM_BCM4309 0x4324 344 345/* 346 * Extended PCI registers 347 */ 348#define BWI_PCIR_BAR PCIR_BAR(0) 349#define BWI_PCIR_SEL_REGWIN 0x80 350/* Register value for BWI_PCIR_SEL_REGWIN */ 351#define BWI_PCIM_REGWIN(id) (((id) * 0x1000) + 0x18000000) 352#define BWI_PCIR_GPIO_IN 0xb0 353#define BWI_PCIR_GPIO_OUT 0xb4 354#define BWI_PCIM_GPIO_OUT_CLKSRC __BIT(4) 355#define BWI_PCIR_GPIO_ENABLE 0xb8 356/* Register values for BWI_PCIR_GPIO_{IN,OUT,ENABLE} */ 357#define BWI_PCIM_GPIO_PWR_ON __BIT(6) 358#define BWI_PCIM_GPIO_PLL_PWR_OFF __BIT(7) 359#define BWI_PCIR_INTCTL 0x94 360 361/* 362 * PCI subdevice IDs 363 */ 364#define BWI_PCI_SUBDEVICE_BU4306 0x416 365#define BWI_PCI_SUBDEVICE_BCM4309G 0x421 366 367#define BWI_IS_BRCM_BU4306(sc) \ 368 ((sc)->sc_pci_subvid == PCI_VENDOR_BROADCOM && \ 369 (sc)->sc_pci_subdid == BWI_PCI_SUBDEVICE_BU4306) 370#define BWI_IS_BRCM_BCM4309G(sc) \ 371 ((sc)->sc_pci_subvid == PCI_VENDOR_BROADCOM && \ 372 (sc)->sc_pci_subdid == BWI_PCI_SUBDEVICE_BCM4309G) 373 374/* 375 * EEPROM start address 376 */ 377#define BWI_SPROM_START 0x1000 378#define BWI_SPROM_11BG_EADDR 0x48 379#define BWI_SPROM_11A_EADDR 0x54 380#define BWI_SPROM_CARD_INFO 0x5c 381#define BWI_SPROM_CARD_INFO_LOCALE __BITS(11, 8) 382#define BWI_SPROM_LOCALE_JAPAN 5 383#define BWI_SPROM_PA_PARAM_11BG 0x5e 384#define BWI_SPROM_GPIO01 0x64 385#define BWI_SPROM_GPIO_0 __BITS(7, 0) 386#define BWI_SPROM_GPIO_1 __BITS(15, 8) 387#define BWI_SPROM_GPIO23 0x66 388#define BWI_SPROM_GPIO_2 __BITS(7, 0) 389#define BWI_SPROM_GPIO_3 __BITS(15, 8) 390#define BWI_SPROM_MAX_TXPWR 0x68 391#define BWI_SPROM_MAX_TXPWR_MASK_11BG __BITS(7, 0) /* XXX */ 392#define BWI_SPROM_MAX_TXPWR_MASK_11A __BITS(15, 8) /* XXX */ 393#define BWI_SPROM_PA_PARAM_11A 0x6a 394#define BWI_SPROM_IDLE_TSSI 0x70 395#define BWI_SPROM_IDLE_TSSI_MASK_11BG __BITS(7, 0) /* XXX */ 396#define BWI_SPROM_IDLE_TSSI_MASK_11A __BITS(15, 8) /* XXX */ 397#define BWI_SPROM_CARD_FLAGS 0x72 398#define BWI_SPROM_ANT_GAIN 0x74 399#define BWI_SPROM_ANT_GAIN_MASK_11A __BITS(7, 0) 400#define BWI_SPROM_ANT_GAIN_MASK_11BG __BITS(15, 8) 401 402/* 403 * SPROM card flags 404 */ 405#define BWI_CARD_F_BT_COEXIST __BIT(0) /* Bluetooth coexist */ 406#define BWI_CARD_F_PA_GPIO9 __BIT(1) /* GPIO 9 controls PA */ 407#define BWI_CARD_F_SW_NRSSI __BIT(3) 408#define BWI_CARD_F_NO_SLOWCLK __BIT(5) /* no slow clock */ 409#define BWI_CARD_F_EXT_LNA __BIT(12) /* external LNA */ 410#define BWI_CARD_F_ALT_IQ __BIT(15) /* alternate I/Q */ 411 412/* 413 * SPROM GPIO 414 */ 415#define BWI_LED_ACT_LOW __BIT(7) 416#define BWI_LED_ACT_MASK __BITS(6, 0) 417#define BWI_LED_ACT_OFF 0 418#define BWI_LED_ACT_ON 1 419#define BWI_LED_ACT_BLINK 2 420#define BWI_LED_ACT_RF_ENABLED 3 421#define BWI_LED_ACT_5GHZ 4 422#define BWI_LED_ACT_2GHZ 5 423#define BWI_LED_ACT_11G 6 424#define BWI_LED_ACT_BLINK_SLOW 7 425#define BWI_LED_ACT_BLINK_POLL 8 426#define BWI_LED_ACT_UNKN 9 427#define BWI_LED_ACT_ASSOC 10 428#define BWI_LED_ACT_NULL 11 429 430#define BWI_VENDOR_LED_ACT_COMPAQ \ 431 BWI_LED_ACT_RF_ENABLED, \ 432 BWI_LED_ACT_2GHZ, \ 433 BWI_LED_ACT_5GHZ, \ 434 BWI_LED_ACT_OFF 435 436#define BWI_VENDOR_LED_ACT_LINKSYS \ 437 BWI_LED_ACT_ASSOC, \ 438 BWI_LED_ACT_2GHZ, \ 439 BWI_LED_ACT_5GHZ, \ 440 BWI_LED_ACT_OFF 441 442#define BWI_VENDOR_LED_ACT_DEFAULT \ 443 BWI_LED_ACT_BLINK, \ 444 BWI_LED_ACT_2GHZ, \ 445 BWI_LED_ACT_5GHZ, \ 446 BWI_LED_ACT_OFF 447 448/* 449 * BBP IDs 450 */ 451#define BWI_BBPID_BCM4301 0x4301 452#define BWI_BBPID_BCM4306 0x4306 453#define BWI_BBPID_BCM4317 0x4317 454#define BWI_BBPID_BCM4320 0x4320 455#define BWI_BBPID_BCM4321 0x4321 456 457/* 458 * Register window types 459 */ 460#define BWI_REGWIN_T_COM 0x800 461#define BWI_REGWIN_T_BUSPCI 0x804 462#define BWI_REGWIN_T_MAC 0x812 463#define BWI_REGWIN_T_BUSPCIE 0x820 464 465/* 466 * MAC interrupts 467 */ 468#define BWI_INTR_READY __BIT(0) 469#define BWI_INTR_BEACON __BIT(1) 470#define BWI_INTR_TBTT __BIT(2) 471#define BWI_INTR_EO_ATIM __BIT(5) /* End of ATIM */ 472#define BWI_INTR_PMQ __BIT(6) /* XXX?? */ 473#define BWI_INTR_MAC_TXERR __BIT(9) 474#define BWI_INTR_PHY_TXERR __BIT(11) 475#define BWI_INTR_TIMER1 __BIT(14) 476#define BWI_INTR_RX_DONE __BIT(15) 477#define BWI_INTR_TX_FIFO __BIT(16) /* XXX?? */ 478#define BWI_INTR_NOISE __BIT(18) 479#define BWI_INTR_RF_DISABLED __BIT(28) 480#define BWI_INTR_TX_DONE __BIT(29) 481 482#define BWI_INIT_INTRS \ 483 (BWI_INTR_READY | BWI_INTR_BEACON | BWI_INTR_TBTT | \ 484 BWI_INTR_EO_ATIM | BWI_INTR_PMQ | BWI_INTR_MAC_TXERR | \ 485 BWI_INTR_PHY_TXERR | BWI_INTR_RX_DONE | BWI_INTR_TX_FIFO | \ 486 BWI_INTR_NOISE | BWI_INTR_RF_DISABLED | BWI_INTR_TX_DONE) 487#define BWI_ALL_INTRS 0xffffffff 488 489/* 490 * TX/RX interrupts 491 */ 492#define BWI_TXRX_INTR_ERROR (__BIT(15) | __BIT(14) | __BITS(12, 10)) 493#define BWI_TXRX_INTR_RX __BIT(16) 494#define BWI_TXRX_TX_INTRS BWI_TXRX_INTR_ERROR 495#define BWI_TXRX_RX_INTRS (BWI_TXRX_INTR_ERROR | BWI_TXRX_INTR_RX) 496#define BWI_TXRX_IS_RX(i) ((i) % 3 == 0) 497 498#endif /* !_IF_BWIREG_H */ 499