1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: releng/12.0/sys/dev/ath/if_ath_rx.c 326255 2017-11-27 14:52:40Z pfg $"); 34 35/* 36 * Driver for the Atheros Wireless LAN controller. 37 * 38 * This software is derived from work of Atsushi Onoe; his contribution 39 * is greatly appreciated. 40 */ 41 42#include "opt_inet.h" 43#include "opt_ath.h" 44/* 45 * This is needed for register operations which are performed 46 * by the driver - eg, calls to ath_hal_gettsf32(). 47 * 48 * It's also required for any AH_DEBUG checks in here, eg the 49 * module dependencies. 50 */ 51#include "opt_ah.h" 52#include "opt_wlan.h" 53 54#include <sys/param.h> 55#include <sys/systm.h> 56#include <sys/sysctl.h> 57#include <sys/mbuf.h> 58#include <sys/malloc.h> 59#include <sys/lock.h> 60#include <sys/mutex.h> 61#include <sys/kernel.h> 62#include <sys/socket.h> 63#include <sys/sockio.h> 64#include <sys/errno.h> 65#include <sys/callout.h> 66#include <sys/bus.h> 67#include <sys/endian.h> 68#include <sys/kthread.h> 69#include <sys/taskqueue.h> 70#include <sys/priv.h> 71#include <sys/module.h> 72#include <sys/ktr.h> 73#include <sys/smp.h> /* for mp_ncpus */ 74 75#include <machine/bus.h> 76 77#include <net/if.h> 78#include <net/if_var.h> 79#include <net/if_dl.h> 80#include <net/if_media.h> 81#include <net/if_types.h> 82#include <net/if_arp.h> 83#include <net/ethernet.h> 84#include <net/if_llc.h> 85 86#include <net80211/ieee80211_var.h> 87#include <net80211/ieee80211_regdomain.h> 88#ifdef IEEE80211_SUPPORT_SUPERG 89#include <net80211/ieee80211_superg.h> 90#endif 91#ifdef IEEE80211_SUPPORT_TDMA 92#include <net80211/ieee80211_tdma.h> 93#endif 94 95#include <net/bpf.h> 96 97#ifdef INET 98#include <netinet/in.h> 99#include <netinet/if_ether.h> 100#endif 101 102#include <dev/ath/if_athvar.h> 103#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 104#include <dev/ath/ath_hal/ah_diagcodes.h> 105 106#include <dev/ath/if_ath_debug.h> 107#include <dev/ath/if_ath_misc.h> 108#include <dev/ath/if_ath_tsf.h> 109#include <dev/ath/if_ath_tx.h> 110#include <dev/ath/if_ath_sysctl.h> 111#include <dev/ath/if_ath_led.h> 112#include <dev/ath/if_ath_keycache.h> 113#include <dev/ath/if_ath_rx.h> 114#include <dev/ath/if_ath_beacon.h> 115#include <dev/ath/if_athdfs.h> 116#include <dev/ath/if_ath_descdma.h> 117 118#ifdef ATH_TX99_DIAG 119#include <dev/ath/ath_tx99/ath_tx99.h> 120#endif 121 122#ifdef ATH_DEBUG_ALQ 123#include <dev/ath/if_ath_alq.h> 124#endif 125 126#include <dev/ath/if_ath_lna_div.h> 127 128/* 129 * Calculate the receive filter according to the 130 * operating mode and state: 131 * 132 * o always accept unicast, broadcast, and multicast traffic 133 * o accept PHY error frames when hardware doesn't have MIB support 134 * to count and we need them for ANI (sta mode only until recently) 135 * and we are not scanning (ANI is disabled) 136 * NB: older hal's add rx filter bits out of sight and we need to 137 * blindly preserve them 138 * o probe request frames are accepted only when operating in 139 * hostap, adhoc, mesh, or monitor modes 140 * o enable promiscuous mode 141 * - when in monitor mode 142 * - if interface marked PROMISC (assumes bridge setting is filtered) 143 * o accept beacons: 144 * - when operating in station mode for collecting rssi data when 145 * the station is otherwise quiet, or 146 * - when operating in adhoc mode so the 802.11 layer creates 147 * node table entries for peers, 148 * - when scanning 149 * - when doing s/w beacon miss (e.g. for ap+sta) 150 * - when operating in ap mode in 11g to detect overlapping bss that 151 * require protection 152 * - when operating in mesh mode to detect neighbors 153 * o accept control frames: 154 * - when in monitor mode 155 * XXX HT protection for 11n 156 */ 157u_int32_t 158ath_calcrxfilter(struct ath_softc *sc) 159{ 160 struct ieee80211com *ic = &sc->sc_ic; 161 u_int32_t rfilt; 162 163 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 164 if (!sc->sc_needmib && !sc->sc_scanning) 165 rfilt |= HAL_RX_FILTER_PHYERR; 166 if (ic->ic_opmode != IEEE80211_M_STA) 167 rfilt |= HAL_RX_FILTER_PROBEREQ; 168 /* XXX ic->ic_monvaps != 0? */ 169 if (ic->ic_opmode == IEEE80211_M_MONITOR || ic->ic_promisc > 0) 170 rfilt |= HAL_RX_FILTER_PROM; 171 172 /* 173 * Only listen to all beacons if we're scanning. 174 * 175 * Otherwise we only really need to hear beacons from 176 * our own BSSID. 177 * 178 * IBSS? software beacon miss? Just receive all beacons. 179 * We need to hear beacons/probe requests from everyone so 180 * we can merge ibss. 181 */ 182 if (ic->ic_opmode == IEEE80211_M_IBSS || sc->sc_swbmiss) { 183 rfilt |= HAL_RX_FILTER_BEACON; 184 } else if (ic->ic_opmode == IEEE80211_M_STA) { 185 if (sc->sc_do_mybeacon && ! sc->sc_scanning) { 186 rfilt |= HAL_RX_FILTER_MYBEACON; 187 } else { /* scanning, non-mybeacon chips */ 188 rfilt |= HAL_RX_FILTER_BEACON; 189 } 190 } 191 192 /* 193 * NB: We don't recalculate the rx filter when 194 * ic_protmode changes; otherwise we could do 195 * this only when ic_protmode != NONE. 196 */ 197 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 198 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 199 rfilt |= HAL_RX_FILTER_BEACON; 200 201 /* 202 * Enable hardware PS-POLL RX only for hostap mode; 203 * STA mode sends PS-POLL frames but never 204 * receives them. 205 */ 206 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL, 207 0, NULL) == HAL_OK && 208 ic->ic_opmode == IEEE80211_M_HOSTAP) 209 rfilt |= HAL_RX_FILTER_PSPOLL; 210 211 if (sc->sc_nmeshvaps) { 212 rfilt |= HAL_RX_FILTER_BEACON; 213 if (sc->sc_hasbmatch) 214 rfilt |= HAL_RX_FILTER_BSSID; 215 else 216 rfilt |= HAL_RX_FILTER_PROM; 217 } 218 if (ic->ic_opmode == IEEE80211_M_MONITOR) 219 rfilt |= HAL_RX_FILTER_CONTROL; 220 221 /* 222 * Enable RX of compressed BAR frames only when doing 223 * 802.11n. Required for A-MPDU. 224 */ 225 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan)) 226 rfilt |= HAL_RX_FILTER_COMPBAR; 227 228 /* 229 * Enable radar PHY errors if requested by the 230 * DFS module. 231 */ 232 if (sc->sc_dodfs) 233 rfilt |= HAL_RX_FILTER_PHYRADAR; 234 235 /* 236 * Enable spectral PHY errors if requested by the 237 * spectral module. 238 */ 239 if (sc->sc_dospectral) 240 rfilt |= HAL_RX_FILTER_PHYRADAR; 241 242 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s\n", 243 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode]); 244 return rfilt; 245} 246 247static int 248ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 249{ 250 struct ath_hal *ah = sc->sc_ah; 251 int error; 252 struct mbuf *m; 253 struct ath_desc *ds; 254 255 /* XXX TODO: ATH_RX_LOCK_ASSERT(sc); */ 256 257 m = bf->bf_m; 258 if (m == NULL) { 259 /* 260 * NB: by assigning a page to the rx dma buffer we 261 * implicitly satisfy the Atheros requirement that 262 * this buffer be cache-line-aligned and sized to be 263 * multiple of the cache line size. Not doing this 264 * causes weird stuff to happen (for the 5210 at least). 265 */ 266 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 267 if (m == NULL) { 268 DPRINTF(sc, ATH_DEBUG_ANY, 269 "%s: no mbuf/cluster\n", __func__); 270 sc->sc_stats.ast_rx_nombuf++; 271 return ENOMEM; 272 } 273 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 274 275 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 276 bf->bf_dmamap, m, 277 bf->bf_segs, &bf->bf_nseg, 278 BUS_DMA_NOWAIT); 279 if (error != 0) { 280 DPRINTF(sc, ATH_DEBUG_ANY, 281 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 282 __func__, error); 283 sc->sc_stats.ast_rx_busdma++; 284 m_freem(m); 285 return error; 286 } 287 KASSERT(bf->bf_nseg == 1, 288 ("multi-segment packet; nseg %u", bf->bf_nseg)); 289 bf->bf_m = m; 290 } 291 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 292 293 /* 294 * Setup descriptors. For receive we always terminate 295 * the descriptor list with a self-linked entry so we'll 296 * not get overrun under high load (as can happen with a 297 * 5212 when ANI processing enables PHY error frames). 298 * 299 * To insure the last descriptor is self-linked we create 300 * each descriptor as self-linked and add it to the end. As 301 * each additional descriptor is added the previous self-linked 302 * entry is ``fixed'' naturally. This should be safe even 303 * if DMA is happening. When processing RX interrupts we 304 * never remove/process the last, self-linked, entry on the 305 * descriptor list. This insures the hardware always has 306 * someplace to write a new frame. 307 */ 308 /* 309 * 11N: we can no longer afford to self link the last descriptor. 310 * MAC acknowledges BA status as long as it copies frames to host 311 * buffer (or rx fifo). This can incorrectly acknowledge packets 312 * to a sender if last desc is self-linked. 313 */ 314 ds = bf->bf_desc; 315 if (sc->sc_rxslink) 316 ds->ds_link = bf->bf_daddr; /* link to self */ 317 else 318 ds->ds_link = 0; /* terminate the list */ 319 ds->ds_data = bf->bf_segs[0].ds_addr; 320 ath_hal_setuprxdesc(ah, ds 321 , m->m_len /* buffer size */ 322 , 0 323 ); 324 325 if (sc->sc_rxlink != NULL) 326 *sc->sc_rxlink = bf->bf_daddr; 327 sc->sc_rxlink = &ds->ds_link; 328 return 0; 329} 330 331/* 332 * Intercept management frames to collect beacon rssi data 333 * and to do ibss merges. 334 */ 335void 336ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 337 int subtype, const struct ieee80211_rx_stats *rxs, int rssi, int nf) 338{ 339 struct ieee80211vap *vap = ni->ni_vap; 340 struct ath_softc *sc = vap->iv_ic->ic_softc; 341 uint64_t tsf_beacon_old, tsf_beacon; 342 uint64_t nexttbtt; 343 int64_t tsf_delta; 344 int32_t tsf_delta_bmiss; 345 int32_t tsf_remainder; 346 uint64_t tsf_beacon_target; 347 int tsf_intval; 348 349 tsf_beacon_old = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32; 350 tsf_beacon_old |= le32dec(ni->ni_tstamp.data); 351 352#define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) 353 tsf_intval = 1; 354 if (ni->ni_intval > 0) { 355 tsf_intval = TU_TO_TSF(ni->ni_intval); 356 } 357#undef TU_TO_TSF 358 359 /* 360 * Call up first so subsequent work can use information 361 * potentially stored in the node (e.g. for ibss merge). 362 */ 363 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rxs, rssi, nf); 364 switch (subtype) { 365 case IEEE80211_FC0_SUBTYPE_BEACON: 366 /* 367 * Always update the per-node beacon RSSI if we're hearing 368 * beacons from that node. 369 */ 370 ATH_RSSI_LPF(ATH_NODE(ni)->an_node_stats.ns_avgbrssi, rssi); 371 372 /* 373 * Only do the following processing if it's for 374 * the current BSS. 375 * 376 * In scan and IBSS mode we receive all beacons, 377 * which means we need to filter out stuff 378 * that isn't for us or we'll end up constantly 379 * trying to sync / merge to BSSes that aren't 380 * actually us. 381 */ 382 if ((vap->iv_opmode != IEEE80211_M_HOSTAP) && 383 IEEE80211_ADDR_EQ(ni->ni_bssid, vap->iv_bss->ni_bssid)) { 384 /* update rssi statistics for use by the hal */ 385 /* XXX unlocked check against vap->iv_bss? */ 386 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 387 388 tsf_beacon = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32; 389 tsf_beacon |= le32dec(ni->ni_tstamp.data); 390 391 nexttbtt = ath_hal_getnexttbtt(sc->sc_ah); 392 393 /* 394 * Let's calculate the delta and remainder, so we can see 395 * if the beacon timer from the AP is varying by more than 396 * a few TU. (Which would be a huge, huge problem.) 397 */ 398 tsf_delta = (long long) tsf_beacon - (long long) tsf_beacon_old; 399 400 tsf_delta_bmiss = tsf_delta / tsf_intval; 401 402 /* 403 * If our delta is greater than half the beacon interval, 404 * let's round the bmiss value up to the next beacon 405 * interval. Ie, we're running really, really early 406 * on the next beacon. 407 */ 408 if (tsf_delta % tsf_intval > (tsf_intval / 2)) 409 tsf_delta_bmiss ++; 410 411 tsf_beacon_target = tsf_beacon_old + 412 (((unsigned long long) tsf_delta_bmiss) * (long long) tsf_intval); 413 414 /* 415 * The remainder using '%' is between 0 .. intval-1. 416 * If we're actually running too fast, then the remainder 417 * will be some large number just under intval-1. 418 * So we need to look at whether we're running 419 * before or after the target beacon interval 420 * and if we are, modify how we do the remainder 421 * calculation. 422 */ 423 if (tsf_beacon < tsf_beacon_target) { 424 tsf_remainder = 425 -(tsf_intval - ((tsf_beacon - tsf_beacon_old) % tsf_intval)); 426 } else { 427 tsf_remainder = (tsf_beacon - tsf_beacon_old) % tsf_intval; 428 } 429 430 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: %s: old_tsf=%llu (%u), new_tsf=%llu (%u), target_tsf=%llu (%u), delta=%lld, bmiss=%d, remainder=%d\n", 431 __func__, 432 ieee80211_get_vap_ifname(vap), 433 (unsigned long long) tsf_beacon_old, 434 (unsigned int) (tsf_beacon_old >> 10), 435 (unsigned long long) tsf_beacon, 436 (unsigned int ) (tsf_beacon >> 10), 437 (unsigned long long) tsf_beacon_target, 438 (unsigned int) (tsf_beacon_target >> 10), 439 (long long) tsf_delta, 440 tsf_delta_bmiss, 441 tsf_remainder); 442 443 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: %s: ni=%6D bssid=%6D tsf=%llu (%u), nexttbtt=%llu (%u), delta=%d\n", 444 __func__, 445 ieee80211_get_vap_ifname(vap), 446 ni->ni_bssid, ":", 447 vap->iv_bss->ni_bssid, ":", 448 (unsigned long long) tsf_beacon, 449 (unsigned int) (tsf_beacon >> 10), 450 (unsigned long long) nexttbtt, 451 (unsigned int) (nexttbtt >> 10), 452 (int32_t) tsf_beacon - (int32_t) nexttbtt + tsf_intval); 453 454 /* 455 * We only do syncbeacon on STA VAPs; not on IBSS; 456 * but don't do it with swbmiss enabled or we 457 * may end up overwriting AP mode beacon config. 458 * 459 * The driver (and net80211) should be smarter about 460 * this.. 461 */ 462 if (vap->iv_opmode == IEEE80211_M_STA && 463 sc->sc_syncbeacon && 464 (!sc->sc_swbmiss) && 465 ni == vap->iv_bss && 466 (vap->iv_state == IEEE80211_S_RUN || vap->iv_state == IEEE80211_S_SLEEP)) { 467 DPRINTF(sc, ATH_DEBUG_BEACON, 468 "%s: syncbeacon=1; syncing\n", 469 __func__); 470 /* 471 * Resync beacon timers using the tsf of the beacon 472 * frame we just received. 473 */ 474 ath_beacon_config(sc, vap); 475 sc->sc_syncbeacon = 0; 476 } 477 } 478 479 /* fall thru... */ 480 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 481 if (vap->iv_opmode == IEEE80211_M_IBSS && 482 vap->iv_state == IEEE80211_S_RUN && 483 ieee80211_ibss_merge_check(ni)) { 484 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 485 uint64_t tsf = ath_extend_tsf(sc, rstamp, 486 ath_hal_gettsf64(sc->sc_ah)); 487 /* 488 * Handle ibss merge as needed; check the tsf on the 489 * frame before attempting the merge. The 802.11 spec 490 * says the station should change it's bssid to match 491 * the oldest station with the same ssid, where oldest 492 * is determined by the tsf. Note that hardware 493 * reconfiguration happens through callback to 494 * ath_newstate as the state machine will go from 495 * RUN -> RUN when this happens. 496 */ 497 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 498 DPRINTF(sc, ATH_DEBUG_STATE, 499 "ibss merge, rstamp %u tsf %ju " 500 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 501 (uintmax_t)ni->ni_tstamp.tsf); 502 (void) ieee80211_ibss_merge(ni); 503 } 504 } 505 break; 506 } 507} 508 509#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 510static void 511ath_rx_tap_vendor(struct ath_softc *sc, struct mbuf *m, 512 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 513{ 514 515 /* Fill in the extension bitmap */ 516 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER); 517 518 /* Fill in the vendor header */ 519 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f; 520 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03; 521 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00; 522 523 /* XXX what should this be? */ 524 sc->sc_rx_th.wr_vh.vh_sub_ns = 0; 525 sc->sc_rx_th.wr_vh.vh_skip_len = 526 htole16(sizeof(struct ath_radiotap_vendor_hdr)); 527 528 /* General version info */ 529 sc->sc_rx_th.wr_v.vh_version = 1; 530 531 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask; 532 533 /* rssi */ 534 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0]; 535 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1]; 536 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2]; 537 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0]; 538 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1]; 539 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2]; 540 541 /* evm */ 542 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0; 543 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1; 544 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2; 545 /* These are only populated from the AR9300 or later */ 546 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3; 547 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4; 548 549 /* direction */ 550 sc->sc_rx_th.wr_v.vh_flags = ATH_VENDOR_PKT_RX; 551 552 /* RX rate */ 553 sc->sc_rx_th.wr_v.vh_rx_hwrate = rs->rs_rate; 554 555 /* RX flags */ 556 sc->sc_rx_th.wr_v.vh_rs_flags = rs->rs_flags; 557 558 if (rs->rs_isaggr) 559 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_ISAGGR; 560 if (rs->rs_moreaggr) 561 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_MOREAGGR; 562 563 /* phyerr info */ 564 if (rs->rs_status & HAL_RXERR_PHY) { 565 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr; 566 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_RXPHYERR; 567 } else { 568 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff; 569 } 570 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status; 571 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi; 572} 573#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 574 575static void 576ath_rx_tap(struct ath_softc *sc, struct mbuf *m, 577 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 578{ 579#define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 580#define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 581#define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 582#define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 583 const HAL_RATE_TABLE *rt; 584 uint8_t rix; 585 586 rt = sc->sc_currates; 587 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 588 rix = rt->rateCodeToIndex[rs->rs_rate]; 589 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 590 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 591 592 /* 802.11 specific flags */ 593 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 594 if (rs->rs_status & HAL_RXERR_PHY) { 595 /* 596 * PHY error - make sure the channel flags 597 * reflect the actual channel configuration, 598 * not the received frame. 599 */ 600 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan)) 601 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 602 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan)) 603 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 604 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan)) 605 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 606 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 607 struct ieee80211com *ic = &sc->sc_ic; 608 609 if ((rs->rs_flags & HAL_RX_2040) == 0) 610 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 611 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 612 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 613 else 614 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 615 616 if (rs->rs_flags & HAL_RX_GI) 617 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 618 } 619 620 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf)); 621 if (rs->rs_status & HAL_RXERR_CRC) 622 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 623 /* XXX propagate other error flags from descriptor */ 624 sc->sc_rx_th.wr_antnoise = nf; 625 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 626 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 627#undef CHAN_HT 628#undef CHAN_HT20 629#undef CHAN_HT40U 630#undef CHAN_HT40D 631} 632 633static void 634ath_handle_micerror(struct ieee80211com *ic, 635 struct ieee80211_frame *wh, int keyix) 636{ 637 struct ieee80211_node *ni; 638 639 /* XXX recheck MIC to deal w/ chips that lie */ 640 /* XXX discard MIC errors on !data frames */ 641 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 642 if (ni != NULL) { 643 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 644 ieee80211_free_node(ni); 645 } 646} 647 648/* 649 * Process a single packet. 650 * 651 * The mbuf must already be synced, unmapped and removed from bf->bf_m 652 * by this stage. 653 * 654 * The mbuf must be consumed by this routine - either passed up the 655 * net80211 stack, put on the holding queue, or freed. 656 */ 657int 658ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status, 659 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf, 660 struct mbuf *m) 661{ 662 uint64_t rstamp; 663 /* XXX TODO: make this an mbuf tag? */ 664 struct ieee80211_rx_stats rxs; 665 int len, type, i; 666 struct ieee80211com *ic = &sc->sc_ic; 667 struct ieee80211_node *ni; 668 int is_good = 0; 669 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 670 671 /* 672 * Calculate the correct 64 bit TSF given 673 * the TSF64 register value and rs_tstamp. 674 */ 675 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf); 676 677 /* 802.11 return codes - These aren't specifically errors */ 678 if (rs->rs_flags & HAL_RX_GI) 679 sc->sc_stats.ast_rx_halfgi++; 680 if (rs->rs_flags & HAL_RX_2040) 681 sc->sc_stats.ast_rx_2040++; 682 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE) 683 sc->sc_stats.ast_rx_pre_crc_err++; 684 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST) 685 sc->sc_stats.ast_rx_post_crc_err++; 686 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY) 687 sc->sc_stats.ast_rx_decrypt_busy_err++; 688 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN) 689 sc->sc_stats.ast_rx_hi_rx_chain++; 690 if (rs->rs_flags & HAL_RX_STBC) 691 sc->sc_stats.ast_rx_stbc++; 692 693 if (rs->rs_status != 0) { 694 if (rs->rs_status & HAL_RXERR_CRC) 695 sc->sc_stats.ast_rx_crcerr++; 696 if (rs->rs_status & HAL_RXERR_FIFO) 697 sc->sc_stats.ast_rx_fifoerr++; 698 if (rs->rs_status & HAL_RXERR_PHY) { 699 sc->sc_stats.ast_rx_phyerr++; 700 /* Process DFS radar events */ 701 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) || 702 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) { 703 /* Now pass it to the radar processing code */ 704 ath_dfs_process_phy_err(sc, m, rstamp, rs); 705 } 706 707 /* 708 * Be suitably paranoid about receiving phy errors 709 * out of the stats array bounds 710 */ 711 if (rs->rs_phyerr < ATH_IOCTL_STATS_NUM_RX_PHYERR) 712 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++; 713 goto rx_error; /* NB: don't count in ierrors */ 714 } 715 if (rs->rs_status & HAL_RXERR_DECRYPT) { 716 /* 717 * Decrypt error. If the error occurred 718 * because there was no hardware key, then 719 * let the frame through so the upper layers 720 * can process it. This is necessary for 5210 721 * parts which have no way to setup a ``clear'' 722 * key cache entry. 723 * 724 * XXX do key cache faulting 725 */ 726 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 727 goto rx_accept; 728 sc->sc_stats.ast_rx_badcrypt++; 729 } 730 /* 731 * Similar as above - if the failure was a keymiss 732 * just punt it up to the upper layers for now. 733 */ 734 if (rs->rs_status & HAL_RXERR_KEYMISS) { 735 sc->sc_stats.ast_rx_keymiss++; 736 goto rx_accept; 737 } 738 if (rs->rs_status & HAL_RXERR_MIC) { 739 sc->sc_stats.ast_rx_badmic++; 740 /* 741 * Do minimal work required to hand off 742 * the 802.11 header for notification. 743 */ 744 /* XXX frag's and qos frames */ 745 len = rs->rs_datalen; 746 if (len >= sizeof (struct ieee80211_frame)) { 747 ath_handle_micerror(ic, 748 mtod(m, struct ieee80211_frame *), 749 sc->sc_splitmic ? 750 rs->rs_keyix-32 : rs->rs_keyix); 751 } 752 } 753 counter_u64_add(ic->ic_ierrors, 1); 754rx_error: 755 /* 756 * Cleanup any pending partial frame. 757 */ 758 if (re->m_rxpending != NULL) { 759 m_freem(re->m_rxpending); 760 re->m_rxpending = NULL; 761 } 762 /* 763 * When a tap is present pass error frames 764 * that have been requested. By default we 765 * pass decrypt+mic errors but others may be 766 * interesting (e.g. crc). 767 */ 768 if (ieee80211_radiotap_active(ic) && 769 (rs->rs_status & sc->sc_monpass)) { 770 /* NB: bpf needs the mbuf length setup */ 771 len = rs->rs_datalen; 772 m->m_pkthdr.len = m->m_len = len; 773 ath_rx_tap(sc, m, rs, rstamp, nf); 774#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 775 ath_rx_tap_vendor(sc, m, rs, rstamp, nf); 776#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 777 ieee80211_radiotap_rx_all(ic, m); 778 } 779 /* XXX pass MIC errors up for s/w reclaculation */ 780 m_freem(m); m = NULL; 781 goto rx_next; 782 } 783rx_accept: 784 len = rs->rs_datalen; 785 m->m_len = len; 786 787 if (rs->rs_more) { 788 /* 789 * Frame spans multiple descriptors; save 790 * it for the next completed descriptor, it 791 * will be used to construct a jumbogram. 792 */ 793 if (re->m_rxpending != NULL) { 794 /* NB: max frame size is currently 2 clusters */ 795 sc->sc_stats.ast_rx_toobig++; 796 m_freem(re->m_rxpending); 797 } 798 m->m_pkthdr.len = len; 799 re->m_rxpending = m; 800 m = NULL; 801 goto rx_next; 802 } else if (re->m_rxpending != NULL) { 803 /* 804 * This is the second part of a jumbogram, 805 * chain it to the first mbuf, adjust the 806 * frame length, and clear the rxpending state. 807 */ 808 re->m_rxpending->m_next = m; 809 re->m_rxpending->m_pkthdr.len += len; 810 m = re->m_rxpending; 811 re->m_rxpending = NULL; 812 } else { 813 /* 814 * Normal single-descriptor receive; setup packet length. 815 */ 816 m->m_pkthdr.len = len; 817 } 818 819 /* 820 * Validate rs->rs_antenna. 821 * 822 * Some users w/ AR9285 NICs have reported crashes 823 * here because rs_antenna field is bogusly large. 824 * Let's enforce the maximum antenna limit of 8 825 * (and it shouldn't be hard coded, but that's a 826 * separate problem) and if there's an issue, print 827 * out an error and adjust rs_antenna to something 828 * sensible. 829 * 830 * This code should be removed once the actual 831 * root cause of the issue has been identified. 832 * For example, it may be that the rs_antenna 833 * field is only valid for the last frame of 834 * an aggregate and it just happens that it is 835 * "mostly" right. (This is a general statement - 836 * the majority of the statistics are only valid 837 * for the last frame in an aggregate. 838 */ 839 if (rs->rs_antenna >= ATH_IOCTL_STATS_NUM_RX_ANTENNA) { 840 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n", 841 __func__, rs->rs_antenna); 842#ifdef ATH_DEBUG 843 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 844#endif /* ATH_DEBUG */ 845 rs->rs_antenna = 0; /* XXX better than nothing */ 846 } 847 848 /* 849 * If this is an AR9285/AR9485, then the receive and LNA 850 * configuration is stored in RSSI[2] / EXTRSSI[2]. 851 * We can extract this out to build a much better 852 * receive antenna profile. 853 * 854 * Yes, this just blurts over the above RX antenna field 855 * for now. It's fine, the AR9285 doesn't really use 856 * that. 857 * 858 * Later on we should store away the fine grained LNA 859 * information and keep separate counters just for 860 * that. It'll help when debugging the AR9285/AR9485 861 * combined diversity code. 862 */ 863 if (sc->sc_rx_lnamixer) { 864 rs->rs_antenna = 0; 865 866 /* Bits 0:1 - the LNA configuration used */ 867 rs->rs_antenna |= 868 ((rs->rs_rssi_ctl[2] & HAL_RX_LNA_CFG_USED) 869 >> HAL_RX_LNA_CFG_USED_S); 870 871 /* Bit 2 - the external RX antenna switch */ 872 if (rs->rs_rssi_ctl[2] & HAL_RX_LNA_EXTCFG) 873 rs->rs_antenna |= 0x4; 874 } 875 876 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 877 878 /* 879 * Populate the rx status block. When there are bpf 880 * listeners we do the additional work to provide 881 * complete status. Otherwise we fill in only the 882 * material required by ieee80211_input. Note that 883 * noise setting is filled in above. 884 */ 885 if (ieee80211_radiotap_active(ic)) { 886 ath_rx_tap(sc, m, rs, rstamp, nf); 887#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 888 ath_rx_tap_vendor(sc, m, rs, rstamp, nf); 889#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 890 } 891 892 /* 893 * From this point on we assume the frame is at least 894 * as large as ieee80211_frame_min; verify that. 895 */ 896 if (len < IEEE80211_MIN_LEN) { 897 if (!ieee80211_radiotap_active(ic)) { 898 DPRINTF(sc, ATH_DEBUG_RECV, 899 "%s: short packet %d\n", __func__, len); 900 sc->sc_stats.ast_rx_tooshort++; 901 } else { 902 /* NB: in particular this captures ack's */ 903 ieee80211_radiotap_rx_all(ic, m); 904 } 905 m_freem(m); m = NULL; 906 goto rx_next; 907 } 908 909 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 910 const HAL_RATE_TABLE *rt = sc->sc_currates; 911 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 912 913 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 914 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 915 } 916 917 m_adj(m, -IEEE80211_CRC_LEN); 918 919 /* 920 * Locate the node for sender, track state, and then 921 * pass the (referenced) node up to the 802.11 layer 922 * for its use. 923 */ 924 ni = ieee80211_find_rxnode_withkey(ic, 925 mtod(m, const struct ieee80211_frame_min *), 926 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 927 IEEE80211_KEYIX_NONE : rs->rs_keyix); 928 sc->sc_lastrs = rs; 929 930 if (rs->rs_isaggr) 931 sc->sc_stats.ast_rx_agg++; 932 933 /* 934 * Populate the per-chain RSSI values where appropriate. 935 */ 936 bzero(&rxs, sizeof(rxs)); 937 rxs.r_flags |= IEEE80211_R_NF | IEEE80211_R_RSSI | 938 IEEE80211_R_C_CHAIN | 939 IEEE80211_R_C_NF | 940 IEEE80211_R_C_RSSI | 941 IEEE80211_R_TSF64 | 942 IEEE80211_R_TSF_START; /* XXX TODO: validate */ 943 rxs.c_rssi = rs->rs_rssi; 944 rxs.c_nf = nf; 945 rxs.c_chain = 3; /* XXX TODO: check */ 946 rxs.c_rx_tsf = rstamp; 947 948 for (i = 0; i < 3; i++) { 949 rxs.c_rssi_ctl[i] = rs->rs_rssi_ctl[i]; 950 rxs.c_rssi_ext[i] = rs->rs_rssi_ext[i]; 951 /* 952 * XXX note: we currently don't track 953 * per-chain noisefloor. 954 */ 955 rxs.c_nf_ctl[i] = nf; 956 rxs.c_nf_ext[i] = nf; 957 } 958 959 if (ni != NULL) { 960 /* 961 * Only punt packets for ampdu reorder processing for 962 * 11n nodes; net80211 enforces that M_AMPDU is only 963 * set for 11n nodes. 964 */ 965 if (ni->ni_flags & IEEE80211_NODE_HT) 966 m->m_flags |= M_AMPDU; 967 968 /* 969 * Inform rate control about the received RSSI. 970 * It can then use this information to potentially drastically 971 * alter the available rate based on the RSSI estimate. 972 * 973 * This is super important when associating to a far away station; 974 * you don't want to waste time trying higher rates at some low 975 * packet exchange rate (like during DHCP) just to establish 976 * that higher MCS rates aren't available. 977 */ 978 ATH_RSSI_LPF(ATH_NODE(ni)->an_node_stats.ns_avgrssi, 979 rs->rs_rssi); 980 ath_rate_update_rx_rssi(sc, ATH_NODE(ni), 981 ATH_RSSI(ATH_NODE(ni)->an_node_stats.ns_avgrssi)); 982 983 /* 984 * Sending station is known, dispatch directly. 985 */ 986 (void) ieee80211_add_rx_params(m, &rxs); 987 type = ieee80211_input_mimo(ni, m); 988 ieee80211_free_node(ni); 989 m = NULL; 990 /* 991 * Arrange to update the last rx timestamp only for 992 * frames from our ap when operating in station mode. 993 * This assumes the rx key is always setup when 994 * associated. 995 */ 996 if (ic->ic_opmode == IEEE80211_M_STA && 997 rs->rs_keyix != HAL_RXKEYIX_INVALID) 998 is_good = 1; 999 } else { 1000 (void) ieee80211_add_rx_params(m, &rxs); 1001 type = ieee80211_input_mimo_all(ic, m); 1002 m = NULL; 1003 } 1004 1005 /* 1006 * At this point we have passed the frame up the stack; thus 1007 * the mbuf is no longer ours. 1008 */ 1009 1010 /* 1011 * Track legacy station RX rssi and do any rx antenna management. 1012 */ 1013 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 1014 if (sc->sc_diversity) { 1015 /* 1016 * When using fast diversity, change the default rx 1017 * antenna if diversity chooses the other antenna 3 1018 * times in a row. 1019 */ 1020 if (sc->sc_defant != rs->rs_antenna) { 1021 if (++sc->sc_rxotherant >= 3) 1022 ath_setdefantenna(sc, rs->rs_antenna); 1023 } else 1024 sc->sc_rxotherant = 0; 1025 } 1026 1027 /* Handle slow diversity if enabled */ 1028 if (sc->sc_dolnadiv) { 1029 ath_lna_rx_comb_scan(sc, rs, ticks, hz); 1030 } 1031 1032 if (sc->sc_softled) { 1033 /* 1034 * Blink for any data frame. Otherwise do a 1035 * heartbeat-style blink when idle. The latter 1036 * is mainly for station mode where we depend on 1037 * periodic beacon frames to trigger the poll event. 1038 */ 1039 if (type == IEEE80211_FC0_TYPE_DATA) { 1040 const HAL_RATE_TABLE *rt = sc->sc_currates; 1041 ath_led_event(sc, 1042 rt->rateCodeToIndex[rs->rs_rate]); 1043 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 1044 ath_led_event(sc, 0); 1045 } 1046rx_next: 1047 /* 1048 * Debugging - complain if we didn't NULL the mbuf pointer 1049 * here. 1050 */ 1051 if (m != NULL) { 1052 device_printf(sc->sc_dev, 1053 "%s: mbuf %p should've been freed!\n", 1054 __func__, 1055 m); 1056 } 1057 return (is_good); 1058} 1059 1060#define ATH_RX_MAX 128 1061 1062/* 1063 * XXX TODO: break out the "get buffers" from "call ath_rx_pkt()" like 1064 * the EDMA code does. 1065 * 1066 * XXX TODO: then, do all of the RX list management stuff inside 1067 * ATH_RX_LOCK() so we don't end up potentially racing. The EDMA 1068 * code is doing it right. 1069 */ 1070static void 1071ath_rx_proc(struct ath_softc *sc, int resched) 1072{ 1073#define PA2DESC(_sc, _pa) \ 1074 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1075 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1076 struct ath_buf *bf; 1077 struct ath_hal *ah = sc->sc_ah; 1078#ifdef IEEE80211_SUPPORT_SUPERG 1079 struct ieee80211com *ic = &sc->sc_ic; 1080#endif 1081 struct ath_desc *ds; 1082 struct ath_rx_status *rs; 1083 struct mbuf *m; 1084 int ngood; 1085 HAL_STATUS status; 1086 int16_t nf; 1087 u_int64_t tsf; 1088 int npkts = 0; 1089 int kickpcu = 0; 1090 int ret; 1091 1092 /* XXX we must not hold the ATH_LOCK here */ 1093 ATH_UNLOCK_ASSERT(sc); 1094 ATH_PCU_UNLOCK_ASSERT(sc); 1095 1096 ATH_PCU_LOCK(sc); 1097 sc->sc_rxproc_cnt++; 1098 kickpcu = sc->sc_kickpcu; 1099 ATH_PCU_UNLOCK(sc); 1100 1101 ATH_LOCK(sc); 1102 ath_power_set_power_state(sc, HAL_PM_AWAKE); 1103 ATH_UNLOCK(sc); 1104 1105 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__); 1106 ngood = 0; 1107 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 1108 sc->sc_stats.ast_rx_noise = nf; 1109 tsf = ath_hal_gettsf64(ah); 1110 do { 1111 /* 1112 * Don't process too many packets at a time; give the 1113 * TX thread time to also run - otherwise the TX 1114 * latency can jump by quite a bit, causing throughput 1115 * degredation. 1116 */ 1117 if (!kickpcu && npkts >= ATH_RX_MAX) 1118 break; 1119 1120 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1121 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */ 1122 device_printf(sc->sc_dev, "%s: no buffer!\n", __func__); 1123 break; 1124 } else if (bf == NULL) { 1125 /* 1126 * End of List: 1127 * this can happen for non-self-linked RX chains 1128 */ 1129 sc->sc_stats.ast_rx_hitqueueend++; 1130 break; 1131 } 1132 m = bf->bf_m; 1133 if (m == NULL) { /* NB: shouldn't happen */ 1134 /* 1135 * If mbuf allocation failed previously there 1136 * will be no mbuf; try again to re-populate it. 1137 */ 1138 /* XXX make debug msg */ 1139 device_printf(sc->sc_dev, "%s: no mbuf!\n", __func__); 1140 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1141 goto rx_proc_next; 1142 } 1143 ds = bf->bf_desc; 1144 if (ds->ds_link == bf->bf_daddr) { 1145 /* NB: never process the self-linked entry at the end */ 1146 sc->sc_stats.ast_rx_hitqueueend++; 1147 break; 1148 } 1149 /* XXX sync descriptor memory */ 1150 /* 1151 * Must provide the virtual address of the current 1152 * descriptor, the physical address, and the virtual 1153 * address of the next descriptor in the h/w chain. 1154 * This allows the HAL to look ahead to see if the 1155 * hardware is done with a descriptor by checking the 1156 * done bit in the following descriptor and the address 1157 * of the current descriptor the DMA engine is working 1158 * on. All this is necessary because of our use of 1159 * a self-linked list to avoid rx overruns. 1160 */ 1161 rs = &bf->bf_status.ds_rxstat; 1162 status = ath_hal_rxprocdesc(ah, ds, 1163 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1164#ifdef ATH_DEBUG 1165 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 1166 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 1167#endif 1168 1169#ifdef ATH_DEBUG_ALQ 1170 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS)) 1171 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS, 1172 sc->sc_rx_statuslen, (char *) ds); 1173#endif /* ATH_DEBUG_ALQ */ 1174 1175 if (status == HAL_EINPROGRESS) 1176 break; 1177 1178 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1179 npkts++; 1180 1181 /* 1182 * Process a single frame. 1183 */ 1184 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD); 1185 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1186 bf->bf_m = NULL; 1187 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf, m)) 1188 ngood++; 1189rx_proc_next: 1190 /* 1191 * If there's a holding buffer, insert that onto 1192 * the RX list; the hardware is now definitely not pointing 1193 * to it now. 1194 */ 1195 ret = 0; 1196 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf != NULL) { 1197 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, 1198 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf, 1199 bf_list); 1200 ret = ath_rxbuf_init(sc, 1201 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf); 1202 } 1203 /* 1204 * Next, throw our buffer into the holding entry. The hardware 1205 * may use the descriptor to read the link pointer before 1206 * DMAing the next descriptor in to write out a packet. 1207 */ 1208 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = bf; 1209 } while (ret == 0); 1210 1211 /* rx signal state monitoring */ 1212 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 1213 if (ngood) 1214 sc->sc_lastrx = tsf; 1215 1216 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood); 1217 /* Queue DFS tasklet if needed */ 1218 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan)) 1219 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask); 1220 1221 /* 1222 * Now that all the RX frames were handled that 1223 * need to be handled, kick the PCU if there's 1224 * been an RXEOL condition. 1225 */ 1226 if (resched && kickpcu) { 1227 ATH_PCU_LOCK(sc); 1228 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu"); 1229 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n", 1230 __func__, npkts); 1231 1232 /* 1233 * Go through the process of fully tearing down 1234 * the RX buffers and reinitialising them. 1235 * 1236 * There's a hardware bug that causes the RX FIFO 1237 * to get confused under certain conditions and 1238 * constantly write over the same frame, leading 1239 * the RX driver code here to get heavily confused. 1240 */ 1241 /* 1242 * XXX Has RX DMA stopped enough here to just call 1243 * ath_startrecv()? 1244 * XXX Do we need to use the holding buffer to restart 1245 * RX DMA by appending entries to the final 1246 * descriptor? Quite likely. 1247 */ 1248#if 1 1249 ath_startrecv(sc); 1250#else 1251 /* 1252 * Disabled for now - it'd be nice to be able to do 1253 * this in order to limit the amount of CPU time spent 1254 * reinitialising the RX side (and thus minimise RX 1255 * drops) however there's a hardware issue that 1256 * causes things to get too far out of whack. 1257 */ 1258 /* 1259 * XXX can we hold the PCU lock here? 1260 * Are there any net80211 buffer calls involved? 1261 */ 1262 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1263 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1264 ath_hal_rxena(ah); /* enable recv descriptors */ 1265 ath_mode_init(sc); /* set filters, etc. */ 1266 ath_hal_startpcurecv(ah, (!! sc->sc_scanning)); /* re-enable PCU/DMA engine */ 1267#endif 1268 1269 ath_hal_intrset(ah, sc->sc_imask); 1270 sc->sc_kickpcu = 0; 1271 ATH_PCU_UNLOCK(sc); 1272 } 1273 1274#ifdef IEEE80211_SUPPORT_SUPERG 1275 if (resched) 1276 ieee80211_ff_age_all(ic, 100); 1277#endif 1278 1279 /* 1280 * Put the hardware to sleep again if we're done with it. 1281 */ 1282 ATH_LOCK(sc); 1283 ath_power_restore_power_state(sc); 1284 ATH_UNLOCK(sc); 1285 1286 /* 1287 * If we hit the maximum number of frames in this round, 1288 * reschedule for another immediate pass. This gives 1289 * the TX and TX completion routines time to run, which 1290 * will reduce latency. 1291 */ 1292 if (npkts >= ATH_RX_MAX) 1293 sc->sc_rx.recv_sched(sc, resched); 1294 1295 ATH_PCU_LOCK(sc); 1296 sc->sc_rxproc_cnt--; 1297 ATH_PCU_UNLOCK(sc); 1298} 1299#undef PA2DESC 1300#undef ATH_RX_MAX 1301 1302/* 1303 * Only run the RX proc if it's not already running. 1304 * Since this may get run as part of the reset/flush path, 1305 * the task can't clash with an existing, running tasklet. 1306 */ 1307static void 1308ath_legacy_rx_tasklet(void *arg, int npending) 1309{ 1310 struct ath_softc *sc = arg; 1311 1312 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending); 1313 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 1314 ATH_PCU_LOCK(sc); 1315 if (sc->sc_inreset_cnt > 0) { 1316 device_printf(sc->sc_dev, 1317 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 1318 ATH_PCU_UNLOCK(sc); 1319 return; 1320 } 1321 ATH_PCU_UNLOCK(sc); 1322 1323 ath_rx_proc(sc, 1); 1324} 1325 1326static void 1327ath_legacy_flushrecv(struct ath_softc *sc) 1328{ 1329 1330 ath_rx_proc(sc, 0); 1331} 1332 1333static void 1334ath_legacy_flush_rxpending(struct ath_softc *sc) 1335{ 1336 1337 /* XXX ATH_RX_LOCK_ASSERT(sc); */ 1338 1339 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) { 1340 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending); 1341 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1342 } 1343 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) { 1344 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending); 1345 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1346 } 1347} 1348 1349static int 1350ath_legacy_flush_rxholdbf(struct ath_softc *sc) 1351{ 1352 struct ath_buf *bf; 1353 1354 /* XXX ATH_RX_LOCK_ASSERT(sc); */ 1355 /* 1356 * If there are RX holding buffers, free them here and return 1357 * them to the list. 1358 * 1359 * XXX should just verify that bf->bf_m is NULL, as it must 1360 * be at this point! 1361 */ 1362 bf = sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf; 1363 if (bf != NULL) { 1364 if (bf->bf_m != NULL) 1365 m_freem(bf->bf_m); 1366 bf->bf_m = NULL; 1367 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1368 (void) ath_rxbuf_init(sc, bf); 1369 } 1370 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = NULL; 1371 1372 bf = sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf; 1373 if (bf != NULL) { 1374 if (bf->bf_m != NULL) 1375 m_freem(bf->bf_m); 1376 bf->bf_m = NULL; 1377 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1378 (void) ath_rxbuf_init(sc, bf); 1379 } 1380 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf = NULL; 1381 1382 return (0); 1383} 1384 1385/* 1386 * Disable the receive h/w in preparation for a reset. 1387 */ 1388static void 1389ath_legacy_stoprecv(struct ath_softc *sc, int dodelay) 1390{ 1391#define PA2DESC(_sc, _pa) \ 1392 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1393 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1394 struct ath_hal *ah = sc->sc_ah; 1395 1396 ATH_RX_LOCK(sc); 1397 1398 ath_hal_stoppcurecv(ah); /* disable PCU */ 1399 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 1400 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 1401 /* 1402 * TODO: see if this particular DELAY() is required; it may be 1403 * masking some missing FIFO flush or DMA sync. 1404 */ 1405#if 0 1406 if (dodelay) 1407#endif 1408 DELAY(3000); /* 3ms is long enough for 1 frame */ 1409#ifdef ATH_DEBUG 1410 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 1411 struct ath_buf *bf; 1412 u_int ix; 1413 1414 device_printf(sc->sc_dev, 1415 "%s: rx queue %p, link %p\n", 1416 __func__, 1417 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP), 1418 sc->sc_rxlink); 1419 ix = 0; 1420 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1421 struct ath_desc *ds = bf->bf_desc; 1422 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 1423 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 1424 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1425 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 1426 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 1427 ix++; 1428 } 1429 } 1430#endif 1431 1432 (void) ath_legacy_flush_rxpending(sc); 1433 (void) ath_legacy_flush_rxholdbf(sc); 1434 1435 sc->sc_rxlink = NULL; /* just in case */ 1436 1437 ATH_RX_UNLOCK(sc); 1438#undef PA2DESC 1439} 1440 1441/* 1442 * XXX TODO: something was calling startrecv without calling 1443 * stoprecv. Let's figure out what/why. It was showing up 1444 * as a mbuf leak (rxpending) and ath_buf leak (holdbf.) 1445 */ 1446 1447/* 1448 * Enable the receive h/w following a reset. 1449 */ 1450static int 1451ath_legacy_startrecv(struct ath_softc *sc) 1452{ 1453 struct ath_hal *ah = sc->sc_ah; 1454 struct ath_buf *bf; 1455 1456 ATH_RX_LOCK(sc); 1457 1458 /* 1459 * XXX should verify these are already all NULL! 1460 */ 1461 sc->sc_rxlink = NULL; 1462 (void) ath_legacy_flush_rxpending(sc); 1463 (void) ath_legacy_flush_rxholdbf(sc); 1464 1465 /* 1466 * Re-chain all of the buffers in the RX buffer list. 1467 */ 1468 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1469 int error = ath_rxbuf_init(sc, bf); 1470 if (error != 0) { 1471 DPRINTF(sc, ATH_DEBUG_RECV, 1472 "%s: ath_rxbuf_init failed %d\n", 1473 __func__, error); 1474 return error; 1475 } 1476 } 1477 1478 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1479 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1480 ath_hal_rxena(ah); /* enable recv descriptors */ 1481 ath_mode_init(sc); /* set filters, etc. */ 1482 ath_hal_startpcurecv(ah, (!! sc->sc_scanning)); /* re-enable PCU/DMA engine */ 1483 1484 ATH_RX_UNLOCK(sc); 1485 return 0; 1486} 1487 1488static int 1489ath_legacy_dma_rxsetup(struct ath_softc *sc) 1490{ 1491 int error; 1492 1493 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 1494 "rx", sizeof(struct ath_desc), ath_rxbuf, 1); 1495 if (error != 0) 1496 return (error); 1497 1498 return (0); 1499} 1500 1501static int 1502ath_legacy_dma_rxteardown(struct ath_softc *sc) 1503{ 1504 1505 if (sc->sc_rxdma.dd_desc_len != 0) 1506 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 1507 return (0); 1508} 1509 1510static void 1511ath_legacy_recv_sched(struct ath_softc *sc, int dosched) 1512{ 1513 1514 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1515} 1516 1517static void 1518ath_legacy_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE q, 1519 int dosched) 1520{ 1521 1522 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1523} 1524 1525void 1526ath_recv_setup_legacy(struct ath_softc *sc) 1527{ 1528 1529 /* Sensible legacy defaults */ 1530 /* 1531 * XXX this should be changed to properly support the 1532 * exact RX descriptor size for each HAL. 1533 */ 1534 sc->sc_rx_statuslen = sizeof(struct ath_desc); 1535 1536 sc->sc_rx.recv_start = ath_legacy_startrecv; 1537 sc->sc_rx.recv_stop = ath_legacy_stoprecv; 1538 sc->sc_rx.recv_flush = ath_legacy_flushrecv; 1539 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet; 1540 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init; 1541 1542 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup; 1543 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown; 1544 sc->sc_rx.recv_sched = ath_legacy_recv_sched; 1545 sc->sc_rx.recv_sched_queue = ath_legacy_recv_sched_queue; 1546} 1547