1/*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD: releng/12.0/sys/dev/ath/ath_hal/ah.h 334197 2018-05-25 01:27:39Z adrian $ 20 */ 21 22#ifndef _ATH_AH_H_ 23#define _ATH_AH_H_ 24/* 25 * Atheros Hardware Access Layer 26 * 27 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 28 * structure for use with the device. Hardware-related operations that 29 * follow must call back into the HAL through interface, supplying the 30 * reference as the first parameter. 31 */ 32 33#include "ah_osdep.h" 34 35/* 36 * Endianness macros; used by various structures and code. 37 */ 38#define AH_BIG_ENDIAN 4321 39#define AH_LITTLE_ENDIAN 1234 40 41#if _BYTE_ORDER == _BIG_ENDIAN 42#define AH_BYTE_ORDER AH_BIG_ENDIAN 43#else 44#define AH_BYTE_ORDER AH_LITTLE_ENDIAN 45#endif 46 47/* 48 * The maximum number of TX/RX chains supported. 49 * This is intended to be used by various statistics gathering operations 50 * (NF, RSSI, EVM). 51 */ 52#define AH_MAX_CHAINS 3 53#define AH_MIMO_MAX_EVM_PILOTS 6 54 55/* 56 * __ahdecl is analogous to _cdecl; it defines the calling 57 * convention used within the HAL. For most systems this 58 * can just default to be empty and the compiler will (should) 59 * use _cdecl. For systems where _cdecl is not compatible this 60 * must be defined. See linux/ah_osdep.h for an example. 61 */ 62#ifndef __ahdecl 63#define __ahdecl 64#endif 65 66/* 67 * Status codes that may be returned by the HAL. Note that 68 * interfaces that return a status code set it only when an 69 * error occurs--i.e. you cannot check it for success. 70 */ 71typedef enum { 72 HAL_OK = 0, /* No error */ 73 HAL_ENXIO = 1, /* No hardware present */ 74 HAL_ENOMEM = 2, /* Memory allocation failed */ 75 HAL_EIO = 3, /* Hardware didn't respond as expected */ 76 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 77 HAL_EEVERSION = 5, /* EEPROM version invalid */ 78 HAL_EELOCKED = 6, /* EEPROM unreadable */ 79 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 80 HAL_EEREAD = 8, /* EEPROM read problem */ 81 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 82 HAL_EESIZE = 10, /* EEPROM size not supported */ 83 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 84 HAL_EINVAL = 12, /* Invalid parameter to function */ 85 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 86 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 87 HAL_EINPROGRESS = 15, /* Operation incomplete */ 88 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 89 HAL_EEBADCC = 17, /* EEPROM invalid country code */ 90 HAL_INV_PMODE = 18, /* Couldn't bring out of sleep state */ 91} HAL_STATUS; 92 93typedef enum { 94 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 95 AH_TRUE = 1, 96} HAL_BOOL; 97 98typedef enum { 99 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 100 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 101 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 102 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 103 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 104 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 105 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 106 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 107 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 108 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 109 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 110 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 111 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 112 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 113 HAL_CAP_TXPOW = 15, /* global tx power limit */ 114 HAL_CAP_TPC = 16, /* per-packet tx power control */ 115 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 116 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 117 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 118 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 119 /* 21 was HAL_CAP_XR */ 120 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 121 /* 23 was HAL_CAP_CHAN_HALFRATE */ 122 /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 123 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 124 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 125 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 126 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 127 HAL_CAP_PCIE_PS = 29, 128 HAL_CAP_HT = 30, /* hardware can support HT */ 129 HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */ 130 HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */ 131 HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */ 132 HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */ 133 HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */ 134 135 HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */ 136 HAL_CAP_RIFS_RX = 39, 137 HAL_CAP_RIFS_TX = 40, 138 HAL_CAP_FORCE_PPM = 41, 139 HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */ 140 HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */ 141 HAL_CAP_DFS_DMN = 44, /* current DFS domain */ 142 HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */ 143 HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */ 144 145 HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep 146 automatically after waking up to receive TIM */ 147 HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */ 148 HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */ 149 HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */ 150 HAL_CAP_BB_RIFS_HANG = 52, 151 HAL_CAP_RIFS_RX_ENABLED = 53, 152 HAL_CAP_BB_DFS_HANG = 54, 153 154 HAL_CAP_RX_STBC = 58, 155 HAL_CAP_TX_STBC = 59, 156 157 HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */ 158 HAL_CAP_DYNAMIC_SMPS = 61, /* Dynamic MIMO Power Save hardware support */ 159 160 HAL_CAP_DS = 67, /* 2 stream */ 161 HAL_CAP_BB_RX_CLEAR_STUCK_HANG = 68, 162 HAL_CAP_MAC_HANG = 69, /* can MAC hang */ 163 HAL_CAP_MFP = 70, /* Management Frame Protection in hardware */ 164 165 HAL_CAP_TS = 72, /* 3 stream */ 166 167 HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */ 168 HAL_CAP_NUM_TXMAPS = 76, /* Number of buffers in a transmit descriptor */ 169 HAL_CAP_TXDESCLEN = 77, /* Length of transmit descriptor */ 170 HAL_CAP_TXSTATUSLEN = 78, /* Length of transmit status descriptor */ 171 HAL_CAP_RXSTATUSLEN = 79, /* Length of transmit status descriptor */ 172 HAL_CAP_RXFIFODEPTH = 80, /* Receive hardware FIFO depth */ 173 HAL_CAP_RXBUFSIZE = 81, /* Receive Buffer Length */ 174 HAL_CAP_NUM_MR_RETRIES = 82, /* limit on multirate retries */ 175 HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */ 176 HAL_CAP_SPECTRAL_SCAN = 90, /* Hardware supports spectral scan */ 177 178 HAL_CAP_BB_PANIC_WATCHDOG = 92, 179 180 HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */ 181 182 HAL_CAP_LDPC = 99, 183 184 HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */ 185 186 HAL_CAP_ANT_DIV_COMB = 105, /* Enable antenna diversity/combining */ 187 HAL_CAP_PHYRESTART_CLR_WAR = 106, /* in some cases, clear phy restart to fix bb hang */ 188 HAL_CAP_ENTERPRISE_MODE = 107, /* Enterprise mode features */ 189 HAL_CAP_LDPCWAR = 108, 190 HAL_CAP_CHANNEL_SWITCH_TIME_USEC = 109, /* Channel change time, usec */ 191 HAL_CAP_ENABLE_APM = 110, /* APM enabled */ 192 HAL_CAP_PCIE_LCR_EXTSYNC_EN = 111, 193 HAL_CAP_PCIE_LCR_OFFSET = 112, 194 195 HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */ 196 HAL_CAP_MCI = 118, 197 HAL_CAP_SMARTANTENNA = 119, 198 HAL_CAP_TRAFFIC_FAST_RECOVER = 120, 199 HAL_CAP_TX_DIVERSITY = 121, 200 HAL_CAP_CRDC = 122, 201 202 /* The following are private to the FreeBSD HAL (224 onward) */ 203 204 HAL_CAP_INTMIT = 229, /* interference mitigation */ 205 HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */ 206 HAL_CAP_BB_HANG = 235, /* can baseband hang */ 207 HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */ 208 HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */ 209 HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */ 210 HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */ 211 HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */ 212 HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */ 213 HAL_CAP_ENFORCE_TXOP = 246, /* Enforce TXOP if supported */ 214 HAL_CAP_RX_LNA_MIXING = 247, /* RX hardware uses LNA mixing */ 215 HAL_CAP_DO_MYBEACON = 248, /* Supports HAL_RX_FILTER_MYBEACON */ 216 HAL_CAP_TOA_LOCATIONING = 249, /* time of flight / arrival locationing */ 217 HAL_CAP_TXTSTAMP_PREC = 250, /* tx desc tstamp precision (bits) */ 218} HAL_CAPABILITY_TYPE; 219 220/* 221 * "States" for setting the LED. These correspond to 222 * the possible 802.11 operational states and there may 223 * be a many-to-one mapping between these states and the 224 * actual hardware state for the LED's (i.e. the hardware 225 * may have fewer states). 226 */ 227typedef enum { 228 HAL_LED_INIT = 0, 229 HAL_LED_SCAN = 1, 230 HAL_LED_AUTH = 2, 231 HAL_LED_ASSOC = 3, 232 HAL_LED_RUN = 4 233} HAL_LED_STATE; 234 235/* 236 * Transmit queue types/numbers. These are used to tag 237 * each transmit queue in the hardware and to identify a set 238 * of transmit queues for operations such as start/stop dma. 239 */ 240typedef enum { 241 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 242 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 243 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 244 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 245 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 246 HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ 247 HAL_TX_QUEUE_CFEND = 6, 248 HAL_TX_QUEUE_PAPRD = 7, 249} HAL_TX_QUEUE; 250 251#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 252 253/* 254 * Receive queue types. These are used to tag 255 * each transmit queue in the hardware and to identify a set 256 * of transmit queues for operations such as start/stop dma. 257 */ 258typedef enum { 259 HAL_RX_QUEUE_HP = 0, /* high priority recv queue */ 260 HAL_RX_QUEUE_LP = 1, /* low priority recv queue */ 261} HAL_RX_QUEUE; 262 263#define HAL_NUM_RX_QUEUES 2 /* max possible # of queues */ 264 265#define HAL_TXFIFO_DEPTH 8 /* transmit fifo depth */ 266 267/* 268 * Transmit queue subtype. These map directly to 269 * WME Access Categories (except for UPSD). Refer 270 * to Table 5 of the WME spec. 271 */ 272typedef enum { 273 HAL_WME_AC_BK = 0, /* background access category */ 274 HAL_WME_AC_BE = 1, /* best effort access category*/ 275 HAL_WME_AC_VI = 2, /* video access category */ 276 HAL_WME_AC_VO = 3, /* voice access category */ 277 HAL_WME_UPSD = 4, /* uplink power save */ 278} HAL_TX_QUEUE_SUBTYPE; 279 280/* 281 * Transmit queue flags that control various 282 * operational parameters. 283 */ 284typedef enum { 285 /* 286 * Per queue interrupt enables. When set the associated 287 * interrupt may be delivered for packets sent through 288 * the queue. Without these enabled no interrupts will 289 * be delivered for transmits through the queue. 290 */ 291 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 292 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 293 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 294 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 295 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 296 /* 297 * Enable hardware compression for packets sent through 298 * the queue. The compression buffer must be setup and 299 * packets must have a key entry marked in the tx descriptor. 300 */ 301 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 302 /* 303 * Disable queue when veol is hit or ready time expires. 304 * By default the queue is disabled only on reaching the 305 * physical end of queue (i.e. a null link ptr in the 306 * descriptor chain). 307 */ 308 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 309 /* 310 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 311 * event. Frames will be transmitted only when this timer 312 * fires, e.g to transmit a beacon in ap or adhoc modes. 313 */ 314 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 315 /* 316 * Each transmit queue has a counter that is incremented 317 * each time the queue is enabled and decremented when 318 * the list of frames to transmit is traversed (or when 319 * the ready time for the queue expires). This counter 320 * must be non-zero for frames to be scheduled for 321 * transmission. The following controls disable bumping 322 * this counter under certain conditions. Typically this 323 * is used to gate frames based on the contents of another 324 * queue (e.g. CAB traffic may only follow a beacon frame). 325 * These are meaningful only when frames are scheduled 326 * with a non-ASAP policy (e.g. DBA-gated). 327 */ 328 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 329 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 330 331 /* 332 * Fragment burst backoff policy. Normally the no backoff 333 * is done after a successful transmission, the next fragment 334 * is sent at SIFS. If this flag is set backoff is done 335 * after each fragment, regardless whether it was ack'd or 336 * not, after the backoff count reaches zero a normal channel 337 * access procedure is done before the next transmit (i.e. 338 * wait AIFS instead of SIFS). 339 */ 340 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 341 /* 342 * Disable post-tx backoff following each frame. 343 */ 344 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 345 /* 346 * DCU arbiter lockout control. This controls how 347 * lower priority tx queues are handled with respect to 348 * to a specific queue when multiple queues have frames 349 * to send. No lockout means lower priority queues arbitrate 350 * concurrently with this queue. Intra-frame lockout 351 * means lower priority queues are locked out until the 352 * current frame transmits (e.g. including backoffs and bursting). 353 * Global lockout means nothing lower can arbitrary so 354 * long as there is traffic activity on this queue (frames, 355 * backoff, etc). 356 */ 357 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 358 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 359 360 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 361 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 362} HAL_TX_QUEUE_FLAGS; 363 364typedef struct { 365 uint32_t tqi_ver; /* hal TXQ version */ 366 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 367 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 368 uint32_t tqi_priority; /* (not used) */ 369 uint32_t tqi_aifs; /* aifs */ 370 uint32_t tqi_cwmin; /* cwMin */ 371 uint32_t tqi_cwmax; /* cwMax */ 372 uint16_t tqi_shretry; /* rts retry limit */ 373 uint16_t tqi_lgretry; /* long retry limit (not used)*/ 374 uint32_t tqi_cbrPeriod; /* CBR period (us) */ 375 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 376 uint32_t tqi_burstTime; /* max burst duration (us) */ 377 uint32_t tqi_readyTime; /* frame schedule time (us) */ 378 uint32_t tqi_compBuf; /* comp buffer phys addr */ 379} HAL_TXQ_INFO; 380 381#define HAL_TQI_NONVAL 0xffff 382 383/* token to use for aifs, cwmin, cwmax */ 384#define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 385 386/* compression definitions */ 387#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 388#define HAL_COMP_BUF_ALIGN_SIZE 512 389 390/* 391 * Transmit packet types. This belongs in ah_desc.h, but 392 * is here so we can give a proper type to various parameters 393 * (and not require everyone include the file). 394 * 395 * NB: These values are intentionally assigned for 396 * direct use when setting up h/w descriptors. 397 */ 398typedef enum { 399 HAL_PKT_TYPE_NORMAL = 0, 400 HAL_PKT_TYPE_ATIM = 1, 401 HAL_PKT_TYPE_PSPOLL = 2, 402 HAL_PKT_TYPE_BEACON = 3, 403 HAL_PKT_TYPE_PROBE_RESP = 4, 404 HAL_PKT_TYPE_CHIRP = 5, 405 HAL_PKT_TYPE_GRP_POLL = 6, 406 HAL_PKT_TYPE_AMPDU = 7, 407} HAL_PKT_TYPE; 408 409/* Rx Filter Frame Types */ 410typedef enum { 411 /* 412 * These bits correspond to AR_RX_FILTER for all chips. 413 * Not all bits are supported by all chips. 414 */ 415 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 416 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 417 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 418 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 419 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 420 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 421 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 422 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 423 HAL_RX_FILTER_MYBEACON = 0x00000200, /* Filter beacons other than mine */ 424 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 425 HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */ 426 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */ 427 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */ 428 HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 429 /* Allow all mcast/bcast frames */ 430 431 /* 432 * Magic RX filter flags that aren't targeting hardware bits 433 * but instead the HAL sets individual bits - eg PHYERR will result 434 * in OFDM/CCK timing error frames being received. 435 */ 436 HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */ 437} HAL_RX_FILTER; 438 439typedef enum { 440 HAL_PM_AWAKE = 0, 441 HAL_PM_FULL_SLEEP = 1, 442 HAL_PM_NETWORK_SLEEP = 2, 443 HAL_PM_UNDEFINED = 3 444} HAL_POWER_MODE; 445 446/* 447 * Enterprise mode flags 448 */ 449#define AH_ENT_DUAL_BAND_DISABLE 0x00000001 450#define AH_ENT_CHAIN2_DISABLE 0x00000002 451#define AH_ENT_5MHZ_DISABLE 0x00000004 452#define AH_ENT_10MHZ_DISABLE 0x00000008 453#define AH_ENT_49GHZ_DISABLE 0x00000010 454#define AH_ENT_LOOPBACK_DISABLE 0x00000020 455#define AH_ENT_TPC_PERF_DISABLE 0x00000040 456#define AH_ENT_MIN_PKT_SIZE_DISABLE 0x00000080 457#define AH_ENT_SPECTRAL_PRECISION 0x00000300 458#define AH_ENT_SPECTRAL_PRECISION_S 8 459#define AH_ENT_RTSCTS_DELIM_WAR 0x00010000 460 461#define AH_FIRST_DESC_NDELIMS 60 462 463/* 464 * NOTE WELL: 465 * These are mapped to take advantage of the common locations for many of 466 * the bits on all of the currently supported MAC chips. This is to make 467 * the ISR as efficient as possible, while still abstracting HW differences. 468 * When new hardware breaks this commonality this enumerated type, as well 469 * as the HAL functions using it, must be modified. All values are directly 470 * mapped unless commented otherwise. 471 */ 472typedef enum { 473 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 474 HAL_INT_RXDESC = 0x00000002, /* Legacy mapping */ 475 HAL_INT_RXERR = 0x00000004, 476 HAL_INT_RXHP = 0x00000001, /* EDMA */ 477 HAL_INT_RXLP = 0x00000002, /* EDMA */ 478 HAL_INT_RXNOFRM = 0x00000008, 479 HAL_INT_RXEOL = 0x00000010, 480 HAL_INT_RXORN = 0x00000020, 481 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 482 HAL_INT_TXDESC = 0x00000080, 483 HAL_INT_TIM_TIMER= 0x00000100, 484 HAL_INT_MCI = 0x00000200, 485 HAL_INT_BBPANIC = 0x00000400, 486 HAL_INT_TXURN = 0x00000800, 487 HAL_INT_MIB = 0x00001000, 488 HAL_INT_RXPHY = 0x00004000, 489 HAL_INT_RXKCM = 0x00008000, 490 HAL_INT_SWBA = 0x00010000, 491 HAL_INT_BRSSI = 0x00020000, 492 HAL_INT_BMISS = 0x00040000, 493 HAL_INT_BNR = 0x00100000, 494 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 495 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 496 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 497 HAL_INT_GPIO = 0x01000000, 498 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 499 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 500 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 501 /* Atheros ref driver has a generic timer interrupt now..*/ 502 HAL_INT_GENTIMER = 0x08000000, /* Non-common mapping */ 503 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 504 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 505 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 506#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 507 HAL_INT_BMISC = HAL_INT_TIM 508 | HAL_INT_DTIM 509 | HAL_INT_DTIMSYNC 510 | HAL_INT_CABEND 511 | HAL_INT_TBTT, 512 513 /* Interrupt bits that map directly to ISR/IMR bits */ 514 HAL_INT_COMMON = HAL_INT_RXNOFRM 515 | HAL_INT_RXDESC 516 | HAL_INT_RXEOL 517 | HAL_INT_RXORN 518 | HAL_INT_TXDESC 519 | HAL_INT_TXURN 520 | HAL_INT_MIB 521 | HAL_INT_RXPHY 522 | HAL_INT_RXKCM 523 | HAL_INT_SWBA 524 | HAL_INT_BMISS 525 | HAL_INT_BRSSI 526 | HAL_INT_BNR 527 | HAL_INT_GPIO, 528} HAL_INT; 529 530/* 531 * MSI vector assignments 532 */ 533typedef enum { 534 HAL_MSIVEC_MISC = 0, 535 HAL_MSIVEC_TX = 1, 536 HAL_MSIVEC_RXLP = 2, 537 HAL_MSIVEC_RXHP = 3, 538} HAL_MSIVEC; 539 540typedef enum { 541 HAL_INT_LINE = 0, 542 HAL_INT_MSI = 1, 543} HAL_INT_TYPE; 544 545/* For interrupt mitigation registers */ 546typedef enum { 547 HAL_INT_RX_FIRSTPKT=0, 548 HAL_INT_RX_LASTPKT, 549 HAL_INT_TX_FIRSTPKT, 550 HAL_INT_TX_LASTPKT, 551 HAL_INT_THRESHOLD 552} HAL_INT_MITIGATION; 553 554/* XXX this is duplicate information! */ 555typedef struct { 556 u_int32_t cyclecnt_diff; /* delta cycle count */ 557 u_int32_t rxclr_cnt; /* rx clear count */ 558 u_int32_t extrxclr_cnt; /* ext chan rx clear count */ 559 u_int32_t txframecnt_diff; /* delta tx frame count */ 560 u_int32_t rxframecnt_diff; /* delta rx frame count */ 561 u_int32_t listen_time; /* listen time in msec - time for which ch is free */ 562 u_int32_t ofdmphyerr_cnt; /* OFDM err count since last reset */ 563 u_int32_t cckphyerr_cnt; /* CCK err count since last reset */ 564 u_int32_t ofdmphyerrcnt_diff; /* delta OFDM Phy Error Count */ 565 HAL_BOOL valid; /* if the stats are valid*/ 566} HAL_ANISTATS; 567 568typedef struct { 569 u_int8_t txctl_offset; 570 u_int8_t txctl_numwords; 571 u_int8_t txstatus_offset; 572 u_int8_t txstatus_numwords; 573 574 u_int8_t rxctl_offset; 575 u_int8_t rxctl_numwords; 576 u_int8_t rxstatus_offset; 577 u_int8_t rxstatus_numwords; 578 579 u_int8_t macRevision; 580} HAL_DESC_INFO; 581 582typedef enum { 583 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0, 584 HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1, 585 HAL_GPIO_OUTPUT_MUX_PCIE_POWER_LED = 2, 586 HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED = 3, 587 HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED = 4, 588 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE = 5, 589 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME = 6, 590 591 HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA, 592 HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK, 593 HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA, 594 HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK, 595 HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX, 596 HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX, 597 HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX, 598 HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX, 599 HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE, 600 HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA, 601 HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0, 602 HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1, 603 HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2, 604 HAL_GPIO_OUTPUT_MUX_NUM_ENTRIES 605} HAL_GPIO_MUX_TYPE; 606 607typedef enum { 608 HAL_GPIO_INTR_LOW = 0, 609 HAL_GPIO_INTR_HIGH = 1, 610 HAL_GPIO_INTR_DISABLE = 2 611} HAL_GPIO_INTR_TYPE; 612 613typedef struct halCounters { 614 u_int32_t tx_frame_count; 615 u_int32_t rx_frame_count; 616 u_int32_t rx_clear_count; 617 u_int32_t cycle_count; 618 u_int8_t is_rx_active; // true (1) or false (0) 619 u_int8_t is_tx_active; // true (1) or false (0) 620} HAL_COUNTERS; 621 622typedef enum { 623 HAL_RFGAIN_INACTIVE = 0, 624 HAL_RFGAIN_READ_REQUESTED = 1, 625 HAL_RFGAIN_NEED_CHANGE = 2 626} HAL_RFGAIN; 627 628typedef uint16_t HAL_CTRY_CODE; /* country code */ 629typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 630 631#define HAL_ANTENNA_MIN_MODE 0 632#define HAL_ANTENNA_FIXED_A 1 633#define HAL_ANTENNA_FIXED_B 2 634#define HAL_ANTENNA_MAX_MODE 3 635 636typedef struct { 637 uint32_t ackrcv_bad; 638 uint32_t rts_bad; 639 uint32_t rts_good; 640 uint32_t fcs_bad; 641 uint32_t beacons; 642} HAL_MIB_STATS; 643 644/* 645 * These bits represent what's in ah_currentRDext. 646 */ 647typedef enum { 648 REG_EXT_FCC_MIDBAND = 0, 649 REG_EXT_JAPAN_MIDBAND = 1, 650 REG_EXT_FCC_DFS_HT40 = 2, 651 REG_EXT_JAPAN_NONDFS_HT40 = 3, 652 REG_EXT_JAPAN_DFS_HT40 = 4, 653 REG_EXT_FCC_CH_144 = 5, 654} REG_EXT_BITMAP; 655 656enum { 657 HAL_MODE_11A = 0x001, /* 11a channels */ 658 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 659 HAL_MODE_11B = 0x004, /* 11b channels */ 660 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 661#ifdef notdef 662 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 663#else 664 HAL_MODE_11G = 0x008, /* XXX historical */ 665#endif 666 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 667 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 668 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 669 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 670 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 671 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 672 HAL_MODE_11NG_HT20 = 0x008000, 673 HAL_MODE_11NA_HT20 = 0x010000, 674 HAL_MODE_11NG_HT40PLUS = 0x020000, 675 HAL_MODE_11NG_HT40MINUS = 0x040000, 676 HAL_MODE_11NA_HT40PLUS = 0x080000, 677 HAL_MODE_11NA_HT40MINUS = 0x100000, 678 HAL_MODE_ALL = 0xffffff 679}; 680 681typedef struct { 682 int rateCount; /* NB: for proper padding */ 683 uint8_t rateCodeToIndex[256]; /* back mapping */ 684 struct { 685 uint8_t valid; /* valid for rate control use */ 686 uint8_t phy; /* CCK/OFDM/XR */ 687 uint32_t rateKbps; /* transfer rate in kbs */ 688 uint8_t rateCode; /* rate for h/w descriptors */ 689 uint8_t shortPreamble; /* mask for enabling short 690 * preamble in CCK rate code */ 691 uint8_t dot11Rate; /* value for supported rates 692 * info element of MLME */ 693 uint8_t controlRate; /* index of next lower basic 694 * rate; used for dur. calcs */ 695 uint16_t lpAckDuration; /* long preamble ACK duration */ 696 uint16_t spAckDuration; /* short preamble ACK duration*/ 697 } info[64]; 698} HAL_RATE_TABLE; 699 700typedef struct { 701 u_int rs_count; /* number of valid entries */ 702 uint8_t rs_rates[64]; /* rates */ 703} HAL_RATE_SET; 704 705/* 706 * 802.11n specific structures and enums 707 */ 708typedef enum { 709 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 710 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 711} HAL_CHAIN_TYPE; 712 713typedef struct { 714 u_int Tries; 715 u_int Rate; /* hardware rate code */ 716 u_int RateIndex; /* rate series table index */ 717 u_int PktDuration; 718 u_int ChSel; 719 u_int RateFlags; 720#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 721#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 722#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 723#define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */ 724 u_int tx_power_cap; /* in 1/2 dBm units XXX TODO */ 725} HAL_11N_RATE_SERIES; 726 727typedef enum { 728 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 729 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 730} HAL_HT_MACMODE; 731 732typedef enum { 733 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 734 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 735} HAL_HT_PHYMODE; 736 737typedef enum { 738 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 739 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 740} HAL_HT_EXTPROTSPACING; 741 742typedef enum { 743 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 744 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 745} HAL_HT_RXCLEAR; 746 747typedef enum { 748 HAL_FREQ_BAND_5GHZ = 0, 749 HAL_FREQ_BAND_2GHZ = 1, 750} HAL_FREQ_BAND; 751 752/* 753 * Antenna switch control. By default antenna selection 754 * enables multiple (2) antenna use. To force use of the 755 * A or B antenna only specify a fixed setting. Fixing 756 * the antenna will also disable any diversity support. 757 */ 758typedef enum { 759 HAL_ANT_VARIABLE = 0, /* variable by programming */ 760 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 761 HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 762} HAL_ANT_SETTING; 763 764typedef enum { 765 HAL_M_STA = 1, /* infrastructure station */ 766 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 767 HAL_M_HOSTAP = 6, /* Software Access Point */ 768 HAL_M_MONITOR = 8 /* Monitor mode */ 769} HAL_OPMODE; 770 771typedef enum { 772 HAL_RESET_NORMAL = 0, /* Do normal reset */ 773 HAL_RESET_BBPANIC = 1, /* Reset because of BB panic */ 774 HAL_RESET_FORCE_COLD = 2, /* Force full reset */ 775} HAL_RESET_TYPE; 776 777enum { 778 HAL_RESET_POWER_ON, 779 HAL_RESET_WARM, 780 HAL_RESET_COLD 781}; 782 783typedef struct { 784 uint8_t kv_type; /* one of HAL_CIPHER */ 785 uint8_t kv_apsd; /* Mask for APSD enabled ACs */ 786 uint16_t kv_len; /* length in bits */ 787 uint8_t kv_val[16]; /* enough for 128-bit keys */ 788 uint8_t kv_mic[8]; /* TKIP MIC key */ 789 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 790} HAL_KEYVAL; 791 792/* 793 * This is the TX descriptor field which marks the key padding requirement. 794 * The naming is unfortunately unclear. 795 */ 796#define AH_KEYTYPE_MASK 0x0F 797typedef enum { 798 HAL_KEY_TYPE_CLEAR, 799 HAL_KEY_TYPE_WEP, 800 HAL_KEY_TYPE_AES, 801 HAL_KEY_TYPE_TKIP, 802} HAL_KEY_TYPE; 803 804typedef enum { 805 HAL_CIPHER_WEP = 0, 806 HAL_CIPHER_AES_OCB = 1, 807 HAL_CIPHER_AES_CCM = 2, 808 HAL_CIPHER_CKIP = 3, 809 HAL_CIPHER_TKIP = 4, 810 HAL_CIPHER_CLR = 5, /* no encryption */ 811 812 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 813} HAL_CIPHER; 814 815enum { 816 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 817 HAL_SLOT_TIME_9 = 9, 818 HAL_SLOT_TIME_20 = 20, 819}; 820 821/* 822 * Per-station beacon timer state. Note that the specified 823 * beacon interval (given in TU's) can also include flags 824 * to force a TSF reset and to enable the beacon xmit logic. 825 * If bs_cfpmaxduration is non-zero the hardware is setup to 826 * coexist with a PCF-capable AP. 827 */ 828typedef struct { 829 uint32_t bs_nexttbtt; /* next beacon in TU */ 830 uint32_t bs_nextdtim; /* next DTIM in TU */ 831 uint32_t bs_intval; /* beacon interval+flags */ 832/* 833 * HAL_BEACON_PERIOD, HAL_BEACON_ENA and HAL_BEACON_RESET_TSF 834 * are all 1:1 correspondances with the pre-11n chip AR_BEACON 835 * register. 836 */ 837#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 838#define HAL_BEACON_PERIOD_TU8 0x0007ffff /* beacon interval, tu/8 */ 839#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 840#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 841#define HAL_TSFOOR_THRESHOLD 0x00004240 /* TSF OOR thresh (16k uS) */ 842 uint32_t bs_dtimperiod; 843 uint16_t bs_cfpperiod; /* CFP period in TU */ 844 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 845 uint32_t bs_cfpnext; /* next CFP in TU */ 846 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 847 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 848 uint32_t bs_sleepduration; /* max sleep duration */ 849 uint32_t bs_tsfoor_threshold; /* TSF out of range threshold */ 850} HAL_BEACON_STATE; 851 852/* 853 * Like HAL_BEACON_STATE but for non-station mode setup. 854 * NB: see above flag definitions for bt_intval. 855 */ 856typedef struct { 857 uint32_t bt_intval; /* beacon interval+flags */ 858 uint32_t bt_nexttbtt; /* next beacon in TU */ 859 uint32_t bt_nextatim; /* next ATIM in TU */ 860 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 861 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 862 uint32_t bt_flags; /* timer enables */ 863#define HAL_BEACON_TBTT_EN 0x00000001 864#define HAL_BEACON_DBA_EN 0x00000002 865#define HAL_BEACON_SWBA_EN 0x00000004 866} HAL_BEACON_TIMERS; 867 868/* 869 * Per-node statistics maintained by the driver for use in 870 * optimizing signal quality and other operational aspects. 871 */ 872typedef struct { 873 uint32_t ns_avgbrssi; /* average beacon rssi */ 874 uint32_t ns_avgrssi; /* average data rssi */ 875 uint32_t ns_avgtxrssi; /* average tx rssi */ 876} HAL_NODE_STATS; 877 878#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 879 880/* 881 * This is the ANI state and MIB stats. 882 * 883 * It's used by the HAL modules to keep state /and/ by the debug ioctl 884 * to fetch ANI information. 885 */ 886typedef struct { 887 uint32_t ast_ani_niup; /* ANI increased noise immunity */ 888 uint32_t ast_ani_nidown; /* ANI decreased noise immunity */ 889 uint32_t ast_ani_spurup; /* ANI increased spur immunity */ 890 uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */ 891 uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ 892 uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ 893 uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ 894 uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ 895 uint32_t ast_ani_stepup; /* ANI increased first step level */ 896 uint32_t ast_ani_stepdown;/* ANI decreased first step level */ 897 uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ 898 uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ 899 uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ 900 uint32_t ast_ani_lzero; /* ANI listen time forced to zero */ 901 uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ 902 HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ 903 HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ 904} HAL_ANI_STATS; 905 906typedef struct { 907 uint8_t noiseImmunityLevel; /* Global for pre-AR9380; OFDM later*/ 908 uint8_t cckNoiseImmunityLevel; /* AR9380: CCK specific NI */ 909 uint8_t spurImmunityLevel; 910 uint8_t firstepLevel; 911 uint8_t ofdmWeakSigDetectOff; 912 uint8_t cckWeakSigThreshold; 913 uint8_t mrcCck; /* MRC CCK is enabled */ 914 uint32_t listenTime; 915 916 /* NB: intentionally ordered so data exported to user space is first */ 917 uint32_t txFrameCount; /* Last txFrameCount */ 918 uint32_t rxFrameCount; /* Last rx Frame count */ 919 uint32_t cycleCount; /* Last cycleCount 920 (to detect wrap-around) */ 921 uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */ 922 uint32_t cckPhyErrCount; /* CCK err count since last reset */ 923} HAL_ANI_STATE; 924 925struct ath_desc; 926struct ath_tx_status; 927struct ath_rx_status; 928struct ieee80211_channel; 929 930/* 931 * This is a channel survey sample entry. 932 * 933 * The AR5212 ANI routines fill these samples. The ANI code then uses it 934 * when calculating listen time; it is also exported via a diagnostic 935 * API. 936 */ 937typedef struct { 938 uint32_t seq_num; 939 uint32_t tx_busy; 940 uint32_t rx_busy; 941 uint32_t chan_busy; 942 uint32_t ext_chan_busy; 943 uint32_t cycle_count; 944 /* XXX TODO */ 945 uint32_t ofdm_phyerr_count; 946 uint32_t cck_phyerr_count; 947} HAL_SURVEY_SAMPLE; 948 949/* 950 * This provides 3.2 seconds of sample space given an 951 * ANI time of 1/10th of a second. This may not be enough! 952 */ 953#define CHANNEL_SURVEY_SAMPLE_COUNT 32 954 955typedef struct { 956 HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; 957 uint32_t cur_sample; /* current sample in sequence */ 958 uint32_t cur_seq; /* current sequence number */ 959} HAL_CHANNEL_SURVEY; 960 961/* 962 * ANI commands. 963 * 964 * These are used both internally and externally via the diagnostic 965 * API. 966 * 967 * Note that this is NOT the ANI commands being used via the INTMIT 968 * capability - that has a different mapping for some reason. 969 */ 970typedef enum { 971 HAL_ANI_PRESENT = 0, /* is ANI support present */ 972 HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level (global or ofdm) */ 973 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */ 974 HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */ 975 HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */ 976 HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */ 977 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 978 HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */ 979 HAL_ANI_MRC_CCK = 8, 980 HAL_ANI_CCK_NOISE_IMMUNITY_LEVEL = 9, /* set level (cck) */ 981} HAL_ANI_CMD; 982 983#define HAL_ANI_ALL 0xffffffff 984 985/* 986 * This is the layout of the ANI INTMIT capability. 987 * 988 * Notice that the command values differ to HAL_ANI_CMD. 989 */ 990typedef enum { 991 HAL_CAP_INTMIT_PRESENT = 0, 992 HAL_CAP_INTMIT_ENABLE = 1, 993 HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2, 994 HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3, 995 HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4, 996 HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5, 997 HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6 998} HAL_CAP_INTMIT_CMD; 999 1000typedef struct { 1001 int32_t pe_firpwr; /* FIR pwr out threshold */ 1002 int32_t pe_rrssi; /* Radar rssi thresh */ 1003 int32_t pe_height; /* Pulse height thresh */ 1004 int32_t pe_prssi; /* Pulse rssi thresh */ 1005 int32_t pe_inband; /* Inband thresh */ 1006 1007 /* The following params are only for AR5413 and later */ 1008 u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */ 1009 u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */ 1010 u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */ 1011 int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */ 1012 int32_t pe_blockradar; /* 1013 * Enable to block radar check if pkt detect is done via OFDM 1014 * weak signal detect or pkt is detected immediately after tx 1015 * to rx transition 1016 */ 1017 int32_t pe_enmaxrssi; /* 1018 * Enable to use the max rssi instead of the last rssi during 1019 * fine gain changes for radar detection 1020 */ 1021 int32_t pe_extchannel; /* Enable DFS on ext channel */ 1022 int32_t pe_enabled; /* Whether radar detection is enabled */ 1023 int32_t pe_enrelpwr; 1024 int32_t pe_en_relstep_check; 1025} HAL_PHYERR_PARAM; 1026 1027#define HAL_PHYERR_PARAM_NOVAL 65535 1028 1029typedef struct { 1030 u_int16_t ss_fft_period; /* Skip interval for FFT reports */ 1031 u_int16_t ss_period; /* Spectral scan period */ 1032 u_int16_t ss_count; /* # of reports to return from ss_active */ 1033 u_int16_t ss_short_report;/* Set to report ony 1 set of FFT results */ 1034 u_int8_t radar_bin_thresh_sel; /* strong signal radar FFT threshold configuration */ 1035 u_int16_t ss_spectral_pri; /* are we doing a noise power cal ? */ 1036 int8_t ss_nf_cal[AH_MAX_CHAINS*2]; /* nf calibrated values for ctl+ext from eeprom */ 1037 int8_t ss_nf_pwr[AH_MAX_CHAINS*2]; /* nf pwr values for ctl+ext from eeprom */ 1038 int32_t ss_nf_temp_data; /* temperature data taken during nf scan */ 1039 int ss_enabled; 1040 int ss_active; 1041} HAL_SPECTRAL_PARAM; 1042#define HAL_SPECTRAL_PARAM_NOVAL 0xFFFF 1043#define HAL_SPECTRAL_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */ 1044 1045/* 1046 * DFS operating mode flags. 1047 */ 1048typedef enum { 1049 HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ 1050 HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ 1051 HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ 1052 HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ 1053} HAL_DFS_DOMAIN; 1054 1055/* 1056 * MFP decryption options for initializing the MAC. 1057 */ 1058typedef enum { 1059 HAL_MFP_QOSDATA = 0, /* Decrypt MFP frames like QoS data frames. All chips before Merlin. */ 1060 HAL_MFP_PASSTHRU, /* Don't decrypt MFP frames at all. Passthrough */ 1061 HAL_MFP_HW_CRYPTO /* hardware decryption enabled. Merlin can do it. */ 1062} HAL_MFP_OPT_T; 1063 1064/* LNA config supported */ 1065typedef enum { 1066 HAL_ANT_DIV_COMB_LNA1_MINUS_LNA2 = 0, 1067 HAL_ANT_DIV_COMB_LNA2 = 1, 1068 HAL_ANT_DIV_COMB_LNA1 = 2, 1069 HAL_ANT_DIV_COMB_LNA1_PLUS_LNA2 = 3, 1070} HAL_ANT_DIV_COMB_LNA_CONF; 1071 1072typedef struct { 1073 u_int8_t main_lna_conf; 1074 u_int8_t alt_lna_conf; 1075 u_int8_t fast_div_bias; 1076 u_int8_t main_gaintb; 1077 u_int8_t alt_gaintb; 1078 u_int8_t antdiv_configgroup; 1079 int8_t lna1_lna2_delta; 1080} HAL_ANT_COMB_CONFIG; 1081 1082#define DEFAULT_ANTDIV_CONFIG_GROUP 0x00 1083#define HAL_ANTDIV_CONFIG_GROUP_1 0x01 1084#define HAL_ANTDIV_CONFIG_GROUP_2 0x02 1085#define HAL_ANTDIV_CONFIG_GROUP_3 0x03 1086 1087/* 1088 * Flag for setting QUIET period 1089 */ 1090typedef enum { 1091 HAL_QUIET_DISABLE = 0x0, 1092 HAL_QUIET_ENABLE = 0x1, 1093 HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */ 1094 HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */ 1095} HAL_QUIET_FLAG; 1096 1097#define HAL_DFS_EVENT_PRICH 0x0000001 1098#define HAL_DFS_EVENT_EXTCH 0x0000002 1099#define HAL_DFS_EVENT_EXTEARLY 0x0000004 1100#define HAL_DFS_EVENT_ISDC 0x0000008 1101 1102struct hal_dfs_event { 1103 uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */ 1104 uint32_t re_ts; /* Original 15 bit recv timestamp */ 1105 uint8_t re_rssi; /* rssi of radar event */ 1106 uint8_t re_dur; /* duration of radar pulse */ 1107 uint32_t re_flags; /* Flags (see above) */ 1108}; 1109typedef struct hal_dfs_event HAL_DFS_EVENT; 1110 1111/* 1112 * Generic Timer domain 1113 */ 1114typedef enum { 1115 HAL_GEN_TIMER_TSF = 0, 1116 HAL_GEN_TIMER_TSF2, 1117 HAL_GEN_TIMER_TSF_ANY 1118} HAL_GEN_TIMER_DOMAIN; 1119 1120/* 1121 * BT Co-existence definitions 1122 */ 1123#include "ath_hal/ah_btcoex.h" 1124 1125struct hal_bb_panic_info { 1126 u_int32_t status; 1127 u_int32_t tsf; 1128 u_int32_t phy_panic_wd_ctl1; 1129 u_int32_t phy_panic_wd_ctl2; 1130 u_int32_t phy_gen_ctrl; 1131 u_int32_t rxc_pcnt; 1132 u_int32_t rxf_pcnt; 1133 u_int32_t txf_pcnt; 1134 u_int32_t cycles; 1135 u_int32_t wd; 1136 u_int32_t det; 1137 u_int32_t rdar; 1138 u_int32_t r_odfm; 1139 u_int32_t r_cck; 1140 u_int32_t t_odfm; 1141 u_int32_t t_cck; 1142 u_int32_t agc; 1143 u_int32_t src; 1144}; 1145 1146/* Serialize Register Access Mode */ 1147typedef enum { 1148 SER_REG_MODE_OFF = 0, 1149 SER_REG_MODE_ON = 1, 1150 SER_REG_MODE_AUTO = 2, 1151} SER_REG_MODE; 1152 1153typedef struct 1154{ 1155 int ah_debug; /* only used if AH_DEBUG is defined */ 1156 int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */ 1157 1158 /* NB: these are deprecated; they exist for now for compatibility */ 1159 int ah_dma_beacon_response_time;/* in TU's */ 1160 int ah_sw_beacon_response_time; /* in TU's */ 1161 int ah_additional_swba_backoff; /* in TU's */ 1162 int ah_force_full_reset; /* force full chip reset rather then warm reset */ 1163 int ah_serialise_reg_war; /* force serialisation of register IO */ 1164 1165 /* XXX these don't belong here, they're just for the ar9300 HAL port effort */ 1166 int ath_hal_desc_tpc; /* Per-packet TPC */ 1167 int ath_hal_sta_update_tx_pwr_enable; /* GreenTX */ 1168 int ath_hal_sta_update_tx_pwr_enable_S1; /* GreenTX */ 1169 int ath_hal_sta_update_tx_pwr_enable_S2; /* GreenTX */ 1170 int ath_hal_sta_update_tx_pwr_enable_S3; /* GreenTX */ 1171 1172 /* I'm not sure what the default values for these should be */ 1173 int ath_hal_pll_pwr_save; 1174 int ath_hal_pcie_power_save_enable; 1175 int ath_hal_intr_mitigation_rx; 1176 int ath_hal_intr_mitigation_tx; 1177 1178 int ath_hal_pcie_clock_req; 1179#define AR_PCIE_PLL_PWRSAVE_CONTROL (1<<0) 1180#define AR_PCIE_PLL_PWRSAVE_ON_D3 (1<<1) 1181#define AR_PCIE_PLL_PWRSAVE_ON_D0 (1<<2) 1182 1183 int ath_hal_pcie_waen; 1184 int ath_hal_pcie_ser_des_write; 1185 1186 /* these are important for correct AR9300 behaviour */ 1187 int ath_hal_ht_enable; /* needs to be enabled for AR9300 HT */ 1188 int ath_hal_diversity_control; 1189 int ath_hal_antenna_switch_swap; 1190 int ath_hal_ext_lna_ctl_gpio; 1191 int ath_hal_spur_mode; 1192 int ath_hal_6mb_ack; /* should set this to 1 for 11a/11na? */ 1193 int ath_hal_enable_msi; /* enable MSI interrupts (needed?) */ 1194 int ath_hal_beacon_filter_interval; /* ok to be 0 for now? */ 1195 1196 /* For now, set this to 0 - net80211 needs to know about hardware MFP support */ 1197 int ath_hal_mfp_support; 1198 1199 int ath_hal_enable_ani; /* should set this.. */ 1200 int ath_hal_cwm_ignore_ext_cca; 1201 int ath_hal_show_bb_panic; 1202 int ath_hal_ant_ctrl_comm2g_switch_enable; 1203 int ath_hal_ext_atten_margin_cfg; 1204 int ath_hal_min_gainidx; 1205 int ath_hal_war70c; 1206 uint32_t ath_hal_mci_config; 1207} HAL_OPS_CONFIG; 1208 1209/* 1210 * Hardware Access Layer (HAL) API. 1211 * 1212 * Clients of the HAL call ath_hal_attach to obtain a reference to an 1213 * ath_hal structure for use with the device. Hardware-related operations 1214 * that follow must call back into the HAL through interface, supplying 1215 * the reference as the first parameter. Note that before using the 1216 * reference returned by ath_hal_attach the caller should verify the 1217 * ABI version number. 1218 */ 1219struct ath_hal { 1220 uint32_t ah_magic; /* consistency check magic number */ 1221 uint16_t ah_devid; /* PCI device ID */ 1222 uint16_t ah_subvendorid; /* PCI subvendor ID */ 1223 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 1224 HAL_BUS_TAG ah_st; /* params for register r+w */ 1225 HAL_BUS_HANDLE ah_sh; 1226 HAL_CTRY_CODE ah_countryCode; 1227 1228 uint32_t ah_macVersion; /* MAC version id */ 1229 uint16_t ah_macRev; /* MAC revision */ 1230 uint16_t ah_phyRev; /* PHY revision */ 1231 /* NB: when only one radio is present the rev is in 5Ghz */ 1232 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 1233 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 1234 1235 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 1236 1237 uint32_t ah_intrstate[8]; /* last int state */ 1238 uint32_t ah_syncstate; /* last sync intr state */ 1239 1240 /* Current powerstate from HAL calls */ 1241 HAL_POWER_MODE ah_powerMode; 1242 1243 HAL_OPS_CONFIG ah_config; 1244 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 1245 u_int mode); 1246 void __ahdecl(*ah_detach)(struct ath_hal*); 1247 1248 /* Reset functions */ 1249 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 1250 struct ieee80211_channel *, 1251 HAL_BOOL bChannelChange, 1252 HAL_RESET_TYPE resetType, 1253 HAL_STATUS *status); 1254 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 1255 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 1256 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore, 1257 HAL_BOOL power_off); 1258 void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 1259 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 1260 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 1261 struct ieee80211_channel *, HAL_BOOL *); 1262 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 1263 struct ieee80211_channel *, u_int chainMask, 1264 HAL_BOOL longCal, HAL_BOOL *isCalDone); 1265 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 1266 const struct ieee80211_channel *); 1267 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 1268 const struct ieee80211_channel *, uint16_t *); 1269 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 1270 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 1271 const struct ieee80211_channel *); 1272 1273 /* Transmit functions */ 1274 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 1275 HAL_BOOL incTrigLevel); 1276 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 1277 const HAL_TXQ_INFO *qInfo); 1278 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 1279 const HAL_TXQ_INFO *qInfo); 1280 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 1281 HAL_TXQ_INFO *qInfo); 1282 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 1283 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 1284 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 1285 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 1286 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 1287 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 1288 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 1289 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 1290 u_int pktLen, u_int hdrLen, 1291 HAL_PKT_TYPE type, u_int txPower, 1292 u_int txRate0, u_int txTries0, 1293 u_int keyIx, u_int antMode, u_int flags, 1294 u_int rtsctsRate, u_int rtsctsDuration, 1295 u_int compicvLen, u_int compivLen, 1296 u_int comp); 1297 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 1298 u_int txRate1, u_int txTries1, 1299 u_int txRate2, u_int txTries2, 1300 u_int txRate3, u_int txTries3); 1301 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 1302 HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, 1303 u_int descId, u_int qcuId, HAL_BOOL firstSeg, 1304 HAL_BOOL lastSeg, const struct ath_desc *); 1305 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 1306 struct ath_desc *, struct ath_tx_status *); 1307 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 1308 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 1309 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 1310 const struct ath_desc *ds, int *rates, int *tries); 1311 void __ahdecl(*ah_setTxDescLink)(struct ath_hal *ah, void *ds, 1312 uint32_t link); 1313 void __ahdecl(*ah_getTxDescLink)(struct ath_hal *ah, void *ds, 1314 uint32_t *link); 1315 void __ahdecl(*ah_getTxDescLinkPtr)(struct ath_hal *ah, void *ds, 1316 uint32_t **linkptr); 1317 void __ahdecl(*ah_setupTxStatusRing)(struct ath_hal *, 1318 void *ts_start, uint32_t ts_paddr_start, 1319 uint16_t size); 1320 void __ahdecl(*ah_getTxRawTxDesc)(struct ath_hal *, u_int32_t *); 1321 1322 /* Receive Functions */ 1323 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*, HAL_RX_QUEUE); 1324 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp, HAL_RX_QUEUE); 1325 void __ahdecl(*ah_enableReceive)(struct ath_hal*); 1326 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 1327 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*, HAL_BOOL); 1328 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 1329 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 1330 uint32_t filter0, uint32_t filter1); 1331 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 1332 uint32_t index); 1333 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 1334 uint32_t index); 1335 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 1336 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 1337 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 1338 uint32_t size, u_int flags); 1339 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 1340 struct ath_desc *, uint32_t phyAddr, 1341 struct ath_desc *next, uint64_t tsf, 1342 struct ath_rx_status *); 1343 void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 1344 const HAL_NODE_STATS *, 1345 const struct ieee80211_channel *); 1346 void __ahdecl(*ah_aniPoll)(struct ath_hal *, 1347 const struct ieee80211_channel *); 1348 void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 1349 const HAL_NODE_STATS *); 1350 1351 /* Misc Functions */ 1352 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 1353 HAL_CAPABILITY_TYPE, uint32_t capability, 1354 uint32_t *result); 1355 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 1356 HAL_CAPABILITY_TYPE, uint32_t capability, 1357 uint32_t setting, HAL_STATUS *); 1358 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 1359 const void *args, uint32_t argsize, 1360 void **result, uint32_t *resultsize); 1361 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 1362 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 1363 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 1364 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 1365 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 1366 uint16_t, HAL_STATUS *); 1367 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 1368 void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 1369 const uint8_t *bssid, uint16_t assocId); 1370 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 1371 uint32_t gpio, HAL_GPIO_MUX_TYPE); 1372 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 1373 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 1374 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 1375 uint32_t gpio, uint32_t val); 1376 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 1377 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 1378 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 1379 void __ahdecl(*ah_setTsf64)(struct ath_hal *, uint64_t); 1380 void __ahdecl(*ah_resetTsf)(struct ath_hal*); 1381 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 1382 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 1383 HAL_MIB_STATS*); 1384 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 1385 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 1386 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 1387 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 1388 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 1389 HAL_ANT_SETTING); 1390 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 1391 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 1392 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 1393 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 1394 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 1395 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 1396 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 1397 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 1398 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 1399 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 1400 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 1401 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 1402 HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period, 1403 uint32_t duration, uint32_t nextStart, 1404 HAL_QUIET_FLAG flag); 1405 void __ahdecl(*ah_setChainMasks)(struct ath_hal *, 1406 uint32_t, uint32_t); 1407 1408 /* DFS functions */ 1409 void __ahdecl(*ah_enableDfs)(struct ath_hal *ah, 1410 HAL_PHYERR_PARAM *pe); 1411 void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah, 1412 HAL_PHYERR_PARAM *pe); 1413 HAL_BOOL __ahdecl(*ah_getDfsDefaultThresh)(struct ath_hal *ah, 1414 HAL_PHYERR_PARAM *pe); 1415 HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah, 1416 struct ath_rx_status *rxs, uint64_t fulltsf, 1417 const char *buf, HAL_DFS_EVENT *event); 1418 HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah); 1419 void __ahdecl(*ah_setDfsCacTxQuiet)(struct ath_hal *, HAL_BOOL); 1420 1421 /* Spectral Scan functions */ 1422 void __ahdecl(*ah_spectralConfigure)(struct ath_hal *ah, 1423 HAL_SPECTRAL_PARAM *sp); 1424 void __ahdecl(*ah_spectralGetConfig)(struct ath_hal *ah, 1425 HAL_SPECTRAL_PARAM *sp); 1426 void __ahdecl(*ah_spectralStart)(struct ath_hal *); 1427 void __ahdecl(*ah_spectralStop)(struct ath_hal *); 1428 HAL_BOOL __ahdecl(*ah_spectralIsEnabled)(struct ath_hal *); 1429 HAL_BOOL __ahdecl(*ah_spectralIsActive)(struct ath_hal *); 1430 /* XXX getNfPri() and getNfExt() */ 1431 1432 /* Key Cache Functions */ 1433 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 1434 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 1435 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 1436 uint16_t); 1437 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 1438 uint16_t, const HAL_KEYVAL *, 1439 const uint8_t *, int); 1440 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 1441 uint16_t, const uint8_t *); 1442 1443 /* Power Management Functions */ 1444 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 1445 HAL_POWER_MODE mode, int setChip); 1446 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 1447 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 1448 const struct ieee80211_channel *); 1449 1450 /* Beacon Management Functions */ 1451 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 1452 const HAL_BEACON_TIMERS *); 1453 /* NB: deprecated, use ah_setBeaconTimers instead */ 1454 void __ahdecl(*ah_beaconInit)(struct ath_hal *, 1455 uint32_t nexttbtt, uint32_t intval); 1456 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 1457 const HAL_BEACON_STATE *); 1458 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 1459 uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *); 1460 1461 /* 802.11n Functions */ 1462 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 1463 struct ath_desc *, 1464 HAL_DMA_ADDR *bufAddrList, 1465 uint32_t *segLenList, 1466 u_int, u_int, HAL_PKT_TYPE, 1467 u_int, HAL_CIPHER, uint8_t, HAL_BOOL, 1468 HAL_BOOL, HAL_BOOL); 1469 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 1470 struct ath_desc *, u_int, u_int, u_int, 1471 u_int, u_int, u_int, u_int, u_int); 1472 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 1473 struct ath_desc *, const struct ath_desc *); 1474 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 1475 struct ath_desc *, u_int, u_int, 1476 HAL_11N_RATE_SERIES [], u_int, u_int); 1477 1478 /* 1479 * The next 4 (set11ntxdesc -> set11naggrlast) are specific 1480 * to the EDMA HAL. Descriptors are chained together by 1481 * using filltxdesc (not ChainTxDesc) and then setting the 1482 * aggregate flags appropriately using first/middle/last. 1483 */ 1484 void __ahdecl(*ah_set11nTxDesc)(struct ath_hal *, 1485 void *, u_int, HAL_PKT_TYPE, u_int, u_int, 1486 u_int); 1487 void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *, 1488 struct ath_desc *, u_int, u_int); 1489 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 1490 struct ath_desc *, u_int); 1491 void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *, 1492 struct ath_desc *); 1493 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 1494 struct ath_desc *); 1495 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 1496 struct ath_desc *, u_int); 1497 void __ahdecl(*ah_set11nVirtMoreFrag)(struct ath_hal *, 1498 struct ath_desc *, u_int); 1499 1500 HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *, 1501 HAL_SURVEY_SAMPLE *); 1502 1503 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 1504 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 1505 HAL_HT_MACMODE); 1506 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 1507 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 1508 HAL_HT_RXCLEAR); 1509 1510 /* Interrupt functions */ 1511 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 1512 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 1513 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 1514 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 1515 1516 /* Bluetooth Coexistence functions */ 1517 void __ahdecl(*ah_btCoexSetInfo)(struct ath_hal *, 1518 HAL_BT_COEX_INFO *); 1519 void __ahdecl(*ah_btCoexSetConfig)(struct ath_hal *, 1520 HAL_BT_COEX_CONFIG *); 1521 void __ahdecl(*ah_btCoexSetQcuThresh)(struct ath_hal *, 1522 int); 1523 void __ahdecl(*ah_btCoexSetWeights)(struct ath_hal *, 1524 uint32_t); 1525 void __ahdecl(*ah_btCoexSetBmissThresh)(struct ath_hal *, 1526 uint32_t); 1527 void __ahdecl(*ah_btCoexSetParameter)(struct ath_hal *, 1528 uint32_t, uint32_t); 1529 void __ahdecl(*ah_btCoexDisable)(struct ath_hal *); 1530 int __ahdecl(*ah_btCoexEnable)(struct ath_hal *); 1531 1532 /* Bluetooth MCI methods */ 1533 void __ahdecl(*ah_btMciSetup)(struct ath_hal *, 1534 uint32_t, void *, uint16_t, uint32_t); 1535 HAL_BOOL __ahdecl(*ah_btMciSendMessage)(struct ath_hal *, 1536 uint8_t, uint32_t, uint32_t *, uint8_t, 1537 HAL_BOOL, HAL_BOOL); 1538 uint32_t __ahdecl(*ah_btMciGetInterrupt)(struct ath_hal *, 1539 uint32_t *, uint32_t *); 1540 uint32_t __ahdecl(*ah_btMciState)(struct ath_hal *, 1541 uint32_t, uint32_t *); 1542 void __ahdecl(*ah_btMciDetach)(struct ath_hal *); 1543 1544 /* LNA diversity configuration */ 1545 void __ahdecl(*ah_divLnaConfGet)(struct ath_hal *, 1546 HAL_ANT_COMB_CONFIG *); 1547 void __ahdecl(*ah_divLnaConfSet)(struct ath_hal *, 1548 HAL_ANT_COMB_CONFIG *); 1549}; 1550 1551/* 1552 * Check the PCI vendor ID and device ID against Atheros' values 1553 * and return a printable description for any Atheros hardware. 1554 * AH_NULL is returned if the ID's do not describe Atheros hardware. 1555 */ 1556extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 1557 1558/* 1559 * Attach the HAL for use with the specified device. The device is 1560 * defined by the PCI device ID. The caller provides an opaque pointer 1561 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 1562 * HAL state block for later use. Hardware register accesses are done 1563 * using the specified bus tag and handle. On successful return a 1564 * reference to a state block is returned that must be supplied in all 1565 * subsequent HAL calls. Storage associated with this reference is 1566 * dynamically allocated and must be freed by calling the ah_detach 1567 * method when the client is done. If the attach operation fails a 1568 * null (AH_NULL) reference will be returned and a status code will 1569 * be returned if the status parameter is non-zero. 1570 */ 1571extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 1572 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 1573 HAL_OPS_CONFIG *ah_config, HAL_STATUS* status); 1574 1575extern const char *ath_hal_mac_name(struct ath_hal *); 1576extern const char *ath_hal_rf_name(struct ath_hal *); 1577 1578/* 1579 * Regulatory interfaces. Drivers should use ath_hal_init_channels to 1580 * request a set of channels for a particular country code and/or 1581 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 1582 * this list is constructed according to the contents of the EEPROM. 1583 * ath_hal_getchannels acts similarly but does not alter the operating 1584 * state; this can be used to collect information for a particular 1585 * regulatory configuration. Finally ath_hal_set_channels installs a 1586 * channel list constructed outside the driver. The HAL will adopt the 1587 * channel list and setup internal state according to the specified 1588 * regulatory configuration (e.g. conformance test limits). 1589 * 1590 * For all interfaces the channel list is returned in the supplied array. 1591 * maxchans defines the maximum size of this array. nchans contains the 1592 * actual number of channels returned. If a problem occurred then a 1593 * status code != HAL_OK is returned. 1594 */ 1595struct ieee80211_channel; 1596 1597/* 1598 * Return a list of channels according to the specified regulatory. 1599 */ 1600extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 1601 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1602 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 1603 HAL_BOOL enableExtendedChannels); 1604 1605/* 1606 * Return a list of channels and install it as the current operating 1607 * regulatory list. 1608 */ 1609extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 1610 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1611 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 1612 HAL_BOOL enableExtendedChannels); 1613 1614/* 1615 * Install the list of channels as the current operating regulatory 1616 * and setup related state according to the country code and sku. 1617 */ 1618extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 1619 struct ieee80211_channel *chans, int nchans, 1620 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 1621 1622/* 1623 * Fetch the ctl/ext noise floor values reported by a MIMO 1624 * radio. Returns 1 for valid results, 0 for invalid channel. 1625 */ 1626extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah, 1627 const struct ieee80211_channel *chan, int16_t *nf_ctl, 1628 int16_t *nf_ext); 1629 1630/* 1631 * Calibrate noise floor data following a channel scan or similar. 1632 * This must be called prior retrieving noise floor data. 1633 */ 1634extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 1635 1636/* 1637 * Return bit mask of wireless modes supported by the hardware. 1638 */ 1639extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 1640 1641/* 1642 * Get the HAL wireless mode for the given channel. 1643 */ 1644extern int ath_hal_get_curmode(struct ath_hal *ah, 1645 const struct ieee80211_channel *chan); 1646 1647/* 1648 * Calculate the packet TX time for a legacy or 11n frame 1649 */ 1650extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 1651 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1652 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble, 1653 HAL_BOOL includeSifs); 1654 1655/* 1656 * Calculate the duration of an 11n frame. 1657 */ 1658extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 1659 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 1660 1661/* 1662 * Calculate the transmit duration of a legacy frame. 1663 */ 1664extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 1665 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1666 uint16_t rateix, HAL_BOOL shortPreamble, 1667 HAL_BOOL includeSifs); 1668 1669/* 1670 * Adjust the TSF. 1671 */ 1672extern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta); 1673 1674/* 1675 * Enable or disable CCA. 1676 */ 1677void __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena); 1678 1679/* 1680 * Get CCA setting. 1681 */ 1682int __ahdecl ath_hal_getcca(struct ath_hal *ah); 1683 1684/* 1685 * Enable/disable and get self-gen frame (ACK, CTS) for CAC. 1686 */ 1687void __ahdecl ath_hal_set_dfs_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL ena); 1688 1689/* 1690 * Read EEPROM data from ah_eepromdata 1691 */ 1692HAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah, 1693 u_int off, uint16_t *data); 1694 1695/* 1696 * For now, simply pass through MFP frames. 1697 */ 1698static inline u_int32_t 1699ath_hal_get_mfp_qos(struct ath_hal *ah) 1700{ 1701 //return AH_PRIVATE(ah)->ah_mfp_qos; 1702 return HAL_MFP_QOSDATA; 1703} 1704 1705/* 1706 * Convert between microseconds and core system clocks. 1707 */ 1708extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 1709extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 1710extern uint64_t ath_hal_mac_psec(struct ath_hal *ah, u_int clks); 1711 1712#endif /* _ATH_AH_H_ */ 1713