1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18/* 19 * READ THIS NOTICE! 20 * 21 * Values defined in this file may only be changed under exceptional circumstances. 22 * 23 * Please ask Fiona Cain before making any changes. 24 */ 25 26#ifndef __ar9300templateAphrodite_h__ 27#define __ar9300templateAphrodite_h__ 28 29static ar9300_eeprom_t ar9300_template_aphrodite= 30{ 31 32 0, // eeprom_version; 33 34 ar9300_eeprom_template_aphrodite, // template_version; 35 36 {0x00,0x03,0x7f,0x0,0x0,0x11}, //mac_addr[6]; 37 38 //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= 39 40 {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 41 42 //static OSPREY_BASE_EEP_HEADER base_eep_header= 43 44 { 45 {0,0x1f}, // reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration 46 0x11, // txrx_mask; //4 bits tx and 4 bits rx 47 {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 0}, // op_cap_flags; 48 0, // rf_silent; 49 0, // blue_tooth_options; 50 0, // device_cap; 51 4, // device_type; // takes lower byte in eeprom location 52 OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration 53 {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don 54 0x10, //feature_enable; //bit0 - enable tx temp comp 55 //bit1 - enable tx volt comp 56 //bit2 - enable fastClock - default to 1 57 //bit3 - enable doubling - default to 1 58 //bit4 - enable internal regulator - default to 0 59 0, //misc_configuration: bit0 - turn down drivestrength 60 3, // eeprom_write_enable_gpio 61 0, // wlan_disable_gpio 62 8, // wlan_led_gpio 63 0xff, // rx_band_select_gpio 64 0, // txrxgain 65 0, // swreg 66 }, 67 68 69 //static OSPREY_MODAL_EEP_HEADER modal_header_2g= 70 { 71 72 0x0, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) 73 0x0, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 74 {0x0,0x150,0x150}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 75 {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 76 {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 77 36, // temp_slope; 78 0, // voltSlope; 79 {0,0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 80 {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 81 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 82 0, // quick drop 83 0, // xpa_bias_lvl; // 1 84 0x0e, // tx_frame_to_data_start; // 1 85 0x0e, // tx_frame_to_pa_on; // 1 86 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 87 0, // antenna_gain; // 1 88 0x2c, // switchSettling; // 1 89 -30, // adcDesiredSize; // 1 90 0, // txEndToXpaOff; // 1 91 0x2, // txEndToRxOn; // 1 92 0xe, // tx_frame_to_xpa_on; // 1 93 28, // thresh62; // 1 94 0x0c80C080, // paprd_rate_mask_ht20 // 4 95 0x0080C080, // paprd_rate_mask_ht40 96 0, // switchcomspdt; // 2 97 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 98 0, // rf_gain_cap 99 0, // tx_gain_cap 100 {0,0,0,0,0} //futureModal[5]; 101 }, 102 103 { 104 0, // ant_div_control 105 {0,0}, // base_ext1 106 0, // misc_enable 107 {0,0,0,0,0,0,0,0}, // temp slop extension 108 0, // quick drop low 109 0, // quick drop high 110 }, 111 112 //static A_UINT8 cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS]= 113 { 114 FREQ2FBIN(2412, 1), 115 FREQ2FBIN(2437, 1), 116 FREQ2FBIN(2472, 1) 117 }, 118 119 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= 120 121 { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 122 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 123 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 124 }, 125 126 //A_UINT8 cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; 127 128 { 129 FREQ2FBIN(2412, 1), 130 FREQ2FBIN(2484, 1) 131 }, 132 133 //static CAL_TARGET_POWER_LEG cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS] 134 { 135 FREQ2FBIN(2412, 1), 136 FREQ2FBIN(2437, 1), 137 FREQ2FBIN(2472, 1) 138 }, 139 140 //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS] 141 { 142 FREQ2FBIN(2412, 1), 143 FREQ2FBIN(2437, 1), 144 FREQ2FBIN(2472, 1) 145 }, 146 147 //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS] 148 { 149 FREQ2FBIN(2412, 1), 150 FREQ2FBIN(2437, 1), 151 FREQ2FBIN(2472, 1) 152 }, 153 154 //static CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= 155 { 156 //1L-5L,5S,11L,11S 157 {{36,36,36,36}}, 158 {{36,36,36,36}} 159 }, 160 161 //static CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS]= 162 { 163 //6-24,36,48,54 164 {{32,32,28,24}}, 165 {{32,32,28,24}}, 166 {{32,32,28,24}}, 167 }, 168 169 //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]= 170 { 171 //0_8_16,1-3_9-11_17-19, 172 // 4,5,6,7,12,13,14,15,20,21,22,23 173 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 174 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 175 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 176 }, 177 178 //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]= 179 { 180 //0_8_16,1-3_9-11_17-19, 181 // 4,5,6,7,12,13,14,15,20,21,22,23 182 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 183 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 184 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 185 }, 186 187//static A_UINT8 ctl_index_2g[OSPREY_NUM_CTLS_2G]= 188 189 { 190 191 0x11, 192 0x12, 193 0x15, 194 0x17, 195 0x41, 196 0x42, 197 0x45, 198 0x47, 199 0x31, 200 0x32, 201 0x35, 202 0x37 203 204 }, 205 206//A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; 207 208 { 209 {FREQ2FBIN(2412, 1), 210 FREQ2FBIN(2417, 1), 211 FREQ2FBIN(2457, 1), 212 FREQ2FBIN(2462, 1)}, 213 214 {FREQ2FBIN(2412, 1), 215 FREQ2FBIN(2417, 1), 216 FREQ2FBIN(2462, 1), 217 0xFF}, 218 219 {FREQ2FBIN(2412, 1), 220 FREQ2FBIN(2417, 1), 221 FREQ2FBIN(2462, 1), 222 0xFF}, 223 224 {FREQ2FBIN(2422, 1), 225 FREQ2FBIN(2427, 1), 226 FREQ2FBIN(2447, 1), 227 FREQ2FBIN(2452, 1)}, 228 229 {/*Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 230 /*Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 231 /*Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 232 /*Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(2484, 1)}, 233 234 {/*Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 235 /*Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 236 /*Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 237 0}, 238 239 {/*Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 240 /*Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 241 FREQ2FBIN(2472, 1), 242 0}, 243 244 {/*Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), 245 /*Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), 246 /*Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), 247 /*Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)}, 248 249 {/*Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 250 /*Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 251 /*Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 252 0}, 253 254 {/*Data[9].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 255 /*Data[9].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 256 /*Data[9].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 257 0}, 258 259 {/*Data[10].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 260 /*Data[10].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 261 /*Data[10].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 262 0}, 263 264 {/*Data[11].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), 265 /*Data[11].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), 266 /*Data[11].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), 267 /*Data[11].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)} 268 }, 269 270 271//OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G]; 272 273#if AH_BYTE_ORDER == AH_BIG_ENDIAN 274 { 275 276 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 277 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 278 {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, 279 280 {{{1, 60}, {0, 60}, {0, 0}, {0, 0}}}, 281 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 282 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 283 284 {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, 285 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 286 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 287 288 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 289 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, 290 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, 291 292 }, 293#else 294 { 295 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 296 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 297 {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, 298 299 {{{60, 1}, {60, 0}, {0, 0}, {0, 0}}}, 300 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 301 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 302 303 {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, 304 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 305 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 306 307 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 308 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, 309 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, 310 }, 311#endif 312 313//static OSPREY_MODAL_EEP_HEADER modal_header_5g= 314 315 { 316 317 0x110, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) 318 0x22222, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 319 {0x000,0x000,0x000}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 320 {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 321 {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 322 68, // temp_slope; 323 0, // voltSlope; 324 {0,0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 325 {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 326 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 327 0, // quick drop 328 0, // xpa_bias_lvl; // 1 329 0x0e, // tx_frame_to_data_start; // 1 330 0x0e, // tx_frame_to_pa_on; // 1 331 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 332 0, // antenna_gain; // 1 333 0x2d, // switchSettling; // 1 334 -30, // adcDesiredSize; // 1 335 0, // txEndToXpaOff; // 1 336 0x2, // txEndToRxOn; // 1 337 0xe, // tx_frame_to_xpa_on; // 1 338 28, // thresh62; // 1 339 0x0cf0e0e0, // paprd_rate_mask_ht20 // 4 340 0x6cf0e0e0, // paprd_rate_mask_ht40 // 4 341 0, // switchcomspdt; // 2 342 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 343 0, // rf_gain_cap 344 0, // tx_gain_cap 345 {0,0,0,0,0} //futureModal[5]; 346 }, 347 348 { // base_ext2 349 0, 350 0, 351 {0,0,0}, 352 {0,0,0}, 353 {0,0,0}, 354 {0,0,0} 355 }, 356 357//static A_UINT8 cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS]= 358 { 359 //pPiers[0] = 360 FREQ2FBIN(5180, 0), 361 //pPiers[1] = 362 FREQ2FBIN(5220, 0), 363 //pPiers[2] = 364 FREQ2FBIN(5320, 0), 365 //pPiers[3] = 366 FREQ2FBIN(5400, 0), 367 //pPiers[4] = 368 FREQ2FBIN(5500, 0), 369 //pPiers[5] = 370 FREQ2FBIN(5600, 0), 371 //pPiers[6] = 372 FREQ2FBIN(5725, 0), 373 //pPiers[7] = 374 FREQ2FBIN(5825, 0) 375 }, 376 377//static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= 378 379 { 380 {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, 381 {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, 382 {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, 383 384 }, 385 386//static CAL_TARGET_POWER_LEG cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= 387 388 { 389 FREQ2FBIN(5180, 0), 390 FREQ2FBIN(5220, 0), 391 FREQ2FBIN(5320, 0), 392 FREQ2FBIN(5400, 0), 393 FREQ2FBIN(5500, 0), 394 FREQ2FBIN(5600, 0), 395 FREQ2FBIN(5725, 0), 396 FREQ2FBIN(5825, 0) 397 }, 398 399//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= 400 401 { 402 FREQ2FBIN(5180, 0), 403 FREQ2FBIN(5240, 0), 404 FREQ2FBIN(5320, 0), 405 FREQ2FBIN(5500, 0), 406 FREQ2FBIN(5700, 0), 407 FREQ2FBIN(5745, 0), 408 FREQ2FBIN(5725, 0), 409 FREQ2FBIN(5825, 0) 410 }, 411 412//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= 413 414 { 415 FREQ2FBIN(5180, 0), 416 FREQ2FBIN(5240, 0), 417 FREQ2FBIN(5320, 0), 418 FREQ2FBIN(5500, 0), 419 FREQ2FBIN(5700, 0), 420 FREQ2FBIN(5745, 0), 421 FREQ2FBIN(5725, 0), 422 FREQ2FBIN(5825, 0) 423 }, 424 425 426//static CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= 427 428 429 { 430 //6-24,36,48,54 431 {{20,20,20,10}}, 432 {{20,20,20,10}}, 433 {{20,20,20,10}}, 434 {{20,20,20,10}}, 435 {{20,20,20,10}}, 436 {{20,20,20,10}}, 437 {{20,20,20,10}}, 438 {{20,20,20,10}}, 439 }, 440 441//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= 442 443 { 444 //0_8_16,1-3_9-11_17-19, 445 // 4,5,6,7,12,13,14,15,20,21,22,23 446 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 447 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 448 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 449 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 450 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 451 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 452 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 453 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 454 }, 455 456//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= 457 { 458 //0_8_16,1-3_9-11_17-19, 459 // 4,5,6,7,12,13,14,15,20,21,22,23 460 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 461 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 462 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 463 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 464 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 465 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 466 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 467 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 468 }, 469 470//static A_UINT8 ctl_index_5g[OSPREY_NUM_CTLS_5G]= 471 472 { 473 //pCtlIndex[0] = 474 0x10, 475 //pCtlIndex[1] = 476 0x16, 477 //pCtlIndex[2] = 478 0x18, 479 //pCtlIndex[3] = 480 0x40, 481 //pCtlIndex[4] = 482 0x46, 483 //pCtlIndex[5] = 484 0x48, 485 //pCtlIndex[6] = 486 0x30, 487 //pCtlIndex[7] = 488 0x36, 489 //pCtlIndex[8] = 490 0x38 491 }, 492 493// A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; 494 495 { 496 {/* Data[0].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 497 /* Data[0].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 498 /* Data[0].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), 499 /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 500 /* Data[0].ctl_edges[4].bChannel*/FREQ2FBIN(5600, 0), 501 /* Data[0].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 502 /* Data[0].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 503 /* Data[0].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 504 505 {/* Data[1].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 506 /* Data[1].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 507 /* Data[1].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), 508 /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 509 /* Data[1].ctl_edges[4].bChannel*/FREQ2FBIN(5520, 0), 510 /* Data[1].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 511 /* Data[1].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 512 /* Data[1].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 513 514 {/* Data[2].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 515 /* Data[2].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), 516 /* Data[2].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), 517 /* Data[2].ctl_edges[3].bChannel*/FREQ2FBIN(5310, 0), 518 /* Data[2].ctl_edges[4].bChannel*/FREQ2FBIN(5510, 0), 519 /* Data[2].ctl_edges[5].bChannel*/FREQ2FBIN(5550, 0), 520 /* Data[2].ctl_edges[6].bChannel*/FREQ2FBIN(5670, 0), 521 /* Data[2].ctl_edges[7].bChannel*/FREQ2FBIN(5755, 0)}, 522 523 {/* Data[3].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 524 /* Data[3].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), 525 /* Data[3].ctl_edges[2].bChannel*/FREQ2FBIN(5260, 0), 526 /* Data[3].ctl_edges[3].bChannel*/FREQ2FBIN(5320, 0), 527 /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), 528 /* Data[3].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 529 /* Data[3].ctl_edges[6].bChannel*/0xFF, 530 /* Data[3].ctl_edges[7].bChannel*/0xFF}, 531 532 {/* Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 533 /* Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 534 /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0), 535 /* Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(5700, 0), 536 /* Data[4].ctl_edges[4].bChannel*/0xFF, 537 /* Data[4].ctl_edges[5].bChannel*/0xFF, 538 /* Data[4].ctl_edges[6].bChannel*/0xFF, 539 /* Data[4].ctl_edges[7].bChannel*/0xFF}, 540 541 {/* Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 542 /* Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(5270, 0), 543 /* Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(5310, 0), 544 /* Data[5].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), 545 /* Data[5].ctl_edges[4].bChannel*/FREQ2FBIN(5590, 0), 546 /* Data[5].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), 547 /* Data[5].ctl_edges[6].bChannel*/0xFF, 548 /* Data[5].ctl_edges[7].bChannel*/0xFF}, 549 550 {/* Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 551 /* Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), 552 /* Data[6].ctl_edges[2].bChannel*/FREQ2FBIN(5220, 0), 553 /* Data[6].ctl_edges[3].bChannel*/FREQ2FBIN(5260, 0), 554 /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), 555 /* Data[6].ctl_edges[5].bChannel*/FREQ2FBIN(5600, 0), 556 /* Data[6].ctl_edges[6].bChannel*/FREQ2FBIN(5700, 0), 557 /* Data[6].ctl_edges[7].bChannel*/FREQ2FBIN(5745, 0)}, 558 559 {/* Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 560 /* Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 561 /* Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(5320, 0), 562 /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 563 /* Data[7].ctl_edges[4].bChannel*/FREQ2FBIN(5560, 0), 564 /* Data[7].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 565 /* Data[7].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 566 /* Data[7].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 567 568 {/* Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 569 /* Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), 570 /* Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), 571 /* Data[8].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), 572 /* Data[8].ctl_edges[4].bChannel*/FREQ2FBIN(5550, 0), 573 /* Data[8].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), 574 /* Data[8].ctl_edges[6].bChannel*/FREQ2FBIN(5755, 0), 575 /* Data[8].ctl_edges[7].bChannel*/FREQ2FBIN(5795, 0)} 576 }, 577 578//static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= 579 580#if AH_BYTE_ORDER == AH_BIG_ENDIAN 581 { 582 {{{1, 60}, 583 {1, 60}, 584 {1, 60}, 585 {1, 60}, 586 {1, 60}, 587 {1, 60}, 588 {1, 60}, 589 {0, 60}}}, 590 591 {{{1, 60}, 592 {1, 60}, 593 {1, 60}, 594 {1, 60}, 595 {1, 60}, 596 {1, 60}, 597 {1, 60}, 598 {0, 60}}}, 599 600 {{{0, 60}, 601 {1, 60}, 602 {0, 60}, 603 {1, 60}, 604 {1, 60}, 605 {1, 60}, 606 {1, 60}, 607 {1, 60}}}, 608 609 {{{0, 60}, 610 {1, 60}, 611 {1, 60}, 612 {0, 60}, 613 {1, 60}, 614 {0, 60}, 615 {0, 60}, 616 {0, 60}}}, 617 618 {{{1, 60}, 619 {1, 60}, 620 {1, 60}, 621 {0, 60}, 622 {0, 60}, 623 {0, 60}, 624 {0, 60}, 625 {0, 60}}}, 626 627 {{{1, 60}, 628 {1, 60}, 629 {1, 60}, 630 {1, 60}, 631 {1, 60}, 632 {0, 60}, 633 {0, 60}, 634 {0, 60}}}, 635 636 {{{1, 60}, 637 {1, 60}, 638 {1, 60}, 639 {1, 60}, 640 {1, 60}, 641 {1, 60}, 642 {1, 60}, 643 {1, 60}}}, 644 645 {{{1, 60}, 646 {1, 60}, 647 {0, 60}, 648 {1, 60}, 649 {1, 60}, 650 {1, 60}, 651 {1, 60}, 652 {0, 60}}}, 653 654 {{{1, 60}, 655 {0, 60}, 656 {1, 60}, 657 {1, 60}, 658 {1, 60}, 659 {1, 60}, 660 {0, 60}, 661 {1, 60}}}, 662 } 663#else 664 { 665 {{{60, 1}, 666 {60, 1}, 667 {60, 1}, 668 {60, 1}, 669 {60, 1}, 670 {60, 1}, 671 {60, 1}, 672 {60, 0}}}, 673 674 {{{60, 1}, 675 {60, 1}, 676 {60, 1}, 677 {60, 1}, 678 {60, 1}, 679 {60, 1}, 680 {60, 1}, 681 {60, 0}}}, 682 683 {{{60, 0}, 684 {60, 1}, 685 {60, 0}, 686 {60, 1}, 687 {60, 1}, 688 {60, 1}, 689 {60, 1}, 690 {60, 1}}}, 691 692 {{{60, 0}, 693 {60, 1}, 694 {60, 1}, 695 {60, 0}, 696 {60, 1}, 697 {60, 0}, 698 {60, 0}, 699 {60, 0}}}, 700 701 {{{60, 1}, 702 {60, 1}, 703 {60, 1}, 704 {60, 0}, 705 {60, 0}, 706 {60, 0}, 707 {60, 0}, 708 {60, 0}}}, 709 710 {{{60, 1}, 711 {60, 1}, 712 {60, 1}, 713 {60, 1}, 714 {60, 1}, 715 {60, 0}, 716 {60, 0}, 717 {60, 0}}}, 718 719 {{{60, 1}, 720 {60, 1}, 721 {60, 1}, 722 {60, 1}, 723 {60, 1}, 724 {60, 1}, 725 {60, 1}, 726 {60, 1}}}, 727 728 {{{60, 1}, 729 {60, 1}, 730 {60, 0}, 731 {60, 1}, 732 {60, 1}, 733 {60, 1}, 734 {60, 1}, 735 {60, 0}}}, 736 737 {{{60, 1}, 738 {60, 0}, 739 {60, 1}, 740 {60, 1}, 741 {60, 1}, 742 {60, 1}, 743 {60, 0}, 744 {60, 1}}}, 745 } 746#endif 747}; 748 749#endif 750