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33******************************************************************************/
34/*$FreeBSD$*/
35
36#ifndef _E1000_BASE_H_
37#define _E1000_BASE_H_
38
39/* forward declaration */
40s32 e1000_init_hw_base(struct e1000_hw *hw);
41void e1000_power_down_phy_copper_base(struct e1000_hw *hw);
42extern void e1000_rx_fifo_flush_base(struct e1000_hw *hw);
43s32 e1000_acquire_phy_base(struct e1000_hw *hw);
44void e1000_release_phy_base(struct e1000_hw *hw);
45
46/* Transmit Descriptor - Advanced */
47union e1000_adv_tx_desc {
48	struct {
49		__le64 buffer_addr;    /* Address of descriptor's data buf */
50		__le32 cmd_type_len;
51		__le32 olinfo_status;
52	} read;
53	struct {
54		__le64 rsvd;       /* Reserved */
55		__le32 nxtseq_seed;
56		__le32 status;
57	} wb;
58};
59
60/* Context descriptors */
61struct e1000_adv_tx_context_desc {
62	__le32 vlan_macip_lens;
63	union {
64		__le32 launch_time;
65		__le32 seqnum_seed;
66	} u;
67	__le32 type_tucmd_mlhl;
68	__le32 mss_l4len_idx;
69};
70
71/* Adv Transmit Descriptor Config Masks */
72#define E1000_ADVTXD_DTYP_CTXT	0x00200000 /* Advanced Context Descriptor */
73#define E1000_ADVTXD_DTYP_DATA	0x00300000 /* Advanced Data Descriptor */
74#define E1000_ADVTXD_DCMD_EOP	0x01000000 /* End of Packet */
75#define E1000_ADVTXD_DCMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
76#define E1000_ADVTXD_DCMD_RS	0x08000000 /* Report Status */
77#define E1000_ADVTXD_DCMD_DDTYP_ISCSI	0x10000000 /* DDP hdr type or iSCSI */
78#define E1000_ADVTXD_DCMD_DEXT	0x20000000 /* Descriptor extension (1=Adv) */
79#define E1000_ADVTXD_DCMD_VLE	0x40000000 /* VLAN pkt enable */
80#define E1000_ADVTXD_DCMD_TSE	0x80000000 /* TCP Seg enable */
81#define E1000_ADVTXD_MAC_LINKSEC	0x00040000 /* Apply LinkSec on pkt */
82#define E1000_ADVTXD_MAC_TSTAMP		0x00080000 /* IEEE1588 Timestamp pkt */
83#define E1000_ADVTXD_STAT_SN_CRC	0x00000002 /* NXTSEQ/SEED prsnt in WB */
84#define E1000_ADVTXD_IDX_SHIFT		4  /* Adv desc Index shift */
85#define E1000_ADVTXD_POPTS_ISCO_1ST	0x00000000 /* 1st TSO of iSCSI PDU */
86#define E1000_ADVTXD_POPTS_ISCO_MDL	0x00000800 /* Middle TSO of iSCSI PDU */
87#define E1000_ADVTXD_POPTS_ISCO_LAST	0x00001000 /* Last TSO of iSCSI PDU */
88/* 1st & Last TSO-full iSCSI PDU*/
89#define E1000_ADVTXD_POPTS_ISCO_FULL	0x00001800
90#define E1000_ADVTXD_POPTS_IPSEC	0x00000400 /* IPSec offload request */
91#define E1000_ADVTXD_PAYLEN_SHIFT	14 /* Adv desc PAYLEN shift */
92
93/* Advanced Transmit Context Descriptor Config */
94#define E1000_ADVTXD_MACLEN_SHIFT	9  /* Adv ctxt desc mac len shift */
95#define E1000_ADVTXD_VLAN_SHIFT		16  /* Adv ctxt vlan tag shift */
96#define E1000_ADVTXD_TUCMD_IPV4		0x00000400  /* IP Packet Type: 1=IPv4 */
97#define E1000_ADVTXD_TUCMD_IPV6		0x00000000  /* IP Packet Type: 0=IPv6 */
98#define E1000_ADVTXD_TUCMD_L4T_UDP	0x00000000  /* L4 Packet TYPE of UDP */
99#define E1000_ADVTXD_TUCMD_L4T_TCP	0x00000800  /* L4 Packet TYPE of TCP */
100#define E1000_ADVTXD_TUCMD_L4T_SCTP	0x00001000  /* L4 Packet TYPE of SCTP */
101#define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP	0x00002000 /* IPSec Type ESP */
102/* IPSec Encrypt Enable for ESP */
103#define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN	0x00004000
104/* Req requires Markers and CRC */
105#define E1000_ADVTXD_TUCMD_MKRREQ	0x00002000
106#define E1000_ADVTXD_L4LEN_SHIFT	8  /* Adv ctxt L4LEN shift */
107#define E1000_ADVTXD_MSS_SHIFT		16  /* Adv ctxt MSS shift */
108/* Adv ctxt IPSec SA IDX mask */
109#define E1000_ADVTXD_IPSEC_SA_INDEX_MASK	0x000000FF
110/* Adv ctxt IPSec ESP len mask */
111#define E1000_ADVTXD_IPSEC_ESP_LEN_MASK		0x000000FF
112
113#define E1000_RAR_ENTRIES_BASE		16
114
115/* Receive Descriptor - Advanced */
116union e1000_adv_rx_desc {
117	struct {
118		__le64 pkt_addr; /* Packet buffer address */
119		__le64 hdr_addr; /* Header buffer address */
120	} read;
121	struct {
122		struct {
123			union {
124				__le32 data;
125				struct {
126					__le16 pkt_info; /*RSS type, Pkt type*/
127					/* Split Header, header buffer len */
128					__le16 hdr_info;
129				} hs_rss;
130			} lo_dword;
131			union {
132				__le32 rss; /* RSS Hash */
133				struct {
134					__le16 ip_id; /* IP id */
135					__le16 csum; /* Packet Checksum */
136				} csum_ip;
137			} hi_dword;
138		} lower;
139		struct {
140			__le32 status_error; /* ext status/error */
141			__le16 length; /* Packet length */
142			__le16 vlan; /* VLAN tag */
143		} upper;
144	} wb;  /* writeback */
145};
146
147/* Additional Transmit Descriptor Control definitions */
148#define E1000_TXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Tx Queue */
149
150/* Additional Receive Descriptor Control definitions */
151#define E1000_RXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Rx Queue */
152
153/* SRRCTL bit definitions */
154#define E1000_SRRCTL_BSIZEPKT_SHIFT		10 /* Shift _right_ */
155#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT		2  /* Shift _left_ */
156#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF	0x02000000
157
158#endif /* _E1000_BASE_H_ */
159