1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Matthew Macy <mmacy@mattmacy.io> 5 * All rights reserved. 6 * Copyright (c) 2021 Rubicon Communications, LLC (Netgate) 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD$"); 32 33#include "if_igc.h" 34 35#ifdef RSS 36#include <net/rss_config.h> 37#include <netinet/in_rss.h> 38#endif 39 40#ifdef VERBOSE_DEBUG 41#define DPRINTF device_printf 42#else 43#define DPRINTF(...) 44#endif 45 46/********************************************************************* 47 * Local Function prototypes 48 *********************************************************************/ 49static int igc_isc_txd_encap(void *arg, if_pkt_info_t pi); 50static void igc_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx); 51static int igc_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear); 52 53static void igc_isc_rxd_refill(void *arg, if_rxd_update_t iru); 54 55static void igc_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused, 56 qidx_t pidx); 57static int igc_isc_rxd_available(void *arg, uint16_t rxqid, qidx_t idx, 58 qidx_t budget); 59 60static int igc_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri); 61 62static int igc_tx_ctx_setup(struct tx_ring *txr, if_pkt_info_t pi, 63 uint32_t *cmd_type_len, uint32_t *olinfo_status); 64static int igc_tso_setup(struct tx_ring *txr, if_pkt_info_t pi, 65 uint32_t *cmd_type_len, uint32_t *olinfo_status); 66 67static void igc_rx_checksum(uint32_t staterr, if_rxd_info_t ri, uint32_t ptype); 68static int igc_determine_rsstype(uint16_t pkt_info); 69 70extern void igc_if_enable_intr(if_ctx_t ctx); 71extern int igc_intr(void *arg); 72 73struct if_txrx igc_txrx = { 74 .ift_txd_encap = igc_isc_txd_encap, 75 .ift_txd_flush = igc_isc_txd_flush, 76 .ift_txd_credits_update = igc_isc_txd_credits_update, 77 .ift_rxd_available = igc_isc_rxd_available, 78 .ift_rxd_pkt_get = igc_isc_rxd_pkt_get, 79 .ift_rxd_refill = igc_isc_rxd_refill, 80 .ift_rxd_flush = igc_isc_rxd_flush, 81 .ift_legacy_intr = igc_intr 82}; 83 84void 85igc_dump_rs(struct igc_adapter *adapter) 86{ 87 if_softc_ctx_t scctx = adapter->shared; 88 struct igc_tx_queue *que; 89 struct tx_ring *txr; 90 qidx_t i, ntxd, qid, cur; 91 int16_t rs_cidx; 92 uint8_t status; 93 94 printf("\n"); 95 ntxd = scctx->isc_ntxd[0]; 96 for (qid = 0; qid < adapter->tx_num_queues; qid++) { 97 que = &adapter->tx_queues[qid]; 98 txr = &que->txr; 99 rs_cidx = txr->tx_rs_cidx; 100 if (rs_cidx != txr->tx_rs_pidx) { 101 cur = txr->tx_rsq[rs_cidx]; 102 status = txr->tx_base[cur].upper.fields.status; 103 if (!(status & IGC_TXD_STAT_DD)) 104 printf("qid[%d]->tx_rsq[%d]: %d clear ", qid, rs_cidx, cur); 105 } else { 106 rs_cidx = (rs_cidx-1)&(ntxd-1); 107 cur = txr->tx_rsq[rs_cidx]; 108 printf("qid[%d]->tx_rsq[rs_cidx-1=%d]: %d ", qid, rs_cidx, cur); 109 } 110 printf("cidx_prev=%d rs_pidx=%d ",txr->tx_cidx_processed, txr->tx_rs_pidx); 111 for (i = 0; i < ntxd; i++) { 112 if (txr->tx_base[i].upper.fields.status & IGC_TXD_STAT_DD) 113 printf("%d set ", i); 114 } 115 printf("\n"); 116 } 117} 118 119/********************************************************************** 120 * 121 * Setup work for hardware segmentation offload (TSO) on 122 * adapters using advanced tx descriptors 123 * 124 **********************************************************************/ 125static int 126igc_tso_setup(struct tx_ring *txr, if_pkt_info_t pi, uint32_t *cmd_type_len, 127 uint32_t *olinfo_status) 128{ 129 struct igc_adv_tx_context_desc *TXD; 130 uint32_t type_tucmd_mlhl = 0, vlan_macip_lens = 0; 131 uint32_t mss_l4len_idx = 0; 132 uint32_t paylen; 133 134 switch(pi->ipi_etype) { 135 case ETHERTYPE_IPV6: 136 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV6; 137 break; 138 case ETHERTYPE_IP: 139 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV4; 140 /* Tell transmit desc to also do IPv4 checksum. */ 141 *olinfo_status |= IGC_TXD_POPTS_IXSM << 8; 142 break; 143 default: 144 panic("%s: CSUM_TSO but no supported IP version (0x%04x)", 145 __func__, ntohs(pi->ipi_etype)); 146 break; 147 } 148 149 TXD = (struct igc_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx]; 150 151 /* This is used in the transmit desc in encap */ 152 paylen = pi->ipi_len - pi->ipi_ehdrlen - pi->ipi_ip_hlen - pi->ipi_tcp_hlen; 153 154 /* VLAN MACLEN IPLEN */ 155 if (pi->ipi_mflags & M_VLANTAG) { 156 vlan_macip_lens |= (pi->ipi_vtag << IGC_ADVTXD_VLAN_SHIFT); 157 } 158 159 vlan_macip_lens |= pi->ipi_ehdrlen << IGC_ADVTXD_MACLEN_SHIFT; 160 vlan_macip_lens |= pi->ipi_ip_hlen; 161 TXD->vlan_macip_lens = htole32(vlan_macip_lens); 162 163 /* ADV DTYPE TUCMD */ 164 type_tucmd_mlhl |= IGC_ADVTXD_DCMD_DEXT | IGC_ADVTXD_DTYP_CTXT; 165 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_TCP; 166 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl); 167 168 /* MSS L4LEN IDX */ 169 mss_l4len_idx |= (pi->ipi_tso_segsz << IGC_ADVTXD_MSS_SHIFT); 170 mss_l4len_idx |= (pi->ipi_tcp_hlen << IGC_ADVTXD_L4LEN_SHIFT); 171 TXD->mss_l4len_idx = htole32(mss_l4len_idx); 172 173 TXD->seqnum_seed = htole32(0); 174 *cmd_type_len |= IGC_ADVTXD_DCMD_TSE; 175 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8; 176 *olinfo_status |= paylen << IGC_ADVTXD_PAYLEN_SHIFT; 177 178 return (1); 179} 180 181/********************************************************************* 182 * 183 * Advanced Context Descriptor setup for VLAN, CSUM or TSO 184 * 185 **********************************************************************/ 186static int 187igc_tx_ctx_setup(struct tx_ring *txr, if_pkt_info_t pi, uint32_t *cmd_type_len, 188 uint32_t *olinfo_status) 189{ 190 struct igc_adv_tx_context_desc *TXD; 191 uint32_t vlan_macip_lens, type_tucmd_mlhl; 192 uint32_t mss_l4len_idx; 193 mss_l4len_idx = vlan_macip_lens = type_tucmd_mlhl = 0; 194 195 /* First check if TSO is to be used */ 196 if (pi->ipi_csum_flags & CSUM_TSO) 197 return (igc_tso_setup(txr, pi, cmd_type_len, olinfo_status)); 198 199 /* Indicate the whole packet as payload when not doing TSO */ 200 *olinfo_status |= pi->ipi_len << IGC_ADVTXD_PAYLEN_SHIFT; 201 202 /* Now ready a context descriptor */ 203 TXD = (struct igc_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx]; 204 205 /* 206 ** In advanced descriptors the vlan tag must 207 ** be placed into the context descriptor. Hence 208 ** we need to make one even if not doing offloads. 209 */ 210 if (pi->ipi_mflags & M_VLANTAG) { 211 vlan_macip_lens |= (pi->ipi_vtag << IGC_ADVTXD_VLAN_SHIFT); 212 } else if ((pi->ipi_csum_flags & IGC_CSUM_OFFLOAD) == 0) { 213 return (0); 214 } 215 216 /* Set the ether header length */ 217 vlan_macip_lens |= pi->ipi_ehdrlen << IGC_ADVTXD_MACLEN_SHIFT; 218 219 switch(pi->ipi_etype) { 220 case ETHERTYPE_IP: 221 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV4; 222 break; 223 case ETHERTYPE_IPV6: 224 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV6; 225 break; 226 default: 227 break; 228 } 229 230 vlan_macip_lens |= pi->ipi_ip_hlen; 231 type_tucmd_mlhl |= IGC_ADVTXD_DCMD_DEXT | IGC_ADVTXD_DTYP_CTXT; 232 233 switch (pi->ipi_ipproto) { 234 case IPPROTO_TCP: 235 if (pi->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP6_TCP)) { 236 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_TCP; 237 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8; 238 } 239 break; 240 case IPPROTO_UDP: 241 if (pi->ipi_csum_flags & (CSUM_IP_UDP | CSUM_IP6_UDP)) { 242 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_UDP; 243 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8; 244 } 245 break; 246#ifndef __HAIKU__ 247 case IPPROTO_SCTP: 248 if (pi->ipi_csum_flags & (CSUM_IP_SCTP | CSUM_IP6_SCTP)) { 249 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_SCTP; 250 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8; 251 } 252 break; 253#endif 254 default: 255 break; 256 } 257 258 /* Now copy bits into descriptor */ 259 TXD->vlan_macip_lens = htole32(vlan_macip_lens); 260 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl); 261 TXD->seqnum_seed = htole32(0); 262 TXD->mss_l4len_idx = htole32(mss_l4len_idx); 263 264 return (1); 265} 266 267static int 268igc_isc_txd_encap(void *arg, if_pkt_info_t pi) 269{ 270 struct igc_adapter *sc = arg; 271 if_softc_ctx_t scctx = sc->shared; 272 struct igc_tx_queue *que = &sc->tx_queues[pi->ipi_qsidx]; 273 struct tx_ring *txr = &que->txr; 274 int nsegs = pi->ipi_nsegs; 275 bus_dma_segment_t *segs = pi->ipi_segs; 276 union igc_adv_tx_desc *txd = NULL; 277 int i, j, pidx_last; 278 uint32_t olinfo_status, cmd_type_len, txd_flags; 279 qidx_t ntxd; 280 281 pidx_last = olinfo_status = 0; 282 /* Basic descriptor defines */ 283 cmd_type_len = (IGC_ADVTXD_DTYP_DATA | 284 IGC_ADVTXD_DCMD_IFCS | IGC_ADVTXD_DCMD_DEXT); 285 286 if (pi->ipi_mflags & M_VLANTAG) 287 cmd_type_len |= IGC_ADVTXD_DCMD_VLE; 288 289 i = pi->ipi_pidx; 290 ntxd = scctx->isc_ntxd[0]; 291 txd_flags = pi->ipi_flags & IPI_TX_INTR ? IGC_ADVTXD_DCMD_RS : 0; 292 /* Consume the first descriptor */ 293 i += igc_tx_ctx_setup(txr, pi, &cmd_type_len, &olinfo_status); 294 if (i == scctx->isc_ntxd[0]) 295 i = 0; 296 297 for (j = 0; j < nsegs; j++) { 298 bus_size_t seglen; 299 bus_addr_t segaddr; 300 301 txd = (union igc_adv_tx_desc *)&txr->tx_base[i]; 302 seglen = segs[j].ds_len; 303 segaddr = htole64(segs[j].ds_addr); 304 305 txd->read.buffer_addr = segaddr; 306 txd->read.cmd_type_len = htole32(IGC_ADVTXD_DCMD_IFCS | 307 cmd_type_len | seglen); 308 txd->read.olinfo_status = htole32(olinfo_status); 309 pidx_last = i; 310 if (++i == scctx->isc_ntxd[0]) { 311 i = 0; 312 } 313 } 314 if (txd_flags) { 315 txr->tx_rsq[txr->tx_rs_pidx] = pidx_last; 316 txr->tx_rs_pidx = (txr->tx_rs_pidx+1) & (ntxd-1); 317 MPASS(txr->tx_rs_pidx != txr->tx_rs_cidx); 318 } 319 320 txd->read.cmd_type_len |= htole32(IGC_ADVTXD_DCMD_EOP | txd_flags); 321 pi->ipi_new_pidx = i; 322 323 return (0); 324} 325 326static void 327igc_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx) 328{ 329 struct igc_adapter *adapter = arg; 330 struct igc_tx_queue *que = &adapter->tx_queues[txqid]; 331 struct tx_ring *txr = &que->txr; 332 333 IGC_WRITE_REG(&adapter->hw, IGC_TDT(txr->me), pidx); 334} 335 336static int 337igc_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear) 338{ 339 struct igc_adapter *adapter = arg; 340 if_softc_ctx_t scctx = adapter->shared; 341 struct igc_tx_queue *que = &adapter->tx_queues[txqid]; 342 struct tx_ring *txr = &que->txr; 343 344 qidx_t processed = 0; 345 int updated; 346 qidx_t cur, prev, ntxd, rs_cidx; 347 int32_t delta; 348 uint8_t status; 349 350 rs_cidx = txr->tx_rs_cidx; 351 if (rs_cidx == txr->tx_rs_pidx) 352 return (0); 353 cur = txr->tx_rsq[rs_cidx]; 354 status = ((union igc_adv_tx_desc *)&txr->tx_base[cur])->wb.status; 355 updated = !!(status & IGC_TXD_STAT_DD); 356 357 if (!updated) 358 return (0); 359 360 /* If clear is false just let caller know that there 361 * are descriptors to reclaim */ 362 if (!clear) 363 return (1); 364 365 prev = txr->tx_cidx_processed; 366 ntxd = scctx->isc_ntxd[0]; 367 do { 368 MPASS(prev != cur); 369 delta = (int32_t)cur - (int32_t)prev; 370 if (delta < 0) 371 delta += ntxd; 372 MPASS(delta > 0); 373 374 processed += delta; 375 prev = cur; 376 rs_cidx = (rs_cidx + 1) & (ntxd-1); 377 if (rs_cidx == txr->tx_rs_pidx) 378 break; 379 cur = txr->tx_rsq[rs_cidx]; 380 status = ((union igc_adv_tx_desc *)&txr->tx_base[cur])->wb.status; 381 } while ((status & IGC_TXD_STAT_DD)); 382 383 txr->tx_rs_cidx = rs_cidx; 384 txr->tx_cidx_processed = prev; 385 return (processed); 386} 387 388static void 389igc_isc_rxd_refill(void *arg, if_rxd_update_t iru) 390{ 391 struct igc_adapter *sc = arg; 392 if_softc_ctx_t scctx = sc->shared; 393 uint16_t rxqid = iru->iru_qsidx; 394 struct igc_rx_queue *que = &sc->rx_queues[rxqid]; 395 union igc_adv_rx_desc *rxd; 396 struct rx_ring *rxr = &que->rxr; 397 uint64_t *paddrs; 398 uint32_t next_pidx, pidx; 399 uint16_t count; 400 int i; 401 402 paddrs = iru->iru_paddrs; 403 pidx = iru->iru_pidx; 404 count = iru->iru_count; 405 406 for (i = 0, next_pidx = pidx; i < count; i++) { 407 rxd = (union igc_adv_rx_desc *)&rxr->rx_base[next_pidx]; 408 409 rxd->read.pkt_addr = htole64(paddrs[i]); 410 if (++next_pidx == scctx->isc_nrxd[0]) 411 next_pidx = 0; 412 } 413} 414 415static void 416igc_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused, qidx_t pidx) 417{ 418 struct igc_adapter *sc = arg; 419 struct igc_rx_queue *que = &sc->rx_queues[rxqid]; 420 struct rx_ring *rxr = &que->rxr; 421 422 IGC_WRITE_REG(&sc->hw, IGC_RDT(rxr->me), pidx); 423} 424 425static int 426igc_isc_rxd_available(void *arg, uint16_t rxqid, qidx_t idx, qidx_t budget) 427{ 428 struct igc_adapter *sc = arg; 429 if_softc_ctx_t scctx = sc->shared; 430 struct igc_rx_queue *que = &sc->rx_queues[rxqid]; 431 struct rx_ring *rxr = &que->rxr; 432 union igc_adv_rx_desc *rxd; 433 uint32_t staterr = 0; 434 int cnt, i; 435 436 for (cnt = 0, i = idx; cnt < scctx->isc_nrxd[0] && cnt <= budget;) { 437 rxd = (union igc_adv_rx_desc *)&rxr->rx_base[i]; 438 staterr = le32toh(rxd->wb.upper.status_error); 439 440 if ((staterr & IGC_RXD_STAT_DD) == 0) 441 break; 442 if (++i == scctx->isc_nrxd[0]) 443 i = 0; 444 if (staterr & IGC_RXD_STAT_EOP) 445 cnt++; 446 } 447 return (cnt); 448} 449 450/**************************************************************** 451 * Routine sends data which has been dma'ed into host memory 452 * to upper layer. Initialize ri structure. 453 * 454 * Returns 0 upon success, errno on failure 455 ***************************************************************/ 456 457static int 458igc_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri) 459{ 460 struct igc_adapter *adapter = arg; 461 if_softc_ctx_t scctx = adapter->shared; 462 struct igc_rx_queue *que = &adapter->rx_queues[ri->iri_qsidx]; 463 struct rx_ring *rxr = &que->rxr; 464 union igc_adv_rx_desc *rxd; 465 466 uint16_t pkt_info, len; 467 uint32_t ptype, staterr; 468 int i, cidx; 469 bool eop; 470 471 staterr = i = 0; 472 cidx = ri->iri_cidx; 473 474 do { 475 rxd = (union igc_adv_rx_desc *)&rxr->rx_base[cidx]; 476 staterr = le32toh(rxd->wb.upper.status_error); 477 pkt_info = le16toh(rxd->wb.lower.lo_dword.hs_rss.pkt_info); 478 479 MPASS ((staterr & IGC_RXD_STAT_DD) != 0); 480 481 len = le16toh(rxd->wb.upper.length); 482 ptype = le32toh(rxd->wb.lower.lo_dword.data) & IGC_PKTTYPE_MASK; 483 484 ri->iri_len += len; 485 rxr->rx_bytes += ri->iri_len; 486 487 rxd->wb.upper.status_error = 0; 488 eop = ((staterr & IGC_RXD_STAT_EOP) == IGC_RXD_STAT_EOP); 489 490 /* Make sure bad packets are discarded */ 491 if (eop && ((staterr & IGC_RXDEXT_STATERR_RXE) != 0)) { 492 adapter->dropped_pkts++; 493 ++rxr->rx_discarded; 494 return (EBADMSG); 495 } 496 ri->iri_frags[i].irf_flid = 0; 497 ri->iri_frags[i].irf_idx = cidx; 498 ri->iri_frags[i].irf_len = len; 499 500 if (++cidx == scctx->isc_nrxd[0]) 501 cidx = 0; 502#ifdef notyet 503 if (rxr->hdr_split == true) { 504 ri->iri_frags[i].irf_flid = 1; 505 ri->iri_frags[i].irf_idx = cidx; 506 if (++cidx == scctx->isc_nrxd[0]) 507 cidx = 0; 508 } 509#endif 510 i++; 511 } while (!eop); 512 513 rxr->rx_packets++; 514 515 if ((scctx->isc_capenable & IFCAP_RXCSUM) != 0) 516 igc_rx_checksum(staterr, ri, ptype); 517 518 if (staterr & IGC_RXD_STAT_VP) { 519 ri->iri_vtag = le16toh(rxd->wb.upper.vlan); 520 ri->iri_flags |= M_VLANTAG; 521 } 522 523 ri->iri_flowid = 524 le32toh(rxd->wb.lower.hi_dword.rss); 525 ri->iri_rsstype = igc_determine_rsstype(pkt_info); 526 ri->iri_nfrags = i; 527 528 return (0); 529} 530 531/********************************************************************* 532 * 533 * Verify that the hardware indicated that the checksum is valid. 534 * Inform the stack about the status of checksum so that stack 535 * doesn't spend time verifying the checksum. 536 * 537 *********************************************************************/ 538static void 539igc_rx_checksum(uint32_t staterr, if_rxd_info_t ri, uint32_t ptype) 540{ 541 uint16_t status = (uint16_t)staterr; 542 uint8_t errors = (uint8_t)(staterr >> 24); 543 544 if (__predict_false(status & IGC_RXD_STAT_IXSM)) 545 return; 546 547 /* If there is a layer 3 or 4 error we are done */ 548 if (__predict_false(errors & (IGC_RXD_ERR_IPE | IGC_RXD_ERR_TCPE))) 549 return; 550 551 /* IP Checksum Good */ 552 if (status & IGC_RXD_STAT_IPCS) 553 ri->iri_csum_flags = (CSUM_IP_CHECKED | CSUM_IP_VALID); 554 555 /* Valid L4E checksum */ 556 if (__predict_true(status & 557 (IGC_RXD_STAT_TCPCS | IGC_RXD_STAT_UDPCS))) { 558 /* SCTP header present */ 559 if (__predict_false((ptype & IGC_RXDADV_PKTTYPE_ETQF) == 0 && 560 (ptype & IGC_RXDADV_PKTTYPE_SCTP) != 0)) { 561 ri->iri_csum_flags |= CSUM_SCTP_VALID; 562 } else { 563 ri->iri_csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 564 ri->iri_csum_data = htons(0xffff); 565 } 566 } 567} 568 569/******************************************************************** 570 * 571 * Parse the packet type to determine the appropriate hash 572 * 573 ******************************************************************/ 574static int 575igc_determine_rsstype(uint16_t pkt_info) 576{ 577 switch (pkt_info & IGC_RXDADV_RSSTYPE_MASK) { 578 case IGC_RXDADV_RSSTYPE_IPV4_TCP: 579 return M_HASHTYPE_RSS_TCP_IPV4; 580 case IGC_RXDADV_RSSTYPE_IPV4: 581 return M_HASHTYPE_RSS_IPV4; 582 case IGC_RXDADV_RSSTYPE_IPV6_TCP: 583 return M_HASHTYPE_RSS_TCP_IPV6; 584 case IGC_RXDADV_RSSTYPE_IPV6_EX: 585 return M_HASHTYPE_RSS_IPV6_EX; 586 case IGC_RXDADV_RSSTYPE_IPV6: 587 return M_HASHTYPE_RSS_IPV6; 588 case IGC_RXDADV_RSSTYPE_IPV6_TCP_EX: 589 return M_HASHTYPE_RSS_TCP_IPV6_EX; 590 default: 591 return M_HASHTYPE_OPAQUE; 592 } 593} 594