1/*- 2 * BSD LICENSE 3 * 4 * Copyright (c) Intel Corporation. All rights reserved. 5 * Copyright (c) 2017, Western Digital Corporation or its affiliates. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#ifndef __LIBNVME_SPEC_H__ 35#define __LIBNVME_SPEC_H__ 36 37#include <stdint.h> 38#include <stddef.h> 39 40/* 41 * Use to mark a command to apply to all namespaces, 42 * or to retrieve global log pages. 43 */ 44#define NVME_GLOBAL_NS_TAG ((uint32_t)0xFFFFFFFF) 45 46#define NVME_MAX_IO_QUEUES (65535) 47 48#define NVME_ADMIN_QUEUE_MIN_ENTRIES 2 49#define NVME_ADMIN_QUEUE_MAX_ENTRIES 4096 50 51#define NVME_IO_QUEUE_MIN_ENTRIES 2 52#define NVME_IO_QUEUE_MAX_ENTRIES 65536 53 54#define NVME_MAX_NS 1024 55 56/* 57 * Number of characters in the serial number. 58 */ 59#define NVME_SERIAL_NUMBER_CHARACTERS 20 60 61/* 62 * Number of characters in the model number. 63 */ 64#define NVME_MODEL_NUMBER_CHARACTERS 40 65 66/* 67 * Indicates the maximum number of range sets that may be specified 68 * in the dataset mangement command. 69 */ 70#define NVME_DATASET_MANAGEMENT_MAX_RANGES 256 71 72/* 73 * Compile time assert check. 74 */ 75#if __GNUC__ > 3 76#ifdef __cplusplus 77#define nvme_static_assert(cond, msg) static_assert(cond, msg) 78#else 79#define nvme_static_assert(cond, msg) _Static_assert(cond, msg) 80#endif 81#else 82#define nvme_static_assert(cond, msg) 83#endif 84 85union nvme_cap_register { 86 87 uint64_t raw; 88 89 struct { 90 /* Maximum queue entries supported */ 91 uint32_t mqes : 16; 92 93 /* Contiguous queues required */ 94 uint32_t cqr : 1; 95 96 /* Arbitration mechanism supported */ 97 uint32_t ams : 2; 98 99 uint32_t reserved1 : 5; 100 101 /* 102 * Worst case time in 500 millisecond units 103 * to wait for the controller to become ready 104 * (CSTS.RDY set to '1') after a power-on or reset 105 */ 106 uint32_t to : 8; 107 108 /* Doorbell stride */ 109 uint32_t dstrd : 4; 110 111 /* NVM subsystem reset supported */ 112 uint32_t nssrs : 1; 113 114 /* Command sets supported */ 115 uint32_t css_nvm : 1; 116 117 uint32_t css_reserved : 3; 118 uint32_t reserved2 : 7; 119 120 /* Memory page size minimum */ 121 uint32_t mpsmin : 4; 122 123 /* Memory page size maximum */ 124 uint32_t mpsmax : 4; 125 126 uint32_t reserved3 : 8; 127 } bits; 128 129}; 130nvme_static_assert(sizeof(union nvme_cap_register) == 8, "Incorrect size"); 131 132union nvme_cc_register { 133 134 uint32_t raw; 135 136 struct { 137 /* Enable */ 138 uint32_t en : 1; 139 140 uint32_t reserved1 : 3; 141 142 /* I/O command set selected */ 143 uint32_t css : 3; 144 145 /* Memory page size */ 146 uint32_t mps : 4; 147 148 /* Arbitration mechanism selected */ 149 uint32_t ams : 3; 150 151 /* Shutdown notification */ 152 uint32_t shn : 2; 153 154 /* I/O submission queue entry size */ 155 uint32_t iosqes : 4; 156 157 /* I/O completion queue entry size */ 158 uint32_t iocqes : 4; 159 160 uint32_t reserved2 : 8; 161 } bits; 162 163}; 164nvme_static_assert(sizeof(union nvme_cc_register) == 4, "Incorrect size"); 165 166enum nvme_shn_value { 167 NVME_SHN_NORMAL = 0x1, 168 NVME_SHN_ABRUPT = 0x2, 169}; 170 171union nvme_csts_register { 172 173 uint32_t raw; 174 175 struct { 176 /* Ready */ 177 uint32_t rdy : 1; 178 179 /* Controller fatal status */ 180 uint32_t cfs : 1; 181 182 /* Shutdown status */ 183 uint32_t shst : 2; 184 185 uint32_t reserved1 : 28; 186 } bits; 187}; 188nvme_static_assert(sizeof(union nvme_csts_register) == 4, "Incorrect size"); 189 190enum nvme_shst_value { 191 NVME_SHST_NORMAL = 0x0, 192 NVME_SHST_OCCURRING = 0x1, 193 NVME_SHST_COMPLETE = 0x2, 194}; 195 196union nvme_aqa_register { 197 198 uint32_t raw; 199 200 struct { 201 /* Admin submission queue size */ 202 uint32_t asqs : 12; 203 204 uint32_t reserved1 : 4; 205 206 /* Admin completion queue size */ 207 uint32_t acqs : 12; 208 209 uint32_t reserved2 : 4; 210 } bits; 211 212}; 213nvme_static_assert(sizeof(union nvme_aqa_register) == 4, "Incorrect size"); 214 215union nvme_vs_register { 216 217 uint32_t raw; 218 219 struct { 220 /* Indicates the tertiary version */ 221 uint32_t ter : 8; 222 223 /* Indicates the minor version */ 224 uint32_t mnr : 8; 225 226 /* Indicates the major version */ 227 uint32_t mjr : 16; 228 } bits; 229 230}; 231nvme_static_assert(sizeof(union nvme_vs_register) == 4, "Incorrect size"); 232 233/* 234 * Generate raw version. 235 */ 236#define NVME_VERSION(mjr, mnr, ter) \ 237 (((uint32_t)(mjr) << 16) | \ 238 ((uint32_t)(mnr) << 8) | \ 239 (uint32_t)(ter)) 240 241/* 242 * Test that the shifts are correct 243 */ 244nvme_static_assert(NVME_VERSION(1, 0, 0) == 0x00010000, "version macro error"); 245nvme_static_assert(NVME_VERSION(1, 2, 1) == 0x00010201, "version macro error"); 246 247union nvme_cmbloc_register { 248 249 uint32_t raw; 250 251 struct { 252 /* 253 * Indicator of BAR which contains controller 254 * memory buffer(CMB). 255 */ 256 uint32_t bir : 3; 257 258 uint32_t reserved1 : 9; 259 260 /* Offset of CMB in multiples of the size unit */ 261 uint32_t ofst : 20; 262 } bits; 263}; 264nvme_static_assert(sizeof(union nvme_cmbloc_register) == 4, "Incorrect size"); 265 266union nvme_cmbsz_register { 267 268 uint32_t raw; 269 270 struct { 271 /* Support submission queues in CMB */ 272 uint32_t sqs : 1; 273 274 /* Support completion queues in CMB */ 275 uint32_t cqs : 1; 276 277 /* Support PRP and SGLs lists in CMB */ 278 uint32_t lists : 1; 279 280 /* Support read data and metadata in CMB */ 281 uint32_t rds : 1; 282 283 /* Support write data and metadata in CMB */ 284 uint32_t wds : 1; 285 286 uint32_t reserved1 : 3; 287 288 /* Indicates the granularity of the size unit */ 289 uint32_t szu : 4; 290 291 /* Size of CMB in multiples of the size unit */ 292 uint32_t sz : 20; 293 } bits; 294}; 295nvme_static_assert(sizeof(union nvme_cmbsz_register) == 4, "Incorrect size"); 296 297struct nvme_registers { 298 299 /* Controller capabilities */ 300 union nvme_cap_register cap; 301 302 /* Version of NVMe specification */ 303 union nvme_vs_register vs; 304 305 /* Interrupt mask set */ 306 uint32_t intms; 307 308 /* Interrupt mask clear */ 309 uint32_t intmc; 310 311 /* Controller configuration */ 312 union nvme_cc_register cc; 313 314 uint32_t reserved1; 315 316 /* Controller status */ 317 union nvme_csts_register csts; 318 319 /* NVM subsystem reset */ 320 uint32_t nssr; 321 322 /* Admin queue attributes */ 323 union nvme_aqa_register aqa; 324 325 /* Admin submission queue base addr */ 326 uint64_t asq; 327 328 /* Admin completion queue base addr */ 329 uint64_t acq; 330 331 /* Controller memory buffer location */ 332 union nvme_cmbloc_register cmbloc; 333 334 /* Controller memory buffer size */ 335 union nvme_cmbsz_register cmbsz; 336 337 uint32_t reserved3[0x3f0]; 338 339 struct { 340 /* Submission queue tail doorbell */ 341 uint32_t sq_tdbl; 342 343 /* Completion queue head doorbell */ 344 uint32_t cq_hdbl; 345 } doorbell[1]; 346}; 347 348/* 349 * Return the offset of a field in a structure. 350 */ 351#ifndef offsetof 352#define offsetof(TYPE, MEMBER) __builtin_offsetof (TYPE, MEMBER) 353#endif 354 355/* 356 * NVMe controller register space offsets. 357 */ 358nvme_static_assert(0x00 == offsetof(struct nvme_registers, cap), 359 "Incorrect register offset"); 360nvme_static_assert(0x08 == offsetof(struct nvme_registers, vs), 361 "Incorrect register offset"); 362nvme_static_assert(0x0C == offsetof(struct nvme_registers, intms), 363 "Incorrect register offset"); 364nvme_static_assert(0x10 == offsetof(struct nvme_registers, intmc), 365 "Incorrect register offset"); 366nvme_static_assert(0x14 == offsetof(struct nvme_registers, cc), 367 "Incorrect register offset"); 368nvme_static_assert(0x1C == offsetof(struct nvme_registers, csts), 369 "Incorrect register offset"); 370nvme_static_assert(0x20 == offsetof(struct nvme_registers, nssr), 371 "Incorrect register offset"); 372nvme_static_assert(0x24 == offsetof(struct nvme_registers, aqa), 373 "Incorrect register offset"); 374nvme_static_assert(0x28 == offsetof(struct nvme_registers, asq), 375 "Incorrect register offset"); 376nvme_static_assert(0x30 == offsetof(struct nvme_registers, acq), 377 "Incorrect register offset"); 378nvme_static_assert(0x38 == offsetof(struct nvme_registers, cmbloc), 379 "Incorrect register offset"); 380nvme_static_assert(0x3C == offsetof(struct nvme_registers, cmbsz), 381 "Incorrect register offset"); 382 383enum nvme_sgl_descriptor_type { 384 385 NVME_SGL_TYPE_DATA_BLOCK = 0x0, 386 NVME_SGL_TYPE_BIT_BUCKET = 0x1, 387 NVME_SGL_TYPE_SEGMENT = 0x2, 388 NVME_SGL_TYPE_LAST_SEGMENT = 0x3, 389 NVME_SGL_TYPE_KEYED_DATA_BLOCK = 0x4, 390 391 /* 0x5 - 0xE reserved */ 392 393 NVME_SGL_TYPE_VENDOR_SPECIFIC = 0xF 394 395}; 396 397enum nvme_sgl_descriptor_subtype { 398 NVME_SGL_SUBTYPE_ADDRESS = 0x0, 399 NVME_SGL_SUBTYPE_OFFSET = 0x1, 400}; 401 402/* 403 * Scatter Gather List descriptor 404 */ 405struct __attribute__((packed)) nvme_sgl_descriptor { 406 407 uint64_t address; 408 409 union { 410 struct { 411 uint8_t reserved[7]; 412 uint8_t subtype : 4; 413 uint8_t type : 4; 414 } generic; 415 416 struct { 417 uint32_t length; 418 uint8_t reserved[3]; 419 uint8_t subtype : 4; 420 uint8_t type : 4; 421 } unkeyed; 422 423 struct { 424 uint64_t length : 24; 425 uint64_t key : 32; 426 uint64_t subtype : 4; 427 uint64_t type : 4; 428 } keyed; 429 }; 430 431}; 432nvme_static_assert(sizeof(struct nvme_sgl_descriptor) == 16, 433 "Incorrect size"); 434 435enum nvme_psdt_value { 436 NVME_PSDT_PRP = 0x0, 437 NVME_PSDT_SGL_MPTR_CONTIG = 0x1, 438 NVME_PSDT_SGL_MPTR_SGL = 0x2, 439 NVME_PSDT_RESERVED = 0x3 440}; 441 442/* 443 * Submission queue priority values for Create I/O Submission Queue Command. 444 * Only valid for weighted round robin arbitration method. 445 */ 446enum nvme_qprio { 447 NVME_QPRIO_URGENT = 0x0, 448 NVME_QPRIO_HIGH = 0x1, 449 NVME_QPRIO_MEDIUM = 0x2, 450 NVME_QPRIO_LOW = 0x3 451}; 452 453/* 454 * Optional Arbitration Mechanism Supported by the controller. 455 * Two bits for CAP.AMS (18:17) field are set to '1' when the controller 456 * supports. There is no bit for AMS_RR where all controllers support and 457 * set to 0x0 by default. 458 */ 459enum nvme_cap_ams { 460 461 /* 462 * Weighted round robin 463 */ 464 NVME_CAP_AMS_WRR = 0x1, 465 466 /* 467 * Vendor specific. 468 */ 469 NVME_CAP_AMS_VS = 0x2, 470 471}; 472 473/* 474 * Arbitration Mechanism Selected to the controller. 475 * Value 0x2 to 0x6 is reserved. 476 */ 477enum nvme_cc_ams { 478 479 /* 480 * Default round robin. 481 */ 482 NVME_CC_AMS_RR = 0x0, 483 484 /* 485 * Weighted round robin. 486 */ 487 NVME_CC_AMS_WRR = 0x1, 488 489 /* 490 * Vendor specific. 491 */ 492 NVME_CC_AMS_VS = 0x7, 493 494}; 495 496struct nvme_cmd { 497 498 /* dword 0 */ 499 uint16_t opc : 8; /* opcode */ 500 uint16_t fuse : 2; /* fused operation */ 501 uint16_t rsvd1 : 4; 502 uint16_t psdt : 2; 503 uint16_t cid; /* command identifier */ 504 505 /* dword 1 */ 506 uint32_t nsid; /* namespace identifier */ 507 508 /* dword 2-3 */ 509 uint32_t rsvd2; 510 uint32_t rsvd3; 511 512 /* dword 4-5 */ 513 uint64_t mptr; /* metadata pointer */ 514 515 /* dword 6-9: data pointer */ 516 union { 517 struct { 518 uint64_t prp1; /* prp entry 1 */ 519 uint64_t prp2; /* prp entry 2 */ 520 } prp; 521 522 struct nvme_sgl_descriptor sgl1; 523 } dptr; 524 525 /* dword 10-15 */ 526 uint32_t cdw10; /* command-specific */ 527 uint32_t cdw11; /* command-specific */ 528 uint32_t cdw12; /* command-specific */ 529 uint32_t cdw13; /* command-specific */ 530 uint32_t cdw14; /* command-specific */ 531 uint32_t cdw15; /* command-specific */ 532 533}; 534nvme_static_assert(sizeof(struct nvme_cmd) == 64, "Incorrect size"); 535 536struct nvme_status { 537 uint16_t p : 1; /* phase tag */ 538 uint16_t sc : 8; /* status code */ 539 uint16_t sct : 3; /* status code type */ 540 uint16_t rsvd2 : 2; 541 uint16_t m : 1; /* more */ 542 uint16_t dnr : 1; /* do not retry */ 543}; 544nvme_static_assert(sizeof(struct nvme_status) == 2, "Incorrect size"); 545 546/* 547 * Completion queue entry 548 */ 549struct nvme_cpl { 550 551 /* dword 0 */ 552 uint32_t cdw0; /* command-specific */ 553 554 /* dword 1 */ 555 uint32_t rsvd1; 556 557 /* dword 2 */ 558 uint16_t sqhd; /* submission queue head pointer */ 559 uint16_t sqid; /* submission queue identifier */ 560 561 /* dword 3 */ 562 uint16_t cid; /* command identifier */ 563 564 struct nvme_status status; 565 566}; 567nvme_static_assert(sizeof(struct nvme_cpl) == 16, "Incorrect size"); 568 569/* 570 * Dataset Management range 571 */ 572struct nvme_dsm_range { 573 uint32_t attributes; 574 uint32_t length; 575 uint64_t starting_lba; 576}; 577nvme_static_assert(sizeof(struct nvme_dsm_range) == 16, "Incorrect size"); 578 579/* 580 * Status code types 581 */ 582enum nvme_status_code_type { 583 584 NVME_SCT_GENERIC = 0x0, 585 NVME_SCT_COMMAND_SPECIFIC = 0x1, 586 NVME_SCT_MEDIA_ERROR = 0x2, 587 588 /* 0x3-0x6 - reserved */ 589 NVME_SCT_VENDOR_SPECIFIC = 0x7, 590 591}; 592 593/* 594 * Generic command status codes 595 */ 596enum nvme_generic_command_status_code { 597 598 NVME_SC_SUCCESS = 0x00, 599 NVME_SC_INVALID_OPCODE = 0x01, 600 NVME_SC_INVALID_FIELD = 0x02, 601 NVME_SC_COMMAND_ID_CONFLICT = 0x03, 602 NVME_SC_DATA_TRANSFER_ERROR = 0x04, 603 NVME_SC_ABORTED_POWER_LOSS = 0x05, 604 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06, 605 NVME_SC_ABORTED_BY_REQUEST = 0x07, 606 NVME_SC_ABORTED_SQ_DELETION = 0x08, 607 NVME_SC_ABORTED_FAILED_FUSED = 0x09, 608 NVME_SC_ABORTED_MISSING_FUSED = 0x0a, 609 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b, 610 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c, 611 NVME_SC_INVALID_SGL_SEG_DESCRIPTOR = 0x0d, 612 NVME_SC_INVALID_NUM_SGL_DESCIRPTORS = 0x0e, 613 NVME_SC_DATA_SGL_LENGTH_INVALID = 0x0f, 614 NVME_SC_METADATA_SGL_LENGTH_INVALID = 0x10, 615 NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID = 0x11, 616 NVME_SC_INVALID_CONTROLLER_MEM_BUF = 0x12, 617 NVME_SC_INVALID_PRP_OFFSET = 0x13, 618 NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED = 0x14, 619 NVME_SC_INVALID_SGL_OFFSET = 0x16, 620 NVME_SC_INVALID_SGL_SUBTYPE = 0x17, 621 NVME_SC_HOSTID_INCONSISTENT_FORMAT = 0x18, 622 NVME_SC_KEEP_ALIVE_EXPIRED = 0x19, 623 NVME_SC_KEEP_ALIVE_INVALID = 0x1a, 624 625 NVME_SC_LBA_OUT_OF_RANGE = 0x80, 626 NVME_SC_CAPACITY_EXCEEDED = 0x81, 627 NVME_SC_NAMESPACE_NOT_READY = 0x82, 628 NVME_SC_RESERVATION_CONFLICT = 0x83, 629 NVME_SC_FORMAT_IN_PROGRESS = 0x84, 630 631}; 632 633/* 634 * Command specific status codes 635 */ 636enum nvme_command_specific_status_code { 637 638 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00, 639 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01, 640 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02, 641 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03, 642 643 /* 0x04 - reserved */ 644 645 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05, 646 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06, 647 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07, 648 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08, 649 NVME_SC_INVALID_LOG_PAGE = 0x09, 650 NVME_SC_INVALID_FORMAT = 0x0a, 651 NVME_SC_FIRMWARE_REQ_CONVENTIONAL_RESET = 0x0b, 652 NVME_SC_INVALID_QUEUE_DELETION = 0x0c, 653 NVME_SC_FEATURE_ID_NOT_SAVEABLE = 0x0d, 654 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x0e, 655 NVME_SC_FEATURE_NOT_NAMESPACE_SPECIFIC = 0x0f, 656 NVME_SC_FIRMWARE_REQ_NVM_RESET = 0x10, 657 NVME_SC_FIRMWARE_REQ_RESET = 0x11, 658 NVME_SC_FIRMWARE_REQ_MAX_TIME_VIOLATION = 0x12, 659 NVME_SC_FIRMWARE_ACTIVATION_PROHIBITED = 0x13, 660 NVME_SC_OVERLAPPING_RANGE = 0x14, 661 NVME_SC_NAMESPACE_INSUFFICIENT_CAPACITY = 0x15, 662 NVME_SC_NAMESPACE_ID_UNAVAILABLE = 0x16, 663 664 /* 0x17 - reserved */ 665 666 NVME_SC_NAMESPACE_ALREADY_ATTACHED = 0x18, 667 NVME_SC_NAMESPACE_IS_PRIVATE = 0x19, 668 NVME_SC_NAMESPACE_NOT_ATTACHED = 0x1a, 669 NVME_SC_THINPROVISIONING_NOT_SUPPORTED = 0x1b, 670 NVME_SC_CONTROLLER_LIST_INVALID = 0x1c, 671 672 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80, 673 NVME_SC_INVALID_PROTECTION_INFO = 0x81, 674 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82, 675 676}; 677 678/* 679 * Media error status codes 680 */ 681enum nvme_media_error_status_code { 682 NVME_SC_WRITE_FAULTS = 0x80, 683 NVME_SC_UNRECOVERED_READ_ERROR = 0x81, 684 NVME_SC_GUARD_CHECK_ERROR = 0x82, 685 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83, 686 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84, 687 NVME_SC_COMPARE_FAILURE = 0x85, 688 NVME_SC_ACCESS_DENIED = 0x86, 689 NVME_SC_DEALLOCATED_OR_UNWRITTEN_BLOCK = 0x87, 690}; 691 692/* 693 * Admin opcodes 694 */ 695enum nvme_admin_opcode { 696 697 NVME_OPC_DELETE_IO_SQ = 0x00, 698 NVME_OPC_CREATE_IO_SQ = 0x01, 699 NVME_OPC_GET_LOG_PAGE = 0x02, 700 701 /* 0x03 - reserved */ 702 703 NVME_OPC_DELETE_IO_CQ = 0x04, 704 NVME_OPC_CREATE_IO_CQ = 0x05, 705 NVME_OPC_IDENTIFY = 0x06, 706 707 /* 0x07 - reserved */ 708 709 NVME_OPC_ABORT = 0x08, 710 NVME_OPC_SET_FEATURES = 0x09, 711 NVME_OPC_GET_FEATURES = 0x0a, 712 713 /* 0x0b - reserved */ 714 715 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c, 716 NVME_OPC_NS_MANAGEMENT = 0x0d, 717 718 /* 0x0e-0x0f - reserved */ 719 720 NVME_OPC_FIRMWARE_COMMIT = 0x10, 721 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11, 722 723 NVME_OPC_NS_ATTACHMENT = 0x15, 724 725 NVME_OPC_KEEP_ALIVE = 0x18, 726 727 NVME_OPC_FORMAT_NVM = 0x80, 728 NVME_OPC_SECURITY_SEND = 0x81, 729 NVME_OPC_SECURITY_RECEIVE = 0x82, 730 731}; 732 733/* 734 * NVM command set opcodes 735 */ 736enum nvme_nvm_opcode { 737 738 NVME_OPC_FLUSH = 0x00, 739 NVME_OPC_WRITE = 0x01, 740 NVME_OPC_READ = 0x02, 741 742 /* 0x03 - reserved */ 743 744 NVME_OPC_WRITE_UNCORRECTABLE = 0x04, 745 NVME_OPC_COMPARE = 0x05, 746 747 /* 0x06-0x07 - reserved */ 748 749 NVME_OPC_WRITE_ZEROES = 0x08, 750 NVME_OPC_DATASET_MANAGEMENT = 0x09, 751 752 NVME_OPC_RESERVATION_REGISTER = 0x0d, 753 NVME_OPC_RESERVATION_REPORT = 0x0e, 754 755 NVME_OPC_RESERVATION_ACQUIRE = 0x11, 756 NVME_OPC_RESERVATION_RELEASE = 0x15, 757 758}; 759 760/* 761 * Data transfer (bits 1:0) of an NVMe opcode. 762 */ 763enum nvme_data_transfer { 764 765 /* 766 * Opcode does not transfer data. 767 */ 768 NVME_DATA_NONE = 0, 769 770 /* 771 * Opcode transfers data from host to controller (e.g. Write). 772 */ 773 NVME_DATA_HOST_TO_CONTROLLER = 1, 774 775 /* 776 * Opcode transfers data from controller to host (e.g. Read). 777 */ 778 NVME_DATA_CONTROLLER_TO_HOST = 2, 779 780 /* 781 * Opcode transfers data both directions. 782 */ 783 NVME_DATA_BIDIRECTIONAL = 3 784 785}; 786 787/* 788 * Extract the Data Transfer bits from an NVMe opcode. 789 * 790 * This determines whether a command requires a data buffer and 791 * which direction (host to controller or controller to host) it is 792 * transferred. 793 */ 794static inline enum nvme_data_transfer nvme_opc_get_data_transfer(uint8_t opc) 795{ 796 return (enum nvme_data_transfer)(opc & 3); 797} 798 799/* 800 * Features. 801 */ 802enum nvme_feat { 803 804 /* 0x00 - reserved */ 805 806 NVME_FEAT_ARBITRATION = 0x01, 807 NVME_FEAT_POWER_MANAGEMENT = 0x02, 808 NVME_FEAT_LBA_RANGE_TYPE = 0x03, 809 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04, 810 NVME_FEAT_ERROR_RECOVERY = 0x05, 811 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06, 812 NVME_FEAT_NUMBER_OF_QUEUES = 0x07, 813 NVME_FEAT_INTERRUPT_COALESCING = 0x08, 814 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09, 815 NVME_FEAT_WRITE_ATOMICITY = 0x0A, 816 NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B, 817 NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C, 818 NVME_FEAT_HOST_MEM_BUFFER = 0x0D, 819 NVME_FEAT_KEEP_ALIVE_TIMER = 0x0F, 820 821 /* 0x0C-0x7F - reserved */ 822 823 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80, 824 825 /* 0x81-0xBF - command set specific */ 826 827 NVME_FEAT_HOST_IDENTIFIER = 0x81, 828 NVME_FEAT_HOST_RESERVE_MASK = 0x82, 829 NVME_FEAT_HOST_RESERVE_PERSIST = 0x83, 830 831 /* 0xC0-0xFF - vendor specific */ 832 833}; 834 835/* 836 * Get features selection. 837 */ 838enum nvme_feat_sel { 839 NVME_FEAT_CURRENT = 0x0, 840 NVME_FEAT_DEFAULT = 0x1, 841 NVME_FEAT_SAVED = 0x2, 842 NVME_FEAT_SUPPORTED = 0x3, 843}; 844 845enum nvme_dsm_attribute { 846 NVME_DSM_ATTR_INTEGRAL_READ = 0x1, 847 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2, 848 NVME_DSM_ATTR_DEALLOCATE = 0x4, 849}; 850 851struct nvme_power_state { 852 853 /* 854 * bits 15:00: maximum power. 855 */ 856 uint16_t mp; 857 858 uint8_t reserved1; 859 860 /* 861 * bit 24: max power scale. 862 */ 863 uint8_t mps : 1; 864 865 /* 866 * bit 25: non-operational state. 867 */ 868 uint8_t nops : 1; 869 uint8_t reserved2 : 6; 870 871 /* 872 * bits 63:32: entry latency in microseconds. 873 */ 874 uint32_t enlat; 875 876 /* 877 * bits 95:64: exit latency in microseconds. 878 */ 879 uint32_t exlat; 880 881 /* 882 * bits 100:96: relative read throughput. 883 */ 884 uint8_t rrt : 5; 885 uint8_t reserved3 : 3; 886 887 /* 888 * bits 108:104: relative read latency. 889 */ 890 uint8_t rrl : 5; 891 uint8_t reserved4 : 3; 892 893 /* 894 * bits 116:112: relative write throughput. 895 */ 896 uint8_t rwt : 5; 897 uint8_t reserved5 : 3; 898 899 /* 900 * bits 124:120: relative write latency. 901 */ 902 uint8_t rwl : 5; 903 uint8_t reserved6 : 3; 904 905 uint8_t reserved7[16]; 906 907}; 908nvme_static_assert(sizeof(struct nvme_power_state) == 32, "Incorrect size"); 909 910/* 911 * Identify command CNS value 912 */ 913enum nvme_identify_cns { 914 915 /* 916 * Identify namespace indicated in CDW1.NSID. 917 */ 918 NVME_IDENTIFY_NS = 0x00, 919 920 /* 921 * Identify controller. 922 */ 923 NVME_IDENTIFY_CTRLR = 0x01, 924 925 /* 926 * List active NSIDs greater than CDW1.NSID. 927 */ 928 NVME_IDENTIFY_ACTIVE_NS_LIST = 0x02, 929 930 /* 931 * List allocated NSIDs greater than CDW1.NSID. 932 */ 933 NVME_IDENTIFY_ALLOCATED_NS_LIST = 0x10, 934 935 /* 936 * Identify namespace if CDW1.NSID is allocated. 937 */ 938 NVME_IDENTIFY_NS_ALLOCATED = 0x11, 939 940 /* 941 * Get list of controllers starting at CDW10.CNTID 942 * that are attached to CDW1.NSID. 943 */ 944 NVME_IDENTIFY_NS_ATTACHED_CTRLR_LIST = 0x12, 945 946 /* 947 * Get list of controllers starting at CDW10.CNTID. 948 */ 949 NVME_IDENTIFY_CTRLR_LIST = 0x13, 950}; 951 952/* 953 * NVMe over Fabrics controller model. 954 */ 955enum nvmf_ctrlr_model { 956 957 /* 958 * NVM subsystem uses dynamic controller model. 959 */ 960 NVMF_CTRLR_MODEL_DYNAMIC = 0, 961 962 /* 963 * NVM subsystem uses static controller model. 964 */ 965 NVMF_CTRLR_MODEL_STATIC = 1, 966 967}; 968 969struct __attribute__((packed)) nvme_ctrlr_data { 970 971 /* Bytes 0-255: controller capabilities and features */ 972 973 /* 974 * PCI vendor id. 975 */ 976 uint16_t vid; 977 978 /* 979 * PCI subsystem vendor id. 980 */ 981 uint16_t ssvid; 982 983 /* 984 * Serial number. 985 */ 986 int8_t sn[NVME_SERIAL_NUMBER_CHARACTERS]; 987 988 /* 989 * Model number. 990 */ 991 int8_t mn[NVME_MODEL_NUMBER_CHARACTERS]; 992 993 /* 994 * Firmware revision. 995 */ 996 uint8_t fr[8]; 997 998 /* 999 * Recommended arbitration burst. 1000 */ 1001 uint8_t rab; 1002 1003 /* 1004 * IEEE oui identifier. 1005 */ 1006 uint8_t ieee[3]; 1007 1008 /* 1009 * Controller multi-path I/O and namespace sharing capabilities. 1010 */ 1011 struct { 1012 uint8_t multi_port : 1; 1013 uint8_t multi_host : 1; 1014 uint8_t sr_iov : 1; 1015 uint8_t reserved : 5; 1016 } cmic; 1017 1018 /* 1019 * Maximum data transfer size. 1020 */ 1021 uint8_t mdts; 1022 1023 /* 1024 * Controller ID. 1025 */ 1026 uint16_t cntlid; 1027 1028 /* 1029 * Version. 1030 */ 1031 union nvme_vs_register ver; 1032 1033 /* 1034 * RTD3 resume latency. 1035 */ 1036 uint32_t rtd3r; 1037 1038 /* 1039 * RTD3 entry latency. 1040 */ 1041 uint32_t rtd3e; 1042 1043 /* 1044 * Optional asynchronous events supported. 1045 */ 1046 uint32_t oaes; 1047 1048 /* 1049 * Controller attributes. 1050 */ 1051 struct { 1052 uint32_t host_id_exhid_supported: 1; 1053 uint32_t reserved: 31; 1054 } ctratt; 1055 1056 uint8_t reserved1[156]; 1057 1058 /* 1059 * Bytes 256-511: admin command set attributes. 1060 */ 1061 1062 /* 1063 * Optional admin command support. 1064 */ 1065 struct { 1066 /* 1067 * Supports security send/receive commands. 1068 */ 1069 uint16_t security : 1; 1070 1071 /* 1072 * Supports format nvm command. 1073 */ 1074 uint16_t format : 1; 1075 1076 /* 1077 * Supports firmware activate/download commands. 1078 */ 1079 uint16_t firmware : 1; 1080 1081 /* 1082 * Supports ns manage/ns attach commands. 1083 */ 1084 uint16_t ns_manage : 1; 1085 1086 uint16_t oacs_rsvd : 12; 1087 } oacs; 1088 1089 /* 1090 * Abort command limit. 1091 */ 1092 uint8_t acl; 1093 1094 /* 1095 * Asynchronous event request limit. 1096 */ 1097 uint8_t aerl; 1098 1099 /* 1100 * Firmware updates. 1101 */ 1102 struct { 1103 /* 1104 * First slot is read-only. 1105 */ 1106 uint8_t slot1_ro : 1; 1107 1108 /* 1109 * Number of firmware slots. 1110 */ 1111 uint8_t num_slots : 3; 1112 1113 /* 1114 * Support activation without reset. 1115 */ 1116 uint8_t activation_without_reset : 1; 1117 1118 uint8_t frmw_rsvd : 3; 1119 } frmw; 1120 1121 /* 1122 * Log page attributes. 1123 */ 1124 struct { 1125 /* 1126 * Per namespace smart/health log page. 1127 */ 1128 uint8_t ns_smart : 1; 1129 /* 1130 * Command effects log page. 1131 */ 1132 uint8_t celp : 1; 1133 /* 1134 * Extended data for get log page. 1135 */ 1136 uint8_t edlp : 1; 1137 uint8_t lpa_rsvd : 5; 1138 } lpa; 1139 1140 /* 1141 * Error log page entries. 1142 */ 1143 uint8_t elpe; 1144 1145 /* 1146 * Number of power states supported. 1147 */ 1148 uint8_t npss; 1149 1150 /* 1151 * Admin vendor specific command configuration. 1152 */ 1153 struct { 1154 /* 1155 * Admin vendor specific commands use disk format. 1156 */ 1157 uint8_t spec_format : 1; 1158 uint8_t avscc_rsvd : 7; 1159 } avscc; 1160 1161 /* 1162 * Autonomous power state transition attributes. 1163 */ 1164 struct { 1165 uint8_t supported : 1; 1166 uint8_t apsta_rsvd : 7; 1167 } apsta; 1168 1169 /* 1170 * Warning composite temperature threshold. 1171 */ 1172 uint16_t wctemp; 1173 1174 /* 1175 * Critical composite temperature threshold. 1176 */ 1177 uint16_t cctemp; 1178 1179 /* 1180 * Maximum time for firmware activation. 1181 */ 1182 uint16_t mtfa; 1183 1184 /* 1185 * Host memory buffer preferred size. 1186 */ 1187 uint32_t hmpre; 1188 1189 /* 1190 * Host memory buffer minimum size. 1191 */ 1192 uint32_t hmmin; 1193 1194 /* 1195 * Total NVM capacity. 1196 */ 1197 uint64_t tnvmcap[2]; 1198 1199 /* 1200 * Unallocated NVM capacity. 1201 */ 1202 uint64_t unvmcap[2]; 1203 1204 /* 1205 * Replay protected memory block support. 1206 */ 1207 struct { 1208 uint8_t num_rpmb_units : 3; 1209 uint8_t auth_method : 3; 1210 uint8_t reserved1 : 2; 1211 1212 uint8_t reserved2; 1213 1214 uint8_t total_size; 1215 uint8_t access_size; 1216 } rpmbs; 1217 1218 uint8_t reserved2[4]; 1219 1220 uint16_t kas; 1221 1222 uint8_t reserved3[190]; 1223 1224 /* 1225 * Bytes 512-703: nvm command set attributes. 1226 */ 1227 1228 /* 1229 * Submission queue entry size. 1230 */ 1231 struct { 1232 uint8_t min : 4; 1233 uint8_t max : 4; 1234 } sqes; 1235 1236 /* 1237 * Completion queue entry size. 1238 */ 1239 struct { 1240 uint8_t min : 4; 1241 uint8_t max : 4; 1242 } cqes; 1243 1244 uint16_t maxcmd; 1245 1246 /* 1247 * Number of namespaces. 1248 */ 1249 uint32_t nn; 1250 1251 /* 1252 * Optional nvm command support. 1253 */ 1254 struct { 1255 uint16_t compare : 1; 1256 uint16_t write_unc : 1; 1257 uint16_t dsm : 1; 1258 uint16_t write_zeroes : 1; 1259 uint16_t set_features_save : 1; 1260 uint16_t reservations : 1; 1261 uint16_t reserved : 10; 1262 } oncs; 1263 1264 /* 1265 * Fused operation support. 1266 */ 1267 uint16_t fuses; 1268 1269 /* 1270 * Format nvm attributes. 1271 */ 1272 struct { 1273 uint8_t format_all_ns : 1; 1274 uint8_t erase_all_ns : 1; 1275 uint8_t crypto_erase_supported : 1; 1276 uint8_t reserved : 5; 1277 } fna; 1278 1279 /* 1280 * Volatile write cache. 1281 */ 1282 struct { 1283 uint8_t present : 1; 1284 uint8_t reserved : 7; 1285 } vwc; 1286 1287 /* 1288 * Atomic write unit normal. 1289 */ 1290 uint16_t awun; 1291 1292 /* 1293 * Atomic write unit power fail. 1294 */ 1295 uint16_t awupf; 1296 1297 /* 1298 * NVM vendor specific command configuration. 1299 */ 1300 uint8_t nvscc; 1301 1302 uint8_t reserved531; 1303 1304 /* 1305 * Atomic compare & write unit. 1306 */ 1307 uint16_t acwu; 1308 1309 uint16_t reserved534; 1310 1311 /* 1312 * SGL support. 1313 */ 1314 struct { 1315 uint32_t supported : 1; 1316 uint32_t reserved0 : 1; 1317 uint32_t keyed_sgl : 1; 1318 uint32_t reserved1 : 13; 1319 uint32_t bit_bucket_descriptor : 1; 1320 uint32_t metadata_pointer : 1; 1321 uint32_t oversized_sgl : 1; 1322 uint32_t metadata_address : 1; 1323 uint32_t sgl_offset : 1; 1324 uint32_t reserved2 : 11; 1325 } sgls; 1326 1327 uint8_t reserved4[228]; 1328 1329 uint8_t subnqn[256]; 1330 1331 uint8_t reserved5[768]; 1332 1333 /* 1334 * NVMe over Fabrics-specific fields. 1335 */ 1336 struct { 1337 /* 1338 * I/O queue command capsule supported size (16-byte units). 1339 */ 1340 uint32_t ioccsz; 1341 1342 /* 1343 * I/O queue response capsule supported size (16-byte units). 1344 */ 1345 uint32_t iorcsz; 1346 1347 /* 1348 * In-capsule data offset (16-byte units). 1349 */ 1350 uint16_t icdoff; 1351 1352 /* 1353 * Controller attributes: model. 1354 */ 1355 struct { 1356 uint8_t ctrlr_model : 1; 1357 uint8_t reserved : 7; 1358 } ctrattr; 1359 1360 /* 1361 * Maximum SGL block descriptors (0 = no limit). 1362 */ 1363 uint8_t msdbd; 1364 1365 uint8_t reserved[244]; 1366 } nvmf_specific; 1367 1368 /* 1369 * Bytes 2048-3071: power state descriptors. 1370 */ 1371 struct nvme_power_state psd[32]; 1372 1373 /* 1374 * Bytes 3072-4095: vendor specific. 1375 */ 1376 uint8_t vs[1024]; 1377 1378}; 1379nvme_static_assert(sizeof(struct nvme_ctrlr_data) == 4096, "Incorrect size"); 1380 1381struct nvme_ns_data { 1382 1383 /* 1384 * Namespace size (number of sectors). 1385 */ 1386 uint64_t nsze; 1387 1388 /* 1389 * Namespace capacity. 1390 */ 1391 uint64_t ncap; 1392 1393 /* 1394 * Namespace utilization. 1395 */ 1396 uint64_t nuse; 1397 1398 /* 1399 * Namespace features. 1400 */ 1401 struct { 1402 /* 1403 * Thin provisioning. 1404 */ 1405 uint8_t thin_prov : 1; 1406 uint8_t reserved1 : 7; 1407 } nsfeat; 1408 1409 /* 1410 * Number of lba formats. 1411 */ 1412 uint8_t nlbaf; 1413 1414 /* 1415 * Formatted lba size. 1416 */ 1417 struct { 1418 uint8_t format : 4; 1419 uint8_t extended : 1; 1420 uint8_t reserved2 : 3; 1421 } flbas; 1422 1423 /* 1424 * Metadata capabilities. 1425 */ 1426 struct { 1427 /* 1428 * Metadata can be transferred as part of data prp list. 1429 */ 1430 uint8_t extended : 1; 1431 1432 /* 1433 * Metadata can be transferred with separate metadata pointer. 1434 */ 1435 uint8_t pointer : 1; 1436 1437 uint8_t reserved3 : 6; 1438 } mc; 1439 1440 /* 1441 * End-to-end data protection capabilities. 1442 */ 1443 struct { 1444 /* 1445 * Protection information type 1. 1446 */ 1447 uint8_t pit1 : 1; 1448 1449 /* 1450 * Protection information type 2. 1451 */ 1452 uint8_t pit2 : 1; 1453 1454 /* 1455 * Protection information type 3. 1456 */ 1457 uint8_t pit3 : 1; 1458 1459 /* 1460 * First eight bytes of metadata. 1461 */ 1462 uint8_t md_start : 1; 1463 1464 /* 1465 * Last eight bytes of metadata. 1466 */ 1467 uint8_t md_end : 1; 1468 } dpc; 1469 1470 /* 1471 * End-to-end data protection type settings. 1472 */ 1473 struct { 1474 /* 1475 * Protection information type. 1476 */ 1477 uint8_t pit : 3; 1478 1479 /* 1480 * 1 == protection info transferred at start of metadata. 1481 * 0 == protection info transferred at end of metadata. 1482 */ 1483 uint8_t md_start : 1; 1484 1485 uint8_t reserved4 : 4; 1486 } dps; 1487 1488 /* 1489 * Namespace multi-path I/O and namespace sharing capabilities. 1490 */ 1491 struct { 1492 uint8_t can_share : 1; 1493 uint8_t reserved : 7; 1494 } nmic; 1495 1496 /* 1497 * Reservation capabilities. 1498 */ 1499 union { 1500 struct { 1501 /* 1502 * Supports persist through power loss. 1503 */ 1504 uint8_t persist : 1; 1505 1506 /* 1507 * Supports write exclusive. 1508 */ 1509 uint8_t write_exclusive : 1; 1510 1511 /* 1512 * Supports exclusive access. 1513 */ 1514 uint8_t exclusive_access : 1; 1515 1516 /* 1517 * Supports write exclusive - registrants only. 1518 */ 1519 uint8_t write_exclusive_reg_only : 1; 1520 1521 /* 1522 * Supports exclusive access - registrants only. 1523 */ 1524 uint8_t exclusive_access_reg_only : 1; 1525 1526 /* 1527 * Supports write exclusive - all registrants. 1528 */ 1529 uint8_t write_exclusive_all_reg : 1; 1530 1531 /* 1532 * Supports exclusive access - all registrants. 1533 */ 1534 uint8_t exclusive_access_all_reg : 1; 1535 1536 uint8_t reserved : 1; 1537 } rescap; 1538 uint8_t raw; 1539 } nsrescap; 1540 1541 /* 1542 * Format progress indicator. 1543 */ 1544 struct { 1545 uint8_t percentage_remaining : 7; 1546 uint8_t fpi_supported : 1; 1547 } fpi; 1548 1549 uint8_t reserved33; 1550 1551 /* 1552 * Namespace atomic write unit normal. 1553 */ 1554 uint16_t nawun; 1555 1556 /* 1557 * Namespace atomic write unit power fail. 1558 */ 1559 uint16_t nawupf; 1560 1561 /* 1562 * Namespace atomic compare & write unit. 1563 */ 1564 uint16_t nacwu; 1565 1566 /* 1567 * Namespace atomic boundary size normal. 1568 */ 1569 uint16_t nabsn; 1570 1571 /* 1572 * Namespace atomic boundary offset. 1573 */ 1574 uint16_t nabo; 1575 1576 /* 1577 * Namespace atomic boundary size power fail. 1578 */ 1579 uint16_t nabspf; 1580 1581 uint16_t reserved46; 1582 1583 /* 1584 * NVM capacity. 1585 */ 1586 uint64_t nvmcap[2]; 1587 1588 uint8_t reserved64[40]; 1589 1590 /* 1591 * Namespace globally unique identifier. 1592 */ 1593 uint8_t nguid[16]; 1594 1595 /* 1596 * IEEE extended unique identifier. 1597 */ 1598 uint64_t eui64; 1599 1600 /* 1601 * LBA format support. 1602 */ 1603 struct { 1604 /* 1605 * Metadata size. 1606 */ 1607 uint32_t ms : 16; 1608 1609 /* 1610 * LBA data size. 1611 */ 1612 uint32_t lbads : 8; 1613 1614 /* 1615 * Relative performance. 1616 */ 1617 uint32_t rp : 2; 1618 1619 uint32_t reserved6 : 6; 1620 } lbaf[16]; 1621 1622 uint8_t reserved6[192]; 1623 1624 uint8_t vendor_specific[3712]; 1625}; 1626nvme_static_assert(sizeof(struct nvme_ns_data) == 4096, "Incorrect size"); 1627 1628/* 1629 * Reservation Type Encoding 1630 */ 1631enum nvme_reservation_type { 1632 1633 /* 0x00 - reserved */ 1634 1635 /* 1636 * Write Exclusive Reservation. 1637 */ 1638 NVME_RESERVE_WRITE_EXCLUSIVE = 0x1, 1639 1640 /* 1641 * Exclusive Access Reservation. 1642 */ 1643 NVME_RESERVE_EXCLUSIVE_ACCESS = 0x2, 1644 1645 /* 1646 * Write Exclusive - Registrants Only Reservation. 1647 */ 1648 NVME_RESERVE_WRITE_EXCLUSIVE_REG_ONLY = 0x3, 1649 1650 /* 1651 * Exclusive Access - Registrants Only Reservation. 1652 */ 1653 NVME_RESERVE_EXCLUSIVE_ACCESS_REG_ONLY = 0x4, 1654 1655 /* 1656 * Write Exclusive - All Registrants Reservation. 1657 */ 1658 NVME_RESERVE_WRITE_EXCLUSIVE_ALL_REGS = 0x5, 1659 1660 /* 1661 * Exclusive Access - All Registrants Reservation. 1662 */ 1663 NVME_RESERVE_EXCLUSIVE_ACCESS_ALL_REGS = 0x6, 1664 1665 /* 0x7-0xFF - Reserved */ 1666}; 1667 1668struct nvme_reservation_acquire_data { 1669 1670 /* 1671 * Current reservation key. 1672 */ 1673 uint64_t crkey; 1674 1675 /* 1676 * Preempt reservation key. 1677 */ 1678 uint64_t prkey; 1679 1680}; 1681nvme_static_assert(sizeof(struct nvme_reservation_acquire_data) == 16, 1682 "Incorrect size"); 1683 1684/* 1685 * Reservation Acquire action 1686 */ 1687enum nvme_reservation_acquire_action { 1688 NVME_RESERVE_ACQUIRE = 0x0, 1689 NVME_RESERVE_PREEMPT = 0x1, 1690 NVME_RESERVE_PREEMPT_ABORT = 0x2, 1691}; 1692 1693struct __attribute__((packed)) nvme_reservation_status_data { 1694 1695 /* 1696 * Reservation action generation counter. 1697 */ 1698 uint32_t generation; 1699 1700 /* 1701 * Reservation type. 1702 */ 1703 uint8_t type; 1704 1705 /* 1706 * Number of registered controllers. 1707 */ 1708 uint16_t nr_regctl; 1709 uint16_t reserved1; 1710 1711 /* 1712 * Persist through power loss state. 1713 */ 1714 uint8_t ptpl_state; 1715 uint8_t reserved[14]; 1716 1717}; 1718nvme_static_assert(sizeof(struct nvme_reservation_status_data) == 24, 1719 "Incorrect size"); 1720 1721struct __attribute__((packed)) nvme_reservation_ctrlr_data { 1722 1723 uint16_t ctrlr_id; 1724 1725 /* 1726 * Reservation status. 1727 */ 1728 struct { 1729 uint8_t status : 1; 1730 uint8_t reserved1 : 7; 1731 } rcsts; 1732 uint8_t reserved2[5]; 1733 1734 /* 1735 * Host identifier. 1736 */ 1737 uint64_t host_id; 1738 1739 /* 1740 * Reservation key. 1741 */ 1742 uint64_t key; 1743}; 1744nvme_static_assert(sizeof(struct nvme_reservation_ctrlr_data) == 24, 1745 "Incorrect size"); 1746 1747/* 1748 * Change persist through power loss state for 1749 * Reservation Register command 1750 */ 1751enum nvme_reservation_register_cptpl { 1752 NVME_RESERVE_PTPL_NO_CHANGES = 0x0, 1753 NVME_RESERVE_PTPL_CLEAR_POWER_ON = 0x2, 1754 NVME_RESERVE_PTPL_PERSIST_POWER_LOSS = 0x3, 1755}; 1756 1757/* 1758 * Registration action for Reservation Register command 1759 */ 1760enum nvme_reservation_register_action { 1761 NVME_RESERVE_REGISTER_KEY = 0x0, 1762 NVME_RESERVE_UNREGISTER_KEY = 0x1, 1763 NVME_RESERVE_REPLACE_KEY = 0x2, 1764}; 1765 1766struct nvme_reservation_register_data { 1767 1768 /* 1769 * Current reservation key. 1770 */ 1771 uint64_t crkey; 1772 1773 /* 1774 * New reservation key. 1775 */ 1776 uint64_t nrkey; 1777 1778}; 1779nvme_static_assert(sizeof(struct nvme_reservation_register_data) == 16, 1780 "Incorrect size"); 1781 1782struct nvme_reservation_key_data { 1783 1784 /* 1785 * Current reservation key. 1786 */ 1787 uint64_t crkey; 1788 1789}; 1790nvme_static_assert(sizeof(struct nvme_reservation_key_data) == 8, 1791 "Incorrect size"); 1792 1793/* 1794 * Reservation Release action 1795 */ 1796enum nvme_reservation_release_action { 1797 NVME_RESERVE_RELEASE = 0x0, 1798 NVME_RESERVE_CLEAR = 0x1, 1799}; 1800 1801/* 1802 * Log page identifiers for NVME_OPC_GET_LOG_PAGE 1803 */ 1804enum nvme_log_page { 1805 1806 /* 0x00 - reserved */ 1807 1808 /* 1809 * Error information (mandatory). 1810 */ 1811 NVME_LOG_ERROR = 0x01, 1812 1813 /* 1814 * SMART / health information (mandatory). 1815 */ 1816 NVME_LOG_HEALTH_INFORMATION = 0x02, 1817 1818 /* 1819 * Firmware slot information (mandatory). 1820 */ 1821 NVME_LOG_FIRMWARE_SLOT = 0x03, 1822 1823 /* 1824 * Changed namespace list (optional). 1825 */ 1826 NVME_LOG_CHANGED_NS_LIST = 0x04, 1827 1828 /* 1829 * Command effects log (optional). 1830 */ 1831 NVME_LOG_COMMAND_EFFECTS_LOG = 0x05, 1832 1833 /* 0x06-0x6F - reserved */ 1834 1835 /* 1836 * Discovery(refer to the NVMe over Fabrics specification). 1837 */ 1838 NVME_LOG_DISCOVERY = 0x70, 1839 1840 /* 0x71-0x7f - reserved for NVMe over Fabrics */ 1841 1842 /* 1843 * Reservation notification (optional). 1844 */ 1845 NVME_LOG_RESERVATION_NOTIFICATION = 0x80, 1846 1847 /* 0x81-0xBF - I/O command set specific */ 1848 1849 /* 0xC0-0xFF - vendor specific */ 1850}; 1851 1852/* 1853 * Error information log page (\ref NVME_LOG_ERROR) 1854 */ 1855struct nvme_error_information_entry { 1856 uint64_t error_count; 1857 uint16_t sqid; 1858 uint16_t cid; 1859 struct nvme_status status; 1860 uint16_t error_location; 1861 uint64_t lba; 1862 uint32_t nsid; 1863 uint8_t vendor_specific; 1864 uint8_t reserved[35]; 1865}; 1866nvme_static_assert(sizeof(struct nvme_error_information_entry) == 64, 1867 "Incorrect size"); 1868 1869union nvme_critical_warning_state { 1870 1871 uint8_t raw; 1872 1873 struct { 1874 uint8_t available_spare : 1; 1875 uint8_t temperature : 1; 1876 uint8_t device_reliability : 1; 1877 uint8_t read_only : 1; 1878 uint8_t volatile_memory_backup : 1; 1879 uint8_t reserved : 3; 1880 } bits; 1881 1882}; 1883nvme_static_assert(sizeof(union nvme_critical_warning_state) == 1, 1884 "Incorrect size"); 1885 1886/* 1887 * SMART / health information page (\ref NVME_LOG_HEALTH_INFORMATION) 1888 */ 1889struct __attribute__((packed)) nvme_health_information_page { 1890 1891 union nvme_critical_warning_state critical_warning; 1892 1893 uint16_t temperature; 1894 uint8_t available_spare; 1895 uint8_t available_spare_threshold; 1896 uint8_t percentage_used; 1897 1898 uint8_t reserved[26]; 1899 1900 /* 1901 * Note that the following are 128-bit values, but are 1902 * defined as an array of 2 64-bit values. 1903 */ 1904 1905 /* 1906 * Data Units Read is always in 512-byte units. 1907 */ 1908 uint64_t data_units_read[2]; 1909 1910 /* 1911 * Data Units Written is always in 512-byte units. 1912 */ 1913 uint64_t data_units_written[2]; 1914 1915 /* 1916 * For NVM command set, this includes Compare commands. 1917 */ 1918 uint64_t host_read_commands[2]; 1919 uint64_t host_write_commands[2]; 1920 1921 /* 1922 * Controller Busy Time is reported in minutes. 1923 */ 1924 uint64_t controller_busy_time[2]; 1925 uint64_t power_cycles[2]; 1926 uint64_t power_on_hours[2]; 1927 uint64_t unsafe_shutdowns[2]; 1928 uint64_t media_errors[2]; 1929 uint64_t num_error_info_log_entries[2]; 1930 1931 uint8_t reserved2[320]; 1932}; 1933nvme_static_assert(sizeof(struct nvme_health_information_page) == 512, 1934 "Incorrect size"); 1935 1936/* 1937 * Firmware slot information page (\ref NVME_LOG_FIRMWARE_SLOT) 1938 */ 1939struct nvme_firmware_page { 1940 1941 struct { 1942 /* 1943 * Slot for current FW. 1944 */ 1945 uint8_t slot : 3; 1946 uint8_t reserved : 5; 1947 } afi; 1948 1949 uint8_t reserved[7]; 1950 1951 /* 1952 * Revisions for 7 slots. 1953 */ 1954 uint64_t revision[7]; 1955 1956 uint8_t reserved2[448]; 1957 1958}; 1959nvme_static_assert(sizeof(struct nvme_firmware_page) == 512, 1960 "Incorrect size"); 1961 1962/* 1963 * Namespace attachment Type Encoding 1964 */ 1965enum nvme_ns_attach_type { 1966 1967 /* 1968 * Controller attach. 1969 */ 1970 NVME_NS_CTRLR_ATTACH = 0x0, 1971 1972 /* 1973 * Controller detach. 1974 */ 1975 NVME_NS_CTRLR_DETACH = 0x1, 1976 1977 /* 0x2-0xF - Reserved */ 1978 1979}; 1980 1981/* 1982 * Namespace management Type Encoding 1983 */ 1984enum nvme_ns_management_type { 1985 1986 /* 1987 * Create. 1988 */ 1989 NVME_NS_MANAGEMENT_CREATE = 0x0, 1990 1991 /* 1992 * Delete. 1993 */ 1994 NVME_NS_MANAGEMENT_DELETE = 0x1, 1995 1996 /* 0x2-0xF - Reserved */ 1997 1998}; 1999 2000struct nvme_ns_list { 2001 uint32_t ns_list[NVME_MAX_NS]; 2002}; 2003nvme_static_assert(sizeof(struct nvme_ns_list) == 4096, "Incorrect size"); 2004 2005struct nvme_ctrlr_list { 2006 uint16_t ctrlr_count; 2007 uint16_t ctrlr_list[2047]; 2008}; 2009nvme_static_assert(sizeof(struct nvme_ctrlr_list) == 4096, "Incorrect size"); 2010 2011enum nvme_secure_erase_setting { 2012 NVME_FMT_NVM_SES_NO_SECURE_ERASE = 0x0, 2013 NVME_FMT_NVM_SES_USER_DATA_ERASE = 0x1, 2014 NVME_FMT_NVM_SES_CRYPTO_ERASE = 0x2, 2015}; 2016 2017enum nvme_pi_location { 2018 NVME_FMT_NVM_PROTECTION_AT_TAIL = 0x0, 2019 NVME_FMT_NVM_PROTECTION_AT_HEAD = 0x1, 2020}; 2021 2022enum nvme_pi_type { 2023 NVME_FMT_NVM_PROTECTION_DISABLE = 0x0, 2024 NVME_FMT_NVM_PROTECTION_TYPE1 = 0x1, 2025 NVME_FMT_NVM_PROTECTION_TYPE2 = 0x2, 2026 NVME_FMT_NVM_PROTECTION_TYPE3 = 0x3, 2027}; 2028 2029enum nvme_metadata_setting { 2030 NVME_FMT_NVM_METADATA_TRANSFER_AS_BUFFER = 0x0, 2031 NVME_FMT_NVM_METADATA_TRANSFER_AS_LBA = 0x1, 2032}; 2033 2034struct nvme_format { 2035 uint32_t lbaf : 4; 2036 uint32_t ms : 1; 2037 uint32_t pi : 3; 2038 uint32_t pil : 1; 2039 uint32_t ses : 3; 2040 uint32_t reserved : 20; 2041}; 2042nvme_static_assert(sizeof(struct nvme_format) == 4, "Incorrect size"); 2043 2044struct nvme_protection_info { 2045 uint16_t guard; 2046 uint16_t app_tag; 2047 uint32_t ref_tag; 2048}; 2049nvme_static_assert(sizeof(struct nvme_protection_info) == 8, "Incorrect size"); 2050 2051/* 2052 * Parameters for NVME_OPC_FIRMWARE_COMMIT cdw10: commit action. 2053 */ 2054enum nvme_fw_commit_action { 2055 2056 /* 2057 * Downloaded image replaces the image specified by 2058 * the Firmware Slot field. This image is not activated. 2059 */ 2060 NVME_FW_COMMIT_REPLACE_IMG = 0x0, 2061 2062 /* 2063 * Downloaded image replaces the image specified by 2064 * the Firmware Slot field. This image is activated at the next reset. 2065 */ 2066 NVME_FW_COMMIT_REPLACE_AND_ENABLE_IMG = 0x1, 2067 2068 /* 2069 * The image specified by the Firmware Slot field is 2070 * activated at the next reset. 2071 */ 2072 NVME_FW_COMMIT_ENABLE_IMG = 0x2, 2073 2074 /* 2075 * The image specified by the Firmware Slot field is 2076 * requested to be activated immediately without reset. 2077 */ 2078 NVME_FW_COMMIT_RUN_IMG = 0x3, 2079 2080}; 2081 2082/* 2083 * Parameters for NVME_OPC_FIRMWARE_COMMIT cdw10. 2084 */ 2085struct nvme_fw_commit { 2086 2087 /* 2088 * Firmware Slot. Specifies the firmware slot that shall be used for the 2089 * Commit Action. The controller shall choose the firmware slot (slot 1 - 7) 2090 * to use for the operation if the value specified is 0h. 2091 */ 2092 uint32_t fs : 3; 2093 2094 /* 2095 * Commit Action. Specifies the action that is taken on the image downloaded 2096 * with the Firmware Image Download command or on a previously downloaded and 2097 * placed image. 2098 */ 2099 uint32_t ca : 3; 2100 2101 uint32_t reserved : 26; 2102 2103}; 2104nvme_static_assert(sizeof(struct nvme_fw_commit) == 4, "Incorrect size"); 2105 2106#define nvme_cpl_is_error(cpl) \ 2107 ((cpl)->status.sc != 0 || (cpl)->status.sct != 0) 2108 2109/* 2110 * Enable protection information checking of the 2111 * Logical Block Reference Tag field. 2112 */ 2113#define NVME_IO_FLAGS_PRCHK_REFTAG (1U << 26) 2114 2115/* 2116 * Enable protection information checking of the 2117 * Application Tag field. 2118 */ 2119#define NVME_IO_FLAGS_PRCHK_APPTAG (1U << 27) 2120 2121/* 2122 * Enable protection information checking of the Guard field. 2123 */ 2124#define NVME_IO_FLAGS_PRCHK_GUARD (1U << 28) 2125 2126/* 2127 * Strip or insert (when set) the protection information. 2128 */ 2129#define NVME_IO_FLAGS_PRACT (1U << 29) 2130 2131/* 2132 * Bypass device cache. 2133 */ 2134#define NVME_IO_FLAGS_FORCE_UNIT_ACCESS (1U << 30) 2135 2136/* 2137 * Limit retries on error. 2138 */ 2139#define NVME_IO_FLAGS_LIMITED_RETRY (1U << 31) 2140 2141#endif /* define __LIBNVME_SPEC_H__ */ 2142 2143