1/*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * Copyright (c) 2015 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Andrew Turner under 7 * sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32#ifndef _MACHINE_ARMREG_H_ 33#define _MACHINE_ARMREG_H_ 34 35#define INSN_SIZE 4 36 37#define __ARMREG_STRING(x) #x 38 39#define READ_SPECIALREG(reg) \ 40({ uint64_t val; \ 41 __asm __volatile("mrs %0, " __ARMREG_STRING(reg) : "=&r" (val)); \ 42 val; \ 43}) 44#define WRITE_SPECIALREG(reg, val) \ 45 __asm __volatile("msr " __ARMREG_STRING(reg) ", %0" : : "r"((uint64_t)val)) 46 47/* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */ 48#define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ 49#define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ 50#define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ 51#define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */ 52#define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/ 53 54/* CPACR_EL1 */ 55#define CPACR_FPEN_MASK (0x3 << 20) 56#define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */ 57#define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */ 58#define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */ 59#define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */ 60#define CPACR_TTA (0x1 << 28) 61 62/* CTR_EL0 - Cache Type Register */ 63#define CTR_DLINE_SHIFT 16 64#define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) 65#define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT) 66#define CTR_ILINE_SHIFT 0 67#define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) 68#define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT) 69 70/* DAIF - Interrupt Mask Bits */ 71#define DAIF_D_MASKED (1 << 9) 72#define DAIF_A_MASKED (1 << 8) 73#define DAIF_I_MASKED (1 << 7) 74#define DAIF_F_MASKED (1 << 6) 75 76/* DCZID_EL0 - Data Cache Zero ID register */ 77#define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */ 78#define DCZID_BS_SHIFT 0 79#define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT) 80#define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT) 81 82/* ESR_ELx */ 83#define ESR_ELx_ISS_MASK 0x00ffffff 84#define ISS_INSN_FnV (0x01 << 10) 85#define ISS_INSN_EA (0x01 << 9) 86#define ISS_INSN_S1PTW (0x01 << 7) 87#define ISS_INSN_IFSC_MASK (0x1f << 0) 88#define ISS_DATA_ISV (0x01 << 24) 89#define ISS_DATA_SAS_MASK (0x03 << 22) 90#define ISS_DATA_SSE (0x01 << 21) 91#define ISS_DATA_SRT_MASK (0x1f << 16) 92#define ISS_DATA_SF (0x01 << 15) 93#define ISS_DATA_AR (0x01 << 14) 94#define ISS_DATA_FnV (0x01 << 10) 95#define ISS_DATA_EA (0x01 << 9) 96#define ISS_DATA_CM (0x01 << 8) 97#define ISS_INSN_S1PTW (0x01 << 7) 98#define ISS_DATA_WnR (0x01 << 6) 99#define ISS_DATA_DFSC_MASK (0x3f << 0) 100#define ISS_DATA_DFSC_ASF_L0 (0x00 << 0) 101#define ISS_DATA_DFSC_ASF_L1 (0x01 << 0) 102#define ISS_DATA_DFSC_ASF_L2 (0x02 << 0) 103#define ISS_DATA_DFSC_ASF_L3 (0x03 << 0) 104#define ISS_DATA_DFSC_TF_L0 (0x04 << 0) 105#define ISS_DATA_DFSC_TF_L1 (0x05 << 0) 106#define ISS_DATA_DFSC_TF_L2 (0x06 << 0) 107#define ISS_DATA_DFSC_TF_L3 (0x07 << 0) 108#define ISS_DATA_DFSC_AFF_L1 (0x09 << 0) 109#define ISS_DATA_DFSC_AFF_L2 (0x0a << 0) 110#define ISS_DATA_DFSC_AFF_L3 (0x0b << 0) 111#define ISS_DATA_DFSC_PF_L1 (0x0d << 0) 112#define ISS_DATA_DFSC_PF_L2 (0x0e << 0) 113#define ISS_DATA_DFSC_PF_L3 (0x0f << 0) 114#define ISS_DATA_DFSC_EXT (0x10 << 0) 115#define ISS_DATA_DFSC_EXT_L0 (0x14 << 0) 116#define ISS_DATA_DFSC_EXT_L1 (0x15 << 0) 117#define ISS_DATA_DFSC_EXT_L2 (0x16 << 0) 118#define ISS_DATA_DFSC_EXT_L3 (0x17 << 0) 119#define ISS_DATA_DFSC_ECC (0x18 << 0) 120#define ISS_DATA_DFSC_ECC_L0 (0x1c << 0) 121#define ISS_DATA_DFSC_ECC_L1 (0x1d << 0) 122#define ISS_DATA_DFSC_ECC_L2 (0x1e << 0) 123#define ISS_DATA_DFSC_ECC_L3 (0x1f << 0) 124#define ISS_DATA_DFSC_ALIGN (0x21 << 0) 125#define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0) 126#define ESR_ELx_IL (0x01 << 25) 127#define ESR_ELx_EC_SHIFT 26 128#define ESR_ELx_EC_MASK (0x3f << 26) 129#define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 130#define EXCP_UNKNOWN 0x00 /* Unkwn exception */ 131#define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */ 132#define EXCP_ILL_STATE 0x0e /* Illegal execution state */ 133#define EXCP_SVC32 0x11 /* SVC trap for AArch32 */ 134#define EXCP_SVC64 0x15 /* SVC trap for AArch64 */ 135#define EXCP_MSR 0x18 /* MSR/MRS trap */ 136#define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */ 137#define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */ 138#define EXCP_PC_ALIGN 0x22 /* PC alignment fault */ 139#define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */ 140#define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */ 141#define EXCP_SP_ALIGN 0x26 /* SP slignment fault */ 142#define EXCP_TRAP_FP 0x2c /* Trapped FP exception */ 143#define EXCP_SERROR 0x2f /* SError interrupt */ 144#define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */ 145#define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */ 146#define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */ 147#define EXCP_BRK 0x3c /* Breakpoint */ 148 149/* ICC_CTLR_EL1 */ 150#define ICC_CTLR_EL1_EOIMODE (1U << 1) 151 152/* ICC_IAR1_EL1 */ 153#define ICC_IAR1_EL1_SPUR (0x03ff) 154 155/* ICC_IGRPEN0_EL1 */ 156#define ICC_IGRPEN0_EL1_EN (1U << 0) 157 158/* ICC_PMR_EL1 */ 159#define ICC_PMR_EL1_PRIO_MASK (0xFFUL) 160 161/* ICC_SGI1R_EL1 */ 162#define ICC_SGI1R_EL1_TL_MASK 0xffffUL 163#define ICC_SGI1R_EL1_AFF1_SHIFT 16 164#define ICC_SGI1R_EL1_SGIID_SHIFT 24 165#define ICC_SGI1R_EL1_AFF2_SHIFT 32 166#define ICC_SGI1R_EL1_AFF3_SHIFT 48 167#define ICC_SGI1R_EL1_SGIID_MASK 0xfUL 168#define ICC_SGI1R_EL1_IRM (0x1UL << 40) 169 170/* ICC_SRE_EL1 */ 171#define ICC_SRE_EL1_SRE (1U << 0) 172 173/* ICC_SRE_EL2 */ 174#define ICC_SRE_EL2_SRE (1U << 0) 175#define ICC_SRE_EL2_EN (1U << 3) 176 177/* ID_AA64DFR0_EL1 */ 178#define ID_AA64DFR0_MASK 0x0000000ff0f0fffful 179#define ID_AA64DFR0_DEBUG_VER_SHIFT 0 180#define ID_AA64DFR0_DEBUG_VER_MASK (0xf << ID_AA64DFR0_DEBUG_VER_SHIFT) 181#define ID_AA64DFR0_DEBUG_VER(x) ((x) & ID_AA64DFR0_DEBUG_VER_MASK) 182#define ID_AA64DFR0_DEBUG_VER_8 (0x6 << ID_AA64DFR0_DEBUG_VER_SHIFT) 183#define ID_AA64DFR0_DEBUG_VER_8_VHE (0x7 << ID_AA64DFR0_DEBUG_VER_SHIFT) 184#define ID_AA64DFR0_DEBUG_VER_8_2 (0x8 << ID_AA64DFR0_DEBUG_VER_SHIFT) 185#define ID_AA64DFR0_TRACE_VER_SHIFT 4 186#define ID_AA64DFR0_TRACE_VER_MASK (0xf << ID_AA64DFR0_TRACE_VER_SHIFT) 187#define ID_AA64DFR0_TRACE_VER(x) ((x) & ID_AA64DFR0_TRACE_VER_MASK) 188#define ID_AA64DFR0_TRACE_VER_NONE (0x0 << ID_AA64DFR0_TRACE_VER_SHIFT) 189#define ID_AA64DFR0_TRACE_VER_IMPL (0x1 << ID_AA64DFR0_TRACE_VER_SHIFT) 190#define ID_AA64DFR0_PMU_VER_SHIFT 8 191#define ID_AA64DFR0_PMU_VER_MASK (0xf << ID_AA64DFR0_PMU_VER_SHIFT) 192#define ID_AA64DFR0_PMU_VER(x) ((x) & ID_AA64DFR0_PMU_VER_MASK) 193#define ID_AA64DFR0_PMU_VER_NONE (0x0 << ID_AA64DFR0_PMU_VER_SHIFT) 194#define ID_AA64DFR0_PMU_VER_3 (0x1 << ID_AA64DFR0_PMU_VER_SHIFT) 195#define ID_AA64DFR0_PMU_VER_3_1 (0x4 << ID_AA64DFR0_PMU_VER_SHIFT) 196#define ID_AA64DFR0_PMU_VER_IMPL (0xf << ID_AA64DFR0_PMU_VER_SHIFT) 197#define ID_AA64DFR0_BRPS_SHIFT 12 198#define ID_AA64DFR0_BRPS_MASK (0xf << ID_AA64DFR0_BRPS_SHIFT) 199#define ID_AA64DFR0_BRPS(x) \ 200 ((((x) >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) + 1) 201#define ID_AA64DFR0_WRPS_SHIFT 20 202#define ID_AA64DFR0_WRPS_MASK (0xf << ID_AA64DFR0_WRPS_SHIFT) 203#define ID_AA64DFR0_WRPS(x) \ 204 ((((x) >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) + 1) 205#define ID_AA64DFR0_CTX_CMPS_SHIFT 28 206#define ID_AA64DFR0_CTX_CMPS_MASK (0xf << ID_AA64DFR0_CTX_CMPS_SHIFT) 207#define ID_AA64DFR0_CTX_CMPS(x) \ 208 ((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1) 209#define ID_AA64DFR0_PMS_VER_SHIFT 32 210#define ID_AA64DFR0_PMS_VER_MASK (0xful << ID_AA64DFR0_PMS_VER_SHIFT) 211#define ID_AA64DFR0_PMS_VER(x) ((x) & ID_AA64DFR0_PMS_VER_MASK) 212#define ID_AA64DFR0_PMS_VER_NONE (0x0ul << ID_AA64DFR0_PMS_VER_SHIFT) 213#define ID_AA64DFR0_PMS_VER_V1 (0x1ul << ID_AA64DFR0_PMS_VER_SHIFT) 214 215/* ID_AA64ISAR0_EL1 */ 216#define ID_AA64ISAR0_MASK 0x0000fffff0fffff0ul 217#define ID_AA64ISAR0_AES_SHIFT 4 218#define ID_AA64ISAR0_AES_MASK (0xf << ID_AA64ISAR0_AES_SHIFT) 219#define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK) 220#define ID_AA64ISAR0_AES_NONE (0x0 << ID_AA64ISAR0_AES_SHIFT) 221#define ID_AA64ISAR0_AES_BASE (0x1 << ID_AA64ISAR0_AES_SHIFT) 222#define ID_AA64ISAR0_AES_PMULL (0x2 << ID_AA64ISAR0_AES_SHIFT) 223#define ID_AA64ISAR0_SHA1_SHIFT 8 224#define ID_AA64ISAR0_SHA1_MASK (0xf << ID_AA64ISAR0_SHA1_SHIFT) 225#define ID_AA64ISAR0_SHA1(x) ((x) & ID_AA64ISAR0_SHA1_MASK) 226#define ID_AA64ISAR0_SHA1_NONE (0x0 << ID_AA64ISAR0_SHA1_SHIFT) 227#define ID_AA64ISAR0_SHA1_BASE (0x1 << ID_AA64ISAR0_SHA1_SHIFT) 228#define ID_AA64ISAR0_SHA2_SHIFT 12 229#define ID_AA64ISAR0_SHA2_MASK (0xf << ID_AA64ISAR0_SHA2_SHIFT) 230#define ID_AA64ISAR0_SHA2(x) ((x) & ID_AA64ISAR0_SHA2_MASK) 231#define ID_AA64ISAR0_SHA2_NONE (0x0 << ID_AA64ISAR0_SHA2_SHIFT) 232#define ID_AA64ISAR0_SHA2_BASE (0x1 << ID_AA64ISAR0_SHA2_SHIFT) 233#define ID_AA64ISAR0_SHA2_512 (0x2 << ID_AA64ISAR0_SHA2_SHIFT) 234#define ID_AA64ISAR0_CRC32_SHIFT 16 235#define ID_AA64ISAR0_CRC32_MASK (0xf << ID_AA64ISAR0_CRC32_SHIFT) 236#define ID_AA64ISAR0_CRC32(x) ((x) & ID_AA64ISAR0_CRC32_MASK) 237#define ID_AA64ISAR0_CRC32_NONE (0x0 << ID_AA64ISAR0_CRC32_SHIFT) 238#define ID_AA64ISAR0_CRC32_BASE (0x1 << ID_AA64ISAR0_CRC32_SHIFT) 239#define ID_AA64ISAR0_ATOMIC_SHIFT 20 240#define ID_AA64ISAR0_ATOMIC_MASK (0xf << ID_AA64ISAR0_ATOMIC_SHIFT) 241#define ID_AA64ISAR0_ATOMIC(x) ((x) & ID_AA64ISAR0_ATOMIC_MASK) 242#define ID_AA64ISAR0_ATOMIC_NONE (0x0 << ID_AA64ISAR0_ATOMIC_SHIFT) 243#define ID_AA64ISAR0_ATOMIC_IMPL (0x2 << ID_AA64ISAR0_ATOMIC_SHIFT) 244#define ID_AA64ISAR0_RDM_SHIFT 28 245#define ID_AA64ISAR0_RDM_MASK (0xf << ID_AA64ISAR0_RDM_SHIFT) 246#define ID_AA64ISAR0_RDM(x) ((x) & ID_AA64ISAR0_RDM_MASK) 247#define ID_AA64ISAR0_RDM_NONE (0x0 << ID_AA64ISAR0_RDM_SHIFT) 248#define ID_AA64ISAR0_RDM_IMPL (0x1 << ID_AA64ISAR0_RDM_SHIFT) 249#define ID_AA64ISAR0_SHA3_SHIFT 32 250#define ID_AA64ISAR0_SHA3_MASK (0xful << ID_AA64ISAR0_SHA3_SHIFT) 251#define ID_AA64ISAR0_SHA3(x) ((x) & ID_AA64ISAR0_SHA3_MASK) 252#define ID_AA64ISAR0_SHA3_NONE (0x0ul << ID_AA64ISAR0_SHA3_SHIFT) 253#define ID_AA64ISAR0_SHA3_IMPL (0x1ul << ID_AA64ISAR0_SHA3_SHIFT) 254#define ID_AA64ISAR0_SM3_SHIFT 36 255#define ID_AA64ISAR0_SM3_MASK (0xful << ID_AA64ISAR0_SM3_SHIFT) 256#define ID_AA64ISAR0_SM3(x) ((x) & ID_AA64ISAR0_SM3_MASK) 257#define ID_AA64ISAR0_SM3_NONE (0x0ul << ID_AA64ISAR0_SM3_SHIFT) 258#define ID_AA64ISAR0_SM3_IMPL (0x1ul << ID_AA64ISAR0_SM3_SHIFT) 259#define ID_AA64ISAR0_SM4_SHIFT 40 260#define ID_AA64ISAR0_SM4_MASK (0xful << ID_AA64ISAR0_SM4_SHIFT) 261#define ID_AA64ISAR0_SM4(x) ((x) & ID_AA64ISAR0_SM4_MASK) 262#define ID_AA64ISAR0_SM4_NONE (0x0ul << ID_AA64ISAR0_SM4_SHIFT) 263#define ID_AA64ISAR0_SM4_IMPL (0x1ul << ID_AA64ISAR0_SM4_SHIFT) 264#define ID_AA64ISAR0_DP_SHIFT 44 265#define ID_AA64ISAR0_DP_MASK (0xful << ID_AA64ISAR0_DP_SHIFT) 266#define ID_AA64ISAR0_DP(x) ((x) & ID_AA64ISAR0_DP_MASK) 267#define ID_AA64ISAR0_DP_NONE (0x0ul << ID_AA64ISAR0_DP_SHIFT) 268#define ID_AA64ISAR0_DP_IMPL (0x1ul << ID_AA64ISAR0_DP_SHIFT) 269 270/* ID_AA64ISAR1_EL1 */ 271#define ID_AA64ISAR1_MASK 0xffffffff 272#define ID_AA64ISAR1_DPB_SHIFT 0 273#define ID_AA64ISAR1_DPB_MASK (0xf << ID_AA64ISAR1_DPB_SHIFT) 274#define ID_AA64ISAR1_DPB(x) ((x) & ID_AA64ISAR1_DPB_MASK) 275#define ID_AA64ISAR1_DPB_NONE (0x0 << ID_AA64ISAR1_DPB_SHIFT) 276#define ID_AA64ISAR1_DPB_IMPL (0x1 << ID_AA64ISAR1_DPB_SHIFT) 277#define ID_AA64ISAR1_APA_SHIFT 4 278#define ID_AA64ISAR1_APA_MASK (0xf << ID_AA64ISAR1_APA_SHIFT) 279#define ID_AA64ISAR1_APA(x) ((x) & ID_AA64ISAR1_APA_MASK) 280#define ID_AA64ISAR1_APA_NONE (0x0 << ID_AA64ISAR1_APA_SHIFT) 281#define ID_AA64ISAR1_APA_IMPL (0x1 << ID_AA64ISAR1_APA_SHIFT) 282#define ID_AA64ISAR1_API_SHIFT 8 283#define ID_AA64ISAR1_API_MASK (0xf << ID_AA64ISAR1_API_SHIFT) 284#define ID_AA64ISAR1_API(x) ((x) & ID_AA64ISAR1_API_MASK) 285#define ID_AA64ISAR1_API_NONE (0x0 << ID_AA64ISAR1_API_SHIFT) 286#define ID_AA64ISAR1_API_IMPL (0x1 << ID_AA64ISAR1_API_SHIFT) 287#define ID_AA64ISAR1_JSCVT_SHIFT 12 288#define ID_AA64ISAR1_JSCVT_MASK (0xf << ID_AA64ISAR1_JSCVT_SHIFT) 289#define ID_AA64ISAR1_JSCVT(x) ((x) & ID_AA64ISAR1_JSCVT_MASK) 290#define ID_AA64ISAR1_JSCVT_NONE (0x0 << ID_AA64ISAR1_JSCVT_SHIFT) 291#define ID_AA64ISAR1_JSCVT_IMPL (0x1 << ID_AA64ISAR1_JSCVT_SHIFT) 292#define ID_AA64ISAR1_FCMA_SHIFT 16 293#define ID_AA64ISAR1_FCMA_MASK (0xf << ID_AA64ISAR1_FCMA_SHIFT) 294#define ID_AA64ISAR1_FCMA(x) ((x) & ID_AA64ISAR1_FCMA_MASK) 295#define ID_AA64ISAR1_FCMA_NONE (0x0 << ID_AA64ISAR1_FCMA_SHIFT) 296#define ID_AA64ISAR1_FCMA_IMPL (0x1 << ID_AA64ISAR1_FCMA_SHIFT) 297#define ID_AA64ISAR1_LRCPC_SHIFT 20 298#define ID_AA64ISAR1_LRCPC_MASK (0xf << ID_AA64ISAR1_LRCPC_SHIFT) 299#define ID_AA64ISAR1_LRCPC(x) ((x) & ID_AA64ISAR1_LRCPC_MASK) 300#define ID_AA64ISAR1_LRCPC_NONE (0x0 << ID_AA64ISAR1_LRCPC_SHIFT) 301#define ID_AA64ISAR1_LRCPC_IMPL (0x1 << ID_AA64ISAR1_LRCPC_SHIFT) 302#define ID_AA64ISAR1_GPA_SHIFT 24 303#define ID_AA64ISAR1_GPA_MASK (0xf << ID_AA64ISAR1_GPA_SHIFT) 304#define ID_AA64ISAR1_GPA(x) ((x) & ID_AA64ISAR1_GPA_MASK) 305#define ID_AA64ISAR1_GPA_NONE (0x0 << ID_AA64ISAR1_GPA_SHIFT) 306#define ID_AA64ISAR1_GPA_IMPL (0x1 << ID_AA64ISAR1_GPA_SHIFT) 307#define ID_AA64ISAR1_GPI_SHIFT 28 308#define ID_AA64ISAR1_GPI_MASK (0xf << ID_AA64ISAR1_GPI_SHIFT) 309#define ID_AA64ISAR1_GPI(x) ((x) & ID_AA64ISAR1_GPI_MASK) 310#define ID_AA64ISAR1_GPI_NONE (0x0 << ID_AA64ISAR1_GPI_SHIFT) 311#define ID_AA64ISAR1_GPI_IMPL (0x1 << ID_AA64ISAR1_GPI_SHIFT) 312 313/* ID_AA64MMFR0_EL1 */ 314#define ID_AA64MMFR0_MASK 0xffffffff 315#define ID_AA64MMFR0_PA_RANGE_SHIFT 0 316#define ID_AA64MMFR0_PA_RANGE_MASK (0xf << ID_AA64MMFR0_PA_RANGE_SHIFT) 317#define ID_AA64MMFR0_PA_RANGE(x) ((x) & ID_AA64MMFR0_PA_RANGE_MASK) 318#define ID_AA64MMFR0_PA_RANGE_4G (0x0 << ID_AA64MMFR0_PA_RANGE_SHIFT) 319#define ID_AA64MMFR0_PA_RANGE_64G (0x1 << ID_AA64MMFR0_PA_RANGE_SHIFT) 320#define ID_AA64MMFR0_PA_RANGE_1T (0x2 << ID_AA64MMFR0_PA_RANGE_SHIFT) 321#define ID_AA64MMFR0_PA_RANGE_4T (0x3 << ID_AA64MMFR0_PA_RANGE_SHIFT) 322#define ID_AA64MMFR0_PA_RANGE_16T (0x4 << ID_AA64MMFR0_PA_RANGE_SHIFT) 323#define ID_AA64MMFR0_PA_RANGE_256T (0x5 << ID_AA64MMFR0_PA_RANGE_SHIFT) 324#define ID_AA64MMFR0_PA_RANGE_4P (0x6 << ID_AA64MMFR0_PA_RANGE_SHIFT) 325#define ID_AA64MMFR0_ASID_BITS_SHIFT 4 326#define ID_AA64MMFR0_ASID_BITS_MASK (0xf << ID_AA64MMFR0_ASID_BITS_SHIFT) 327#define ID_AA64MMFR0_ASID_BITS(x) ((x) & ID_AA64MMFR0_ASID_BITS_MASK) 328#define ID_AA64MMFR0_ASID_BITS_8 (0x0 << ID_AA64MMFR0_ASID_BITS_SHIFT) 329#define ID_AA64MMFR0_ASID_BITS_16 (0x2 << ID_AA64MMFR0_ASID_BITS_SHIFT) 330#define ID_AA64MMFR0_BIGEND_SHIFT 8 331#define ID_AA64MMFR0_BIGEND_MASK (0xf << ID_AA64MMFR0_BIGEND_SHIFT) 332#define ID_AA64MMFR0_BIGEND(x) ((x) & ID_AA64MMFR0_BIGEND_MASK) 333#define ID_AA64MMFR0_BIGEND_FIXED (0x0 << ID_AA64MMFR0_BIGEND_SHIFT) 334#define ID_AA64MMFR0_BIGEND_MIXED (0x1 << ID_AA64MMFR0_BIGEND_SHIFT) 335#define ID_AA64MMFR0_S_NS_MEM_SHIFT 12 336#define ID_AA64MMFR0_S_NS_MEM_MASK (0xf << ID_AA64MMFR0_S_NS_MEM_SHIFT) 337#define ID_AA64MMFR0_S_NS_MEM(x) ((x) & ID_AA64MMFR0_S_NS_MEM_MASK) 338#define ID_AA64MMFR0_S_NS_MEM_NONE (0x0 << ID_AA64MMFR0_S_NS_MEM_SHIFT) 339#define ID_AA64MMFR0_S_NS_MEM_DISTINCT (0x1 << ID_AA64MMFR0_S_NS_MEM_SHIFT) 340#define ID_AA64MMFR0_BIGEND_EL0_SHIFT 16 341#define ID_AA64MMFR0_BIGEND_EL0_MASK (0xf << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 342#define ID_AA64MMFR0_BIGEND_EL0(x) ((x) & ID_AA64MMFR0_BIGEND_EL0_MASK) 343#define ID_AA64MMFR0_BIGEND_EL0_FIXED (0x0 << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 344#define ID_AA64MMFR0_BIGEND_EL0_MIXED (0x1 << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 345#define ID_AA64MMFR0_TGRAN16_SHIFT 20 346#define ID_AA64MMFR0_TGRAN16_MASK (0xf << ID_AA64MMFR0_TGRAN16_SHIFT) 347#define ID_AA64MMFR0_TGRAN16(x) ((x) & ID_AA64MMFR0_TGRAN16_MASK) 348#define ID_AA64MMFR0_TGRAN16_NONE (0x0 << ID_AA64MMFR0_TGRAN16_SHIFT) 349#define ID_AA64MMFR0_TGRAN16_IMPL (0x1 << ID_AA64MMFR0_TGRAN16_SHIFT) 350#define ID_AA64MMFR0_TGRAN64_SHIFT 24 351#define ID_AA64MMFR0_TGRAN64_MASK (0xf << ID_AA64MMFR0_TGRAN64_SHIFT) 352#define ID_AA64MMFR0_TGRAN64(x) ((x) & ID_AA64MMFR0_TGRAN64_MASK) 353#define ID_AA64MMFR0_TGRAN64_IMPL (0x0 << ID_AA64MMFR0_TGRAN64_SHIFT) 354#define ID_AA64MMFR0_TGRAN64_NONE (0xf << ID_AA64MMFR0_TGRAN64_SHIFT) 355#define ID_AA64MMFR0_TGRAN4_SHIFT 28 356#define ID_AA64MMFR0_TGRAN4_MASK (0xf << ID_AA64MMFR0_TGRAN4_SHIFT) 357#define ID_AA64MMFR0_TGRAN4(x) ((x) & ID_AA64MMFR0_TGRAN4_MASK) 358#define ID_AA64MMFR0_TGRAN4_IMPL (0x0 << ID_AA64MMFR0_TGRAN4_SHIFT) 359#define ID_AA64MMFR0_TGRAN4_NONE (0xf << ID_AA64MMFR0_TGRAN4_SHIFT) 360 361/* ID_AA64MMFR1_EL1 */ 362#define ID_AA64MMFR1_MASK 0xffffffff 363#define ID_AA64MMFR1_HAFDBS_SHIFT 0 364#define ID_AA64MMFR1_HAFDBS_MASK (0xf << ID_AA64MMFR1_HAFDBS_SHIFT) 365#define ID_AA64MMFR1_HAFDBS(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) 366#define ID_AA64MMFR1_HAFDBS_NONE (0x0 << ID_AA64MMFR1_HAFDBS_SHIFT) 367#define ID_AA64MMFR1_HAFDBS_AF (0x1 << ID_AA64MMFR1_HAFDBS_SHIFT) 368#define ID_AA64MMFR1_HAFDBS_AF_DBS (0x2 << ID_AA64MMFR1_HAFDBS_SHIFT) 369#define ID_AA64MMFR1_VMIDBITS_SHIFT 4 370#define ID_AA64MMFR1_VMIDBITS_MASK (0xf << ID_AA64MMFR1_VMIDBITS_SHIFT) 371#define ID_AA64MMFR1_VMIDBITS(x) ((x) & ID_AA64MMFR1_VMIDBITS_MASK) 372#define ID_AA64MMFR1_VMIDBITS_8 (0x0 << ID_AA64MMFR1_VMIDBITS_SHIFT) 373#define ID_AA64MMFR1_VMIDBITS_16 (0x2 << ID_AA64MMFR1_VMIDBITS_SHIFT) 374#define ID_AA64MMFR1_VH_SHIFT 8 375#define ID_AA64MMFR1_VH_MASK (0xf << ID_AA64MMFR1_VH_SHIFT) 376#define ID_AA64MMFR1_VH(x) ((x) & ID_AA64MMFR1_VH_MASK) 377#define ID_AA64MMFR1_VH_NONE (0x0 << ID_AA64MMFR1_VH_SHIFT) 378#define ID_AA64MMFR1_VH_IMPL (0x1 << ID_AA64MMFR1_VH_SHIFT) 379#define ID_AA64MMFR1_HPDS_SHIFT 12 380#define ID_AA64MMFR1_HPDS_MASK (0xf << ID_AA64MMFR1_HPDS_SHIFT) 381#define ID_AA64MMFR1_HPDS(x) ((x) & ID_AA64MMFR1_HPDS_MASK) 382#define ID_AA64MMFR1_HPDS_NONE (0x0 << ID_AA64MMFR1_HPDS_SHIFT) 383#define ID_AA64MMFR1_HPDS_HPD (0x1 << ID_AA64MMFR1_HPDS_SHIFT) 384#define ID_AA64MMFR1_HPDS_TTPBHA (0x2 << ID_AA64MMFR1_HPDS_SHIFT) 385#define ID_AA64MMFR1_LO_SHIFT 16 386#define ID_AA64MMFR1_LO_MASK (0xf << ID_AA64MMFR1_LO_SHIFT) 387#define ID_AA64MMFR1_LO(x) ((x) & ID_AA64MMFR1_LO_MASK) 388#define ID_AA64MMFR1_LO_NONE (0x0 << ID_AA64MMFR1_LO_SHIFT) 389#define ID_AA64MMFR1_LO_IMPL (0x1 << ID_AA64MMFR1_LO_SHIFT) 390#define ID_AA64MMFR1_PAN_SHIFT 20 391#define ID_AA64MMFR1_PAN_MASK (0xf << ID_AA64MMFR1_PAN_SHIFT) 392#define ID_AA64MMFR1_PAN(x) ((x) & ID_AA64MMFR1_PAN_MASK) 393#define ID_AA64MMFR1_PAN_NONE (0x0 << ID_AA64MMFR1_PAN_SHIFT) 394#define ID_AA64MMFR1_PAN_IMPL (0x1 << ID_AA64MMFR1_PAN_SHIFT) 395#define ID_AA64MMFR1_PAN_ATS1E1 (0x2 << ID_AA64MMFR1_PAN_SHIFT) 396#define ID_AA64MMFR1_SPEC_SEI_SHIFT 24 397#define ID_AA64MMFR1_SPEC_SEI_MASK (0xf << ID_AA64MMFR1_SPEC_SEI_SHIFT) 398#define ID_AA64MMFR1_SPEC_SEI(x) ((x) & ID_AA64MMFR1_SPEC_SEI_MASK) 399#define ID_AA64MMFR1_SPEC_SEI_NONE (0x0 << ID_AA64MMFR1_SPEC_SEI_SHIFT) 400#define ID_AA64MMFR1_SPEC_SEI_IMPL (0x1 << ID_AA64MMFR1_SPEC_SEI_SHIFT) 401#define ID_AA64MMFR1_XNX_SHIFT 28 402#define ID_AA64MMFR1_XNX_MASK (0xf << ID_AA64MMFR1_XNX_SHIFT) 403#define ID_AA64MMFR1_XNX(x) ((x) & ID_AA64MMFR1_XNX_MASK) 404#define ID_AA64MMFR1_XNX_NONE (0x0 << ID_AA64MMFR1_XNX_SHIFT) 405#define ID_AA64MMFR1_XNX_IMPL (0x1 << ID_AA64MMFR1_XNX_SHIFT) 406 407/* ID_AA64MMFR2_EL1 */ 408#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 409#define ID_AA64MMFR2_MASK 0x0fffffff 410#define ID_AA64MMFR2_CNP_SHIFT 0 411#define ID_AA64MMFR2_CNP_MASK (0xf << ID_AA64MMFR2_CNP_SHIFT) 412#define ID_AA64MMFR2_CNP(x) ((x) & ID_AA64MMFR2_CNP_MASK) 413#define ID_AA64MMFR2_CNP_NONE (0x0 << ID_AA64MMFR2_CNP_SHIFT) 414#define ID_AA64MMFR2_CNP_IMPL (0x1 << ID_AA64MMFR2_CNP_SHIFT) 415#define ID_AA64MMFR2_UAO_SHIFT 4 416#define ID_AA64MMFR2_UAO_MASK (0xf << ID_AA64MMFR2_UAO_SHIFT) 417#define ID_AA64MMFR2_UAO(x) ((x) & ID_AA64MMFR2_UAO_MASK) 418#define ID_AA64MMFR2_UAO_NONE (0x0 << ID_AA64MMFR2_UAO_SHIFT) 419#define ID_AA64MMFR2_UAO_IMPL (0x1 << ID_AA64MMFR2_UAO_SHIFT) 420#define ID_AA64MMFR2_LSM_SHIFT 8 421#define ID_AA64MMFR2_LSM_MASK (0xf << ID_AA64MMFR2_LSM_SHIFT) 422#define ID_AA64MMFR2_LSM(x) ((x) & ID_AA64MMFR2_LSM_MASK) 423#define ID_AA64MMFR2_LSM_NONE (0x0 << ID_AA64MMFR2_LSM_SHIFT) 424#define ID_AA64MMFR2_LSM_IMPL (0x1 << ID_AA64MMFR2_LSM_SHIFT) 425#define ID_AA64MMFR2_IESB_SHIFT 12 426#define ID_AA64MMFR2_IESB_MASK (0xf << ID_AA64MMFR2_IESB_SHIFT) 427#define ID_AA64MMFR2_IESB(x) ((x) & ID_AA64MMFR2_IESB_MASK) 428#define ID_AA64MMFR2_IESB_NONE (0x0 << ID_AA64MMFR2_IESB_SHIFT) 429#define ID_AA64MMFR2_IESB_IMPL (0x1 << ID_AA64MMFR2_IESB_SHIFT) 430#define ID_AA64MMFR2_VA_RANGE_SHIFT 16 431#define ID_AA64MMFR2_VA_RANGE_MASK (0xf << ID_AA64MMFR2_VA_RANGE_SHIFT) 432#define ID_AA64MMFR2_VA_RANGE(x) ((x) & ID_AA64MMFR2_VA_RANGE_MASK) 433#define ID_AA64MMFR2_VA_RANGE_48 (0x0 << ID_AA64MMFR2_VA_RANGE_SHIFT) 434#define ID_AA64MMFR2_VA_RANGE_52 (0x1 << ID_AA64MMFR2_VA_RANGE_SHIFT) 435#define ID_AA64MMFR2_CCIDX_SHIFT 20 436#define ID_AA64MMFR2_CCIDX_MASK (0xf << ID_AA64MMFR2_CCIDX_SHIFT) 437#define ID_AA64MMFR2_CCIDX(x) ((x) & ID_AA64MMFR2_CCIDX_MASK) 438#define ID_AA64MMFR2_CCIDX_32 (0x0 << ID_AA64MMFR2_CCIDX_SHIFT) 439#define ID_AA64MMFR2_CCIDX_64 (0x1 << ID_AA64MMFR2_CCIDX_SHIFT) 440#define ID_AA64MMFR2_NV_SHIFT 24 441#define ID_AA64MMFR2_NV_MASK (0xf << ID_AA64MMFR2_NV_SHIFT) 442#define ID_AA64MMFR2_NV(x) ((x) & ID_AA64MMFR2_NV_MASK) 443#define ID_AA64MMFR2_NV_NONE (0x0 << ID_AA64MMFR2_NV_SHIFT) 444#define ID_AA64MMFR2_NV_IMPL (0x1 << ID_AA64MMFR2_NV_SHIFT) 445 446/* ID_AA64PFR0_EL1 */ 447#define ID_AA64PFR0_MASK 0x0000000ffffffffful 448#define ID_AA64PFR0_EL0_SHIFT 0 449#define ID_AA64PFR0_EL0_MASK (0xf << ID_AA64PFR0_EL0_SHIFT) 450#define ID_AA64PFR0_EL0(x) ((x) & ID_AA64PFR0_EL0_MASK) 451#define ID_AA64PFR0_EL0_64 (1 << ID_AA64PFR0_EL0_SHIFT) 452#define ID_AA64PFR0_EL0_64_32 (2 << ID_AA64PFR0_EL0_SHIFT) 453#define ID_AA64PFR0_EL1_SHIFT 4 454#define ID_AA64PFR0_EL1_MASK (0xf << ID_AA64PFR0_EL1_SHIFT) 455#define ID_AA64PFR0_EL1(x) ((x) & ID_AA64PFR0_EL1_MASK) 456#define ID_AA64PFR0_EL1_64 (1 << ID_AA64PFR0_EL1_SHIFT) 457#define ID_AA64PFR0_EL1_64_32 (2 << ID_AA64PFR0_EL1_SHIFT) 458#define ID_AA64PFR0_EL2_SHIFT 8 459#define ID_AA64PFR0_EL2_MASK (0xf << ID_AA64PFR0_EL2_SHIFT) 460#define ID_AA64PFR0_EL2(x) ((x) & ID_AA64PFR0_EL2_MASK) 461#define ID_AA64PFR0_EL2_NONE (0 << ID_AA64PFR0_EL2_SHIFT) 462#define ID_AA64PFR0_EL2_64 (1 << ID_AA64PFR0_EL2_SHIFT) 463#define ID_AA64PFR0_EL2_64_32 (2 << ID_AA64PFR0_EL2_SHIFT) 464#define ID_AA64PFR0_EL3_SHIFT 12 465#define ID_AA64PFR0_EL3_MASK (0xf << ID_AA64PFR0_EL3_SHIFT) 466#define ID_AA64PFR0_EL3(x) ((x) & ID_AA64PFR0_EL3_MASK) 467#define ID_AA64PFR0_EL3_NONE (0 << ID_AA64PFR0_EL3_SHIFT) 468#define ID_AA64PFR0_EL3_64 (1 << ID_AA64PFR0_EL3_SHIFT) 469#define ID_AA64PFR0_EL3_64_32 (2 << ID_AA64PFR0_EL3_SHIFT) 470#define ID_AA64PFR0_FP_SHIFT 16 471#define ID_AA64PFR0_FP_MASK (0xf << ID_AA64PFR0_FP_SHIFT) 472#define ID_AA64PFR0_FP(x) ((x) & ID_AA64PFR0_FP_MASK) 473#define ID_AA64PFR0_FP_IMPL (0x0 << ID_AA64PFR0_FP_SHIFT) 474#define ID_AA64PFR0_FP_HP (0x1 << ID_AA64PFR0_FP_SHIFT) 475#define ID_AA64PFR0_FP_NONE (0xf << ID_AA64PFR0_FP_SHIFT) 476#define ID_AA64PFR0_ADV_SIMD_SHIFT 20 477#define ID_AA64PFR0_ADV_SIMD_MASK (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT) 478#define ID_AA64PFR0_ADV_SIMD(x) ((x) & ID_AA64PFR0_ADV_SIMD_MASK) 479#define ID_AA64PFR0_ADV_SIMD_IMPL (0x0 << ID_AA64PFR0_ADV_SIMD_SHIFT) 480#define ID_AA64PFR0_ADV_SIMD_HP (0x1 << ID_AA64PFR0_ADV_SIMD_SHIFT) 481#define ID_AA64PFR0_ADV_SIMD_NONE (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT) 482#define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ 483#define ID_AA64PFR0_GIC_SHIFT 24 484#define ID_AA64PFR0_GIC_MASK (0xf << ID_AA64PFR0_GIC_SHIFT) 485#define ID_AA64PFR0_GIC(x) ((x) & ID_AA64PFR0_GIC_MASK) 486#define ID_AA64PFR0_GIC_CPUIF_NONE (0x0 << ID_AA64PFR0_GIC_SHIFT) 487#define ID_AA64PFR0_GIC_CPUIF_EN (0x1 << ID_AA64PFR0_GIC_SHIFT) 488#define ID_AA64PFR0_RAS_SHIFT 28 489#define ID_AA64PFR0_RAS_MASK (0xf << ID_AA64PFR0_RAS_SHIFT) 490#define ID_AA64PFR0_RAS(x) ((x) & ID_AA64PFR0_RAS_MASK) 491#define ID_AA64PFR0_RAS_NONE (0x0 << ID_AA64PFR0_RAS_SHIFT) 492#define ID_AA64PFR0_RAS_V1 (0x1 << ID_AA64PFR0_RAS_SHIFT) 493#define ID_AA64PFR0_SVE_SHIFT 32 494#define ID_AA64PFR0_SVE_MASK (0xful << ID_AA64PFR0_SVE_SHIFT) 495#define ID_AA64PFR0_SVE(x) ((x) & ID_AA64PFR0_SVE_MASK) 496#define ID_AA64PFR0_SVE_NONE (0x0ul << ID_AA64PFR0_SVE_SHIFT) 497#define ID_AA64PFR0_SVE_IMPL (0x1ul << ID_AA64PFR0_SVE_SHIFT) 498 499/* MAIR_EL1 - Memory Attribute Indirection Register */ 500#define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) 501#define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) 502#define MAIR_DEVICE_nGnRnE 0x00 503#define MAIR_DEVICE_nGnRE 0x04 504#define MAIR_NORMAL_NC 0x44 505#define MAIR_NORMAL_WT 0xbb 506#define MAIR_NORMAL_WB 0xff 507 508/* PAR_EL1 - Physical Address Register */ 509#define PAR_F_SHIFT 0 510#define PAR_F (0x1 << PAR_F_SHIFT) 511#define PAR_SUCCESS(x) (((x) & PAR_F) == 0) 512/* When PAR_F == 0 (success) */ 513#define PAR_SH_SHIFT 7 514#define PAR_SH_MASK (0x3 << PAR_SH_SHIFT) 515#define PAR_NS_SHIFT 9 516#define PAR_NS_MASK (0x3 << PAR_NS_SHIFT) 517#define PAR_PA_SHIFT 12 518#define PAR_PA_MASK 0x0000fffffffff000 519#define PAR_ATTR_SHIFT 56 520#define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT) 521/* When PAR_F == 1 (aborted) */ 522#define PAR_FST_SHIFT 1 523#define PAR_FST_MASK (0x3f << PAR_FST_SHIFT) 524#define PAR_PTW_SHIFT 8 525#define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT) 526#define PAR_S_SHIFT 9 527#define PAR_S_MASK (0x1 << PAR_S_SHIFT) 528 529/* SCTLR_EL1 - System Control Register */ 530#define SCTLR_RES0 0xc8222440 /* Reserved ARMv8.0, write 0 */ 531#define SCTLR_RES1 0x30d00800 /* Reserved ARMv8.0, write 1 */ 532 533#define SCTLR_M 0x00000001 534#define SCTLR_A 0x00000002 535#define SCTLR_C 0x00000004 536#define SCTLR_SA 0x00000008 537#define SCTLR_SA0 0x00000010 538#define SCTLR_CP15BEN 0x00000020 539/* Bit 6 is reserved */ 540#define SCTLR_ITD 0x00000080 541#define SCTLR_SED 0x00000100 542#define SCTLR_UMA 0x00000200 543/* Bit 10 is reserved */ 544/* Bit 11 is reserved */ 545#define SCTLR_I 0x00001000 546#define SCTLR_EnDB 0x00002000 /* ARMv8.3 */ 547#define SCTLR_DZE 0x00004000 548#define SCTLR_UCT 0x00008000 549#define SCTLR_nTWI 0x00010000 550/* Bit 17 is reserved */ 551#define SCTLR_nTWE 0x00040000 552#define SCTLR_WXN 0x00080000 553/* Bit 20 is reserved */ 554#define SCTLR_IESB 0x00200000 /* ARMv8.2 */ 555/* Bit 22 is reserved */ 556#define SCTLR_SPAN 0x00800000 /* ARMv8.1 */ 557#define SCTLR_EOE 0x01000000 558#define SCTLR_EE 0x02000000 559#define SCTLR_UCI 0x04000000 560#define SCTLR_EnDA 0x08000000 /* ARMv8.3 */ 561#define SCTLR_nTLSMD 0x10000000 /* ARMv8.2 */ 562#define SCTLR_LSMAOE 0x20000000 /* ARMv8.2 */ 563#define SCTLR_EnIB 0x40000000 /* ARMv8.3 */ 564#define SCTLR_EnIA 0x80000000 /* ARMv8.3 */ 565 566/* SPSR_EL1 */ 567/* 568 * When the exception is taken in AArch64: 569 * M[3:2] is the exception level 570 * M[1] is unused 571 * M[0] is the SP select: 572 * 0: always SP0 573 * 1: current ELs SP 574 */ 575#define PSR_M_EL0t 0x00000000 576#define PSR_M_EL1t 0x00000004 577#define PSR_M_EL1h 0x00000005 578#define PSR_M_EL2t 0x00000008 579#define PSR_M_EL2h 0x00000009 580#define PSR_M_64 0x00000000 581#define PSR_M_32 0x00000010 582#define PSR_M_MASK 0x0000000f 583 584#define PSR_T 0x00000020 585 586#define PSR_AARCH32 0x00000010 587#define PSR_F 0x00000040 588#define PSR_I 0x00000080 589#define PSR_A 0x00000100 590#define PSR_D 0x00000200 591#define PSR_IL 0x00100000 592#define PSR_SS 0x00200000 593#define PSR_V 0x10000000 594#define PSR_C 0x20000000 595#define PSR_Z 0x40000000 596#define PSR_N 0x80000000 597#define PSR_FLAGS 0xf0000000 598 599/* TCR_EL1 - Translation Control Register */ 600#define TCR_ASID_16 (1 << 36) 601 602#define TCR_IPS_SHIFT 32 603#define TCR_IPS_32BIT (0 << TCR_IPS_SHIFT) 604#define TCR_IPS_36BIT (1 << TCR_IPS_SHIFT) 605#define TCR_IPS_40BIT (2 << TCR_IPS_SHIFT) 606#define TCR_IPS_42BIT (3 << TCR_IPS_SHIFT) 607#define TCR_IPS_44BIT (4 << TCR_IPS_SHIFT) 608#define TCR_IPS_48BIT (5 << TCR_IPS_SHIFT) 609 610#define TCR_TG1_SHIFT 30 611#define TCR_TG1_16K (1 << TCR_TG1_SHIFT) 612#define TCR_TG1_4K (2 << TCR_TG1_SHIFT) 613#define TCR_TG1_64K (3 << TCR_TG1_SHIFT) 614 615#define TCR_SH1_SHIFT 28 616#define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT) 617#define TCR_ORGN1_SHIFT 26 618#define TCR_ORGN1_WBWA (0x1UL << TCR_ORGN1_SHIFT) 619#define TCR_IRGN1_SHIFT 24 620#define TCR_IRGN1_WBWA (0x1UL << TCR_IRGN1_SHIFT) 621#define TCR_SH0_SHIFT 12 622#define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT) 623#define TCR_ORGN0_SHIFT 10 624#define TCR_ORGN0_WBWA (0x1UL << TCR_ORGN0_SHIFT) 625#define TCR_IRGN0_SHIFT 8 626#define TCR_IRGN0_WBWA (0x1UL << TCR_IRGN0_SHIFT) 627 628#define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\ 629 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)) 630 631#define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS) 632 633#define TCR_T1SZ_SHIFT 16 634#define TCR_T0SZ_SHIFT 0 635#define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) 636#define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) 637#define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) 638 639/* Saved Program Status Register */ 640#define DBG_SPSR_SS (0x1 << 21) 641 642/* Monitor Debug System Control Register */ 643#define DBG_MDSCR_SS (0x1 << 0) 644#define DBG_MDSCR_KDE (0x1 << 13) 645#define DBG_MDSCR_MDE (0x1 << 15) 646 647/* Perfomance Monitoring Counters */ 648#define PMCR_E (1 << 0) /* Enable all counters */ 649#define PMCR_P (1 << 1) /* Reset all counters */ 650#define PMCR_C (1 << 2) /* Clock counter reset */ 651#define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ 652#define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ 653#define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ 654#define PMCR_LC (1 << 6) /* Long cycle count enable */ 655#define PMCR_IMP_SHIFT 24 /* Implementer code */ 656#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) 657#define PMCR_IDCODE_SHIFT 16 /* Identification code */ 658#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) 659#define PMCR_IDCODE_CORTEX_A57 0x01 660#define PMCR_IDCODE_CORTEX_A72 0x02 661#define PMCR_IDCODE_CORTEX_A53 0x03 662#define PMCR_N_SHIFT 11 /* Number of counters implemented */ 663#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) 664 665#endif /* !_MACHINE_ARMREG_H_ */ 666