1/*-
2 * Copyright (c) 2013, 2014 Andrew Turner
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29#ifndef _MACHINE_HYPERVISOR_H_
30#define _MACHINE_HYPERVISOR_H_
31
32/*
33 * These registers are only useful when in hypervisor context,
34 * e.g. specific to EL2, or controlling the hypervisor.
35 */
36
37/*
38 * Architecture feature trap register
39 */
40#define	CPTR_RES0	0x7fefc800
41#define	CPTR_RES1	0x000033ff
42#define	CPTR_TFP	0x00000400
43#define	CPTR_TTA	0x00100000
44#define	CPTR_TCPAC	0x80000000
45
46/*
47 * Hypervisor Config Register
48 */
49
50#define	HCR_VM		0x0000000000000001
51#define	HCR_SWIO	0x0000000000000002
52#define	HCR_PTW		0x0000000000000004
53#define	HCR_FMO		0x0000000000000008
54#define	HCR_IMO		0x0000000000000010
55#define	HCR_AMO		0x0000000000000020
56#define	HCR_VF		0x0000000000000040
57#define	HCR_VI		0x0000000000000080
58#define	HCR_VSE		0x0000000000000100
59#define	HCR_FB		0x0000000000000200
60#define	HCR_BSU_MASK	0x0000000000000c00
61#define	HCR_DC		0x0000000000001000
62#define	HCR_TWI		0x0000000000002000
63#define	HCR_TWE		0x0000000000004000
64#define	HCR_TID0	0x0000000000008000
65#define	HCR_TID1	0x0000000000010000
66#define	HCR_TID2	0x0000000000020000
67#define	HCR_TID3	0x0000000000040000
68#define	HCR_TSC		0x0000000000080000
69#define	HCR_TIDCP	0x0000000000100000
70#define	HCR_TACR	0x0000000000200000
71#define	HCR_TSW		0x0000000000400000
72#define	HCR_TPC		0x0000000000800000
73#define	HCR_TPU		0x0000000001000000
74#define	HCR_TTLB	0x0000000002000000
75#define	HCR_TVM		0x0000000004000000
76#define	HCR_TGE		0x0000000008000000
77#define	HCR_TDZ		0x0000000010000000
78#define	HCR_HCD		0x0000000020000000
79#define	HCR_TRVM	0x0000000040000000
80#define	HCR_RW		0x0000000080000000
81#define	HCR_CD		0x0000000100000000
82#define	HCR_ID		0x0000000200000000
83
84#endif
85
86