1/*
2 * Copyright (c) 2012-2015 Haiku, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files
6 * (the "Software"), to deal in the Software without restriction,
7 * including without limitation the rights to use, copy, modify, merge,
8 * publish, distribute, sublicense, and/or sell copies of the Software,
9 * and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 *		Alexander von Gluck, kallisti5@unixzen.com
25 */
26#ifndef __PLATFORM_BCM283X_H
27#define __PLATFORM_BCM283X_H
28
29
30#define SIZE_4K 0x00001000
31
32/*
33 * Found in:
34 * Broadcom BCM2835 ARM Peripherals
35 *  - BCM2835-ARM-Peripherals.pdf
36 */
37
38// Section 1.2.2
39// These board bases should go away when we start using FDT's
40// (all loader drivers compiled in, drivers chosen based on FDT)
41//
42#define BCM283X_SDRAM_BASE		0x00000000
43#define BCM2835_PERIPHERAL_BASE	0x20000000
44#define BCM2836_PERIPHERAL_BASE	0x3f000000
45
46
47// Added to physical addresses to select the different cache behaviours
48#define BCM283X_VIDEO_CORE_L1_L2_CACHED		(0 << 30)
49#define BCM283X_VIDEO_CORE_L2_COHERENT		(1 << 30)
50#define BCM283X_VIDEO_CORE_L2_CACHED		(2 << 30)
51#define BCM283X_VIDEO_CORE_UNCACHED			(3 << 30)
52
53// The highest two bits are used to select aliases to the physical memory
54// with different cache semantic. Clearing them converts the address to
55// physical memory as seen by ARM.
56#define BCM283X_BUS_TO_PHYSICAL(x)			(x & ~BCM283X_VIDEO_CORE_UNCACHED)
57
58
59#define ST_BASE			0x3000
60	// System Timer, sec 12.0, page 172
61#define DMA_BASE		0x7000
62	// DMA Controller, sec 4.2, page 39
63#define ARM_BASE		0xB000
64	// BCM283X ARM Control Block, sec 7.5, page 112
65#define PM_BASE			0x100000
66	// Power Management, Reset controller and Watchdog registers
67#define GPIO_BASE		0x200000
68	// GPIO, sec 6.1, page 90
69#define UART0_BASE		0x201000
70	// UART 0, sec 13.4, page 177
71#define MMCI0_BASE		0x202000
72	// MMC
73#define UART1_BASE		0x215000
74	// UART 1, sec 2.1, page 65
75#define EMMC_BASE		0x300000
76	// eMMC interface, sec 5, page 66
77#define SMI_BASE		0x600000
78	// SMI Base
79#define USB_BASE		0x980000
80	// USB Controller, 15.2, page 202
81// FB_BASE will depend on memory split
82
83
84// 7.5, page 112
85#define ARM_CTRL_BASE			(ARM_BASE + 0x000)
86#define ARM_CTRL_IC_BASa		(ARM_BASE + 0x200)
87	// Interrupt controller
88#define ARM_CTRL_TIMER0_1_BASE	(ARM_BASE + 0x400)
89	// Timer 0 and 1
90#define ARM_CTRL_0_SBM_BASE		(ARM_BASE + 0x800)
91	// ARM Semaphores, Doorbells, and Mailboxes
92
93
94/* UART */
95// TODO: Check these UART defines!
96#define UART_RHR    0
97#define UART_THR    0
98#define UART_DLL    0
99#define UART_IER    1
100#define UART_DLH    1
101#define UART_IIR    2
102#define UART_FCR    2
103#define UART_EFR    2
104#define UART_LCR    3
105#define UART_MCR    4
106#define UART_LSR    5
107#define UART_MSR    6
108#define UART_TCR    6
109#define UART_SPR    7
110#define UART_TLR    7
111#define UART_MDR1   8
112#define UART_MDR2   9
113#define UART_SFLSR  10
114#define UART_RESUME 11
115#define UART_TXFLL  10
116#define UART_TXFLH  11
117#define UART_SFREGL 12
118#define UART_SFREGH 13
119#define UART_RXFLL  12
120#define UART_RXFLH  13
121#define UART_BLR    14
122#define UART_UASR   14
123#define UART_ACREG  15
124#define UART_SCR    16
125#define UART_SSR    17
126#define UART_EBLR   18
127#define UART_MVR    19
128#define UART_SYSC   20
129
130
131/* Mailbox */
132#define ARM_CTRL_0_MAILBOX_BASE				(ARM_CTRL_0_SBM_BASE + 0x80)
133
134#define ARM_MAILBOX_READ					0x00
135#define ARM_MAILBOX_STATUS					0x18
136#define ARM_MAILBOX_WRITE					0x20
137
138#define ARM_MAILBOX_FULL					(1 << 31)
139#define ARM_MAILBOX_EMPTY					(1 << 30)
140
141#define ARM_MAILBOX_DATA_MASK				0xfffffff0
142#define ARM_MAILBOX_CHANNEL_MASK			0x0000000f
143
144#define ARM_MAILBOX_CHANNEL_FRAMEBUFFER		1
145
146#endif /* __PLATFORM_BCM283X_H */
147