1/* 2 * Copyright 2009 Advanced Micro Devices, Inc. 3 * Copyright 2009 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 * Alexander von Gluck <kallisti5@unixzen.com> 27 */ 28#ifndef __R700_REG_H__ 29#define __R700_REG_H__ 30 31 32/* Scratch Registers */ 33#define R700_SCRATCH_REG0 0x8500 34#define R700_SCRATCH_REG1 0x8504 35#define R700_SCRATCH_REG2 0x8508 36#define R700_SCRATCH_REG3 0x850C 37#define R700_SCRATCH_REG4 0x8510 38#define R700_SCRATCH_REG5 0x8514 39#define R700_SCRATCH_REG6 0x8518 40#define R700_SCRATCH_REG7 0x851C 41#define R700_SCRATCH_UMSK 0x8540 42#define R700_SCRATCH_ADDR 0x8544 43 44/* CRT controler register offset */ 45#define R700_CRTC0_REGISTER_OFFSET 0x0 46#define R700_CRTC1_REGISTER_OFFSET 0x800 47 48#define R700_MAX_SH_GPRS 256 49#define R700_MAX_TEMP_GPRS 16 50#define R700_MAX_SH_THREADS 256 51#define R700_MAX_SH_STACK_ENTRIES 4096 52#define R700_MAX_BACKENDS 8 53#define R700_MAX_BACKENDS_MASK 0xff 54#define R700_MAX_SIMDS 16 55#define R700_MAX_SIMDS_MASK 0xffff 56#define R700_MAX_PIPES 8 57#define R700_MAX_PIPES_MASK 0xff 58 59/* Registers */ 60#define R700_CB_COLOR0_BASE 0x28040 61#define R700_CB_COLOR1_BASE 0x28044 62#define R700_CB_COLOR2_BASE 0x28048 63#define R700_CB_COLOR3_BASE 0x2804C 64#define R700_CB_COLOR4_BASE 0x28050 65#define R700_CB_COLOR5_BASE 0x28054 66#define R700_CB_COLOR6_BASE 0x28058 67#define R700_CB_COLOR7_BASE 0x2805C 68#define R700_CB_COLOR7_FRAG 0x280FC 69 70#define R700_CC_GC_SHADER_PIPE_CONFIG 0x8950 71#define R700_CC_RB_BACKEND_DISABLE 0x98F4 72#define R700_BACKEND_DISABLE(x) ((x) << 16) 73#define R700_CC_SYS_RB_BACKEND_DISABLE 0x3F88 74 75#define R700_CGTS_SYS_TCC_DISABLE 0x3F90 76#define R700_CGTS_TCC_DISABLE 0x9148 77#define R700_CGTS_USER_SYS_TCC_DISABLE 0x3F94 78#define R700_CGTS_USER_TCC_DISABLE 0x914C 79 80#define R700_CP_ME_CNTL 0x86D8 81#define R700_CP_ME_HALT (1<<28) 82#define R700_CP_PFP_HALT (1<<26) 83#define R700_CP_ME_RAM_DATA 0xC160 84#define R700_CP_ME_RAM_RADDR 0xC158 85#define R700_CP_ME_RAM_WADDR 0xC15C 86#define R700_CP_MEQ_THRESHOLDS 0x8764 87#define STQ_SPLIT(x) ((x) << 0) 88#define R700_CP_PERFMON_CNTL 0x87FC 89#define R700_CP_PFP_UCODE_ADDR 0xC150 90#define R700_CP_PFP_UCODE_DATA 0xC154 91#define R700_CP_QUEUE_THRESHOLDS 0x8760 92#define R700_ROQ_IB1_START(x) ((x) << 0) 93#define R700_ROQ_IB2_START(x) ((x) << 8) 94#define R700_CP_DEBUG 0xC1FC 95#define R700_CP_RB_BASE 0xC100 96#define R700_CP_RB_CNTL 0xC104 97#define R700_RB_BUFSZ(x) ((x) << 0) 98#define R700_RB_BLKSZ(x) ((x) << 8) 99#define R700_RB_NO_UPDATE (1 << 27) 100#define R700_RB_RPTR_WR_ENA (1 << 31) 101#define R700_BUF_SWAP_32BIT (2 << 16) 102#define R700_CP_RB_RPTR 0x8700 103#define R700_CP_RB_RPTR_ADDR 0xC10C 104#define R700_CP_RB_RPTR_ADDR_HI 0xC110 105#define R700_CP_RB_RPTR_WR 0xC108 106#define R700_CP_RB_WPTR 0xC114 107#define R700_CP_RB_WPTR_ADDR 0xC118 108#define R700_CP_RB_WPTR_ADDR_HI 0xC11C 109#define R700_CP_RB_WPTR_DELAY 0x8704 110#define R700_CP_SEM_WAIT_TIMER 0x85BC 111 112#define R700_DB_DEBUG3 0x98B0 113#define R700_DB_CLK_OFF_DELAY(x) ((x) << 11) 114#define R700_DB_DEBUG 0x9B8C 115#define R700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) 116 117#define R700_DCP_TILING_CONFIG 0x6CA0 118#define R700_PIPE_TILING(x) ((x) << 1) 119#define R700_BANK_TILING(x) ((x) << 4) 120#define R700_GROUP_SIZE(x) ((x) << 6) 121#define R700_ROW_TILING(x) ((x) << 8) 122#define R700_BANK_SWAPS(x) ((x) << 11) 123#define R700_SAMPLE_SPLIT(x) ((x) << 14) 124#define R700_BACKEND_MAP(x) ((x) << 16) 125 126#define R700_GB_TILING_CONFIG 0x98F0 127 128#define R700_GC_USER_SHADER_PIPE_CONFIG 0x8954 129#define R700_INACTIVE_QD_PIPES(x) ((x) << 8) 130#define R700_INACTIVE_QD_PIPES_MASK 0x0000FF00 131#define R700_INACTIVE_SIMDS(x) ((x) << 16) 132#define R700_INACTIVE_SIMDS_MASK 0x00FF0000 133 134#define R700_GRBM_CNTL 0x8000 135#define R700_GRBM_READ_TIMEOUT(x) ((x) << 0) 136#define R700_GRBM_SOFT_RESET 0x8020 137#define R700_SOFT_RESET_CP (1<<0) 138#define R700_GRBM_STATUS 0x8010 139#define R700_CMDFIFO_AVAIL_MASK 0x0000000F 140#define R700_GUI_ACTIVE (1<<31) 141#define R700_GRBM_STATUS2 0x8014 142 143#define R700_CG_MULT_THERMAL_STATUS 0x740 144#define R700_ASIC_T(x) ((x) << 16) 145#define R700_ASIC_T_MASK 0x3FF0000 146#define R700_ASIC_T_SHIFT 16 147 148#define R700_HDP_HOST_PATH_CNTL 0x2C00 149#define R700_HDP_NONSURFACE_BASE 0x2C04 150#define R700_HDP_NONSURFACE_INFO 0x2C08 151#define R700_HDP_NONSURFACE_SIZE 0x2C0C 152#define R700_HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 153#define R700_HDP_TILING_CONFIG 0x2F3C 154#define R700_HDP_DEBUG1 0x2F34 155 156#define R700_MC_SHARED_CHMAP 0x2004 157#define R700_NOOFCHAN_SHIFT 12 158#define R700_NOOFCHAN_MASK 0x00003000 159#define R700_MC_SHARED_CHREMAP 0x2008 160 161#define R700_MC_ARB_RAMCFG 0x2760 162#define R700_NOOFBANK_SHIFT 0 163#define R700_NOOFBANK_MASK 0x00000003 164#define R700_NOOFRANK_SHIFT 2 165#define R700_NOOFRANK_MASK 0x00000004 166#define R700_NOOFROWS_SHIFT 3 167#define R700_NOOFROWS_MASK 0x00000038 168#define R700_NOOFCOLS_SHIFT 6 169#define R700_NOOFCOLS_MASK 0x000000C0 170#define R700_CHANSIZE_SHIFT 8 171#define R700_CHANSIZE_MASK 0x00000100 172#define R700_BURSTLENGTH_SHIFT 9 173#define R700_BURSTLENGTH_MASK 0x00000200 174#define R700_CHANSIZE_OVERRIDE (1 << 11) 175#define R700_MC_VM_AGP_TOP 0x2028 176#define R700_MC_VM_AGP_BOT 0x202C 177#define R700_MC_VM_AGP_BASE 0x2030 178#define R700_MC_VM_FB_LOCATION 0x2024 179#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234 180#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238 181#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223C 182#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240 183#define R700_ENABLE_L1_TLB (1 << 0) 184#define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 185#define R700_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 186#define R700_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 187#define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 188#define R700_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 189#define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 190#define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) 191#define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) 192#define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654 193#define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658 194#define R700_MC_VM_MD_L1_TLB2_CNTL 0x265C 195#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 196#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 197#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 198 199#define R700_PA_CL_ENHANCE 0x8A14 200#define R700_CLIP_VTX_REORDER_ENA (1 << 0) 201#define R700_NUM_CLIP_SEQ(x) ((x) << 1) 202#define R700_PA_SC_AA_CONFIG 0x28C04 203#define R700_PA_SC_CLIPRECT_RULE 0x2820C 204#define R700_PA_SC_EDGERULE 0x28230 205#define R700_PA_SC_FIFO_SIZE 0x8BCC 206#define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0) 207#define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 208#define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 209#define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0) 210#define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16) 211#define R700_PA_SC_LINE_STIPPLE 0x28A0C 212#define R700_PA_SC_LINE_STIPPLE_STATE 0x8B10 213#define R700_PA_SC_MODE_CNTL 0x28A4C 214#define R700_PA_SC_MULTI_CHIP_CNTL 0x8B20 215#define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 216 217#if 0 218#define SMX_DC_CTL0 0xA020 219#define USE_HASH_FUNCTION (1 << 0) 220#define CACHE_DEPTH(x) ((x) << 1) 221#define FLUSH_ALL_ON_EVENT (1 << 10) 222#define STALL_ON_EVENT (1 << 11) 223#define SMX_EVENT_CTL 0xA02C 224#define ES_FLUSH_CTL(x) ((x) << 0) 225#define GS_FLUSH_CTL(x) ((x) << 3) 226#define ACK_FLUSH_CTL(x) ((x) << 6) 227#define SYNC_FLUSH_CTL (1 << 8) 228 229#define SPI_CONFIG_CNTL 0x9100 230#define GPR_WRITE_PRIORITY(x) ((x) << 0) 231#define DISABLE_INTERP_1 (1 << 5) 232#define SPI_CONFIG_CNTL_1 0x913C 233#define VTX_DONE_DELAY(x) ((x) << 0) 234#define INTERP_ONE_PRIM_PER_ROW (1 << 4) 235#define SPI_INPUT_Z 0x286D8 236#define SPI_PS_IN_CONTROL_0 0x286CC 237#define NUM_INTERP(x) ((x)<<0) 238#define POSITION_ENA (1<<8) 239#define POSITION_CENTROID (1<<9) 240#define POSITION_ADDR(x) ((x)<<10) 241#define PARAM_GEN(x) ((x)<<15) 242#define PARAM_GEN_ADDR(x) ((x)<<19) 243#define BARYC_SAMPLE_CNTL(x) ((x)<<26) 244#define PERSP_GRADIENT_ENA (1<<28) 245#define LINEAR_GRADIENT_ENA (1<<29) 246#define POSITION_SAMPLE (1<<30) 247#define BARYC_AT_SAMPLE_ENA (1<<31) 248 249#define SQ_CONFIG 0x8C00 250#define VC_ENABLE (1 << 0) 251#define EXPORT_SRC_C (1 << 1) 252#define DX9_CONSTS (1 << 2) 253#define ALU_INST_PREFER_VECTOR (1 << 3) 254#define DX10_CLAMP (1 << 4) 255#define CLAUSE_SEQ_PRIO(x) ((x) << 8) 256#define PS_PRIO(x) ((x) << 24) 257#define VS_PRIO(x) ((x) << 26) 258#define GS_PRIO(x) ((x) << 28) 259#define SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8DB0 260#define SIMDA_RING0(x) ((x)<<0) 261#define SIMDA_RING1(x) ((x)<<8) 262#define SIMDB_RING0(x) ((x)<<16) 263#define SIMDB_RING1(x) ((x)<<24) 264#define SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8DB4 265#define SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8DB8 266#define SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8DBC 267#define SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8DC0 268#define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4 269#define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8 270#define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC 271#define ES_PRIO(x) ((x) << 30) 272#define SQ_GPR_RESOURCE_MGMT_1 0x8C04 273#define NUM_PS_GPRS(x) ((x) << 0) 274#define NUM_VS_GPRS(x) ((x) << 16) 275#define DYN_GPR_ENABLE (1 << 27) 276#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 277#define SQ_GPR_RESOURCE_MGMT_2 0x8C08 278#define NUM_GS_GPRS(x) ((x) << 0) 279#define NUM_ES_GPRS(x) ((x) << 16) 280#define SQ_MS_FIFO_SIZES 0x8CF0 281#define CACHE_FIFO_SIZE(x) ((x) << 0) 282#define FETCH_FIFO_HIWATER(x) ((x) << 8) 283#define DONE_FIFO_HIWATER(x) ((x) << 16) 284#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 285#define SQ_STACK_RESOURCE_MGMT_1 0x8C10 286#define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 287#define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 288#define SQ_STACK_RESOURCE_MGMT_2 0x8C14 289#define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 290#define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 291#define SQ_THREAD_RESOURCE_MGMT 0x8C0C 292#define NUM_PS_THREADS(x) ((x) << 0) 293#define NUM_VS_THREADS(x) ((x) << 8) 294#define NUM_GS_THREADS(x) ((x) << 16) 295#define NUM_ES_THREADS(x) ((x) << 24) 296 297#define SX_DEBUG_1 0x9058 298#define ENABLE_NEW_SMX_ADDRESS (1 << 16) 299#define SX_EXPORT_BUFFER_SIZES 0x900C 300#define COLOR_BUFFER_SIZE(x) ((x) << 0) 301#define POSITION_BUFFER_SIZE(x) ((x) << 8) 302#define SMX_BUFFER_SIZE(x) ((x) << 16) 303#define SX_MISC 0x28350 304 305#define TA_CNTL_AUX 0x9508 306#define DISABLE_CUBE_WRAP (1 << 0) 307#define DISABLE_CUBE_ANISO (1 << 1) 308#define SYNC_GRADIENT (1 << 24) 309#define SYNC_WALKER (1 << 25) 310#define SYNC_ALIGNER (1 << 26) 311#define BILINEAR_PRECISION_6_BIT (0 << 31) 312#define BILINEAR_PRECISION_8_BIT (1 << 31) 313 314#define TCP_CNTL 0x9610 315#define TCP_CHAN_STEER 0x9614 316 317#define VGT_CACHE_INVALIDATION 0x88C4 318#define CACHE_INVALIDATION(x) ((x)<<0) 319#define VC_ONLY 0 320#define TC_ONLY 1 321#define VC_AND_TC 2 322#define AUTO_INVLD_EN(x) ((x) << 6) 323#define NO_AUTO 0 324#define ES_AUTO 1 325#define GS_AUTO 2 326#define ES_AND_GS_AUTO 3 327#define VGT_ES_PER_GS 0x88CC 328#define VGT_GS_PER_ES 0x88C8 329#define VGT_GS_PER_VS 0x88E8 330#define VGT_GS_VERTEX_REUSE 0x88D4 331#define VGT_NUM_INSTANCES 0x8974 332#define VGT_OUT_DEALLOC_CNTL 0x28C5C 333#define DEALLOC_DIST_MASK 0x0000007F 334#define VGT_STRMOUT_EN 0x28AB0 335#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 336#define VTX_REUSE_DEPTH_MASK 0x000000FF 337 338#define VM_CONTEXT0_CNTL 0x1410 339#define ENABLE_CONTEXT (1 << 0) 340#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 341#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 342#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 343#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 344#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 345#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 346#define VM_L2_CNTL 0x1400 347#define ENABLE_L2_CACHE (1 << 0) 348#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 349#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 350#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 351#define VM_L2_CNTL2 0x1404 352#define INVALIDATE_ALL_L1_TLBS (1 << 0) 353#define INVALIDATE_L2_CACHE (1 << 1) 354#define VM_L2_CNTL3 0x1408 355#define BANK_SELECT(x) ((x) << 0) 356#define CACHE_UPDATE_MODE(x) ((x) << 6) 357#define VM_L2_STATUS 0x140C 358#define L2_BUSY (1 << 0) 359 360#define WAIT_UNTIL 0x8040 361 362#define SRBM_STATUS 0x0E50 363#endif 364 365#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 366#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 367#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 368#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 369#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c 370#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c 371 372/* PCIE link stuff */ 373#define R700_PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 374#define R700_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 375#define R700_LC_LINK_WIDTH_SHIFT 0 376#define R700_LC_LINK_WIDTH_MASK 0x7 377#define R700_LC_LINK_WIDTH_X0 0 378#define R700_LC_LINK_WIDTH_X1 1 379#define R700_LC_LINK_WIDTH_X2 2 380#define R700_LC_LINK_WIDTH_X4 3 381#define R700_LC_LINK_WIDTH_X8 4 382#define R700_LC_LINK_WIDTH_X16 6 383#define R700_LC_LINK_WIDTH_RD_SHIFT 4 384#define R700_LC_LINK_WIDTH_RD_MASK 0x70 385#define R700_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 386#define R700_LC_RECONFIG_NOW (1 << 8) 387#define R700_LC_RENEGOTIATION_SUPPORT (1 << 9) 388#define R700_LC_RENEGOTIATE_EN (1 << 10) 389#define R700_LC_SHORT_RECONFIG_EN (1 << 11) 390#define R700_LC_UPCONFIGURE_SUPPORT (1 << 12) 391#define R700_LC_UPCONFIGURE_DIS (1 << 13) 392#define R700_PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 393#define R700_LC_GEN2_EN_STRAP (1 << 0) 394#define R700_LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 395#define R700_LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 396#define R700_LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 397#define R700_LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 398#define R700_LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 399#define R700_LC_CURRENT_DATA_RATE (1 << 11) 400#define R700_LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 401#define R700_LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 402#define R700_LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 403#define R700_LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 404#define R700_MM_CFGREGS_CNTL 0x544c 405#define R700_MM_WR_TO_CFG_EN (1 << 3) 406#define R700_LINK_CNTL2 0x88 /* F0 */ 407#define R700_TARGET_LINK_SPEED_MASK (0xf << 0) 408#define R700_SELECTABLE_DEEMPHASIS (1 << 6) 409 410 411#endif /* __R700_REG_H__ */