1/* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23#ifndef _PPTABLE_H 24#define _PPTABLE_H 25 26#pragma pack(1) 27 28typedef struct _ATOM_PPLIB_THERMALCONTROLLER 29 30{ 31 UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_* 32 UCHAR ucI2cLine; // as interpreted by DAL I2C 33 UCHAR ucI2cAddress; 34 UCHAR ucFanParameters; // Fan Control Parameters. 35 UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only. 36 UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only. 37 UCHAR ucReserved; // ---- 38 UCHAR ucFlags; // to be defined 39} ATOM_PPLIB_THERMALCONTROLLER; 40 41#define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f 42#define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller. 43 44#define ATOM_PP_THERMALCONTROLLER_NONE 0 45#define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib 46#define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib 47#define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib 48#define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib 49#define ATOM_PP_THERMALCONTROLLER_LM64 5 50#define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib 51#define ATOM_PP_THERMALCONTROLLER_RV6xx 7 52#define ATOM_PP_THERMALCONTROLLER_RV770 8 53#define ATOM_PP_THERMALCONTROLLER_ADT7473 9 54#define ATOM_PP_THERMALCONTROLLER_KONG 10 55#define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11 56#define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12 57#define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen. 58#define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used internally 59#define ATOM_PP_THERMALCONTROLLER_NISLANDS 15 60#define ATOM_PP_THERMALCONTROLLER_SISLANDS 16 61#define ATOM_PP_THERMALCONTROLLER_LM96163 17 62#define ATOM_PP_THERMALCONTROLLER_CISLANDS 18 63#define ATOM_PP_THERMALCONTROLLER_KAVERI 19 64#define ATOM_PP_THERMALCONTROLLER_ICELAND 20 65#define ATOM_PP_THERMALCONTROLLER_TONGA 21 66#define ATOM_PP_THERMALCONTROLLER_FIJI 22 67#define ATOM_PP_THERMALCONTROLLER_POLARIS10 23 68#define ATOM_PP_THERMALCONTROLLER_VEGA10 24 69 70 71// Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal. 72// We probably should reserve the bit 0x80 for this use. 73// To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here). 74// The driver can pick the correct internal controller based on the ASIC. 75#define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller 76#define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal Thermal Controller 77 78typedef struct _ATOM_PPLIB_STATE 79{ 80 UCHAR ucNonClockStateIndex; 81 UCHAR ucClockStateIndices[1]; // variable-sized 82} ATOM_PPLIB_STATE; 83 84 85typedef struct _ATOM_PPLIB_FANTABLE 86{ 87 UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same. 88 UCHAR ucTHyst; // Temperature hysteresis. Integer. 89 USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. 90 USHORT usTMed; // The middle temperature where we change slopes. 91 USHORT usTHigh; // The high point above TMed for adjusting the second slope. 92 USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments). 93 USHORT usPWMMed; // The PWM value (in percent) at TMed. 94 USHORT usPWMHigh; // The PWM value at THigh. 95} ATOM_PPLIB_FANTABLE; 96 97typedef struct _ATOM_PPLIB_FANTABLE2 98{ 99 ATOM_PPLIB_FANTABLE basicTable; 100 USHORT usTMax; // The max temperature 101} ATOM_PPLIB_FANTABLE2; 102 103typedef struct _ATOM_PPLIB_FANTABLE3 104{ 105 ATOM_PPLIB_FANTABLE2 basicTable2; 106 UCHAR ucFanControlMode; 107 USHORT usFanPWMMax; 108 USHORT usFanOutputSensitivity; 109} ATOM_PPLIB_FANTABLE3; 110 111typedef struct _ATOM_PPLIB_FANTABLE4 112{ 113 ATOM_PPLIB_FANTABLE3 basicTable3; 114 USHORT usFanRPMMax; 115} ATOM_PPLIB_FANTABLE4; 116 117typedef struct _ATOM_PPLIB_FANTABLE5 118{ 119 ATOM_PPLIB_FANTABLE4 basicTable4; 120 USHORT usFanCurrentLow; 121 USHORT usFanCurrentHigh; 122 USHORT usFanRPMLow; 123 USHORT usFanRPMHigh; 124} ATOM_PPLIB_FANTABLE5; 125 126typedef struct _ATOM_PPLIB_EXTENDEDHEADER 127{ 128 USHORT usSize; 129 ULONG ulMaxEngineClock; // For Overdrive. 130 ULONG ulMaxMemoryClock; // For Overdrive. 131 // Add extra system parameters here, always adjust size to include all fields. 132 USHORT usVCETableOffset; //points to ATOM_PPLIB_VCE_Table 133 USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table 134 USHORT usSAMUTableOffset; //points to ATOM_PPLIB_SAMU_Table 135 USHORT usPPMTableOffset; //points to ATOM_PPLIB_PPM_Table 136 USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table 137 /* points to ATOM_PPLIB_POWERTUNE_Table */ 138 USHORT usPowerTuneTableOffset; 139 /* points to ATOM_PPLIB_CLOCK_Voltage_Dependency_Table for sclkVddgfxTable */ 140 USHORT usSclkVddgfxTableOffset; 141 USHORT usVQBudgetingTableOffset; /* points to the vqBudgetingTable; */ 142} ATOM_PPLIB_EXTENDEDHEADER; 143 144//// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps 145#define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 146#define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 147#define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 148#define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 149#define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 150#define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 151#define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 152#define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 153#define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 154#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 155#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 156#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 157#define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 158#define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. 159#define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). 160#define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does the driver control VDDCI independently from VDDC. 161#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature. 162#define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state. 163#define ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE 0x00040000 // Does the driver supports new CAC voltage table. 164#define ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY 0x00080000 // Does the driver supports revert GPIO5 polarity. 165#define ATOM_PP_PLATFORM_CAP_OUTPUT_THERMAL2GPIO17 0x00100000 // Does the driver supports thermal2GPIO17. 166#define ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE 0x00200000 // Does the driver supports VR HOT GPIO Configurable. 167#define ATOM_PP_PLATFORM_CAP_TEMP_INVERSION 0x00400000 // Does the driver supports Temp Inversion feature. 168#define ATOM_PP_PLATFORM_CAP_EVV 0x00800000 169#define ATOM_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL 0x01000000 170#define ATOM_PP_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE 0x02000000 171#define ATOM_PP_PLATFORM_CAP_DISABLE_USING_ACTUAL_TEMPERATURE_FOR_POWER_CALC 0x04000000 172#define ATOM_PP_PLATFORM_CAP_VRHOT_POLARITY_HIGH 0x08000000 173 174typedef struct _ATOM_PPLIB_POWERPLAYTABLE 175{ 176 ATOM_COMMON_TABLE_HEADER sHeader; 177 178 UCHAR ucDataRevision; 179 180 UCHAR ucNumStates; 181 UCHAR ucStateEntrySize; 182 UCHAR ucClockInfoSize; 183 UCHAR ucNonClockSize; 184 185 // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures 186 USHORT usStateArrayOffset; 187 188 // offset from start of this table to array of ASIC-specific structures, 189 // currently ATOM_PPLIB_CLOCK_INFO. 190 USHORT usClockInfoArrayOffset; 191 192 // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO 193 USHORT usNonClockInfoArrayOffset; 194 195 USHORT usBackbiasTime; // in microseconds 196 USHORT usVoltageTime; // in microseconds 197 USHORT usTableSize; //the size of this structure, or the extended structure 198 199 ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_* 200 201 ATOM_PPLIB_THERMALCONTROLLER sThermalController; 202 203 USHORT usBootClockInfoOffset; 204 USHORT usBootNonClockInfoOffset; 205 206} ATOM_PPLIB_POWERPLAYTABLE; 207 208typedef struct _ATOM_PPLIB_POWERPLAYTABLE2 209{ 210 ATOM_PPLIB_POWERPLAYTABLE basicTable; 211 UCHAR ucNumCustomThermalPolicy; 212 USHORT usCustomThermalPolicyArrayOffset; 213}ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2; 214 215typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 216{ 217 ATOM_PPLIB_POWERPLAYTABLE2 basicTable2; 218 USHORT usFormatID; // To be used ONLY by PPGen. 219 USHORT usFanTableOffset; 220 USHORT usExtendendedHeaderOffset; 221} ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3; 222 223typedef struct _ATOM_PPLIB_POWERPLAYTABLE4 224{ 225 ATOM_PPLIB_POWERPLAYTABLE3 basicTable3; 226 ULONG ulGoldenPPID; // PPGen use only 227 ULONG ulGoldenRevision; // PPGen use only 228 USHORT usVddcDependencyOnSCLKOffset; 229 USHORT usVddciDependencyOnMCLKOffset; 230 USHORT usVddcDependencyOnMCLKOffset; 231 USHORT usMaxClockVoltageOnDCOffset; 232 USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table 233 USHORT usMvddDependencyOnMCLKOffset; 234} ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4; 235 236typedef struct _ATOM_PPLIB_POWERPLAYTABLE5 237{ 238 ATOM_PPLIB_POWERPLAYTABLE4 basicTable4; 239 ULONG ulTDPLimit; 240 ULONG ulNearTDPLimit; 241 ULONG ulSQRampingThreshold; 242 USHORT usCACLeakageTableOffset; // Points to ATOM_PPLIB_CAC_Leakage_Table 243 ULONG ulCACLeakage; // The iLeakage for driver calculated CAC leakage table 244 USHORT usTDPODLimit; 245 USHORT usLoadLineSlope; // in milliOhms * 100 246} ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5; 247 248//// ATOM_PPLIB_NONCLOCK_INFO::usClassification 249#define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007 250#define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0 251#define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0 252#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 253#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 254#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 255// 2, 4, 6, 7 are reserved 256 257#define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 258#define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 259#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 260#define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 261#define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 262#define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 263#define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 264#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 265#define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 266#define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 267#define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 268#define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 269#define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 270 271//// ATOM_PPLIB_NONCLOCK_INFO::usClassification2 272#define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001 273#define ATOM_PPLIB_CLASSIFICATION2_ULV 0x0002 274#define ATOM_PPLIB_CLASSIFICATION2_MVC 0x0004 //Multi-View Codec (BD-3D) 275 276//// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings 277#define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001 278#define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002 279 280// 0 is 2.5Gb/s, 1 is 5Gb/s 281#define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004 282#define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2 283 284// lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec 285#define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8 286#define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3 287 288// lookup into reduced refresh-rate table 289#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00 290#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8 291 292#define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0 293#define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1 294// 2-15 TBD as needed. 295 296#define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000 297#define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000 298 299#define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000 300 301#define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000 302 303//memory related flags 304#define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF 0x000010000 305 306//M3 Arb //2bits, current 3 sets of parameters in total 307#define ATOM_PPLIB_M3ARB_MASK 0x00060000 308#define ATOM_PPLIB_M3ARB_SHIFT 17 309 310#define ATOM_PPLIB_ENABLE_DRR 0x00080000 311 312// remaining 16 bits are reserved 313typedef struct _ATOM_PPLIB_THERMAL_STATE 314{ 315 UCHAR ucMinTemperature; 316 UCHAR ucMaxTemperature; 317 UCHAR ucThermalAction; 318}ATOM_PPLIB_THERMAL_STATE, *LPATOM_PPLIB_THERMAL_STATE; 319 320// Contained in an array starting at the offset 321// in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset. 322// referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex 323#define ATOM_PPLIB_NONCLOCKINFO_VER1 12 324#define ATOM_PPLIB_NONCLOCKINFO_VER2 24 325typedef struct _ATOM_PPLIB_NONCLOCK_INFO 326{ 327 USHORT usClassification; 328 UCHAR ucMinTemperature; 329 UCHAR ucMaxTemperature; 330 ULONG ulCapsAndSettings; 331 UCHAR ucRequiredPower; 332 USHORT usClassification2; 333 ULONG ulVCLK; 334 ULONG ulDCLK; 335 UCHAR ucUnused[5]; 336} ATOM_PPLIB_NONCLOCK_INFO; 337 338// Contained in an array starting at the offset 339// in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset. 340// referenced from ATOM_PPLIB_STATE::ucClockStateIndices 341typedef struct _ATOM_PPLIB_R600_CLOCK_INFO 342{ 343 USHORT usEngineClockLow; 344 UCHAR ucEngineClockHigh; 345 346 USHORT usMemoryClockLow; 347 UCHAR ucMemoryClockHigh; 348 349 USHORT usVDDC; 350 USHORT usUnused1; 351 USHORT usUnused2; 352 353 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* 354 355} ATOM_PPLIB_R600_CLOCK_INFO; 356 357// ulFlags in ATOM_PPLIB_R600_CLOCK_INFO 358#define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1 359#define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2 360#define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4 361#define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8 362#define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16 363#define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0). 364 365typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO 366 367{ 368 USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600). 369 UCHAR ucLowEngineClockHigh; 370 USHORT usHighEngineClockLow; // High Engine clock in MHz. 371 UCHAR ucHighEngineClockHigh; 372 USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants. 373 UCHAR ucMemoryClockHigh; // Currentyl unused. 374 UCHAR ucPadding; // For proper alignment and size. 375 USHORT usVDDC; // For the 780, use: None, Low, High, Variable 376 UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} 377 UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could 378 USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). 379 ULONG ulFlags; 380} ATOM_PPLIB_RS780_CLOCK_INFO; 381 382#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 383#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 384#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 385#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 386 387#define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is. 388#define ATOM_PPLIB_RS780_SPMCLK_LOW 1 389#define ATOM_PPLIB_RS780_SPMCLK_HIGH 2 390 391#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 392#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 393#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 394 395typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO 396{ 397 USHORT usEngineClockLow; 398 UCHAR ucEngineClockHigh; 399 400 USHORT usMemoryClockLow; 401 UCHAR ucMemoryClockHigh; 402 403 USHORT usVDDC; 404 USHORT usVDDCI; 405 USHORT usUnused; 406 407 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* 408 409} ATOM_PPLIB_EVERGREEN_CLOCK_INFO; 410 411typedef struct _ATOM_PPLIB_SI_CLOCK_INFO 412{ 413 USHORT usEngineClockLow; 414 UCHAR ucEngineClockHigh; 415 416 USHORT usMemoryClockLow; 417 UCHAR ucMemoryClockHigh; 418 419 USHORT usVDDC; 420 USHORT usVDDCI; 421 UCHAR ucPCIEGen; 422 UCHAR ucUnused1; 423 424 ULONG ulFlags; // ATOM_PPLIB_SI_FLAGS_*, no flag is necessary for now 425 426} ATOM_PPLIB_SI_CLOCK_INFO; 427 428typedef struct _ATOM_PPLIB_CI_CLOCK_INFO 429{ 430 USHORT usEngineClockLow; 431 UCHAR ucEngineClockHigh; 432 433 USHORT usMemoryClockLow; 434 UCHAR ucMemoryClockHigh; 435 436 UCHAR ucPCIEGen; 437 USHORT usPCIELane; 438} ATOM_PPLIB_CI_CLOCK_INFO; 439 440typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{ 441 USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz 442 UCHAR ucEngineClockHigh; //clockfrequency >> 16. 443 UCHAR vddcIndex; //2-bit vddc index; 444 USHORT tdpLimit; 445 //please initalize to 0 446 USHORT rsv1; 447 //please initialize to 0s 448 ULONG rsv2[2]; 449}ATOM_PPLIB_SUMO_CLOCK_INFO; 450 451typedef struct _ATOM_PPLIB_KV_CLOCK_INFO { 452 USHORT usEngineClockLow; 453 UCHAR ucEngineClockHigh; 454 UCHAR vddcIndex; 455 USHORT tdpLimit; 456 USHORT rsv1; 457 ULONG rsv2[2]; 458} ATOM_PPLIB_KV_CLOCK_INFO; 459 460typedef struct _ATOM_PPLIB_CZ_CLOCK_INFO { 461 UCHAR index; 462 UCHAR rsv[3]; 463} ATOM_PPLIB_CZ_CLOCK_INFO; 464 465typedef struct _ATOM_PPLIB_STATE_V2 466{ 467 //number of valid dpm levels in this state; Driver uses it to calculate the whole 468 //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR) 469 UCHAR ucNumDPMLevels; 470 471 //a index to the array of nonClockInfos 472 UCHAR nonClockInfoIndex; 473 /** 474 * Driver will read the first ucNumDPMLevels in this array 475 */ 476 UCHAR clockInfoIndex[1]; 477} ATOM_PPLIB_STATE_V2; 478 479typedef struct _StateArray{ 480 //how many states we have 481 UCHAR ucNumEntries; 482 483 ATOM_PPLIB_STATE_V2 states[1]; 484}StateArray; 485 486 487typedef struct _ClockInfoArray{ 488 //how many clock levels we have 489 UCHAR ucNumEntries; 490 491 //sizeof(ATOM_PPLIB_CLOCK_INFO) 492 UCHAR ucEntrySize; 493 494 UCHAR clockInfo[1]; 495}ClockInfoArray; 496 497typedef struct _NonClockInfoArray{ 498 499 //how many non-clock levels we have. normally should be same as number of states 500 UCHAR ucNumEntries; 501 //sizeof(ATOM_PPLIB_NONCLOCK_INFO) 502 UCHAR ucEntrySize; 503 504 ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1]; 505}NonClockInfoArray; 506 507typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record 508{ 509 USHORT usClockLow; 510 UCHAR ucClockHigh; 511 USHORT usVoltage; 512}ATOM_PPLIB_Clock_Voltage_Dependency_Record; 513 514typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table 515{ 516 UCHAR ucNumEntries; // Number of entries. 517 ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; // Dynamically allocate entries. 518}ATOM_PPLIB_Clock_Voltage_Dependency_Table; 519 520typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record 521{ 522 USHORT usSclkLow; 523 UCHAR ucSclkHigh; 524 USHORT usMclkLow; 525 UCHAR ucMclkHigh; 526 USHORT usVddc; 527 USHORT usVddci; 528}ATOM_PPLIB_Clock_Voltage_Limit_Record; 529 530typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table 531{ 532 UCHAR ucNumEntries; // Number of entries. 533 ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries. 534}ATOM_PPLIB_Clock_Voltage_Limit_Table; 535 536union _ATOM_PPLIB_CAC_Leakage_Record 537{ 538 struct 539 { 540 USHORT usVddc; // We use this field for the "fake" standardized VDDC for power calculations; For CI and newer, we use this as the real VDDC value. in CI we read it as StdVoltageHiSidd 541 ULONG ulLeakageValue; // For CI and newer we use this as the "fake" standar VDDC value. in CI we read it as StdVoltageLoSidd 542 543 }; 544 struct 545 { 546 USHORT usVddc1; 547 USHORT usVddc2; 548 USHORT usVddc3; 549 }; 550}; 551 552typedef union _ATOM_PPLIB_CAC_Leakage_Record ATOM_PPLIB_CAC_Leakage_Record; 553 554typedef struct _ATOM_PPLIB_CAC_Leakage_Table 555{ 556 UCHAR ucNumEntries; // Number of entries. 557 ATOM_PPLIB_CAC_Leakage_Record entries[1]; // Dynamically allocate entries. 558}ATOM_PPLIB_CAC_Leakage_Table; 559 560typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record 561{ 562 USHORT usVoltage; 563 USHORT usSclkLow; 564 UCHAR ucSclkHigh; 565 USHORT usMclkLow; 566 UCHAR ucMclkHigh; 567}ATOM_PPLIB_PhaseSheddingLimits_Record; 568 569typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table 570{ 571 UCHAR ucNumEntries; // Number of entries. 572 ATOM_PPLIB_PhaseSheddingLimits_Record entries[1]; // Dynamically allocate entries. 573}ATOM_PPLIB_PhaseSheddingLimits_Table; 574 575typedef struct _VCEClockInfo{ 576 USHORT usEVClkLow; 577 UCHAR ucEVClkHigh; 578 USHORT usECClkLow; 579 UCHAR ucECClkHigh; 580}VCEClockInfo; 581 582typedef struct _VCEClockInfoArray{ 583 UCHAR ucNumEntries; 584 VCEClockInfo entries[1]; 585}VCEClockInfoArray; 586 587typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record 588{ 589 USHORT usVoltage; 590 UCHAR ucVCEClockInfoIndex; 591}ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record; 592 593typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table 594{ 595 UCHAR numEntries; 596 ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[1]; 597}ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table; 598 599typedef struct _ATOM_PPLIB_VCE_State_Record 600{ 601 UCHAR ucVCEClockInfoIndex; 602 UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary 603}ATOM_PPLIB_VCE_State_Record; 604 605typedef struct _ATOM_PPLIB_VCE_State_Table 606{ 607 UCHAR numEntries; 608 ATOM_PPLIB_VCE_State_Record entries[1]; 609}ATOM_PPLIB_VCE_State_Table; 610 611 612typedef struct _ATOM_PPLIB_VCE_Table 613{ 614 UCHAR revid; 615// VCEClockInfoArray array; 616// ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table limits; 617// ATOM_PPLIB_VCE_State_Table states; 618}ATOM_PPLIB_VCE_Table; 619 620 621typedef struct _UVDClockInfo{ 622 USHORT usVClkLow; 623 UCHAR ucVClkHigh; 624 USHORT usDClkLow; 625 UCHAR ucDClkHigh; 626}UVDClockInfo; 627 628typedef struct _UVDClockInfoArray{ 629 UCHAR ucNumEntries; 630 UVDClockInfo entries[1]; 631}UVDClockInfoArray; 632 633typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record 634{ 635 USHORT usVoltage; 636 UCHAR ucUVDClockInfoIndex; 637}ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record; 638 639typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table 640{ 641 UCHAR numEntries; 642 ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[1]; 643}ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table; 644 645typedef struct _ATOM_PPLIB_UVD_Table 646{ 647 UCHAR revid; 648// UVDClockInfoArray array; 649// ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table limits; 650}ATOM_PPLIB_UVD_Table; 651 652typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Record 653{ 654 USHORT usVoltage; 655 USHORT usSAMClockLow; 656 UCHAR ucSAMClockHigh; 657}ATOM_PPLIB_SAMClk_Voltage_Limit_Record; 658 659typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Table{ 660 UCHAR numEntries; 661 ATOM_PPLIB_SAMClk_Voltage_Limit_Record entries[1]; 662}ATOM_PPLIB_SAMClk_Voltage_Limit_Table; 663 664typedef struct _ATOM_PPLIB_SAMU_Table 665{ 666 UCHAR revid; 667 ATOM_PPLIB_SAMClk_Voltage_Limit_Table limits; 668}ATOM_PPLIB_SAMU_Table; 669 670typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Record 671{ 672 USHORT usVoltage; 673 USHORT usACPClockLow; 674 UCHAR ucACPClockHigh; 675}ATOM_PPLIB_ACPClk_Voltage_Limit_Record; 676 677typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Table{ 678 UCHAR numEntries; 679 ATOM_PPLIB_ACPClk_Voltage_Limit_Record entries[1]; 680}ATOM_PPLIB_ACPClk_Voltage_Limit_Table; 681 682typedef struct _ATOM_PPLIB_ACP_Table 683{ 684 UCHAR revid; 685 ATOM_PPLIB_ACPClk_Voltage_Limit_Table limits; 686}ATOM_PPLIB_ACP_Table; 687 688typedef struct _ATOM_PowerTune_Table{ 689 USHORT usTDP; 690 USHORT usConfigurableTDP; 691 USHORT usTDC; 692 USHORT usBatteryPowerLimit; 693 USHORT usSmallPowerLimit; 694 USHORT usLowCACLeakage; 695 USHORT usHighCACLeakage; 696}ATOM_PowerTune_Table; 697 698typedef struct _ATOM_PPLIB_POWERTUNE_Table 699{ 700 UCHAR revid; 701 ATOM_PowerTune_Table power_tune_table; 702}ATOM_PPLIB_POWERTUNE_Table; 703 704typedef struct _ATOM_PPLIB_POWERTUNE_Table_V1 705{ 706 UCHAR revid; 707 ATOM_PowerTune_Table power_tune_table; 708 USHORT usMaximumPowerDeliveryLimit; 709 USHORT usTjMax; 710 USHORT usReserve[6]; 711} ATOM_PPLIB_POWERTUNE_Table_V1; 712 713#define ATOM_PPM_A_A 1 714#define ATOM_PPM_A_I 2 715typedef struct _ATOM_PPLIB_PPM_Table 716{ 717 UCHAR ucRevId; 718 UCHAR ucPpmDesign; //A+I or A+A 719 USHORT usCpuCoreNumber; 720 ULONG ulPlatformTDP; 721 ULONG ulSmallACPlatformTDP; 722 ULONG ulPlatformTDC; 723 ULONG ulSmallACPlatformTDC; 724 ULONG ulApuTDP; 725 ULONG ulDGpuTDP; 726 ULONG ulDGpuUlvPower; 727 ULONG ulTjmax; 728} ATOM_PPLIB_PPM_Table; 729 730#define VQ_DisplayConfig_NoneAWD 1 731#define VQ_DisplayConfig_AWD 2 732 733typedef struct ATOM_PPLIB_VQ_Budgeting_Record{ 734 ULONG ulDeviceID; 735 ULONG ulSustainableSOCPowerLimitLow; /* in mW */ 736 ULONG ulSustainableSOCPowerLimitHigh; /* in mW */ 737 738 ULONG ulDClk; 739 ULONG ulEClk; 740 ULONG ulDispSclk; 741 UCHAR ucDispConfig; 742 743} ATOM_PPLIB_VQ_Budgeting_Record; 744 745typedef struct ATOM_PPLIB_VQ_Budgeting_Table { 746 UCHAR revid; 747 UCHAR numEntries; 748 ATOM_PPLIB_VQ_Budgeting_Record entries[1]; 749} ATOM_PPLIB_VQ_Budgeting_Table; 750 751#pragma pack() 752 753#endif 754