1/**************************************************************************** 2* 3* Realmode X86 Emulator Library 4* 5* Copyright (C) 1996-1999 SciTech Software, Inc. 6* Copyright (C) David Mosberger-Tang 7* Copyright (C) 1999 Egbert Eich 8* 9* ======================================================================== 10* 11* Permission to use, copy, modify, distribute, and sell this software and 12* its documentation for any purpose is hereby granted without fee, 13* provided that the above copyright notice appear in all copies and that 14* both that copyright notice and this permission notice appear in 15* supporting documentation, and that the name of the authors not be used 16* in advertising or publicity pertaining to distribution of the software 17* without specific, written prior permission. The authors makes no 18* representations about the suitability of this software for any purpose. 19* It is provided "as is" without express or implied warranty. 20* 21* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 22* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 23* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 24* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF 25* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 26* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 27* PERFORMANCE OF THIS SOFTWARE. 28* 29* ======================================================================== 30* 31* Language: ANSI C 32* Environment: Any 33* Developer: Kendall Bennett 34* 35* Description: Header file for x86 register definitions. 36* 37****************************************************************************/ 38 39#ifndef __X86EMU_REGS_H 40#define __X86EMU_REGS_H 41 42/*---------------------- Macros and type definitions ----------------------*/ 43 44#ifdef PACK 45#pragma PACK 46#endif 47 48/* 49 * General EAX, EBX, ECX, EDX type registers. Note that for 50 * portability, and speed, the issue of byte swapping is not addressed 51 * in the registers. All registers are stored in the default format 52 * available on the host machine. The only critical issue is that the 53 * registers should line up EXACTLY in the same manner as they do in 54 * the 386. That is: 55 * 56 * EAX & 0xff === AL 57 * EAX & 0xffff == AX 58 * 59 * etc. The result is that alot of the calculations can then be 60 * done using the native instruction set fully. 61 */ 62 63#ifdef __BIG_ENDIAN__ 64 65typedef struct { 66 u32 e_reg; 67} I32_reg_t; 68 69typedef struct { 70 u16 filler0, x_reg; 71} I16_reg_t; 72 73typedef struct { 74 u8 filler0, filler1, h_reg, l_reg; 75} I8_reg_t; 76 77#else /* !__BIG_ENDIAN__ */ 78 79typedef struct { 80 u32 e_reg; 81} I32_reg_t; 82 83typedef struct { 84 u16 x_reg; 85} I16_reg_t; 86 87typedef struct { 88 u8 l_reg, h_reg; 89} I8_reg_t; 90 91#endif /* BIG_ENDIAN */ 92 93typedef union { 94 I32_reg_t I32_reg; 95 I16_reg_t I16_reg; 96 I8_reg_t I8_reg; 97} i386_general_register; 98 99struct i386_general_regs { 100 i386_general_register A, B, C, D; 101}; 102 103typedef struct i386_general_regs Gen_reg_t; 104 105struct i386_special_regs { 106 i386_general_register SP, BP, SI, DI, IP; 107 u32 FLAGS; 108}; 109 110/* 111 * Segment registers here represent the 16 bit quantities 112 * CS, DS, ES, SS. 113 */ 114 115struct i386_segment_regs { 116 u16 CS, DS, SS, ES, FS, GS; 117}; 118 119/* 8 bit registers */ 120#define R_AH gen.A.I8_reg.h_reg 121#define R_AL gen.A.I8_reg.l_reg 122#define R_BH gen.B.I8_reg.h_reg 123#define R_BL gen.B.I8_reg.l_reg 124#define R_CH gen.C.I8_reg.h_reg 125#define R_CL gen.C.I8_reg.l_reg 126#define R_DH gen.D.I8_reg.h_reg 127#define R_DL gen.D.I8_reg.l_reg 128 129/* 16 bit registers */ 130#define R_AX gen.A.I16_reg.x_reg 131#define R_BX gen.B.I16_reg.x_reg 132#define R_CX gen.C.I16_reg.x_reg 133#define R_DX gen.D.I16_reg.x_reg 134 135/* 32 bit extended registers */ 136#define R_EAX gen.A.I32_reg.e_reg 137#define R_EBX gen.B.I32_reg.e_reg 138#define R_ECX gen.C.I32_reg.e_reg 139#define R_EDX gen.D.I32_reg.e_reg 140 141/* special registers */ 142#define R_SP spc.SP.I16_reg.x_reg 143#define R_BP spc.BP.I16_reg.x_reg 144#define R_SI spc.SI.I16_reg.x_reg 145#define R_DI spc.DI.I16_reg.x_reg 146#define R_IP spc.IP.I16_reg.x_reg 147#define R_FLG spc.FLAGS 148 149/* special registers */ 150#define R_SP spc.SP.I16_reg.x_reg 151#define R_BP spc.BP.I16_reg.x_reg 152#define R_SI spc.SI.I16_reg.x_reg 153#define R_DI spc.DI.I16_reg.x_reg 154#define R_IP spc.IP.I16_reg.x_reg 155#define R_FLG spc.FLAGS 156 157/* special registers */ 158#define R_ESP spc.SP.I32_reg.e_reg 159#define R_EBP spc.BP.I32_reg.e_reg 160#define R_ESI spc.SI.I32_reg.e_reg 161#define R_EDI spc.DI.I32_reg.e_reg 162#define R_EIP spc.IP.I32_reg.e_reg 163#define R_EFLG spc.FLAGS 164 165/* segment registers */ 166#define R_CS seg.CS 167#define R_DS seg.DS 168#define R_SS seg.SS 169#define R_ES seg.ES 170#define R_FS seg.FS 171#define R_GS seg.GS 172 173/* flag conditions */ 174#define FB_CF 0x0001 /* CARRY flag */ 175#define FB_PF 0x0004 /* PARITY flag */ 176#define FB_AF 0x0010 /* AUX flag */ 177#define FB_ZF 0x0040 /* ZERO flag */ 178#define FB_SF 0x0080 /* SIGN flag */ 179#define FB_TF 0x0100 /* TRAP flag */ 180#define FB_IF 0x0200 /* INTERRUPT ENABLE flag */ 181#define FB_DF 0x0400 /* DIR flag */ 182#define FB_OF 0x0800 /* OVERFLOW flag */ 183 184/* 80286 and above always have bit#1 set */ 185#define F_ALWAYS_ON (0x0002) /* flag bits always on */ 186 187/* 188 * Define a mask for only those flag bits we will ever pass back 189 * (via PUSHF) 190 */ 191#define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF) 192 193/* following bits masked in to a 16bit quantity */ 194 195#define F_CF 0x0001 /* CARRY flag */ 196#define F_PF 0x0004 /* PARITY flag */ 197#define F_AF 0x0010 /* AUX flag */ 198#define F_ZF 0x0040 /* ZERO flag */ 199#define F_SF 0x0080 /* SIGN flag */ 200#define F_TF 0x0100 /* TRAP flag */ 201#define F_IF 0x0200 /* INTERRUPT ENABLE flag */ 202#define F_DF 0x0400 /* DIR flag */ 203#define F_OF 0x0800 /* OVERFLOW flag */ 204 205#define TOGGLE_FLAG(flag) (M.x86.R_FLG ^= (flag)) 206#define SET_FLAG(flag) (M.x86.R_FLG |= (flag)) 207#define CLEAR_FLAG(flag) (M.x86.R_FLG &= ~(flag)) 208#define ACCESS_FLAG(flag) (M.x86.R_FLG & (flag)) 209#define CLEARALL_FLAG(m) (M.x86.R_FLG = 0) 210 211#define CONDITIONAL_SET_FLAG(COND,FLAG) \ 212 if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG) 213 214#define F_PF_CALC 0x010000 /* PARITY flag has been calced */ 215#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */ 216#define F_SF_CALC 0x040000 /* SIGN flag has been calced */ 217 218#define F_ALL_CALC 0xff0000 /* All have been calced */ 219 220/* 221 * Emulator machine state. 222 * Segment usage control. 223 */ 224#define SYSMODE_SEG_DS_SS 0x00000001 225#define SYSMODE_SEGOVR_CS 0x00000002 226#define SYSMODE_SEGOVR_DS 0x00000004 227#define SYSMODE_SEGOVR_ES 0x00000008 228#define SYSMODE_SEGOVR_FS 0x00000010 229#define SYSMODE_SEGOVR_GS 0x00000020 230#define SYSMODE_SEGOVR_SS 0x00000040 231#define SYSMODE_PREFIX_REPE 0x00000080 232#define SYSMODE_PREFIX_REPNE 0x00000100 233#define SYSMODE_PREFIX_DATA 0x00000200 234#define SYSMODE_PREFIX_ADDR 0x00000400 235#define SYSMODE_INTR_PENDING 0x10000000 236#define SYSMODE_EXTRN_INTR 0x20000000 237#define SYSMODE_HALTED 0x40000000 238 239#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \ 240 SYSMODE_SEGOVR_CS | \ 241 SYSMODE_SEGOVR_DS | \ 242 SYSMODE_SEGOVR_ES | \ 243 SYSMODE_SEGOVR_FS | \ 244 SYSMODE_SEGOVR_GS | \ 245 SYSMODE_SEGOVR_SS) 246#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \ 247 SYSMODE_SEGOVR_CS | \ 248 SYSMODE_SEGOVR_DS | \ 249 SYSMODE_SEGOVR_ES | \ 250 SYSMODE_SEGOVR_FS | \ 251 SYSMODE_SEGOVR_GS | \ 252 SYSMODE_SEGOVR_SS | \ 253 SYSMODE_PREFIX_DATA | \ 254 SYSMODE_PREFIX_ADDR) 255 256#define INTR_SYNCH 0x1 257#define INTR_ASYNCH 0x2 258#define INTR_HALTED 0x4 259 260typedef struct { 261 struct i386_general_regs gen; 262 struct i386_special_regs spc; 263 struct i386_segment_regs seg; 264 /* 265 * MODE contains information on: 266 * REPE prefix 2 bits repe,repne 267 * SEGMENT overrides 5 bits normal,DS,SS,CS,ES 268 * Delayed flag set 3 bits (zero, signed, parity) 269 * reserved 6 bits 270 * interrupt # 8 bits instruction raised interrupt 271 * BIOS video segregs 4 bits 272 * Interrupt Pending 1 bits 273 * Extern interrupt 1 bits 274 * Halted 1 bits 275 */ 276 u32 mode; 277 volatile int intr; /* mask of pending interrupts */ 278 int debug; 279#ifdef DEBUG 280 int check; 281 u16 saved_ip; 282 u16 saved_cs; 283 int enc_pos; 284 int enc_str_pos; 285 char decode_buf[32]; /* encoded byte stream */ 286 char decoded_buf[256]; /* disassembled strings */ 287#endif 288 u8 intno; 289 u8 __pad[3]; 290} X86EMU_regs; 291 292/**************************************************************************** 293REMARKS: 294Structure maintaining the emulator machine state. 295 296MEMBERS: 297mem_base - Base real mode memory for the emulator 298mem_size - Size of the real mode memory block for the emulator 299private - private data pointer 300x86 - X86 registers 301****************************************************************************/ 302typedef struct { 303 unsigned long mem_base; 304 unsigned long mem_size; 305#ifdef __cplusplus 306 void *_private; 307#else 308 void *private; 309#endif 310 X86EMU_regs x86; 311} X86EMU_sysEnv; 312 313#ifdef END_PACK 314#pragma END_PACK 315#endif 316 317/*----------------------------- Global Variables --------------------------*/ 318 319#ifdef __cplusplus 320extern "C" { /* Use "C" linkage when in C++ mode */ 321#endif 322 323/* Global emulator machine state. 324 * 325 * We keep it global to avoid pointer dereferences in the code for speed. 326 */ 327 328 extern X86EMU_sysEnv _X86EMU_env; 329#define M _X86EMU_env 330 331/*-------------------------- Function Prototypes --------------------------*/ 332 333/* Function to log information at runtime */ 334 335#include <KernelExport.h> 336#define printk(fmt...) dprintf(fmt) 337// void printk(const char *fmt, ...); 338 339#ifdef __cplusplus 340} /* End of "C" linkage for C++ */ 341#endif 342#endif /* __X86EMU_REGS_H */ 343