1/* Target-dependent code for Motorola 68HC11 & 68HC12 2 3 Copyright 1999, 2000, 2001, 2002, 2003, 2004 Free Software 4 Foundation, Inc. 5 6 Contributed by Stephane Carrez, stcarrez@nerim.fr 7 8This file is part of GDB. 9 10This program is free software; you can redistribute it and/or modify 11it under the terms of the GNU General Public License as published by 12the Free Software Foundation; either version 2 of the License, or 13(at your option) any later version. 14 15This program is distributed in the hope that it will be useful, 16but WITHOUT ANY WARRANTY; without even the implied warranty of 17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18GNU General Public License for more details. 19 20You should have received a copy of the GNU General Public License 21along with this program; if not, write to the Free Software 22Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 23 24 25#include "defs.h" 26#include "frame.h" 27#include "frame-unwind.h" 28#include "frame-base.h" 29#include "dwarf2-frame.h" 30#include "trad-frame.h" 31#include "symtab.h" 32#include "gdbtypes.h" 33#include "gdbcmd.h" 34#include "gdbcore.h" 35#include "gdb_string.h" 36#include "value.h" 37#include "inferior.h" 38#include "dis-asm.h" 39#include "symfile.h" 40#include "objfiles.h" 41#include "arch-utils.h" 42#include "regcache.h" 43#include "reggroups.h" 44 45#include "target.h" 46#include "opcode/m68hc11.h" 47#include "elf/m68hc11.h" 48#include "elf-bfd.h" 49 50/* Macros for setting and testing a bit in a minimal symbol. 51 For 68HC11/68HC12 we have two flags that tell which return 52 type the function is using. This is used for prologue and frame 53 analysis to compute correct stack frame layout. 54 55 The MSB of the minimal symbol's "info" field is used for this purpose. 56 57 MSYMBOL_SET_RTC Actually sets the "RTC" bit. 58 MSYMBOL_SET_RTI Actually sets the "RTI" bit. 59 MSYMBOL_IS_RTC Tests the "RTC" bit in a minimal symbol. 60 MSYMBOL_IS_RTI Tests the "RTC" bit in a minimal symbol. */ 61 62#define MSYMBOL_SET_RTC(msym) \ 63 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ 64 | 0x80000000) 65 66#define MSYMBOL_SET_RTI(msym) \ 67 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ 68 | 0x40000000) 69 70#define MSYMBOL_IS_RTC(msym) \ 71 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) 72 73#define MSYMBOL_IS_RTI(msym) \ 74 (((long) MSYMBOL_INFO (msym) & 0x40000000) != 0) 75 76enum insn_return_kind { 77 RETURN_RTS, 78 RETURN_RTC, 79 RETURN_RTI 80}; 81 82 83/* Register numbers of various important registers. 84 Note that some of these values are "real" register numbers, 85 and correspond to the general registers of the machine, 86 and some are "phony" register numbers which are too large 87 to be actual register numbers as far as the user is concerned 88 but do serve to get the desired values when passed to read_register. */ 89 90#define HARD_X_REGNUM 0 91#define HARD_D_REGNUM 1 92#define HARD_Y_REGNUM 2 93#define HARD_SP_REGNUM 3 94#define HARD_PC_REGNUM 4 95 96#define HARD_A_REGNUM 5 97#define HARD_B_REGNUM 6 98#define HARD_CCR_REGNUM 7 99 100/* 68HC12 page number register. 101 Note: to keep a compatibility with gcc register naming, we must 102 not have to rename FP and other soft registers. The page register 103 is a real hard register and must therefore be counted by NUM_REGS. 104 For this it has the same number as Z register (which is not used). */ 105#define HARD_PAGE_REGNUM 8 106#define M68HC11_LAST_HARD_REG (HARD_PAGE_REGNUM) 107 108/* Z is replaced by X or Y by gcc during machine reorg. 109 ??? There is no way to get it and even know whether 110 it's in X or Y or in ZS. */ 111#define SOFT_Z_REGNUM 8 112 113/* Soft registers. These registers are special. There are treated 114 like normal hard registers by gcc and gdb (ie, within dwarf2 info). 115 They are physically located in memory. */ 116#define SOFT_FP_REGNUM 9 117#define SOFT_TMP_REGNUM 10 118#define SOFT_ZS_REGNUM 11 119#define SOFT_XY_REGNUM 12 120#define SOFT_UNUSED_REGNUM 13 121#define SOFT_D1_REGNUM 14 122#define SOFT_D32_REGNUM (SOFT_D1_REGNUM+31) 123#define M68HC11_MAX_SOFT_REGS 32 124 125#define M68HC11_NUM_REGS (8) 126#define M68HC11_NUM_PSEUDO_REGS (M68HC11_MAX_SOFT_REGS+5) 127#define M68HC11_ALL_REGS (M68HC11_NUM_REGS+M68HC11_NUM_PSEUDO_REGS) 128 129#define M68HC11_REG_SIZE (2) 130 131#define M68HC12_NUM_REGS (9) 132#define M68HC12_NUM_PSEUDO_REGS ((M68HC11_MAX_SOFT_REGS+5)+1-1) 133#define M68HC12_HARD_PC_REGNUM (SOFT_D32_REGNUM+1) 134 135struct insn_sequence; 136struct gdbarch_tdep 137 { 138 /* Stack pointer correction value. For 68hc11, the stack pointer points 139 to the next push location. An offset of 1 must be applied to obtain 140 the address where the last value is saved. For 68hc12, the stack 141 pointer points to the last value pushed. No offset is necessary. */ 142 int stack_correction; 143 144 /* Description of instructions in the prologue. */ 145 struct insn_sequence *prologue; 146 147 /* True if the page memory bank register is available 148 and must be used. */ 149 int use_page_register; 150 151 /* ELF flags for ABI. */ 152 int elf_flags; 153 }; 154 155#define M6811_TDEP gdbarch_tdep (current_gdbarch) 156#define STACK_CORRECTION (M6811_TDEP->stack_correction) 157#define USE_PAGE_REGISTER (M6811_TDEP->use_page_register) 158 159struct m68hc11_unwind_cache 160{ 161 /* The previous frame's inner most stack address. Used as this 162 frame ID's stack_addr. */ 163 CORE_ADDR prev_sp; 164 /* The frame's base, optionally used by the high-level debug info. */ 165 CORE_ADDR base; 166 CORE_ADDR pc; 167 int size; 168 int prologue_type; 169 CORE_ADDR return_pc; 170 CORE_ADDR sp_offset; 171 int frameless; 172 enum insn_return_kind return_kind; 173 174 /* Table indicating the location of each and every register. */ 175 struct trad_frame_saved_reg *saved_regs; 176}; 177 178/* Table of registers for 68HC11. This includes the hard registers 179 and the soft registers used by GCC. */ 180static char * 181m68hc11_register_names[] = 182{ 183 "x", "d", "y", "sp", "pc", "a", "b", 184 "ccr", "page", "frame","tmp", "zs", "xy", 0, 185 "d1", "d2", "d3", "d4", "d5", "d6", "d7", 186 "d8", "d9", "d10", "d11", "d12", "d13", "d14", 187 "d15", "d16", "d17", "d18", "d19", "d20", "d21", 188 "d22", "d23", "d24", "d25", "d26", "d27", "d28", 189 "d29", "d30", "d31", "d32" 190}; 191 192struct m68hc11_soft_reg 193{ 194 const char *name; 195 CORE_ADDR addr; 196}; 197 198static struct m68hc11_soft_reg soft_regs[M68HC11_ALL_REGS]; 199 200#define M68HC11_FP_ADDR soft_regs[SOFT_FP_REGNUM].addr 201 202static int soft_min_addr; 203static int soft_max_addr; 204static int soft_reg_initialized = 0; 205 206/* Look in the symbol table for the address of a pseudo register 207 in memory. If we don't find it, pretend the register is not used 208 and not available. */ 209static void 210m68hc11_get_register_info (struct m68hc11_soft_reg *reg, const char *name) 211{ 212 struct minimal_symbol *msymbol; 213 214 msymbol = lookup_minimal_symbol (name, NULL, NULL); 215 if (msymbol) 216 { 217 reg->addr = SYMBOL_VALUE_ADDRESS (msymbol); 218 reg->name = xstrdup (name); 219 220 /* Keep track of the address range for soft registers. */ 221 if (reg->addr < (CORE_ADDR) soft_min_addr) 222 soft_min_addr = reg->addr; 223 if (reg->addr > (CORE_ADDR) soft_max_addr) 224 soft_max_addr = reg->addr; 225 } 226 else 227 { 228 reg->name = 0; 229 reg->addr = 0; 230 } 231} 232 233/* Initialize the table of soft register addresses according 234 to the symbol table. */ 235 static void 236m68hc11_initialize_register_info (void) 237{ 238 int i; 239 240 if (soft_reg_initialized) 241 return; 242 243 soft_min_addr = INT_MAX; 244 soft_max_addr = 0; 245 for (i = 0; i < M68HC11_ALL_REGS; i++) 246 { 247 soft_regs[i].name = 0; 248 } 249 250 m68hc11_get_register_info (&soft_regs[SOFT_FP_REGNUM], "_.frame"); 251 m68hc11_get_register_info (&soft_regs[SOFT_TMP_REGNUM], "_.tmp"); 252 m68hc11_get_register_info (&soft_regs[SOFT_ZS_REGNUM], "_.z"); 253 soft_regs[SOFT_Z_REGNUM] = soft_regs[SOFT_ZS_REGNUM]; 254 m68hc11_get_register_info (&soft_regs[SOFT_XY_REGNUM], "_.xy"); 255 256 for (i = SOFT_D1_REGNUM; i < M68HC11_MAX_SOFT_REGS; i++) 257 { 258 char buf[10]; 259 260 sprintf (buf, "_.d%d", i - SOFT_D1_REGNUM + 1); 261 m68hc11_get_register_info (&soft_regs[i], buf); 262 } 263 264 if (soft_regs[SOFT_FP_REGNUM].name == 0) 265 { 266 warning ("No frame soft register found in the symbol table.\n"); 267 warning ("Stack backtrace will not work.\n"); 268 } 269 soft_reg_initialized = 1; 270} 271 272/* Given an address in memory, return the soft register number if 273 that address corresponds to a soft register. Returns -1 if not. */ 274static int 275m68hc11_which_soft_register (CORE_ADDR addr) 276{ 277 int i; 278 279 if (addr < soft_min_addr || addr > soft_max_addr) 280 return -1; 281 282 for (i = SOFT_FP_REGNUM; i < M68HC11_ALL_REGS; i++) 283 { 284 if (soft_regs[i].name && soft_regs[i].addr == addr) 285 return i; 286 } 287 return -1; 288} 289 290/* Fetch a pseudo register. The 68hc11 soft registers are treated like 291 pseudo registers. They are located in memory. Translate the register 292 fetch into a memory read. */ 293static void 294m68hc11_pseudo_register_read (struct gdbarch *gdbarch, 295 struct regcache *regcache, 296 int regno, void *buf) 297{ 298 /* The PC is a pseudo reg only for 68HC12 with the memory bank 299 addressing mode. */ 300 if (regno == M68HC12_HARD_PC_REGNUM) 301 { 302 ULONGEST pc; 303 const int regsize = TYPE_LENGTH (builtin_type_uint32); 304 305 regcache_cooked_read_unsigned (regcache, HARD_PC_REGNUM, &pc); 306 if (pc >= 0x8000 && pc < 0xc000) 307 { 308 ULONGEST page; 309 310 regcache_cooked_read_unsigned (regcache, HARD_PAGE_REGNUM, &page); 311 pc -= 0x8000; 312 pc += (page << 14); 313 pc += 0x1000000; 314 } 315 store_unsigned_integer (buf, regsize, pc); 316 return; 317 } 318 319 m68hc11_initialize_register_info (); 320 321 /* Fetch a soft register: translate into a memory read. */ 322 if (soft_regs[regno].name) 323 { 324 target_read_memory (soft_regs[regno].addr, buf, 2); 325 } 326 else 327 { 328 memset (buf, 0, 2); 329 } 330} 331 332/* Store a pseudo register. Translate the register store 333 into a memory write. */ 334static void 335m68hc11_pseudo_register_write (struct gdbarch *gdbarch, 336 struct regcache *regcache, 337 int regno, const void *buf) 338{ 339 /* The PC is a pseudo reg only for 68HC12 with the memory bank 340 addressing mode. */ 341 if (regno == M68HC12_HARD_PC_REGNUM) 342 { 343 const int regsize = TYPE_LENGTH (builtin_type_uint32); 344 char *tmp = alloca (regsize); 345 CORE_ADDR pc; 346 347 memcpy (tmp, buf, regsize); 348 pc = extract_unsigned_integer (tmp, regsize); 349 if (pc >= 0x1000000) 350 { 351 pc -= 0x1000000; 352 regcache_cooked_write_unsigned (regcache, HARD_PAGE_REGNUM, 353 (pc >> 14) & 0x0ff); 354 pc &= 0x03fff; 355 regcache_cooked_write_unsigned (regcache, HARD_PC_REGNUM, 356 pc + 0x8000); 357 } 358 else 359 regcache_cooked_write_unsigned (regcache, HARD_PC_REGNUM, pc); 360 return; 361 } 362 363 m68hc11_initialize_register_info (); 364 365 /* Store a soft register: translate into a memory write. */ 366 if (soft_regs[regno].name) 367 { 368 const int regsize = 2; 369 char *tmp = alloca (regsize); 370 memcpy (tmp, buf, regsize); 371 target_write_memory (soft_regs[regno].addr, tmp, regsize); 372 } 373} 374 375static const char * 376m68hc11_register_name (int reg_nr) 377{ 378 if (reg_nr == M68HC12_HARD_PC_REGNUM && USE_PAGE_REGISTER) 379 return "pc"; 380 if (reg_nr == HARD_PC_REGNUM && USE_PAGE_REGISTER) 381 return "ppc"; 382 383 if (reg_nr < 0) 384 return NULL; 385 if (reg_nr >= M68HC11_ALL_REGS) 386 return NULL; 387 388 m68hc11_initialize_register_info (); 389 390 /* If we don't know the address of a soft register, pretend it 391 does not exist. */ 392 if (reg_nr > M68HC11_LAST_HARD_REG && soft_regs[reg_nr].name == 0) 393 return NULL; 394 return m68hc11_register_names[reg_nr]; 395} 396 397static const unsigned char * 398m68hc11_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) 399{ 400 static unsigned char breakpoint[] = {0x0}; 401 402 *lenptr = sizeof (breakpoint); 403 return breakpoint; 404} 405 406 407/* 68HC11 & 68HC12 prologue analysis. 408 409 */ 410#define MAX_CODES 12 411 412/* 68HC11 opcodes. */ 413#undef M6811_OP_PAGE2 414#define M6811_OP_PAGE2 (0x18) 415#define M6811_OP_LDX (0xde) 416#define M6811_OP_LDX_EXT (0xfe) 417#define M6811_OP_PSHX (0x3c) 418#define M6811_OP_STS (0x9f) 419#define M6811_OP_STS_EXT (0xbf) 420#define M6811_OP_TSX (0x30) 421#define M6811_OP_XGDX (0x8f) 422#define M6811_OP_ADDD (0xc3) 423#define M6811_OP_TXS (0x35) 424#define M6811_OP_DES (0x34) 425 426/* 68HC12 opcodes. */ 427#define M6812_OP_PAGE2 (0x18) 428#define M6812_OP_MOVW (0x01) 429#define M6812_PB_PSHW (0xae) 430#define M6812_OP_STS (0x5f) 431#define M6812_OP_STS_EXT (0x7f) 432#define M6812_OP_LEAS (0x1b) 433#define M6812_OP_PSHX (0x34) 434#define M6812_OP_PSHY (0x35) 435 436/* Operand extraction. */ 437#define OP_DIRECT (0x100) /* 8-byte direct addressing. */ 438#define OP_IMM_LOW (0x200) /* Low part of 16-bit constant/address. */ 439#define OP_IMM_HIGH (0x300) /* High part of 16-bit constant/address. */ 440#define OP_PBYTE (0x400) /* 68HC12 indexed operand. */ 441 442/* Identification of the sequence. */ 443enum m6811_seq_type 444{ 445 P_LAST = 0, 446 P_SAVE_REG, /* Save a register on the stack. */ 447 P_SET_FRAME, /* Setup the frame pointer. */ 448 P_LOCAL_1, /* Allocate 1 byte for locals. */ 449 P_LOCAL_2, /* Allocate 2 bytes for locals. */ 450 P_LOCAL_N /* Allocate N bytes for locals. */ 451}; 452 453struct insn_sequence { 454 enum m6811_seq_type type; 455 unsigned length; 456 unsigned short code[MAX_CODES]; 457}; 458 459/* Sequence of instructions in the 68HC11 function prologue. */ 460static struct insn_sequence m6811_prologue[] = { 461 /* Sequences to save a soft-register. */ 462 { P_SAVE_REG, 3, { M6811_OP_LDX, OP_DIRECT, 463 M6811_OP_PSHX } }, 464 { P_SAVE_REG, 5, { M6811_OP_PAGE2, M6811_OP_LDX, OP_DIRECT, 465 M6811_OP_PAGE2, M6811_OP_PSHX } }, 466 { P_SAVE_REG, 4, { M6811_OP_LDX_EXT, OP_IMM_HIGH, OP_IMM_LOW, 467 M6811_OP_PSHX } }, 468 { P_SAVE_REG, 6, { M6811_OP_PAGE2, M6811_OP_LDX_EXT, OP_IMM_HIGH, OP_IMM_LOW, 469 M6811_OP_PAGE2, M6811_OP_PSHX } }, 470 471 /* Sequences to allocate local variables. */ 472 { P_LOCAL_N, 7, { M6811_OP_TSX, 473 M6811_OP_XGDX, 474 M6811_OP_ADDD, OP_IMM_HIGH, OP_IMM_LOW, 475 M6811_OP_XGDX, 476 M6811_OP_TXS } }, 477 { P_LOCAL_N, 11, { M6811_OP_PAGE2, M6811_OP_TSX, 478 M6811_OP_PAGE2, M6811_OP_XGDX, 479 M6811_OP_ADDD, OP_IMM_HIGH, OP_IMM_LOW, 480 M6811_OP_PAGE2, M6811_OP_XGDX, 481 M6811_OP_PAGE2, M6811_OP_TXS } }, 482 { P_LOCAL_1, 1, { M6811_OP_DES } }, 483 { P_LOCAL_2, 1, { M6811_OP_PSHX } }, 484 { P_LOCAL_2, 2, { M6811_OP_PAGE2, M6811_OP_PSHX } }, 485 486 /* Initialize the frame pointer. */ 487 { P_SET_FRAME, 2, { M6811_OP_STS, OP_DIRECT } }, 488 { P_SET_FRAME, 3, { M6811_OP_STS_EXT, OP_IMM_HIGH, OP_IMM_LOW } }, 489 { P_LAST, 0, { 0 } } 490}; 491 492 493/* Sequence of instructions in the 68HC12 function prologue. */ 494static struct insn_sequence m6812_prologue[] = { 495 { P_SAVE_REG, 5, { M6812_OP_PAGE2, M6812_OP_MOVW, M6812_PB_PSHW, 496 OP_IMM_HIGH, OP_IMM_LOW } }, 497 { P_SET_FRAME, 2, { M6812_OP_STS, OP_DIRECT } }, 498 { P_SET_FRAME, 3, { M6812_OP_STS_EXT, OP_IMM_HIGH, OP_IMM_LOW } }, 499 { P_LOCAL_N, 2, { M6812_OP_LEAS, OP_PBYTE } }, 500 { P_LOCAL_2, 1, { M6812_OP_PSHX } }, 501 { P_LOCAL_2, 1, { M6812_OP_PSHY } }, 502 { P_LAST, 0 } 503}; 504 505 506/* Analyze the sequence of instructions starting at the given address. 507 Returns a pointer to the sequence when it is recognized and 508 the optional value (constant/address) associated with it. */ 509static struct insn_sequence * 510m68hc11_analyze_instruction (struct insn_sequence *seq, CORE_ADDR pc, 511 CORE_ADDR *val) 512{ 513 unsigned char buffer[MAX_CODES]; 514 unsigned bufsize; 515 unsigned j; 516 CORE_ADDR cur_val; 517 short v = 0; 518 519 bufsize = 0; 520 for (; seq->type != P_LAST; seq++) 521 { 522 cur_val = 0; 523 for (j = 0; j < seq->length; j++) 524 { 525 if (bufsize < j + 1) 526 { 527 buffer[bufsize] = read_memory_unsigned_integer (pc + bufsize, 528 1); 529 bufsize++; 530 } 531 /* Continue while we match the opcode. */ 532 if (seq->code[j] == buffer[j]) 533 continue; 534 535 if ((seq->code[j] & 0xf00) == 0) 536 break; 537 538 /* Extract a sequence parameter (address or constant). */ 539 switch (seq->code[j]) 540 { 541 case OP_DIRECT: 542 cur_val = (CORE_ADDR) buffer[j]; 543 break; 544 545 case OP_IMM_HIGH: 546 cur_val = cur_val & 0x0ff; 547 cur_val |= (buffer[j] << 8); 548 break; 549 550 case OP_IMM_LOW: 551 cur_val &= 0x0ff00; 552 cur_val |= buffer[j]; 553 break; 554 555 case OP_PBYTE: 556 if ((buffer[j] & 0xE0) == 0x80) 557 { 558 v = buffer[j] & 0x1f; 559 if (v & 0x10) 560 v |= 0xfff0; 561 } 562 else if ((buffer[j] & 0xfe) == 0xf0) 563 { 564 v = read_memory_unsigned_integer (pc + j + 1, 1); 565 if (buffer[j] & 1) 566 v |= 0xff00; 567 } 568 else if (buffer[j] == 0xf2) 569 { 570 v = read_memory_unsigned_integer (pc + j + 1, 2); 571 } 572 cur_val = v; 573 break; 574 } 575 } 576 577 /* We have a full match. */ 578 if (j == seq->length) 579 { 580 *val = cur_val; 581 return seq; 582 } 583 } 584 return 0; 585} 586 587/* Return the instruction that the function at the PC is using. */ 588static enum insn_return_kind 589m68hc11_get_return_insn (CORE_ADDR pc) 590{ 591 struct minimal_symbol *sym; 592 593 /* A flag indicating that this is a STO_M68HC12_FAR or STO_M68HC12_INTERRUPT 594 function is stored by elfread.c in the high bit of the info field. 595 Use this to decide which instruction the function uses to return. */ 596 sym = lookup_minimal_symbol_by_pc (pc); 597 if (sym == 0) 598 return RETURN_RTS; 599 600 if (MSYMBOL_IS_RTC (sym)) 601 return RETURN_RTC; 602 else if (MSYMBOL_IS_RTI (sym)) 603 return RETURN_RTI; 604 else 605 return RETURN_RTS; 606} 607 608/* Analyze the function prologue to find some information 609 about the function: 610 - the PC of the first line (for m68hc11_skip_prologue) 611 - the offset of the previous frame saved address (from current frame) 612 - the soft registers which are pushed. */ 613static CORE_ADDR 614m68hc11_scan_prologue (CORE_ADDR pc, CORE_ADDR current_pc, 615 struct m68hc11_unwind_cache *info) 616{ 617 LONGEST save_addr; 618 CORE_ADDR func_end; 619 int size; 620 int found_frame_point; 621 int saved_reg; 622 int done = 0; 623 struct insn_sequence *seq_table; 624 625 info->size = 0; 626 info->sp_offset = 0; 627 if (pc >= current_pc) 628 return current_pc; 629 630 size = 0; 631 632 m68hc11_initialize_register_info (); 633 if (pc == 0) 634 { 635 info->size = 0; 636 return pc; 637 } 638 639 seq_table = gdbarch_tdep (current_gdbarch)->prologue; 640 641 /* The 68hc11 stack is as follows: 642 643 644 | | 645 +-----------+ 646 | | 647 | args | 648 | | 649 +-----------+ 650 | PC-return | 651 +-----------+ 652 | Old frame | 653 +-----------+ 654 | | 655 | Locals | 656 | | 657 +-----------+ <--- current frame 658 | | 659 660 With most processors (like 68K) the previous frame can be computed 661 easily because it is always at a fixed offset (see link/unlink). 662 That is, locals are accessed with negative offsets, arguments are 663 accessed with positive ones. Since 68hc11 only supports offsets 664 in the range [0..255], the frame is defined at the bottom of 665 locals (see picture). 666 667 The purpose of the analysis made here is to find out the size 668 of locals in this function. An alternative to this is to use 669 DWARF2 info. This would be better but I don't know how to 670 access dwarf2 debug from this function. 671 672 Walk from the function entry point to the point where we save 673 the frame. While walking instructions, compute the size of bytes 674 which are pushed. This gives us the index to access the previous 675 frame. 676 677 We limit the search to 128 bytes so that the algorithm is bounded 678 in case of random and wrong code. We also stop and abort if 679 we find an instruction which is not supposed to appear in the 680 prologue (as generated by gcc 2.95, 2.96). 681 */ 682 func_end = pc + 128; 683 found_frame_point = 0; 684 info->size = 0; 685 save_addr = 0; 686 while (!done && pc + 2 < func_end) 687 { 688 struct insn_sequence *seq; 689 CORE_ADDR val; 690 691 seq = m68hc11_analyze_instruction (seq_table, pc, &val); 692 if (seq == 0) 693 break; 694 695 /* If we are within the instruction group, we can't advance the 696 pc nor the stack offset. Otherwise the caller's stack computed 697 from the current stack can be wrong. */ 698 if (pc + seq->length > current_pc) 699 break; 700 701 pc = pc + seq->length; 702 if (seq->type == P_SAVE_REG) 703 { 704 if (found_frame_point) 705 { 706 saved_reg = m68hc11_which_soft_register (val); 707 if (saved_reg < 0) 708 break; 709 710 save_addr -= 2; 711 info->saved_regs[saved_reg].addr = save_addr; 712 } 713 else 714 { 715 size += 2; 716 } 717 } 718 else if (seq->type == P_SET_FRAME) 719 { 720 found_frame_point = 1; 721 info->size = size; 722 } 723 else if (seq->type == P_LOCAL_1) 724 { 725 size += 1; 726 } 727 else if (seq->type == P_LOCAL_2) 728 { 729 size += 2; 730 } 731 else if (seq->type == P_LOCAL_N) 732 { 733 /* Stack pointer is decremented for the allocation. */ 734 if (val & 0x8000) 735 size -= (int) (val) | 0xffff0000; 736 else 737 size -= val; 738 } 739 } 740 if (found_frame_point == 0) 741 info->sp_offset = size; 742 else 743 info->sp_offset = -1; 744 return pc; 745} 746 747static CORE_ADDR 748m68hc11_skip_prologue (CORE_ADDR pc) 749{ 750 CORE_ADDR func_addr, func_end; 751 struct symtab_and_line sal; 752 struct m68hc11_unwind_cache tmp_cache = { 0 }; 753 754 /* If we have line debugging information, then the end of the 755 prologue should be the first assembly instruction of the 756 first source line. */ 757 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 758 { 759 sal = find_pc_line (func_addr, 0); 760 if (sal.end && sal.end < func_end) 761 return sal.end; 762 } 763 764 pc = m68hc11_scan_prologue (pc, (CORE_ADDR) -1, &tmp_cache); 765 return pc; 766} 767 768static CORE_ADDR 769m68hc11_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 770{ 771 ULONGEST pc; 772 773 frame_unwind_unsigned_register (next_frame, gdbarch_pc_regnum (gdbarch), 774 &pc); 775 return pc; 776} 777 778/* Put here the code to store, into fi->saved_regs, the addresses of 779 the saved registers of frame described by FRAME_INFO. This 780 includes special registers such as pc and fp saved in special ways 781 in the stack frame. sp is even more special: the address we return 782 for it IS the sp for the next frame. */ 783 784struct m68hc11_unwind_cache * 785m68hc11_frame_unwind_cache (struct frame_info *next_frame, 786 void **this_prologue_cache) 787{ 788 ULONGEST prev_sp; 789 ULONGEST this_base; 790 struct m68hc11_unwind_cache *info; 791 CORE_ADDR current_pc; 792 int i; 793 794 if ((*this_prologue_cache)) 795 return (*this_prologue_cache); 796 797 info = FRAME_OBSTACK_ZALLOC (struct m68hc11_unwind_cache); 798 (*this_prologue_cache) = info; 799 info->saved_regs = trad_frame_alloc_saved_regs (next_frame); 800 801 info->pc = frame_func_unwind (next_frame); 802 803 info->size = 0; 804 info->return_kind = m68hc11_get_return_insn (info->pc); 805 806 /* The SP was moved to the FP. This indicates that a new frame 807 was created. Get THIS frame's FP value by unwinding it from 808 the next frame. */ 809 frame_unwind_unsigned_register (next_frame, SOFT_FP_REGNUM, &this_base); 810 if (this_base == 0) 811 { 812 info->base = 0; 813 return info; 814 } 815 816 current_pc = frame_pc_unwind (next_frame); 817 if (info->pc != 0) 818 m68hc11_scan_prologue (info->pc, current_pc, info); 819 820 info->saved_regs[HARD_PC_REGNUM].addr = info->size; 821 822 if (info->sp_offset != (CORE_ADDR) -1) 823 { 824 info->saved_regs[HARD_PC_REGNUM].addr = info->sp_offset; 825 frame_unwind_unsigned_register (next_frame, HARD_SP_REGNUM, &this_base); 826 prev_sp = this_base + info->sp_offset + 2; 827 this_base += STACK_CORRECTION; 828 } 829 else 830 { 831 /* The FP points at the last saved register. Adjust the FP back 832 to before the first saved register giving the SP. */ 833 prev_sp = this_base + info->size + 2; 834 835 this_base += STACK_CORRECTION; 836 if (soft_regs[SOFT_FP_REGNUM].name) 837 info->saved_regs[SOFT_FP_REGNUM].addr = info->size - 2; 838 } 839 840 if (info->return_kind == RETURN_RTC) 841 { 842 prev_sp += 1; 843 info->saved_regs[HARD_PAGE_REGNUM].addr = info->size; 844 info->saved_regs[HARD_PC_REGNUM].addr = info->size + 1; 845 } 846 else if (info->return_kind == RETURN_RTI) 847 { 848 prev_sp += 7; 849 info->saved_regs[HARD_CCR_REGNUM].addr = info->size; 850 info->saved_regs[HARD_D_REGNUM].addr = info->size + 1; 851 info->saved_regs[HARD_X_REGNUM].addr = info->size + 3; 852 info->saved_regs[HARD_Y_REGNUM].addr = info->size + 5; 853 info->saved_regs[HARD_PC_REGNUM].addr = info->size + 7; 854 } 855 856 /* Add 1 here to adjust for the post-decrement nature of the push 857 instruction.*/ 858 info->prev_sp = prev_sp; 859 860 info->base = this_base; 861 862 /* Adjust all the saved registers so that they contain addresses and not 863 offsets. */ 864 for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS - 1; i++) 865 if (trad_frame_addr_p (info->saved_regs, i)) 866 { 867 info->saved_regs[i].addr += this_base; 868 } 869 870 /* The previous frame's SP needed to be computed. Save the computed 871 value. */ 872 trad_frame_set_value (info->saved_regs, HARD_SP_REGNUM, info->prev_sp); 873 874 return info; 875} 876 877/* Given a GDB frame, determine the address of the calling function's 878 frame. This will be used to create a new GDB frame struct. */ 879 880static void 881m68hc11_frame_this_id (struct frame_info *next_frame, 882 void **this_prologue_cache, 883 struct frame_id *this_id) 884{ 885 struct m68hc11_unwind_cache *info 886 = m68hc11_frame_unwind_cache (next_frame, this_prologue_cache); 887 CORE_ADDR base; 888 CORE_ADDR func; 889 struct frame_id id; 890 891 /* The FUNC is easy. */ 892 func = frame_func_unwind (next_frame); 893 894 /* Hopefully the prologue analysis either correctly determined the 895 frame's base (which is the SP from the previous frame), or set 896 that base to "NULL". */ 897 base = info->prev_sp; 898 if (base == 0) 899 return; 900 901 id = frame_id_build (base, func); 902 (*this_id) = id; 903} 904 905static void 906m68hc11_frame_prev_register (struct frame_info *next_frame, 907 void **this_prologue_cache, 908 int regnum, int *optimizedp, 909 enum lval_type *lvalp, CORE_ADDR *addrp, 910 int *realnump, void *bufferp) 911{ 912 struct m68hc11_unwind_cache *info 913 = m68hc11_frame_unwind_cache (next_frame, this_prologue_cache); 914 915 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, 916 optimizedp, lvalp, addrp, realnump, bufferp); 917 918 if (regnum == HARD_PC_REGNUM) 919 { 920 /* Take into account the 68HC12 specific call (PC + page). */ 921 if (info->return_kind == RETURN_RTC 922 && *addrp >= 0x08000 && *addrp < 0x0c000 923 && USE_PAGE_REGISTER) 924 { 925 int page_optimized; 926 927 CORE_ADDR page; 928 929 trad_frame_get_prev_register (next_frame, info->saved_regs, 930 HARD_PAGE_REGNUM, &page_optimized, 931 0, &page, 0, 0); 932 *addrp -= 0x08000; 933 *addrp += ((page & 0x0ff) << 14); 934 *addrp += 0x1000000; 935 } 936 } 937} 938 939static const struct frame_unwind m68hc11_frame_unwind = { 940 NORMAL_FRAME, 941 m68hc11_frame_this_id, 942 m68hc11_frame_prev_register 943}; 944 945const struct frame_unwind * 946m68hc11_frame_sniffer (struct frame_info *next_frame) 947{ 948 return &m68hc11_frame_unwind; 949} 950 951static CORE_ADDR 952m68hc11_frame_base_address (struct frame_info *next_frame, void **this_cache) 953{ 954 struct m68hc11_unwind_cache *info 955 = m68hc11_frame_unwind_cache (next_frame, this_cache); 956 957 return info->base; 958} 959 960static CORE_ADDR 961m68hc11_frame_args_address (struct frame_info *next_frame, void **this_cache) 962{ 963 CORE_ADDR addr; 964 struct m68hc11_unwind_cache *info 965 = m68hc11_frame_unwind_cache (next_frame, this_cache); 966 967 addr = info->base + info->size; 968 if (info->return_kind == RETURN_RTC) 969 addr += 1; 970 else if (info->return_kind == RETURN_RTI) 971 addr += 7; 972 973 return addr; 974} 975 976static const struct frame_base m68hc11_frame_base = { 977 &m68hc11_frame_unwind, 978 m68hc11_frame_base_address, 979 m68hc11_frame_base_address, 980 m68hc11_frame_args_address 981}; 982 983static CORE_ADDR 984m68hc11_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) 985{ 986 ULONGEST sp; 987 frame_unwind_unsigned_register (next_frame, HARD_SP_REGNUM, &sp); 988 return sp; 989} 990 991/* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that 992 dummy frame. The frame ID's base needs to match the TOS value 993 saved by save_dummy_frame_tos(), and the PC match the dummy frame's 994 breakpoint. */ 995 996static struct frame_id 997m68hc11_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) 998{ 999 ULONGEST tos; 1000 CORE_ADDR pc = frame_pc_unwind (next_frame); 1001 1002 frame_unwind_unsigned_register (next_frame, SOFT_FP_REGNUM, &tos); 1003 tos += 2; 1004 return frame_id_build (tos, pc); 1005} 1006 1007 1008/* Get and print the register from the given frame. */ 1009static void 1010m68hc11_print_register (struct gdbarch *gdbarch, struct ui_file *file, 1011 struct frame_info *frame, int regno) 1012{ 1013 LONGEST rval; 1014 1015 if (regno == HARD_PC_REGNUM || regno == HARD_SP_REGNUM 1016 || regno == SOFT_FP_REGNUM || regno == M68HC12_HARD_PC_REGNUM) 1017 rval = get_frame_register_unsigned (frame, regno); 1018 else 1019 rval = get_frame_register_signed (frame, regno); 1020 1021 if (regno == HARD_A_REGNUM || regno == HARD_B_REGNUM 1022 || regno == HARD_CCR_REGNUM || regno == HARD_PAGE_REGNUM) 1023 { 1024 fprintf_filtered (file, "0x%02x ", (unsigned char) rval); 1025 if (regno != HARD_CCR_REGNUM) 1026 print_longest (file, 'd', 1, rval); 1027 } 1028 else 1029 { 1030 if (regno == HARD_PC_REGNUM && gdbarch_tdep (gdbarch)->use_page_register) 1031 { 1032 ULONGEST page; 1033 1034 page = get_frame_register_unsigned (frame, HARD_PAGE_REGNUM); 1035 fprintf_filtered (file, "0x%02x:%04x ", (unsigned) page, 1036 (unsigned) rval); 1037 } 1038 else 1039 { 1040 fprintf_filtered (file, "0x%04x ", (unsigned) rval); 1041 if (regno != HARD_PC_REGNUM && regno != HARD_SP_REGNUM 1042 && regno != SOFT_FP_REGNUM && regno != M68HC12_HARD_PC_REGNUM) 1043 print_longest (file, 'd', 1, rval); 1044 } 1045 } 1046 1047 if (regno == HARD_CCR_REGNUM) 1048 { 1049 /* CCR register */ 1050 int C, Z, N, V; 1051 unsigned char l = rval & 0xff; 1052 1053 fprintf_filtered (file, "%c%c%c%c%c%c%c%c ", 1054 l & M6811_S_BIT ? 'S' : '-', 1055 l & M6811_X_BIT ? 'X' : '-', 1056 l & M6811_H_BIT ? 'H' : '-', 1057 l & M6811_I_BIT ? 'I' : '-', 1058 l & M6811_N_BIT ? 'N' : '-', 1059 l & M6811_Z_BIT ? 'Z' : '-', 1060 l & M6811_V_BIT ? 'V' : '-', 1061 l & M6811_C_BIT ? 'C' : '-'); 1062 N = (l & M6811_N_BIT) != 0; 1063 Z = (l & M6811_Z_BIT) != 0; 1064 V = (l & M6811_V_BIT) != 0; 1065 C = (l & M6811_C_BIT) != 0; 1066 1067 /* Print flags following the h8300 */ 1068 if ((C | Z) == 0) 1069 fprintf_filtered (file, "u> "); 1070 else if ((C | Z) == 1) 1071 fprintf_filtered (file, "u<= "); 1072 else if (C == 0) 1073 fprintf_filtered (file, "u< "); 1074 1075 if (Z == 0) 1076 fprintf_filtered (file, "!= "); 1077 else 1078 fprintf_filtered (file, "== "); 1079 1080 if ((N ^ V) == 0) 1081 fprintf_filtered (file, ">= "); 1082 else 1083 fprintf_filtered (file, "< "); 1084 1085 if ((Z | (N ^ V)) == 0) 1086 fprintf_filtered (file, "> "); 1087 else 1088 fprintf_filtered (file, "<= "); 1089 } 1090} 1091 1092/* Same as 'info reg' but prints the registers in a different way. */ 1093static void 1094m68hc11_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, 1095 struct frame_info *frame, int regno, int cpregs) 1096{ 1097 if (regno >= 0) 1098 { 1099 const char *name = gdbarch_register_name (gdbarch, regno); 1100 1101 if (!name || !*name) 1102 return; 1103 1104 fprintf_filtered (file, "%-10s ", name); 1105 m68hc11_print_register (gdbarch, file, frame, regno); 1106 fprintf_filtered (file, "\n"); 1107 } 1108 else 1109 { 1110 int i, nr; 1111 1112 fprintf_filtered (file, "PC="); 1113 m68hc11_print_register (gdbarch, file, frame, HARD_PC_REGNUM); 1114 1115 fprintf_filtered (file, " SP="); 1116 m68hc11_print_register (gdbarch, file, frame, HARD_SP_REGNUM); 1117 1118 fprintf_filtered (file, " FP="); 1119 m68hc11_print_register (gdbarch, file, frame, SOFT_FP_REGNUM); 1120 1121 fprintf_filtered (file, "\nCCR="); 1122 m68hc11_print_register (gdbarch, file, frame, HARD_CCR_REGNUM); 1123 1124 fprintf_filtered (file, "\nD="); 1125 m68hc11_print_register (gdbarch, file, frame, HARD_D_REGNUM); 1126 1127 fprintf_filtered (file, " X="); 1128 m68hc11_print_register (gdbarch, file, frame, HARD_X_REGNUM); 1129 1130 fprintf_filtered (file, " Y="); 1131 m68hc11_print_register (gdbarch, file, frame, HARD_Y_REGNUM); 1132 1133 if (gdbarch_tdep (gdbarch)->use_page_register) 1134 { 1135 fprintf_filtered (file, "\nPage="); 1136 m68hc11_print_register (gdbarch, file, frame, HARD_PAGE_REGNUM); 1137 } 1138 fprintf_filtered (file, "\n"); 1139 1140 nr = 0; 1141 for (i = SOFT_D1_REGNUM; i < M68HC11_ALL_REGS; i++) 1142 { 1143 /* Skip registers which are not defined in the symbol table. */ 1144 if (soft_regs[i].name == 0) 1145 continue; 1146 1147 fprintf_filtered (file, "D%d=", i - SOFT_D1_REGNUM + 1); 1148 m68hc11_print_register (gdbarch, file, frame, i); 1149 nr++; 1150 if ((nr % 8) == 7) 1151 fprintf_filtered (file, "\n"); 1152 else 1153 fprintf_filtered (file, " "); 1154 } 1155 if (nr && (nr % 8) != 7) 1156 fprintf_filtered (file, "\n"); 1157 } 1158} 1159 1160/* Same as 'info reg' but prints the registers in a different way. */ 1161static void 1162show_regs (char *args, int from_tty) 1163{ 1164 m68hc11_print_registers_info (current_gdbarch, gdb_stdout, 1165 get_current_frame (), -1, 1); 1166} 1167 1168static CORE_ADDR 1169m68hc11_stack_align (CORE_ADDR addr) 1170{ 1171 return ((addr + 1) & -2); 1172} 1173 1174static CORE_ADDR 1175m68hc11_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 1176 struct regcache *regcache, CORE_ADDR bp_addr, 1177 int nargs, struct value **args, CORE_ADDR sp, 1178 int struct_return, CORE_ADDR struct_addr) 1179{ 1180 int argnum; 1181 int first_stack_argnum; 1182 struct type *type; 1183 char *val; 1184 int len; 1185 char buf[2]; 1186 1187 first_stack_argnum = 0; 1188 if (struct_return) 1189 { 1190 /* The struct is allocated on the stack and gdb used the stack 1191 pointer for the address of that struct. We must apply the 1192 stack offset on the address. */ 1193 regcache_cooked_write_unsigned (regcache, HARD_D_REGNUM, 1194 struct_addr + STACK_CORRECTION); 1195 } 1196 else if (nargs > 0) 1197 { 1198 type = VALUE_TYPE (args[0]); 1199 len = TYPE_LENGTH (type); 1200 1201 /* First argument is passed in D and X registers. */ 1202 if (len <= 4) 1203 { 1204 ULONGEST v; 1205 1206 v = extract_unsigned_integer (VALUE_CONTENTS (args[0]), len); 1207 first_stack_argnum = 1; 1208 1209 regcache_cooked_write_unsigned (regcache, HARD_D_REGNUM, v); 1210 if (len > 2) 1211 { 1212 v >>= 16; 1213 regcache_cooked_write_unsigned (regcache, HARD_X_REGNUM, v); 1214 } 1215 } 1216 } 1217 1218 for (argnum = nargs - 1; argnum >= first_stack_argnum; argnum--) 1219 { 1220 type = VALUE_TYPE (args[argnum]); 1221 len = TYPE_LENGTH (type); 1222 1223 if (len & 1) 1224 { 1225 static char zero = 0; 1226 1227 sp--; 1228 write_memory (sp, &zero, 1); 1229 } 1230 val = (char*) VALUE_CONTENTS (args[argnum]); 1231 sp -= len; 1232 write_memory (sp, val, len); 1233 } 1234 1235 /* Store return address. */ 1236 sp -= 2; 1237 store_unsigned_integer (buf, 2, bp_addr); 1238 write_memory (sp, buf, 2); 1239 1240 /* Finally, update the stack pointer... */ 1241 sp -= STACK_CORRECTION; 1242 regcache_cooked_write_unsigned (regcache, HARD_SP_REGNUM, sp); 1243 1244 /* ...and fake a frame pointer. */ 1245 regcache_cooked_write_unsigned (regcache, SOFT_FP_REGNUM, sp); 1246 1247 /* DWARF2/GCC uses the stack address *before* the function call as a 1248 frame's CFA. */ 1249 return sp + 2; 1250} 1251 1252 1253/* Return the GDB type object for the "standard" data type 1254 of data in register N. */ 1255 1256static struct type * 1257m68hc11_register_type (struct gdbarch *gdbarch, int reg_nr) 1258{ 1259 switch (reg_nr) 1260 { 1261 case HARD_PAGE_REGNUM: 1262 case HARD_A_REGNUM: 1263 case HARD_B_REGNUM: 1264 case HARD_CCR_REGNUM: 1265 return builtin_type_uint8; 1266 1267 case M68HC12_HARD_PC_REGNUM: 1268 return builtin_type_uint32; 1269 1270 default: 1271 return builtin_type_uint16; 1272 } 1273} 1274 1275static void 1276m68hc11_store_return_value (struct type *type, struct regcache *regcache, 1277 const void *valbuf) 1278{ 1279 int len; 1280 1281 len = TYPE_LENGTH (type); 1282 1283 /* First argument is passed in D and X registers. */ 1284 if (len <= 2) 1285 regcache_raw_write_part (regcache, HARD_D_REGNUM, 2 - len, len, valbuf); 1286 else if (len <= 4) 1287 { 1288 regcache_raw_write_part (regcache, HARD_X_REGNUM, 4 - len, 1289 len - 2, valbuf); 1290 regcache_raw_write (regcache, HARD_D_REGNUM, (char*) valbuf + (len - 2)); 1291 } 1292 else 1293 error ("return of value > 4 is not supported."); 1294} 1295 1296 1297/* Given a return value in `regcache' with a type `type', 1298 extract and copy its value into `valbuf'. */ 1299 1300static void 1301m68hc11_extract_return_value (struct type *type, struct regcache *regcache, 1302 void *valbuf) 1303{ 1304 int len = TYPE_LENGTH (type); 1305 char buf[M68HC11_REG_SIZE]; 1306 1307 regcache_raw_read (regcache, HARD_D_REGNUM, buf); 1308 switch (len) 1309 { 1310 case 1: 1311 memcpy (valbuf, buf + 1, 1); 1312 break; 1313 1314 case 2: 1315 memcpy (valbuf, buf, 2); 1316 break; 1317 1318 case 3: 1319 memcpy ((char*) valbuf + 1, buf, 2); 1320 regcache_raw_read (regcache, HARD_X_REGNUM, buf); 1321 memcpy (valbuf, buf + 1, 1); 1322 break; 1323 1324 case 4: 1325 memcpy ((char*) valbuf + 2, buf, 2); 1326 regcache_raw_read (regcache, HARD_X_REGNUM, buf); 1327 memcpy (valbuf, buf, 2); 1328 break; 1329 1330 default: 1331 error ("bad size for return value"); 1332 } 1333} 1334 1335enum return_value_convention 1336m68hc11_return_value (struct gdbarch *gdbarch, struct type *valtype, 1337 struct regcache *regcache, void *readbuf, 1338 const void *writebuf) 1339{ 1340 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT 1341 || TYPE_CODE (valtype) == TYPE_CODE_UNION 1342 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY 1343 || TYPE_LENGTH (valtype) > 4) 1344 return RETURN_VALUE_STRUCT_CONVENTION; 1345 else 1346 { 1347 if (readbuf != NULL) 1348 m68hc11_extract_return_value (valtype, regcache, readbuf); 1349 if (writebuf != NULL) 1350 m68hc11_store_return_value (valtype, regcache, writebuf); 1351 return RETURN_VALUE_REGISTER_CONVENTION; 1352 } 1353} 1354 1355/* Test whether the ELF symbol corresponds to a function using rtc or 1356 rti to return. */ 1357 1358static void 1359m68hc11_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) 1360{ 1361 unsigned char flags; 1362 1363 flags = ((elf_symbol_type *)sym)->internal_elf_sym.st_other; 1364 if (flags & STO_M68HC12_FAR) 1365 MSYMBOL_SET_RTC (msym); 1366 if (flags & STO_M68HC12_INTERRUPT) 1367 MSYMBOL_SET_RTI (msym); 1368} 1369 1370static int 1371gdb_print_insn_m68hc11 (bfd_vma memaddr, disassemble_info *info) 1372{ 1373 if (TARGET_ARCHITECTURE->arch == bfd_arch_m68hc11) 1374 return print_insn_m68hc11 (memaddr, info); 1375 else 1376 return print_insn_m68hc12 (memaddr, info); 1377} 1378 1379 1380 1381/* 68HC11/68HC12 register groups. 1382 Identify real hard registers and soft registers used by gcc. */ 1383 1384static struct reggroup *m68hc11_soft_reggroup; 1385static struct reggroup *m68hc11_hard_reggroup; 1386 1387static void 1388m68hc11_init_reggroups (void) 1389{ 1390 m68hc11_hard_reggroup = reggroup_new ("hard", USER_REGGROUP); 1391 m68hc11_soft_reggroup = reggroup_new ("soft", USER_REGGROUP); 1392} 1393 1394static void 1395m68hc11_add_reggroups (struct gdbarch *gdbarch) 1396{ 1397 reggroup_add (gdbarch, m68hc11_hard_reggroup); 1398 reggroup_add (gdbarch, m68hc11_soft_reggroup); 1399 reggroup_add (gdbarch, general_reggroup); 1400 reggroup_add (gdbarch, float_reggroup); 1401 reggroup_add (gdbarch, all_reggroup); 1402 reggroup_add (gdbarch, save_reggroup); 1403 reggroup_add (gdbarch, restore_reggroup); 1404 reggroup_add (gdbarch, vector_reggroup); 1405 reggroup_add (gdbarch, system_reggroup); 1406} 1407 1408static int 1409m68hc11_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 1410 struct reggroup *group) 1411{ 1412 /* We must save the real hard register as well as gcc 1413 soft registers including the frame pointer. */ 1414 if (group == save_reggroup || group == restore_reggroup) 1415 { 1416 return (regnum <= gdbarch_num_regs (gdbarch) 1417 || ((regnum == SOFT_FP_REGNUM 1418 || regnum == SOFT_TMP_REGNUM 1419 || regnum == SOFT_ZS_REGNUM 1420 || regnum == SOFT_XY_REGNUM) 1421 && m68hc11_register_name (regnum))); 1422 } 1423 1424 /* Group to identify gcc soft registers (d1..dN). */ 1425 if (group == m68hc11_soft_reggroup) 1426 { 1427 return regnum >= SOFT_D1_REGNUM && m68hc11_register_name (regnum); 1428 } 1429 1430 if (group == m68hc11_hard_reggroup) 1431 { 1432 return regnum == HARD_PC_REGNUM || regnum == HARD_SP_REGNUM 1433 || regnum == HARD_X_REGNUM || regnum == HARD_D_REGNUM 1434 || regnum == HARD_Y_REGNUM || regnum == HARD_CCR_REGNUM; 1435 } 1436 return default_register_reggroup_p (gdbarch, regnum, group); 1437} 1438 1439static struct gdbarch * 1440m68hc11_gdbarch_init (struct gdbarch_info info, 1441 struct gdbarch_list *arches) 1442{ 1443 struct gdbarch *gdbarch; 1444 struct gdbarch_tdep *tdep; 1445 int elf_flags; 1446 1447 soft_reg_initialized = 0; 1448 1449 /* Extract the elf_flags if available. */ 1450 if (info.abfd != NULL 1451 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) 1452 elf_flags = elf_elfheader (info.abfd)->e_flags; 1453 else 1454 elf_flags = 0; 1455 1456 /* try to find a pre-existing architecture */ 1457 for (arches = gdbarch_list_lookup_by_info (arches, &info); 1458 arches != NULL; 1459 arches = gdbarch_list_lookup_by_info (arches->next, &info)) 1460 { 1461 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) 1462 continue; 1463 1464 return arches->gdbarch; 1465 } 1466 1467 /* Need a new architecture. Fill in a target specific vector. */ 1468 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); 1469 gdbarch = gdbarch_alloc (&info, tdep); 1470 tdep->elf_flags = elf_flags; 1471 1472 switch (info.bfd_arch_info->arch) 1473 { 1474 case bfd_arch_m68hc11: 1475 tdep->stack_correction = 1; 1476 tdep->use_page_register = 0; 1477 tdep->prologue = m6811_prologue; 1478 set_gdbarch_addr_bit (gdbarch, 16); 1479 set_gdbarch_num_pseudo_regs (gdbarch, M68HC11_NUM_PSEUDO_REGS); 1480 set_gdbarch_pc_regnum (gdbarch, HARD_PC_REGNUM); 1481 set_gdbarch_num_regs (gdbarch, M68HC11_NUM_REGS); 1482 break; 1483 1484 case bfd_arch_m68hc12: 1485 tdep->stack_correction = 0; 1486 tdep->use_page_register = elf_flags & E_M68HC12_BANKS; 1487 tdep->prologue = m6812_prologue; 1488 set_gdbarch_addr_bit (gdbarch, elf_flags & E_M68HC12_BANKS ? 32 : 16); 1489 set_gdbarch_num_pseudo_regs (gdbarch, 1490 elf_flags & E_M68HC12_BANKS 1491 ? M68HC12_NUM_PSEUDO_REGS 1492 : M68HC11_NUM_PSEUDO_REGS); 1493 set_gdbarch_pc_regnum (gdbarch, elf_flags & E_M68HC12_BANKS 1494 ? M68HC12_HARD_PC_REGNUM : HARD_PC_REGNUM); 1495 set_gdbarch_num_regs (gdbarch, elf_flags & E_M68HC12_BANKS 1496 ? M68HC12_NUM_REGS : M68HC11_NUM_REGS); 1497 break; 1498 1499 default: 1500 break; 1501 } 1502 1503 /* Initially set everything according to the ABI. 1504 Use 16-bit integers since it will be the case for most 1505 programs. The size of these types should normally be set 1506 according to the dwarf2 debug information. */ 1507 set_gdbarch_short_bit (gdbarch, 16); 1508 set_gdbarch_int_bit (gdbarch, elf_flags & E_M68HC11_I32 ? 32 : 16); 1509 set_gdbarch_float_bit (gdbarch, 32); 1510 set_gdbarch_double_bit (gdbarch, elf_flags & E_M68HC11_F64 ? 64 : 32); 1511 set_gdbarch_long_double_bit (gdbarch, 64); 1512 set_gdbarch_long_bit (gdbarch, 32); 1513 set_gdbarch_ptr_bit (gdbarch, 16); 1514 set_gdbarch_long_long_bit (gdbarch, 64); 1515 1516 /* Characters are unsigned. */ 1517 set_gdbarch_char_signed (gdbarch, 0); 1518 1519 set_gdbarch_unwind_pc (gdbarch, m68hc11_unwind_pc); 1520 set_gdbarch_unwind_sp (gdbarch, m68hc11_unwind_sp); 1521 1522 /* Set register info. */ 1523 set_gdbarch_fp0_regnum (gdbarch, -1); 1524 1525 set_gdbarch_write_pc (gdbarch, generic_target_write_pc); 1526 1527 set_gdbarch_sp_regnum (gdbarch, HARD_SP_REGNUM); 1528 set_gdbarch_register_name (gdbarch, m68hc11_register_name); 1529 set_gdbarch_register_type (gdbarch, m68hc11_register_type); 1530 set_gdbarch_pseudo_register_read (gdbarch, m68hc11_pseudo_register_read); 1531 set_gdbarch_pseudo_register_write (gdbarch, m68hc11_pseudo_register_write); 1532 1533 set_gdbarch_push_dummy_call (gdbarch, m68hc11_push_dummy_call); 1534 1535 set_gdbarch_return_value (gdbarch, m68hc11_return_value); 1536 set_gdbarch_skip_prologue (gdbarch, m68hc11_skip_prologue); 1537 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 1538 set_gdbarch_breakpoint_from_pc (gdbarch, m68hc11_breakpoint_from_pc); 1539 set_gdbarch_deprecated_stack_align (gdbarch, m68hc11_stack_align); 1540 set_gdbarch_print_insn (gdbarch, gdb_print_insn_m68hc11); 1541 1542 m68hc11_add_reggroups (gdbarch); 1543 set_gdbarch_register_reggroup_p (gdbarch, m68hc11_register_reggroup_p); 1544 set_gdbarch_print_registers_info (gdbarch, m68hc11_print_registers_info); 1545 1546 /* Hook in the DWARF CFI frame unwinder. */ 1547 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); 1548 1549 frame_unwind_append_sniffer (gdbarch, m68hc11_frame_sniffer); 1550 frame_base_set_default (gdbarch, &m68hc11_frame_base); 1551 1552 /* Methods for saving / extracting a dummy frame's ID. The ID's 1553 stack address must match the SP value returned by 1554 PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ 1555 set_gdbarch_unwind_dummy_id (gdbarch, m68hc11_unwind_dummy_id); 1556 1557 /* Return the unwound PC value. */ 1558 set_gdbarch_unwind_pc (gdbarch, m68hc11_unwind_pc); 1559 1560 /* Minsymbol frobbing. */ 1561 set_gdbarch_elf_make_msymbol_special (gdbarch, 1562 m68hc11_elf_make_msymbol_special); 1563 1564 set_gdbarch_believe_pcc_promotion (gdbarch, 1); 1565 1566 return gdbarch; 1567} 1568 1569extern initialize_file_ftype _initialize_m68hc11_tdep; /* -Wmissing-prototypes */ 1570 1571void 1572_initialize_m68hc11_tdep (void) 1573{ 1574 register_gdbarch_init (bfd_arch_m68hc11, m68hc11_gdbarch_init); 1575 register_gdbarch_init (bfd_arch_m68hc12, m68hc11_gdbarch_init); 1576 m68hc11_init_reggroups (); 1577 1578 deprecate_cmd (add_com ("regs", class_vars, show_regs, 1579 "Print all registers"), 1580 "info registers"); 1581} 1582 1583