1/* Target-dependent code for Renesas M32R, for GDB. 2 3 Copyright 1996, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software 4 Foundation, Inc. 5 6 This file is part of GDB. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 59 Temple Place - Suite 330, 21 Boston, MA 02111-1307, USA. */ 22 23#include "defs.h" 24#include "frame.h" 25#include "frame-unwind.h" 26#include "frame-base.h" 27#include "symtab.h" 28#include "gdbtypes.h" 29#include "gdbcmd.h" 30#include "gdbcore.h" 31#include "gdb_string.h" 32#include "value.h" 33#include "inferior.h" 34#include "symfile.h" 35#include "objfiles.h" 36#include "osabi.h" 37#include "language.h" 38#include "arch-utils.h" 39#include "regcache.h" 40#include "trad-frame.h" 41#include "dis-asm.h" 42 43#include "gdb_assert.h" 44 45#include "m32r-tdep.h" 46 47/* Local functions */ 48 49extern void _initialize_m32r_tdep (void); 50 51static CORE_ADDR 52m32r_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) 53{ 54 /* Align to the size of an instruction (so that they can safely be 55 pushed onto the stack. */ 56 return sp & ~3; 57} 58 59 60/* Breakpoints 61 62 The little endian mode of M32R is unique. In most of architectures, 63 two 16-bit instructions, A and B, are placed as the following: 64 65 Big endian: 66 A0 A1 B0 B1 67 68 Little endian: 69 A1 A0 B1 B0 70 71 In M32R, they are placed like this: 72 73 Big endian: 74 A0 A1 B0 B1 75 76 Little endian: 77 B1 B0 A1 A0 78 79 This is because M32R always fetches instructions in 32-bit. 80 81 The following functions take care of this behavior. */ 82 83static int 84m32r_memory_insert_breakpoint (CORE_ADDR addr, char *contents_cache) 85{ 86 int val; 87 char buf[4]; 88 char bp_entry[] = { 0x10, 0xf1 }; /* dpt */ 89 90 /* Save the memory contents. */ 91 val = target_read_memory (addr & 0xfffffffc, contents_cache, 4); 92 if (val != 0) 93 return val; /* return error */ 94 95 /* Determine appropriate breakpoint contents and size for this address. */ 96 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 97 { 98 if ((addr & 3) == 0) 99 { 100 buf[0] = bp_entry[0]; 101 buf[1] = bp_entry[1]; 102 buf[2] = contents_cache[2] & 0x7f; 103 buf[3] = contents_cache[3]; 104 } 105 else 106 { 107 buf[0] = contents_cache[0]; 108 buf[1] = contents_cache[1]; 109 buf[2] = bp_entry[0]; 110 buf[3] = bp_entry[1]; 111 } 112 } 113 else /* little-endian */ 114 { 115 if ((addr & 3) == 0) 116 { 117 buf[0] = contents_cache[0]; 118 buf[1] = contents_cache[1] & 0x7f; 119 buf[2] = bp_entry[1]; 120 buf[3] = bp_entry[0]; 121 } 122 else 123 { 124 buf[0] = bp_entry[1]; 125 buf[1] = bp_entry[0]; 126 buf[2] = contents_cache[2]; 127 buf[3] = contents_cache[3]; 128 } 129 } 130 131 /* Write the breakpoint. */ 132 val = target_write_memory (addr & 0xfffffffc, buf, 4); 133 return val; 134} 135 136static int 137m32r_memory_remove_breakpoint (CORE_ADDR addr, char *contents_cache) 138{ 139 int val; 140 char buf[4]; 141 142 buf[0] = contents_cache[0]; 143 buf[1] = contents_cache[1]; 144 buf[2] = contents_cache[2]; 145 buf[3] = contents_cache[3]; 146 147 /* Remove parallel bit. */ 148 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 149 { 150 if ((buf[0] & 0x80) == 0 && (buf[2] & 0x80) != 0) 151 buf[2] &= 0x7f; 152 } 153 else /* little-endian */ 154 { 155 if ((buf[3] & 0x80) == 0 && (buf[1] & 0x80) != 0) 156 buf[1] &= 0x7f; 157 } 158 159 /* Write contents. */ 160 val = target_write_memory (addr & 0xfffffffc, buf, 4); 161 return val; 162} 163 164static const unsigned char * 165m32r_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) 166{ 167 static char be_bp_entry[] = { 0x10, 0xf1, 0x70, 0x00 }; /* dpt -> nop */ 168 static char le_bp_entry[] = { 0x00, 0x70, 0xf1, 0x10 }; /* dpt -> nop */ 169 unsigned char *bp; 170 171 /* Determine appropriate breakpoint. */ 172 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 173 { 174 if ((*pcptr & 3) == 0) 175 { 176 bp = be_bp_entry; 177 *lenptr = 4; 178 } 179 else 180 { 181 bp = be_bp_entry; 182 *lenptr = 2; 183 } 184 } 185 else 186 { 187 if ((*pcptr & 3) == 0) 188 { 189 bp = le_bp_entry; 190 *lenptr = 4; 191 } 192 else 193 { 194 bp = le_bp_entry + 2; 195 *lenptr = 2; 196 } 197 } 198 199 return bp; 200} 201 202 203char *m32r_register_names[] = { 204 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 205 "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", 206 "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch", 207 "evb" 208}; 209 210static const char * 211m32r_register_name (int reg_nr) 212{ 213 if (reg_nr < 0) 214 return NULL; 215 if (reg_nr >= M32R_NUM_REGS) 216 return NULL; 217 return m32r_register_names[reg_nr]; 218} 219 220 221/* Return the GDB type object for the "standard" data type 222 of data in register N. */ 223 224static struct type * 225m32r_register_type (struct gdbarch *gdbarch, int reg_nr) 226{ 227 if (reg_nr == M32R_PC_REGNUM) 228 return builtin_type_void_func_ptr; 229 else if (reg_nr == M32R_SP_REGNUM || reg_nr == M32R_FP_REGNUM) 230 return builtin_type_void_data_ptr; 231 else 232 return builtin_type_int32; 233} 234 235 236/* Write into appropriate registers a function return value 237 of type TYPE, given in virtual format. 238 239 Things always get returned in RET1_REGNUM, RET2_REGNUM. */ 240 241static void 242m32r_store_return_value (struct type *type, struct regcache *regcache, 243 const void *valbuf) 244{ 245 CORE_ADDR regval; 246 int len = TYPE_LENGTH (type); 247 248 regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len); 249 regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval); 250 251 if (len > 4) 252 { 253 regval = extract_unsigned_integer ((char *) valbuf + 4, len - 4); 254 regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval); 255 } 256} 257 258/* This is required by skip_prologue. The results of decoding a prologue 259 should be cached because this thrashing is getting nuts. */ 260 261static int 262decode_prologue (CORE_ADDR start_pc, CORE_ADDR scan_limit, 263 CORE_ADDR *pl_endptr, unsigned long *framelength) 264{ 265 unsigned long framesize; 266 int insn; 267 int op1; 268 CORE_ADDR after_prologue = 0; 269 CORE_ADDR after_push = 0; 270 CORE_ADDR after_stack_adjust = 0; 271 CORE_ADDR current_pc; 272 LONGEST return_value; 273 274 framesize = 0; 275 after_prologue = 0; 276 277 for (current_pc = start_pc; current_pc < scan_limit; current_pc += 2) 278 { 279 /* Check if current pc's location is readable. */ 280 if (!safe_read_memory_integer (current_pc, 2, &return_value)) 281 return -1; 282 283 insn = read_memory_unsigned_integer (current_pc, 2); 284 285 if (insn == 0x0000) 286 break; 287 288 /* If this is a 32 bit instruction, we dont want to examine its 289 immediate data as though it were an instruction */ 290 if (current_pc & 0x02) 291 { 292 /* decode this instruction further */ 293 insn &= 0x7fff; 294 } 295 else 296 { 297 if (insn & 0x8000) 298 { 299 if (current_pc == scan_limit) 300 scan_limit += 2; /* extend the search */ 301 302 current_pc += 2; /* skip the immediate data */ 303 304 /* Check if current pc's location is readable. */ 305 if (!safe_read_memory_integer (current_pc, 2, &return_value)) 306 return -1; 307 308 if (insn == 0x8faf) /* add3 sp, sp, xxxx */ 309 /* add 16 bit sign-extended offset */ 310 { 311 framesize += 312 -((short) read_memory_unsigned_integer (current_pc, 2)); 313 } 314 else 315 { 316 if (((insn >> 8) == 0xe4) /* ld24 r4, xxxxxx; sub sp, r4 */ 317 && safe_read_memory_integer (current_pc + 2, 2, 318 &return_value) 319 && read_memory_unsigned_integer (current_pc + 2, 320 2) == 0x0f24) 321 /* subtract 24 bit sign-extended negative-offset */ 322 { 323 insn = read_memory_unsigned_integer (current_pc - 2, 4); 324 if (insn & 0x00800000) /* sign extend */ 325 insn |= 0xff000000; /* negative */ 326 else 327 insn &= 0x00ffffff; /* positive */ 328 framesize += insn; 329 } 330 } 331 after_push = current_pc + 2; 332 continue; 333 } 334 } 335 op1 = insn & 0xf000; /* isolate just the first nibble */ 336 337 if ((insn & 0xf0ff) == 0x207f) 338 { /* st reg, @-sp */ 339 int regno; 340 framesize += 4; 341 regno = ((insn >> 8) & 0xf); 342 after_prologue = 0; 343 continue; 344 } 345 if ((insn >> 8) == 0x4f) /* addi sp, xx */ 346 /* add 8 bit sign-extended offset */ 347 { 348 int stack_adjust = (char) (insn & 0xff); 349 350 /* there are probably two of these stack adjustments: 351 1) A negative one in the prologue, and 352 2) A positive one in the epilogue. 353 We are only interested in the first one. */ 354 355 if (stack_adjust < 0) 356 { 357 framesize -= stack_adjust; 358 after_prologue = 0; 359 /* A frameless function may have no "mv fp, sp". 360 In that case, this is the end of the prologue. */ 361 after_stack_adjust = current_pc + 2; 362 } 363 continue; 364 } 365 if (insn == 0x1d8f) 366 { /* mv fp, sp */ 367 after_prologue = current_pc + 2; 368 break; /* end of stack adjustments */ 369 } 370 371 /* Nop looks like a branch, continue explicitly */ 372 if (insn == 0x7000) 373 { 374 after_prologue = current_pc + 2; 375 continue; /* nop occurs between pushes */ 376 } 377 /* End of prolog if any of these are trap instructions */ 378 if ((insn & 0xfff0) == 0x10f0) 379 { 380 after_prologue = current_pc; 381 break; 382 } 383 /* End of prolog if any of these are branch instructions */ 384 if ((op1 == 0x7000) || (op1 == 0xb000) || (op1 == 0xf000)) 385 { 386 after_prologue = current_pc; 387 continue; 388 } 389 /* Some of the branch instructions are mixed with other types */ 390 if (op1 == 0x1000) 391 { 392 int subop = insn & 0x0ff0; 393 if ((subop == 0x0ec0) || (subop == 0x0fc0)) 394 { 395 after_prologue = current_pc; 396 continue; /* jmp , jl */ 397 } 398 } 399 } 400 401 if (framelength) 402 *framelength = framesize; 403 404 if (current_pc >= scan_limit) 405 { 406 if (pl_endptr) 407 { 408 if (after_stack_adjust != 0) 409 /* We did not find a "mv fp,sp", but we DID find 410 a stack_adjust. Is it safe to use that as the 411 end of the prologue? I just don't know. */ 412 { 413 *pl_endptr = after_stack_adjust; 414 } 415 else if (after_push != 0) 416 /* We did not find a "mv fp,sp", but we DID find 417 a push. Is it safe to use that as the 418 end of the prologue? I just don't know. */ 419 { 420 *pl_endptr = after_push; 421 } 422 else 423 /* We reached the end of the loop without finding the end 424 of the prologue. No way to win -- we should report failure. 425 The way we do that is to return the original start_pc. 426 GDB will set a breakpoint at the start of the function (etc.) */ 427 *pl_endptr = start_pc; 428 } 429 return 0; 430 } 431 432 if (after_prologue == 0) 433 after_prologue = current_pc; 434 435 if (pl_endptr) 436 *pl_endptr = after_prologue; 437 438 return 0; 439} /* decode_prologue */ 440 441/* Function: skip_prologue 442 Find end of function prologue */ 443 444#define DEFAULT_SEARCH_LIMIT 128 445 446CORE_ADDR 447m32r_skip_prologue (CORE_ADDR pc) 448{ 449 CORE_ADDR func_addr, func_end; 450 struct symtab_and_line sal; 451 LONGEST return_value; 452 453 /* See what the symbol table says */ 454 455 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 456 { 457 sal = find_pc_line (func_addr, 0); 458 459 if (sal.line != 0 && sal.end <= func_end) 460 { 461 func_end = sal.end; 462 } 463 else 464 /* Either there's no line info, or the line after the prologue is after 465 the end of the function. In this case, there probably isn't a 466 prologue. */ 467 { 468 func_end = min (func_end, func_addr + DEFAULT_SEARCH_LIMIT); 469 } 470 } 471 else 472 func_end = pc + DEFAULT_SEARCH_LIMIT; 473 474 /* If pc's location is not readable, just quit. */ 475 if (!safe_read_memory_integer (pc, 4, &return_value)) 476 return pc; 477 478 /* Find the end of prologue. */ 479 if (decode_prologue (pc, func_end, &sal.end, NULL) < 0) 480 return pc; 481 482 return sal.end; 483} 484 485struct m32r_unwind_cache 486{ 487 /* The previous frame's inner most stack address. Used as this 488 frame ID's stack_addr. */ 489 CORE_ADDR prev_sp; 490 /* The frame's base, optionally used by the high-level debug info. */ 491 CORE_ADDR base; 492 int size; 493 /* How far the SP and r13 (FP) have been offset from the start of 494 the stack frame (as defined by the previous frame's stack 495 pointer). */ 496 LONGEST sp_offset; 497 LONGEST r13_offset; 498 int uses_frame; 499 /* Table indicating the location of each and every register. */ 500 struct trad_frame_saved_reg *saved_regs; 501}; 502 503/* Put here the code to store, into fi->saved_regs, the addresses of 504 the saved registers of frame described by FRAME_INFO. This 505 includes special registers such as pc and fp saved in special ways 506 in the stack frame. sp is even more special: the address we return 507 for it IS the sp for the next frame. */ 508 509static struct m32r_unwind_cache * 510m32r_frame_unwind_cache (struct frame_info *next_frame, 511 void **this_prologue_cache) 512{ 513 CORE_ADDR pc, scan_limit; 514 ULONGEST prev_sp; 515 ULONGEST this_base; 516 unsigned long op, op2; 517 int i; 518 struct m32r_unwind_cache *info; 519 520 521 if ((*this_prologue_cache)) 522 return (*this_prologue_cache); 523 524 info = FRAME_OBSTACK_ZALLOC (struct m32r_unwind_cache); 525 (*this_prologue_cache) = info; 526 info->saved_regs = trad_frame_alloc_saved_regs (next_frame); 527 528 info->size = 0; 529 info->sp_offset = 0; 530 info->uses_frame = 0; 531 532 scan_limit = frame_pc_unwind (next_frame); 533 for (pc = frame_func_unwind (next_frame); 534 pc > 0 && pc < scan_limit; pc += 2) 535 { 536 if ((pc & 2) == 0) 537 { 538 op = get_frame_memory_unsigned (next_frame, pc, 4); 539 if ((op & 0x80000000) == 0x80000000) 540 { 541 /* 32-bit instruction */ 542 if ((op & 0xffff0000) == 0x8faf0000) 543 { 544 /* add3 sp,sp,xxxx */ 545 short n = op & 0xffff; 546 info->sp_offset += n; 547 } 548 else if (((op >> 8) == 0xe4) 549 && get_frame_memory_unsigned (next_frame, pc + 2, 550 2) == 0x0f24) 551 { 552 /* ld24 r4, xxxxxx; sub sp, r4 */ 553 unsigned long n = op & 0xffffff; 554 info->sp_offset += n; 555 pc += 2; /* skip sub instruction */ 556 } 557 558 if (pc == scan_limit) 559 scan_limit += 2; /* extend the search */ 560 pc += 2; /* skip the immediate data */ 561 continue; 562 } 563 } 564 565 /* 16-bit instructions */ 566 op = get_frame_memory_unsigned (next_frame, pc, 2) & 0x7fff; 567 if ((op & 0xf0ff) == 0x207f) 568 { 569 /* st rn, @-sp */ 570 int regno = ((op >> 8) & 0xf); 571 info->sp_offset -= 4; 572 info->saved_regs[regno].addr = info->sp_offset; 573 } 574 else if ((op & 0xff00) == 0x4f00) 575 { 576 /* addi sp, xx */ 577 int n = (char) (op & 0xff); 578 info->sp_offset += n; 579 } 580 else if (op == 0x1d8f) 581 { 582 /* mv fp, sp */ 583 info->uses_frame = 1; 584 info->r13_offset = info->sp_offset; 585 break; /* end of stack adjustments */ 586 } 587 else if ((op & 0xfff0) == 0x10f0) 588 { 589 /* end of prologue if this is a trap instruction */ 590 break; /* end of stack adjustments */ 591 } 592 } 593 594 info->size = -info->sp_offset; 595 596 /* Compute the previous frame's stack pointer (which is also the 597 frame's ID's stack address), and this frame's base pointer. */ 598 if (info->uses_frame) 599 { 600 /* The SP was moved to the FP. This indicates that a new frame 601 was created. Get THIS frame's FP value by unwinding it from 602 the next frame. */ 603 this_base = frame_unwind_register_unsigned (next_frame, M32R_FP_REGNUM); 604 /* The FP points at the last saved register. Adjust the FP back 605 to before the first saved register giving the SP. */ 606 prev_sp = this_base + info->size; 607 } 608 else 609 { 610 /* Assume that the FP is this frame's SP but with that pushed 611 stack space added back. */ 612 this_base = frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM); 613 prev_sp = this_base + info->size; 614 } 615 616 /* Convert that SP/BASE into real addresses. */ 617 info->prev_sp = prev_sp; 618 info->base = this_base; 619 620 /* Adjust all the saved registers so that they contain addresses and 621 not offsets. */ 622 for (i = 0; i < NUM_REGS - 1; i++) 623 if (trad_frame_addr_p (info->saved_regs, i)) 624 info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr); 625 626 /* The call instruction moves the caller's PC in the callee's LR. 627 Since this is an unwind, do the reverse. Copy the location of LR 628 into PC (the address / regnum) so that a request for PC will be 629 converted into a request for the LR. */ 630 info->saved_regs[M32R_PC_REGNUM] = info->saved_regs[LR_REGNUM]; 631 632 /* The previous frame's SP needed to be computed. Save the computed 633 value. */ 634 trad_frame_set_value (info->saved_regs, M32R_SP_REGNUM, prev_sp); 635 636 return info; 637} 638 639static CORE_ADDR 640m32r_read_pc (ptid_t ptid) 641{ 642 ptid_t save_ptid; 643 ULONGEST pc; 644 645 save_ptid = inferior_ptid; 646 inferior_ptid = ptid; 647 regcache_cooked_read_unsigned (current_regcache, M32R_PC_REGNUM, &pc); 648 inferior_ptid = save_ptid; 649 return pc; 650} 651 652static void 653m32r_write_pc (CORE_ADDR val, ptid_t ptid) 654{ 655 ptid_t save_ptid; 656 657 save_ptid = inferior_ptid; 658 inferior_ptid = ptid; 659 write_register (M32R_PC_REGNUM, val); 660 inferior_ptid = save_ptid; 661} 662 663static CORE_ADDR 664m32r_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) 665{ 666 return frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM); 667} 668 669 670static CORE_ADDR 671m32r_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 672 struct regcache *regcache, CORE_ADDR bp_addr, int nargs, 673 struct value **args, CORE_ADDR sp, int struct_return, 674 CORE_ADDR struct_addr) 675{ 676 int stack_offset, stack_alloc; 677 int argreg = ARG1_REGNUM; 678 int argnum; 679 struct type *type; 680 enum type_code typecode; 681 CORE_ADDR regval; 682 char *val; 683 char valbuf[MAX_REGISTER_SIZE]; 684 int len; 685 int odd_sized_struct; 686 687 /* first force sp to a 4-byte alignment */ 688 sp = sp & ~3; 689 690 /* Set the return address. For the m32r, the return breakpoint is 691 always at BP_ADDR. */ 692 regcache_cooked_write_unsigned (regcache, LR_REGNUM, bp_addr); 693 694 /* If STRUCT_RETURN is true, then the struct return address (in 695 STRUCT_ADDR) will consume the first argument-passing register. 696 Both adjust the register count and store that value. */ 697 if (struct_return) 698 { 699 regcache_cooked_write_unsigned (regcache, argreg, struct_addr); 700 argreg++; 701 } 702 703 /* Now make sure there's space on the stack */ 704 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) 705 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3); 706 sp -= stack_alloc; /* make room on stack for args */ 707 708 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) 709 { 710 type = VALUE_TYPE (args[argnum]); 711 typecode = TYPE_CODE (type); 712 len = TYPE_LENGTH (type); 713 714 memset (valbuf, 0, sizeof (valbuf)); 715 716 /* Passes structures that do not fit in 2 registers by reference. */ 717 if (len > 8 718 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) 719 { 720 store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (args[argnum])); 721 typecode = TYPE_CODE_PTR; 722 len = 4; 723 val = valbuf; 724 } 725 else if (len < 4) 726 { 727 /* value gets right-justified in the register or stack word */ 728 memcpy (valbuf + (register_size (gdbarch, argreg) - len), 729 (char *) VALUE_CONTENTS (args[argnum]), len); 730 val = valbuf; 731 } 732 else 733 val = (char *) VALUE_CONTENTS (args[argnum]); 734 735 while (len > 0) 736 { 737 if (argreg > ARGN_REGNUM) 738 { 739 /* must go on the stack */ 740 write_memory (sp + stack_offset, val, 4); 741 stack_offset += 4; 742 } 743 else if (argreg <= ARGN_REGNUM) 744 { 745 /* there's room in a register */ 746 regval = 747 extract_unsigned_integer (val, 748 register_size (gdbarch, argreg)); 749 regcache_cooked_write_unsigned (regcache, argreg++, regval); 750 } 751 752 /* Store the value 4 bytes at a time. This means that things 753 larger than 4 bytes may go partly in registers and partly 754 on the stack. */ 755 len -= register_size (gdbarch, argreg); 756 val += register_size (gdbarch, argreg); 757 } 758 } 759 760 /* Finally, update the SP register. */ 761 regcache_cooked_write_unsigned (regcache, M32R_SP_REGNUM, sp); 762 763 return sp; 764} 765 766 767/* Given a return value in `regbuf' with a type `valtype', 768 extract and copy its value into `valbuf'. */ 769 770static void 771m32r_extract_return_value (struct type *type, struct regcache *regcache, 772 void *dst) 773{ 774 bfd_byte *valbuf = dst; 775 int len = TYPE_LENGTH (type); 776 ULONGEST tmp; 777 778 /* By using store_unsigned_integer we avoid having to do 779 anything special for small big-endian values. */ 780 regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp); 781 store_unsigned_integer (valbuf, (len > 4 ? len - 4 : len), tmp); 782 783 /* Ignore return values more than 8 bytes in size because the m32r 784 returns anything more than 8 bytes in the stack. */ 785 if (len > 4) 786 { 787 regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp); 788 store_unsigned_integer (valbuf + len - 4, 4, tmp); 789 } 790} 791 792enum return_value_convention 793m32r_return_value (struct gdbarch *gdbarch, struct type *valtype, 794 struct regcache *regcache, void *readbuf, 795 const void *writebuf) 796{ 797 if (TYPE_LENGTH (valtype) > 8) 798 return RETURN_VALUE_STRUCT_CONVENTION; 799 else 800 { 801 if (readbuf != NULL) 802 m32r_extract_return_value (valtype, regcache, readbuf); 803 if (writebuf != NULL) 804 m32r_store_return_value (valtype, regcache, writebuf); 805 return RETURN_VALUE_REGISTER_CONVENTION; 806 } 807} 808 809 810 811static CORE_ADDR 812m32r_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 813{ 814 return frame_unwind_register_unsigned (next_frame, M32R_PC_REGNUM); 815} 816 817/* Given a GDB frame, determine the address of the calling function's 818 frame. This will be used to create a new GDB frame struct. */ 819 820static void 821m32r_frame_this_id (struct frame_info *next_frame, 822 void **this_prologue_cache, struct frame_id *this_id) 823{ 824 struct m32r_unwind_cache *info 825 = m32r_frame_unwind_cache (next_frame, this_prologue_cache); 826 CORE_ADDR base; 827 CORE_ADDR func; 828 struct minimal_symbol *msym_stack; 829 struct frame_id id; 830 831 /* The FUNC is easy. */ 832 func = frame_func_unwind (next_frame); 833 834 /* Check if the stack is empty. */ 835 msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); 836 if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack)) 837 return; 838 839 /* Hopefully the prologue analysis either correctly determined the 840 frame's base (which is the SP from the previous frame), or set 841 that base to "NULL". */ 842 base = info->prev_sp; 843 if (base == 0) 844 return; 845 846 id = frame_id_build (base, func); 847 (*this_id) = id; 848} 849 850static void 851m32r_frame_prev_register (struct frame_info *next_frame, 852 void **this_prologue_cache, 853 int regnum, int *optimizedp, 854 enum lval_type *lvalp, CORE_ADDR *addrp, 855 int *realnump, void *bufferp) 856{ 857 struct m32r_unwind_cache *info 858 = m32r_frame_unwind_cache (next_frame, this_prologue_cache); 859 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, 860 optimizedp, lvalp, addrp, realnump, bufferp); 861} 862 863static const struct frame_unwind m32r_frame_unwind = { 864 NORMAL_FRAME, 865 m32r_frame_this_id, 866 m32r_frame_prev_register 867}; 868 869static const struct frame_unwind * 870m32r_frame_sniffer (struct frame_info *next_frame) 871{ 872 return &m32r_frame_unwind; 873} 874 875static CORE_ADDR 876m32r_frame_base_address (struct frame_info *next_frame, void **this_cache) 877{ 878 struct m32r_unwind_cache *info 879 = m32r_frame_unwind_cache (next_frame, this_cache); 880 return info->base; 881} 882 883static const struct frame_base m32r_frame_base = { 884 &m32r_frame_unwind, 885 m32r_frame_base_address, 886 m32r_frame_base_address, 887 m32r_frame_base_address 888}; 889 890/* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that 891 dummy frame. The frame ID's base needs to match the TOS value 892 saved by save_dummy_frame_tos(), and the PC match the dummy frame's 893 breakpoint. */ 894 895static struct frame_id 896m32r_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) 897{ 898 return frame_id_build (m32r_unwind_sp (gdbarch, next_frame), 899 frame_pc_unwind (next_frame)); 900} 901 902 903static gdbarch_init_ftype m32r_gdbarch_init; 904 905static struct gdbarch * 906m32r_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 907{ 908 struct gdbarch *gdbarch; 909 struct gdbarch_tdep *tdep; 910 911 /* If there is already a candidate, use it. */ 912 arches = gdbarch_list_lookup_by_info (arches, &info); 913 if (arches != NULL) 914 return arches->gdbarch; 915 916 /* Allocate space for the new architecture. */ 917 tdep = XMALLOC (struct gdbarch_tdep); 918 gdbarch = gdbarch_alloc (&info, tdep); 919 920 set_gdbarch_read_pc (gdbarch, m32r_read_pc); 921 set_gdbarch_write_pc (gdbarch, m32r_write_pc); 922 set_gdbarch_unwind_sp (gdbarch, m32r_unwind_sp); 923 924 set_gdbarch_num_regs (gdbarch, M32R_NUM_REGS); 925 set_gdbarch_sp_regnum (gdbarch, M32R_SP_REGNUM); 926 set_gdbarch_register_name (gdbarch, m32r_register_name); 927 set_gdbarch_register_type (gdbarch, m32r_register_type); 928 929 set_gdbarch_push_dummy_call (gdbarch, m32r_push_dummy_call); 930 set_gdbarch_return_value (gdbarch, m32r_return_value); 931 932 set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue); 933 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 934 set_gdbarch_breakpoint_from_pc (gdbarch, m32r_breakpoint_from_pc); 935 set_gdbarch_memory_insert_breakpoint (gdbarch, 936 m32r_memory_insert_breakpoint); 937 set_gdbarch_memory_remove_breakpoint (gdbarch, 938 m32r_memory_remove_breakpoint); 939 940 set_gdbarch_frame_align (gdbarch, m32r_frame_align); 941 942 frame_base_set_default (gdbarch, &m32r_frame_base); 943 944 /* Methods for saving / extracting a dummy frame's ID. The ID's 945 stack address must match the SP value returned by 946 PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ 947 set_gdbarch_unwind_dummy_id (gdbarch, m32r_unwind_dummy_id); 948 949 /* Return the unwound PC value. */ 950 set_gdbarch_unwind_pc (gdbarch, m32r_unwind_pc); 951 952 set_gdbarch_print_insn (gdbarch, print_insn_m32r); 953 954 /* Hook in ABI-specific overrides, if they have been registered. */ 955 gdbarch_init_osabi (info, gdbarch); 956 957 /* Hook in the default unwinders. */ 958 frame_unwind_append_sniffer (gdbarch, m32r_frame_sniffer); 959 960 return gdbarch; 961} 962 963void 964_initialize_m32r_tdep (void) 965{ 966 register_gdbarch_init (bfd_arch_m32r, m32r_gdbarch_init); 967} 968