1/* Target dependent code for CRIS, for GDB, the GNU debugger. 2 3 Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc. 4 5 Contributed by Axis Communications AB. 6 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg. 7 8This file is part of GDB. 9 10This program is free software; you can redistribute it and/or modify 11it under the terms of the GNU General Public License as published by 12the Free Software Foundation; either version 2 of the License, or 13(at your option) any later version. 14 15This program is distributed in the hope that it will be useful, 16but WITHOUT ANY WARRANTY; without even the implied warranty of 17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18GNU General Public License for more details. 19 20You should have received a copy of the GNU General Public License 21along with this program; if not, write to the Free Software 22Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 23 24#include "defs.h" 25#include "frame.h" 26#include "frame-unwind.h" 27#include "frame-base.h" 28#include "trad-frame.h" 29#include "dwarf2-frame.h" 30#include "symtab.h" 31#include "inferior.h" 32#include "gdbtypes.h" 33#include "gdbcore.h" 34#include "gdbcmd.h" 35#include "target.h" 36#include "value.h" 37#include "opcode/cris.h" 38#include "arch-utils.h" 39#include "regcache.h" 40#include "gdb_assert.h" 41 42/* To get entry_point_address. */ 43#include "objfiles.h" 44 45#include "solib.h" /* Support for shared libraries. */ 46#include "solib-svr4.h" /* For struct link_map_offsets. */ 47#include "gdb_string.h" 48#include "dis-asm.h" 49 50enum cris_num_regs 51{ 52 /* There are no floating point registers. Used in gdbserver low-linux.c. */ 53 NUM_FREGS = 0, 54 55 /* There are 16 general registers. */ 56 NUM_GENREGS = 16, 57 58 /* There are 16 special registers. */ 59 NUM_SPECREGS = 16 60}; 61 62/* Register numbers of various important registers. 63 CRIS_FP_REGNUM Contains address of executing stack frame. 64 STR_REGNUM Contains the address of structure return values. 65 RET_REGNUM Contains the return value when shorter than or equal to 32 bits 66 ARG1_REGNUM Contains the first parameter to a function. 67 ARG2_REGNUM Contains the second parameter to a function. 68 ARG3_REGNUM Contains the third parameter to a function. 69 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack. 70 SP_REGNUM Contains address of top of stack. 71 PC_REGNUM Contains address of next instruction. 72 SRP_REGNUM Subroutine return pointer register. 73 BRP_REGNUM Breakpoint return pointer register. */ 74 75enum cris_regnums 76{ 77 /* Enums with respect to the general registers, valid for all 78 CRIS versions. */ 79 CRIS_FP_REGNUM = 8, 80 STR_REGNUM = 9, 81 RET_REGNUM = 10, 82 ARG1_REGNUM = 10, 83 ARG2_REGNUM = 11, 84 ARG3_REGNUM = 12, 85 ARG4_REGNUM = 13, 86 87 /* Enums with respect to the special registers, some of which may not be 88 applicable to all CRIS versions. */ 89 P0_REGNUM = 16, 90 VR_REGNUM = 17, 91 P2_REGNUM = 18, 92 P3_REGNUM = 19, 93 P4_REGNUM = 20, 94 CCR_REGNUM = 21, 95 MOF_REGNUM = 23, 96 P8_REGNUM = 24, 97 IBR_REGNUM = 25, 98 IRP_REGNUM = 26, 99 SRP_REGNUM = 27, 100 BAR_REGNUM = 28, 101 DCCR_REGNUM = 29, 102 BRP_REGNUM = 30, 103 USP_REGNUM = 31 104}; 105 106extern const struct cris_spec_reg cris_spec_regs[]; 107 108/* CRIS version, set via the user command 'set cris-version'. Affects 109 register names and sizes.*/ 110static unsigned int usr_cmd_cris_version; 111 112/* Indicates whether to trust the above variable. */ 113static int usr_cmd_cris_version_valid = 0; 114 115/* Whether to make use of Dwarf-2 CFI (default on). */ 116static int usr_cmd_cris_dwarf2_cfi = 1; 117 118/* CRIS architecture specific information. */ 119struct gdbarch_tdep 120{ 121 unsigned int cris_version; 122 int cris_dwarf2_cfi; 123}; 124 125/* Functions for accessing target dependent data. */ 126 127static int 128cris_version (void) 129{ 130 return (gdbarch_tdep (current_gdbarch)->cris_version); 131} 132 133/* Sigtramp identification code copied from i386-linux-tdep.c. */ 134 135#define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */ 136#define SIGTRAMP_OFFSET0 0 137#define SIGTRAMP_INSN1 0xe93d /* break 13 */ 138#define SIGTRAMP_OFFSET1 4 139 140static const unsigned short sigtramp_code[] = 141{ 142 SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */ 143 SIGTRAMP_INSN1 /* break 13 */ 144}; 145 146#define SIGTRAMP_LEN (sizeof sigtramp_code) 147 148/* Note: same length as normal sigtramp code. */ 149 150static const unsigned short rt_sigtramp_code[] = 151{ 152 SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */ 153 SIGTRAMP_INSN1 /* break 13 */ 154}; 155 156/* If PC is in a sigtramp routine, return the address of the start of 157 the routine. Otherwise, return 0. */ 158 159static CORE_ADDR 160cris_sigtramp_start (struct frame_info *next_frame) 161{ 162 CORE_ADDR pc = frame_pc_unwind (next_frame); 163 unsigned short buf[SIGTRAMP_LEN]; 164 165 if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) 166 return 0; 167 168 if (buf[0] != SIGTRAMP_INSN0) 169 { 170 if (buf[0] != SIGTRAMP_INSN1) 171 return 0; 172 173 pc -= SIGTRAMP_OFFSET1; 174 if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) 175 return 0; 176 } 177 178 if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0) 179 return 0; 180 181 return pc; 182} 183 184/* If PC is in a RT sigtramp routine, return the address of the start of 185 the routine. Otherwise, return 0. */ 186 187static CORE_ADDR 188cris_rt_sigtramp_start (struct frame_info *next_frame) 189{ 190 CORE_ADDR pc = frame_pc_unwind (next_frame); 191 unsigned short buf[SIGTRAMP_LEN]; 192 193 if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) 194 return 0; 195 196 if (buf[0] != SIGTRAMP_INSN0) 197 { 198 if (buf[0] != SIGTRAMP_INSN1) 199 return 0; 200 201 pc -= SIGTRAMP_OFFSET1; 202 if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) 203 return 0; 204 } 205 206 if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0) 207 return 0; 208 209 return pc; 210} 211 212/* Assuming NEXT_FRAME is a frame following a GNU/Linux sigtramp 213 routine, return the address of the associated sigcontext structure. */ 214 215static CORE_ADDR 216cris_sigcontext_addr (struct frame_info *next_frame) 217{ 218 CORE_ADDR pc; 219 CORE_ADDR sp; 220 char buf[4]; 221 222 frame_unwind_register (next_frame, SP_REGNUM, buf); 223 sp = extract_unsigned_integer (buf, 4); 224 225 /* Look for normal sigtramp frame first. */ 226 pc = cris_sigtramp_start (next_frame); 227 if (pc) 228 { 229 /* struct signal_frame (arch/cris/kernel/signal.c) contains 230 struct sigcontext as its first member, meaning the SP points to 231 it already. */ 232 return sp; 233 } 234 235 pc = cris_rt_sigtramp_start (next_frame); 236 if (pc) 237 { 238 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains 239 a struct ucontext, which in turn contains a struct sigcontext. 240 Magic digging: 241 4 + 4 + 128 to struct ucontext, then 242 4 + 4 + 12 to struct sigcontext. */ 243 return (sp + 156); 244 } 245 246 error ("Couldn't recognize signal trampoline."); 247 return 0; 248} 249 250struct cris_unwind_cache 251{ 252 /* The previous frame's inner most stack address. Used as this 253 frame ID's stack_addr. */ 254 CORE_ADDR prev_sp; 255 /* The frame's base, optionally used by the high-level debug info. */ 256 CORE_ADDR base; 257 int size; 258 /* How far the SP and r8 (FP) have been offset from the start of 259 the stack frame (as defined by the previous frame's stack 260 pointer). */ 261 LONGEST sp_offset; 262 LONGEST r8_offset; 263 int uses_frame; 264 265 /* From old frame_extra_info struct. */ 266 CORE_ADDR return_pc; 267 int leaf_function; 268 269 /* Table indicating the location of each and every register. */ 270 struct trad_frame_saved_reg *saved_regs; 271}; 272 273static struct cris_unwind_cache * 274cris_sigtramp_frame_unwind_cache (struct frame_info *next_frame, 275 void **this_cache) 276{ 277 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 278 struct cris_unwind_cache *info; 279 CORE_ADDR pc; 280 CORE_ADDR sp; 281 CORE_ADDR addr; 282 char buf[4]; 283 int i; 284 285 if ((*this_cache)) 286 return (*this_cache); 287 288 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); 289 (*this_cache) = info; 290 info->saved_regs = trad_frame_alloc_saved_regs (next_frame); 291 292 /* Zero all fields. */ 293 info->prev_sp = 0; 294 info->base = 0; 295 info->size = 0; 296 info->sp_offset = 0; 297 info->r8_offset = 0; 298 info->uses_frame = 0; 299 info->return_pc = 0; 300 info->leaf_function = 0; 301 302 frame_unwind_register (next_frame, SP_REGNUM, buf); 303 info->base = extract_unsigned_integer (buf, 4); 304 305 addr = cris_sigcontext_addr (next_frame); 306 307 /* Layout of the sigcontext struct: 308 struct sigcontext { 309 struct pt_regs regs; 310 unsigned long oldmask; 311 unsigned long usp; 312 }; */ 313 314 /* R0 to R13 are stored in reverse order at offset (2 * 4) in 315 struct pt_regs. */ 316 for (i = 0; i <= 13; i++) 317 info->saved_regs[i].addr = addr + ((15 - i) * 4); 318 319 info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4); 320 info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4); 321 info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4); 322 /* Note: IRP is off by 2 at this point. There's no point in correcting it 323 though since that will mean that the backtrace will show a PC different 324 from what is shown when stopped. */ 325 info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4); 326 info->saved_regs[PC_REGNUM] = info->saved_regs[IRP_REGNUM]; 327 info->saved_regs[SP_REGNUM].addr = addr + (24 * 4); 328 329 return info; 330} 331 332static void 333cris_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache, 334 struct frame_id *this_id) 335{ 336 struct cris_unwind_cache *cache = 337 cris_sigtramp_frame_unwind_cache (next_frame, this_cache); 338 (*this_id) = frame_id_build (cache->base, frame_pc_unwind (next_frame)); 339} 340 341/* Forward declaration. */ 342 343static void cris_frame_prev_register (struct frame_info *next_frame, 344 void **this_prologue_cache, 345 int regnum, int *optimizedp, 346 enum lval_type *lvalp, CORE_ADDR *addrp, 347 int *realnump, void *bufferp); 348static void 349cris_sigtramp_frame_prev_register (struct frame_info *next_frame, 350 void **this_cache, 351 int regnum, int *optimizedp, 352 enum lval_type *lvalp, CORE_ADDR *addrp, 353 int *realnump, void *valuep) 354{ 355 /* Make sure we've initialized the cache. */ 356 cris_sigtramp_frame_unwind_cache (next_frame, this_cache); 357 cris_frame_prev_register (next_frame, this_cache, regnum, 358 optimizedp, lvalp, addrp, realnump, valuep); 359} 360 361static const struct frame_unwind cris_sigtramp_frame_unwind = 362{ 363 SIGTRAMP_FRAME, 364 cris_sigtramp_frame_this_id, 365 cris_sigtramp_frame_prev_register 366}; 367 368static const struct frame_unwind * 369cris_sigtramp_frame_sniffer (struct frame_info *next_frame) 370{ 371 if (cris_sigtramp_start (next_frame) 372 || cris_rt_sigtramp_start (next_frame)) 373 return &cris_sigtramp_frame_unwind; 374 375 return NULL; 376} 377 378/* The instruction environment needed to find single-step breakpoints. */ 379typedef 380struct instruction_environment 381{ 382 unsigned long reg[NUM_GENREGS]; 383 unsigned long preg[NUM_SPECREGS]; 384 unsigned long branch_break_address; 385 unsigned long delay_slot_pc; 386 unsigned long prefix_value; 387 int branch_found; 388 int prefix_found; 389 int invalid; 390 int slot_needed; 391 int delay_slot_pc_active; 392 int xflag_found; 393 int disable_interrupt; 394} inst_env_type; 395 396/* Save old breakpoints in order to restore the state before a single_step. 397 At most, two breakpoints will have to be remembered. */ 398typedef 399char binsn_quantum[BREAKPOINT_MAX]; 400static binsn_quantum break_mem[2]; 401static CORE_ADDR next_pc = 0; 402static CORE_ADDR branch_target_address = 0; 403static unsigned char branch_break_inserted = 0; 404 405/* Machine-dependencies in CRIS for opcodes. */ 406 407/* Instruction sizes. */ 408enum cris_instruction_sizes 409{ 410 INST_BYTE_SIZE = 0, 411 INST_WORD_SIZE = 1, 412 INST_DWORD_SIZE = 2 413}; 414 415/* Addressing modes. */ 416enum cris_addressing_modes 417{ 418 REGISTER_MODE = 1, 419 INDIRECT_MODE = 2, 420 AUTOINC_MODE = 3 421}; 422 423/* Prefix addressing modes. */ 424enum cris_prefix_addressing_modes 425{ 426 PREFIX_INDEX_MODE = 2, 427 PREFIX_ASSIGN_MODE = 3, 428 429 /* Handle immediate byte offset addressing mode prefix format. */ 430 PREFIX_OFFSET_MODE = 2 431}; 432 433/* Masks for opcodes. */ 434enum cris_opcode_masks 435{ 436 BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1, 437 SIGNED_EXTEND_BIT_MASK = 0x2, 438 SIGNED_BYTE_MASK = 0x80, 439 SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00, 440 SIGNED_WORD_MASK = 0x8000, 441 SIGNED_WORD_EXTEND_MASK = 0xFFFF0000, 442 SIGNED_DWORD_MASK = 0x80000000, 443 SIGNED_QUICK_VALUE_MASK = 0x20, 444 SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0 445}; 446 447/* Functions for opcodes. The general form of the ETRAX 16-bit instruction: 448 Bit 15 - 12 Operand2 449 11 - 10 Mode 450 9 - 6 Opcode 451 5 - 4 Size 452 3 - 0 Operand1 */ 453 454static int 455cris_get_operand2 (unsigned short insn) 456{ 457 return ((insn & 0xF000) >> 12); 458} 459 460static int 461cris_get_mode (unsigned short insn) 462{ 463 return ((insn & 0x0C00) >> 10); 464} 465 466static int 467cris_get_opcode (unsigned short insn) 468{ 469 return ((insn & 0x03C0) >> 6); 470} 471 472static int 473cris_get_size (unsigned short insn) 474{ 475 return ((insn & 0x0030) >> 4); 476} 477 478static int 479cris_get_operand1 (unsigned short insn) 480{ 481 return (insn & 0x000F); 482} 483 484/* Additional functions in order to handle opcodes. */ 485 486static int 487cris_get_quick_value (unsigned short insn) 488{ 489 return (insn & 0x003F); 490} 491 492static int 493cris_get_bdap_quick_offset (unsigned short insn) 494{ 495 return (insn & 0x00FF); 496} 497 498static int 499cris_get_branch_short_offset (unsigned short insn) 500{ 501 return (insn & 0x00FF); 502} 503 504static int 505cris_get_asr_shift_steps (unsigned long value) 506{ 507 return (value & 0x3F); 508} 509 510static int 511cris_get_clear_size (unsigned short insn) 512{ 513 return ((insn) & 0xC000); 514} 515 516static int 517cris_is_signed_extend_bit_on (unsigned short insn) 518{ 519 return (((insn) & 0x20) == 0x20); 520} 521 522static int 523cris_is_xflag_bit_on (unsigned short insn) 524{ 525 return (((insn) & 0x1000) == 0x1000); 526} 527 528static void 529cris_set_size_to_dword (unsigned short *insn) 530{ 531 *insn &= 0xFFCF; 532 *insn |= 0x20; 533} 534 535static signed char 536cris_get_signed_offset (unsigned short insn) 537{ 538 return ((signed char) (insn & 0x00FF)); 539} 540 541/* Calls an op function given the op-type, working on the insn and the 542 inst_env. */ 543static void cris_gdb_func (enum cris_op_type, unsigned short, inst_env_type *); 544 545static struct gdbarch *cris_gdbarch_init (struct gdbarch_info, 546 struct gdbarch_list *); 547 548static void cris_dump_tdep (struct gdbarch *, struct ui_file *); 549 550static void set_cris_version (char *ignore_args, int from_tty, 551 struct cmd_list_element *c); 552 553static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty, 554 struct cmd_list_element *c); 555 556static CORE_ADDR cris_scan_prologue (CORE_ADDR pc, 557 struct frame_info *next_frame, 558 struct cris_unwind_cache *info); 559 560static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch, 561 struct frame_info *next_frame); 562 563static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch, 564 struct frame_info *next_frame); 565 566/* When arguments must be pushed onto the stack, they go on in reverse 567 order. The below implements a FILO (stack) to do this. 568 Copied from d10v-tdep.c. */ 569 570struct stack_item 571{ 572 int len; 573 struct stack_item *prev; 574 void *data; 575}; 576 577static struct stack_item * 578push_stack_item (struct stack_item *prev, void *contents, int len) 579{ 580 struct stack_item *si; 581 si = xmalloc (sizeof (struct stack_item)); 582 si->data = xmalloc (len); 583 si->len = len; 584 si->prev = prev; 585 memcpy (si->data, contents, len); 586 return si; 587} 588 589static struct stack_item * 590pop_stack_item (struct stack_item *si) 591{ 592 struct stack_item *dead = si; 593 si = si->prev; 594 xfree (dead->data); 595 xfree (dead); 596 return si; 597} 598 599/* Put here the code to store, into fi->saved_regs, the addresses of 600 the saved registers of frame described by FRAME_INFO. This 601 includes special registers such as pc and fp saved in special ways 602 in the stack frame. sp is even more special: the address we return 603 for it IS the sp for the next frame. */ 604 605struct cris_unwind_cache * 606cris_frame_unwind_cache (struct frame_info *next_frame, 607 void **this_prologue_cache) 608{ 609 CORE_ADDR pc; 610 struct cris_unwind_cache *info; 611 int i; 612 613 if ((*this_prologue_cache)) 614 return (*this_prologue_cache); 615 616 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); 617 (*this_prologue_cache) = info; 618 info->saved_regs = trad_frame_alloc_saved_regs (next_frame); 619 620 /* Zero all fields. */ 621 info->prev_sp = 0; 622 info->base = 0; 623 info->size = 0; 624 info->sp_offset = 0; 625 info->r8_offset = 0; 626 info->uses_frame = 0; 627 info->return_pc = 0; 628 info->leaf_function = 0; 629 630 /* Prologue analysis does the rest... */ 631 cris_scan_prologue (frame_func_unwind (next_frame), next_frame, info); 632 633 return info; 634} 635 636/* Given a GDB frame, determine the address of the calling function's 637 frame. This will be used to create a new GDB frame struct. */ 638 639static void 640cris_frame_this_id (struct frame_info *next_frame, 641 void **this_prologue_cache, 642 struct frame_id *this_id) 643{ 644 struct cris_unwind_cache *info 645 = cris_frame_unwind_cache (next_frame, this_prologue_cache); 646 CORE_ADDR base; 647 CORE_ADDR func; 648 struct frame_id id; 649 650 /* The FUNC is easy. */ 651 func = frame_func_unwind (next_frame); 652 653 /* Hopefully the prologue analysis either correctly determined the 654 frame's base (which is the SP from the previous frame), or set 655 that base to "NULL". */ 656 base = info->prev_sp; 657 if (base == 0) 658 return; 659 660 id = frame_id_build (base, func); 661 662 (*this_id) = id; 663} 664 665static void 666cris_frame_prev_register (struct frame_info *next_frame, 667 void **this_prologue_cache, 668 int regnum, int *optimizedp, 669 enum lval_type *lvalp, CORE_ADDR *addrp, 670 int *realnump, void *bufferp) 671{ 672 struct cris_unwind_cache *info 673 = cris_frame_unwind_cache (next_frame, this_prologue_cache); 674 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, 675 optimizedp, lvalp, addrp, realnump, bufferp); 676} 677 678/* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that 679 dummy frame. The frame ID's base needs to match the TOS value 680 saved by save_dummy_frame_tos(), and the PC match the dummy frame's 681 breakpoint. */ 682 683static struct frame_id 684cris_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) 685{ 686 return frame_id_build (cris_unwind_sp (gdbarch, next_frame), 687 frame_pc_unwind (next_frame)); 688} 689 690static CORE_ADDR 691cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) 692{ 693 /* Align to the size of an instruction (so that they can safely be 694 pushed onto the stack). */ 695 return sp & ~3; 696} 697 698static CORE_ADDR 699cris_push_dummy_code (struct gdbarch *gdbarch, 700 CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc, 701 struct value **args, int nargs, 702 struct type *value_type, 703 CORE_ADDR *real_pc, CORE_ADDR *bp_addr) 704{ 705 /* Allocate space sufficient for a breakpoint. */ 706 sp = (sp - 4) & ~3; 707 /* Store the address of that breakpoint */ 708 *bp_addr = sp; 709 /* CRIS always starts the call at the callee's entry point. */ 710 *real_pc = funaddr; 711 return sp; 712} 713 714static CORE_ADDR 715cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 716 struct regcache *regcache, CORE_ADDR bp_addr, 717 int nargs, struct value **args, CORE_ADDR sp, 718 int struct_return, CORE_ADDR struct_addr) 719{ 720 int stack_alloc; 721 int stack_offset; 722 int argreg; 723 int argnum; 724 725 CORE_ADDR regval; 726 727 /* The function's arguments and memory allocated by gdb for the arguments to 728 point at reside in separate areas on the stack. 729 Both frame pointers grow toward higher addresses. */ 730 CORE_ADDR fp_arg; 731 CORE_ADDR fp_mem; 732 733 struct stack_item *si = NULL; 734 735 /* Push the return address. */ 736 regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr); 737 738 /* Are we returning a value using a structure return or a normal value 739 return? struct_addr is the address of the reserved space for the return 740 structure to be written on the stack. */ 741 if (struct_return) 742 { 743 regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr); 744 } 745 746 /* Now load as many as possible of the first arguments into registers, 747 and push the rest onto the stack. */ 748 argreg = ARG1_REGNUM; 749 stack_offset = 0; 750 751 for (argnum = 0; argnum < nargs; argnum++) 752 { 753 int len; 754 char *val; 755 int reg_demand; 756 int i; 757 758 len = TYPE_LENGTH (VALUE_TYPE (args[argnum])); 759 val = (char *) VALUE_CONTENTS (args[argnum]); 760 761 /* How may registers worth of storage do we need for this argument? */ 762 reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0); 763 764 if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM)) 765 { 766 /* Data passed by value. Fits in available register(s). */ 767 for (i = 0; i < reg_demand; i++) 768 { 769 regcache_cooked_write_unsigned (regcache, argreg, 770 *(unsigned long *) val); 771 argreg++; 772 val += 4; 773 } 774 } 775 else if (len <= (2 * 4) && argreg <= ARG4_REGNUM) 776 { 777 /* Data passed by value. Does not fit in available register(s). 778 Use the register(s) first, then the stack. */ 779 for (i = 0; i < reg_demand; i++) 780 { 781 if (argreg <= ARG4_REGNUM) 782 { 783 regcache_cooked_write_unsigned (regcache, argreg, 784 *(unsigned long *) val); 785 argreg++; 786 val += 4; 787 } 788 else 789 { 790 /* Push item for later so that pushed arguments 791 come in the right order. */ 792 si = push_stack_item (si, val, 4); 793 val += 4; 794 } 795 } 796 } 797 else if (len > (2 * 4)) 798 { 799 /* FIXME */ 800 internal_error (__FILE__, __LINE__, "We don't do this"); 801 } 802 else 803 { 804 /* Data passed by value. No available registers. Put it on 805 the stack. */ 806 si = push_stack_item (si, val, len); 807 } 808 } 809 810 while (si) 811 { 812 /* fp_arg must be word-aligned (i.e., don't += len) to match 813 the function prologue. */ 814 sp = (sp - si->len) & ~3; 815 write_memory (sp, si->data, si->len); 816 si = pop_stack_item (si); 817 } 818 819 /* Finally, update the SP register. */ 820 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp); 821 822 return sp; 823} 824 825static const struct frame_unwind cris_frame_unwind = { 826 NORMAL_FRAME, 827 cris_frame_this_id, 828 cris_frame_prev_register 829}; 830 831const struct frame_unwind * 832cris_frame_sniffer (struct frame_info *next_frame) 833{ 834 return &cris_frame_unwind; 835} 836 837static CORE_ADDR 838cris_frame_base_address (struct frame_info *next_frame, void **this_cache) 839{ 840 struct cris_unwind_cache *info 841 = cris_frame_unwind_cache (next_frame, this_cache); 842 return info->base; 843} 844 845static const struct frame_base cris_frame_base = { 846 &cris_frame_unwind, 847 cris_frame_base_address, 848 cris_frame_base_address, 849 cris_frame_base_address 850}; 851 852/* Frames information. The definition of the struct frame_info is 853 854 CORE_ADDR frame 855 CORE_ADDR pc 856 enum frame_type type; 857 CORE_ADDR return_pc 858 int leaf_function 859 860 If the compilation option -fno-omit-frame-pointer is present the 861 variable frame will be set to the content of R8 which is the frame 862 pointer register. 863 864 The variable pc contains the address where execution is performed 865 in the present frame. The innermost frame contains the current content 866 of the register PC. All other frames contain the content of the 867 register PC in the next frame. 868 869 The variable `type' indicates the frame's type: normal, SIGTRAMP 870 (associated with a signal handler), dummy (associated with a dummy 871 frame). 872 873 The variable return_pc contains the address where execution should be 874 resumed when the present frame has finished, the return address. 875 876 The variable leaf_function is 1 if the return address is in the register 877 SRP, and 0 if it is on the stack. 878 879 Prologue instructions C-code. 880 The prologue may consist of (-fno-omit-frame-pointer) 881 1) 2) 882 push srp 883 push r8 push r8 884 move.d sp,r8 move.d sp,r8 885 subq X,sp subq X,sp 886 movem rY,[sp] movem rY,[sp] 887 move.S rZ,[r8-U] move.S rZ,[r8-U] 888 889 where 1 is a non-terminal function, and 2 is a leaf-function. 890 891 Note that this assumption is extremely brittle, and will break at the 892 slightest change in GCC's prologue. 893 894 If local variables are declared or register contents are saved on stack 895 the subq-instruction will be present with X as the number of bytes 896 needed for storage. The reshuffle with respect to r8 may be performed 897 with any size S (b, w, d) and any of the general registers Z={0..13}. 898 The offset U should be representable by a signed 8-bit value in all cases. 899 Thus, the prefix word is assumed to be immediate byte offset mode followed 900 by another word containing the instruction. 901 902 Degenerate cases: 903 3) 904 push r8 905 move.d sp,r8 906 move.d r8,sp 907 pop r8 908 909 Prologue instructions C++-code. 910 Case 1) and 2) in the C-code may be followed by 911 912 move.d r10,rS ; this 913 move.d r11,rT ; P1 914 move.d r12,rU ; P2 915 move.d r13,rV ; P3 916 move.S [r8+U],rZ ; P4 917 918 if any of the call parameters are stored. The host expects these 919 instructions to be executed in order to get the call parameters right. */ 920 921/* Examine the prologue of a function. The variable ip is the address of 922 the first instruction of the prologue. The variable limit is the address 923 of the first instruction after the prologue. The variable fi contains the 924 information in struct frame_info. The variable frameless_p controls whether 925 the entire prologue is examined (0) or just enough instructions to 926 determine that it is a prologue (1). */ 927 928static CORE_ADDR 929cris_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame, 930 struct cris_unwind_cache *info) 931{ 932 /* Present instruction. */ 933 unsigned short insn; 934 935 /* Next instruction, lookahead. */ 936 unsigned short insn_next; 937 int regno; 938 939 /* Is there a push fp? */ 940 int have_fp; 941 942 /* Number of byte on stack used for local variables and movem. */ 943 int val; 944 945 /* Highest register number in a movem. */ 946 int regsave; 947 948 /* move.d r<source_register>,rS */ 949 short source_register; 950 951 /* Scan limit. */ 952 int limit; 953 954 /* This frame is with respect to a leaf until a push srp is found. */ 955 if (info) 956 { 957 info->leaf_function = 1; 958 } 959 960 /* Assume nothing on stack. */ 961 val = 0; 962 regsave = -1; 963 964 /* If we were called without a next_frame, that means we were called 965 from cris_skip_prologue which already tried to find the end of the 966 prologue through the symbol information. 64 instructions past current 967 pc is arbitrarily chosen, but at least it means we'll stop eventually. */ 968 limit = next_frame ? frame_pc_unwind (next_frame) : pc + 64; 969 970 /* Find the prologue instructions. */ 971 while (pc > 0 && pc < limit) 972 { 973 insn = read_memory_unsigned_integer (pc, 2); 974 pc += 2; 975 if (insn == 0xE1FC) 976 { 977 /* push <reg> 32 bit instruction */ 978 insn_next = read_memory_unsigned_integer (pc, 2); 979 pc += 2; 980 regno = cris_get_operand2 (insn_next); 981 if (info) 982 { 983 info->sp_offset += 4; 984 } 985 /* This check, meant to recognize srp, used to be regno == 986 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */ 987 if (insn_next == 0xBE7E) 988 { 989 if (info) 990 { 991 info->leaf_function = 0; 992 } 993 } 994 else if (insn_next == 0x8FEE) 995 { 996 /* push $r8 */ 997 if (info) 998 { 999 info->r8_offset = info->sp_offset; 1000 } 1001 } 1002 } 1003 else if (insn == 0x866E) 1004 { 1005 /* move.d sp,r8 */ 1006 if (info) 1007 { 1008 info->uses_frame = 1; 1009 } 1010 continue; 1011 } 1012 else if (cris_get_operand2 (insn) == SP_REGNUM 1013 && cris_get_mode (insn) == 0x0000 1014 && cris_get_opcode (insn) == 0x000A) 1015 { 1016 /* subq <val>,sp */ 1017 if (info) 1018 { 1019 info->sp_offset += cris_get_quick_value (insn); 1020 } 1021 } 1022 else if (cris_get_mode (insn) == 0x0002 1023 && cris_get_opcode (insn) == 0x000F 1024 && cris_get_size (insn) == 0x0003 1025 && cris_get_operand1 (insn) == SP_REGNUM) 1026 { 1027 /* movem r<regsave>,[sp] */ 1028 regsave = cris_get_operand2 (insn); 1029 } 1030 else if (cris_get_operand2 (insn) == SP_REGNUM 1031 && ((insn & 0x0F00) >> 8) == 0x0001 1032 && (cris_get_signed_offset (insn) < 0)) 1033 { 1034 /* Immediate byte offset addressing prefix word with sp as base 1035 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val> 1036 is between 64 and 128. 1037 movem r<regsave>,[sp=sp-<val>] */ 1038 if (info) 1039 { 1040 info->sp_offset += -cris_get_signed_offset (insn); 1041 } 1042 insn_next = read_memory_unsigned_integer (pc, 2); 1043 pc += 2; 1044 if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE 1045 && cris_get_opcode (insn_next) == 0x000F 1046 && cris_get_size (insn_next) == 0x0003 1047 && cris_get_operand1 (insn_next) == SP_REGNUM) 1048 { 1049 regsave = cris_get_operand2 (insn_next); 1050 } 1051 else 1052 { 1053 /* The prologue ended before the limit was reached. */ 1054 pc -= 4; 1055 break; 1056 } 1057 } 1058 else if (cris_get_mode (insn) == 0x0001 1059 && cris_get_opcode (insn) == 0x0009 1060 && cris_get_size (insn) == 0x0002) 1061 { 1062 /* move.d r<10..13>,r<0..15> */ 1063 source_register = cris_get_operand1 (insn); 1064 1065 /* FIXME? In the glibc solibs, the prologue might contain something 1066 like (this example taken from relocate_doit): 1067 move.d $pc,$r0 1068 sub.d 0xfffef426,$r0 1069 which isn't covered by the source_register check below. Question 1070 is whether to add a check for this combo, or make better use of 1071 the limit variable instead. */ 1072 if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM) 1073 { 1074 /* The prologue ended before the limit was reached. */ 1075 pc -= 2; 1076 break; 1077 } 1078 } 1079 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM 1080 /* The size is a fixed-size. */ 1081 && ((insn & 0x0F00) >> 8) == 0x0001 1082 /* A negative offset. */ 1083 && (cris_get_signed_offset (insn) < 0)) 1084 { 1085 /* move.S rZ,[r8-U] (?) */ 1086 insn_next = read_memory_unsigned_integer (pc, 2); 1087 pc += 2; 1088 regno = cris_get_operand2 (insn_next); 1089 if ((regno >= 0 && regno < SP_REGNUM) 1090 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE 1091 && cris_get_opcode (insn_next) == 0x000F) 1092 { 1093 /* move.S rZ,[r8-U] */ 1094 continue; 1095 } 1096 else 1097 { 1098 /* The prologue ended before the limit was reached. */ 1099 pc -= 4; 1100 break; 1101 } 1102 } 1103 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM 1104 /* The size is a fixed-size. */ 1105 && ((insn & 0x0F00) >> 8) == 0x0001 1106 /* A positive offset. */ 1107 && (cris_get_signed_offset (insn) > 0)) 1108 { 1109 /* move.S [r8+U],rZ (?) */ 1110 insn_next = read_memory_unsigned_integer (pc, 2); 1111 pc += 2; 1112 regno = cris_get_operand2 (insn_next); 1113 if ((regno >= 0 && regno < SP_REGNUM) 1114 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE 1115 && cris_get_opcode (insn_next) == 0x0009 1116 && cris_get_operand1 (insn_next) == regno) 1117 { 1118 /* move.S [r8+U],rZ */ 1119 continue; 1120 } 1121 else 1122 { 1123 /* The prologue ended before the limit was reached. */ 1124 pc -= 4; 1125 break; 1126 } 1127 } 1128 else 1129 { 1130 /* The prologue ended before the limit was reached. */ 1131 pc -= 2; 1132 break; 1133 } 1134 } 1135 1136 /* We only want to know the end of the prologue when next_frame and info 1137 are NULL (called from cris_skip_prologue i.e.). */ 1138 if (next_frame == NULL && info == NULL) 1139 { 1140 return pc; 1141 } 1142 1143 info->size = info->sp_offset; 1144 1145 /* Compute the previous frame's stack pointer (which is also the 1146 frame's ID's stack address), and this frame's base pointer. */ 1147 if (info->uses_frame) 1148 { 1149 ULONGEST this_base; 1150 /* The SP was moved to the FP. This indicates that a new frame 1151 was created. Get THIS frame's FP value by unwinding it from 1152 the next frame. */ 1153 frame_unwind_unsigned_register (next_frame, CRIS_FP_REGNUM, 1154 &this_base); 1155 info->base = this_base; 1156 info->saved_regs[CRIS_FP_REGNUM].addr = info->base; 1157 1158 /* The FP points at the last saved register. Adjust the FP back 1159 to before the first saved register giving the SP. */ 1160 info->prev_sp = info->base + info->r8_offset; 1161 } 1162 else 1163 { 1164 ULONGEST this_base; 1165 /* Assume that the FP is this frame's SP but with that pushed 1166 stack space added back. */ 1167 frame_unwind_unsigned_register (next_frame, SP_REGNUM, &this_base); 1168 info->base = this_base; 1169 info->prev_sp = info->base + info->size; 1170 } 1171 1172 /* Calculate the addresses for the saved registers on the stack. */ 1173 /* FIXME: The address calculation should really be done on the fly while 1174 we're analyzing the prologue (we only hold one regsave value as it is 1175 now). */ 1176 val = info->sp_offset; 1177 1178 for (regno = regsave; regno >= 0; regno--) 1179 { 1180 info->saved_regs[regno].addr = info->base + info->r8_offset - val; 1181 val -= 4; 1182 } 1183 1184 /* The previous frame's SP needed to be computed. Save the computed 1185 value. */ 1186 trad_frame_set_value (info->saved_regs, SP_REGNUM, info->prev_sp); 1187 1188 if (!info->leaf_function) 1189 { 1190 /* SRP saved on the stack. But where? */ 1191 if (info->r8_offset == 0) 1192 { 1193 /* R8 not pushed yet. */ 1194 info->saved_regs[SRP_REGNUM].addr = info->base; 1195 } 1196 else 1197 { 1198 /* R8 pushed, but SP may or may not be moved to R8 yet. */ 1199 info->saved_regs[SRP_REGNUM].addr = info->base + 4; 1200 } 1201 } 1202 1203 /* The PC is found in SRP (the actual register or located on the stack). */ 1204 info->saved_regs[PC_REGNUM] = info->saved_regs[SRP_REGNUM]; 1205 1206 return pc; 1207} 1208 1209/* Advance pc beyond any function entry prologue instructions at pc 1210 to reach some "real" code. */ 1211 1212/* Given a PC value corresponding to the start of a function, return the PC 1213 of the first instruction after the function prologue. */ 1214 1215static CORE_ADDR 1216cris_skip_prologue (CORE_ADDR pc) 1217{ 1218 CORE_ADDR func_addr, func_end; 1219 struct symtab_and_line sal; 1220 CORE_ADDR pc_after_prologue; 1221 1222 /* If we have line debugging information, then the end of the prologue 1223 should the first assembly instruction of the first source line. */ 1224 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 1225 { 1226 sal = find_pc_line (func_addr, 0); 1227 if (sal.end > 0 && sal.end < func_end) 1228 return sal.end; 1229 } 1230 1231 pc_after_prologue = cris_scan_prologue (pc, NULL, NULL); 1232 return pc_after_prologue; 1233} 1234 1235static CORE_ADDR 1236cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 1237{ 1238 ULONGEST pc; 1239 frame_unwind_unsigned_register (next_frame, PC_REGNUM, &pc); 1240 return pc; 1241} 1242 1243static CORE_ADDR 1244cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) 1245{ 1246 ULONGEST sp; 1247 frame_unwind_unsigned_register (next_frame, SP_REGNUM, &sp); 1248 return sp; 1249} 1250 1251/* Use the program counter to determine the contents and size of a breakpoint 1252 instruction. It returns a pointer to a string of bytes that encode a 1253 breakpoint instruction, stores the length of the string to *lenptr, and 1254 adjusts pcptr (if necessary) to point to the actual memory location where 1255 the breakpoint should be inserted. */ 1256 1257static const unsigned char * 1258cris_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) 1259{ 1260 static unsigned char break_insn[] = {0x38, 0xe9}; 1261 *lenptr = 2; 1262 1263 return break_insn; 1264} 1265 1266/* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version, 1267 0 otherwise. */ 1268 1269static int 1270cris_spec_reg_applicable (struct cris_spec_reg spec_reg) 1271{ 1272 int version = cris_version (); 1273 1274 switch (spec_reg.applicable_version) 1275 { 1276 case cris_ver_version_all: 1277 return 1; 1278 case cris_ver_warning: 1279 /* Indeterminate/obsolete. */ 1280 return 0; 1281 case cris_ver_sim: 1282 /* Simulator only. */ 1283 return 0; 1284 case cris_ver_v0_3: 1285 return (version >= 0 && version <= 3); 1286 case cris_ver_v3p: 1287 return (version >= 3); 1288 case cris_ver_v8: 1289 return (version == 8 || version == 9); 1290 case cris_ver_v8p: 1291 return (version >= 8); 1292 case cris_ver_v10p: 1293 return (version >= 10); 1294 default: 1295 /* Invalid cris version. */ 1296 return 0; 1297 } 1298} 1299 1300/* Returns the register size in unit byte. Returns 0 for an unimplemented 1301 register, -1 for an invalid register. */ 1302 1303static int 1304cris_register_size (int regno) 1305{ 1306 int i; 1307 int spec_regno; 1308 1309 if (regno >= 0 && regno < NUM_GENREGS) 1310 { 1311 /* General registers (R0 - R15) are 32 bits. */ 1312 return 4; 1313 } 1314 else if (regno >= NUM_GENREGS && regno < NUM_REGS) 1315 { 1316 /* Special register (R16 - R31). cris_spec_regs is zero-based. 1317 Adjust regno accordingly. */ 1318 spec_regno = regno - NUM_GENREGS; 1319 1320 /* The entries in cris_spec_regs are stored in register number order, 1321 which means we can shortcut into the array when searching it. */ 1322 for (i = spec_regno; cris_spec_regs[i].name != NULL; i++) 1323 { 1324 if (cris_spec_regs[i].number == spec_regno 1325 && cris_spec_reg_applicable (cris_spec_regs[i])) 1326 /* Go with the first applicable register. */ 1327 return cris_spec_regs[i].reg_size; 1328 } 1329 /* Special register not applicable to this CRIS version. */ 1330 return 0; 1331 } 1332 else 1333 { 1334 /* Invalid register. */ 1335 return -1; 1336 } 1337} 1338 1339/* Nonzero if regno should not be fetched from the target. This is the case 1340 for unimplemented (size 0) and non-existant registers. */ 1341 1342static int 1343cris_cannot_fetch_register (int regno) 1344{ 1345 return ((regno < 0 || regno >= NUM_REGS) 1346 || (cris_register_size (regno) == 0)); 1347} 1348 1349/* Nonzero if regno should not be written to the target, for various 1350 reasons. */ 1351 1352static int 1353cris_cannot_store_register (int regno) 1354{ 1355 /* There are three kinds of registers we refuse to write to. 1356 1. Those that not implemented. 1357 2. Those that are read-only (depends on the processor mode). 1358 3. Those registers to which a write has no effect. 1359 */ 1360 1361 if (regno < 0 || regno >= NUM_REGS || cris_register_size (regno) == 0) 1362 /* Not implemented. */ 1363 return 1; 1364 1365 else if (regno == VR_REGNUM) 1366 /* Read-only. */ 1367 return 1; 1368 1369 else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM) 1370 /* Writing has no effect. */ 1371 return 1; 1372 1373 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug 1374 agent decide whether they are writable. */ 1375 1376 return 0; 1377} 1378 1379/* Returns the register offset for the first byte of register regno's space 1380 in the saved register state. Returns -1 for an invalid or unimplemented 1381 register. */ 1382 1383static int 1384cris_register_offset (int regno) 1385{ 1386 int i; 1387 int reg_size; 1388 int offset = 0; 1389 1390 if (regno >= 0 && regno < NUM_REGS) 1391 { 1392 /* FIXME: The offsets should be cached and calculated only once, 1393 when the architecture being debugged has changed. */ 1394 for (i = 0; i < regno; i++) 1395 offset += cris_register_size (i); 1396 1397 return offset; 1398 } 1399 else 1400 { 1401 /* Invalid register. */ 1402 return -1; 1403 } 1404} 1405 1406/* Return the GDB type (defined in gdbtypes.c) for the "standard" data type 1407 of data in register regno. */ 1408 1409static struct type * 1410cris_register_type (struct gdbarch *gdbarch, int regno) 1411{ 1412 if (regno == PC_REGNUM) 1413 return builtin_type_void_func_ptr; 1414 else if (regno == SP_REGNUM || regno == CRIS_FP_REGNUM) 1415 return builtin_type_void_data_ptr; 1416 else if ((regno >= 0 && regno < SP_REGNUM) 1417 || (regno >= MOF_REGNUM && regno <= USP_REGNUM)) 1418 /* Note: R8 taken care of previous clause. */ 1419 return builtin_type_uint32; 1420 else if (regno >= P4_REGNUM && regno <= CCR_REGNUM) 1421 return builtin_type_uint16; 1422 else if (regno >= P0_REGNUM && regno <= VR_REGNUM) 1423 return builtin_type_uint8; 1424 else 1425 /* Invalid (unimplemented) register. */ 1426 return builtin_type_int0; 1427} 1428 1429/* Stores a function return value of type type, where valbuf is the address 1430 of the value to be stored. */ 1431 1432/* In the CRIS ABI, R10 and R11 are used to store return values. */ 1433 1434static void 1435cris_store_return_value (struct type *type, struct regcache *regcache, 1436 const void *valbuf) 1437{ 1438 ULONGEST val; 1439 int len = TYPE_LENGTH (type); 1440 1441 if (len <= 4) 1442 { 1443 /* Put the return value in R10. */ 1444 val = extract_unsigned_integer (valbuf, len); 1445 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); 1446 } 1447 else if (len <= 8) 1448 { 1449 /* Put the return value in R10 and R11. */ 1450 val = extract_unsigned_integer (valbuf, 4); 1451 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); 1452 val = extract_unsigned_integer ((char *)valbuf + 4, len - 4); 1453 regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val); 1454 } 1455 else 1456 error ("cris_store_return_value: type length too large."); 1457} 1458 1459/* Return the name of register regno as a string. Return NULL for an invalid or 1460 unimplemented register. */ 1461 1462static const char * 1463cris_register_name (int regno) 1464{ 1465 static char *cris_genreg_names[] = 1466 { "r0", "r1", "r2", "r3", \ 1467 "r4", "r5", "r6", "r7", \ 1468 "r8", "r9", "r10", "r11", \ 1469 "r12", "r13", "sp", "pc" }; 1470 1471 int i; 1472 int spec_regno; 1473 1474 if (regno >= 0 && regno < NUM_GENREGS) 1475 { 1476 /* General register. */ 1477 return cris_genreg_names[regno]; 1478 } 1479 else if (regno >= NUM_GENREGS && regno < NUM_REGS) 1480 { 1481 /* Special register (R16 - R31). cris_spec_regs is zero-based. 1482 Adjust regno accordingly. */ 1483 spec_regno = regno - NUM_GENREGS; 1484 1485 /* The entries in cris_spec_regs are stored in register number order, 1486 which means we can shortcut into the array when searching it. */ 1487 for (i = spec_regno; cris_spec_regs[i].name != NULL; i++) 1488 { 1489 if (cris_spec_regs[i].number == spec_regno 1490 && cris_spec_reg_applicable (cris_spec_regs[i])) 1491 /* Go with the first applicable register. */ 1492 return cris_spec_regs[i].name; 1493 } 1494 /* Special register not applicable to this CRIS version. */ 1495 return NULL; 1496 } 1497 else 1498 { 1499 /* Invalid register. */ 1500 return NULL; 1501 } 1502} 1503 1504/* Convert DWARF register number REG to the appropriate register 1505 number used by GDB. */ 1506 1507static int 1508cris_dwarf2_reg_to_regnum (int reg) 1509{ 1510 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register 1511 numbering, MOF is 18). 1512 Adapted from gcc/config/cris/cris.h. */ 1513 static int cris_dwarf_regmap[] = { 1514 0, 1, 2, 3, 1515 4, 5, 6, 7, 1516 8, 9, 10, 11, 1517 12, 13, 14, 15, 1518 27, -1, -1, -1, 1519 -1, -1, -1, 23, 1520 -1, -1, -1, 27, 1521 -1, -1, -1, -1 1522 }; 1523 int regnum = -1; 1524 1525 if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap)) 1526 regnum = cris_dwarf_regmap[reg]; 1527 1528 if (regnum == -1) 1529 warning ("Unmapped DWARF Register #%d encountered\n", reg); 1530 1531 return regnum; 1532} 1533 1534/* DWARF-2 frame support. */ 1535 1536static void 1537cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, 1538 struct dwarf2_frame_state_reg *reg) 1539{ 1540 /* The return address column. */ 1541 if (regnum == PC_REGNUM) 1542 reg->how = DWARF2_FRAME_REG_RA; 1543 1544 /* The call frame address. */ 1545 else if (regnum == SP_REGNUM) 1546 reg->how = DWARF2_FRAME_REG_CFA; 1547} 1548 1549/* Extract from an array regbuf containing the raw register state a function 1550 return value of type type, and copy that, in virtual format, into 1551 valbuf. */ 1552 1553/* In the CRIS ABI, R10 and R11 are used to store return values. */ 1554 1555static void 1556cris_extract_return_value (struct type *type, struct regcache *regcache, 1557 void *valbuf) 1558{ 1559 ULONGEST val; 1560 int len = TYPE_LENGTH (type); 1561 1562 if (len <= 4) 1563 { 1564 /* Get the return value from R10. */ 1565 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); 1566 store_unsigned_integer (valbuf, len, val); 1567 } 1568 else if (len <= 8) 1569 { 1570 /* Get the return value from R10 and R11. */ 1571 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); 1572 store_unsigned_integer (valbuf, 4, val); 1573 regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val); 1574 store_unsigned_integer ((char *)valbuf + 4, len - 4, val); 1575 } 1576 else 1577 error ("cris_extract_return_value: type length too large"); 1578} 1579 1580/* Handle the CRIS return value convention. */ 1581 1582static enum return_value_convention 1583cris_return_value (struct gdbarch *gdbarch, struct type *type, 1584 struct regcache *regcache, void *readbuf, 1585 const void *writebuf) 1586{ 1587 if (TYPE_CODE (type) == TYPE_CODE_STRUCT 1588 || TYPE_CODE (type) == TYPE_CODE_UNION 1589 || TYPE_LENGTH (type) > 8) 1590 /* Structs, unions, and anything larger than 8 bytes (2 registers) 1591 goes on the stack. */ 1592 return RETURN_VALUE_STRUCT_CONVENTION; 1593 1594 if (readbuf) 1595 cris_extract_return_value (type, regcache, readbuf); 1596 if (writebuf) 1597 cris_store_return_value (type, regcache, writebuf); 1598 1599 return RETURN_VALUE_REGISTER_CONVENTION; 1600} 1601 1602/* Returns 1 if the given type will be passed by pointer rather than 1603 directly. */ 1604 1605/* In the CRIS ABI, arguments shorter than or equal to 64 bits are passed 1606 by value. */ 1607 1608static int 1609cris_reg_struct_has_addr (int gcc_p, struct type *type) 1610{ 1611 return (TYPE_LENGTH (type) > 8); 1612} 1613 1614/* Calculates a value that measures how good inst_args constraints an 1615 instruction. It stems from cris_constraint, found in cris-dis.c. */ 1616 1617static int 1618constraint (unsigned int insn, const signed char *inst_args, 1619 inst_env_type *inst_env) 1620{ 1621 int retval = 0; 1622 int tmp, i; 1623 1624 const char *s = inst_args; 1625 1626 for (; *s; s++) 1627 switch (*s) 1628 { 1629 case 'm': 1630 if ((insn & 0x30) == 0x30) 1631 return -1; 1632 break; 1633 1634 case 'S': 1635 /* A prefix operand. */ 1636 if (inst_env->prefix_found) 1637 break; 1638 else 1639 return -1; 1640 1641 case 'B': 1642 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for 1643 valid "push" size. In case of special register, it may be != 4. */ 1644 if (inst_env->prefix_found) 1645 break; 1646 else 1647 return -1; 1648 1649 case 'D': 1650 retval = (((insn >> 0xC) & 0xF) == (insn & 0xF)); 1651 if (!retval) 1652 return -1; 1653 else 1654 retval += 4; 1655 break; 1656 1657 case 'P': 1658 tmp = (insn >> 0xC) & 0xF; 1659 1660 for (i = 0; cris_spec_regs[i].name != NULL; i++) 1661 { 1662 /* Since we match four bits, we will give a value of 1663 4 - 1 = 3 in a match. If there is a corresponding 1664 exact match of a special register in another pattern, it 1665 will get a value of 4, which will be higher. This should 1666 be correct in that an exact pattern would match better that 1667 a general pattern. 1668 Note that there is a reason for not returning zero; the 1669 pattern for "clear" is partly matched in the bit-pattern 1670 (the two lower bits must be zero), while the bit-pattern 1671 for a move from a special register is matched in the 1672 register constraint. 1673 This also means we will will have a race condition if 1674 there is a partly match in three bits in the bit pattern. */ 1675 if (tmp == cris_spec_regs[i].number) 1676 { 1677 retval += 3; 1678 break; 1679 } 1680 } 1681 1682 if (cris_spec_regs[i].name == NULL) 1683 return -1; 1684 break; 1685 } 1686 return retval; 1687} 1688 1689/* Returns the number of bits set in the variable value. */ 1690 1691static int 1692number_of_bits (unsigned int value) 1693{ 1694 int number_of_bits = 0; 1695 1696 while (value != 0) 1697 { 1698 number_of_bits += 1; 1699 value &= (value - 1); 1700 } 1701 return number_of_bits; 1702} 1703 1704/* Finds the address that should contain the single step breakpoint(s). 1705 It stems from code in cris-dis.c. */ 1706 1707static int 1708find_cris_op (unsigned short insn, inst_env_type *inst_env) 1709{ 1710 int i; 1711 int max_level_of_match = -1; 1712 int max_matched = -1; 1713 int level_of_match; 1714 1715 for (i = 0; cris_opcodes[i].name != NULL; i++) 1716 { 1717 if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match) 1718 && ((cris_opcodes[i].lose & insn) == 0)) 1719 { 1720 level_of_match = constraint (insn, cris_opcodes[i].args, inst_env); 1721 if (level_of_match >= 0) 1722 { 1723 level_of_match += 1724 number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose); 1725 if (level_of_match > max_level_of_match) 1726 { 1727 max_matched = i; 1728 max_level_of_match = level_of_match; 1729 if (level_of_match == 16) 1730 { 1731 /* All bits matched, cannot find better. */ 1732 break; 1733 } 1734 } 1735 } 1736 } 1737 } 1738 return max_matched; 1739} 1740 1741/* Attempts to find single-step breakpoints. Returns -1 on failure which is 1742 actually an internal error. */ 1743 1744static int 1745find_step_target (inst_env_type *inst_env) 1746{ 1747 int i; 1748 int offset; 1749 unsigned short insn; 1750 1751 /* Create a local register image and set the initial state. */ 1752 for (i = 0; i < NUM_GENREGS; i++) 1753 { 1754 inst_env->reg[i] = (unsigned long) read_register (i); 1755 } 1756 offset = NUM_GENREGS; 1757 for (i = 0; i < NUM_SPECREGS; i++) 1758 { 1759 inst_env->preg[i] = (unsigned long) read_register (offset + i); 1760 } 1761 inst_env->branch_found = 0; 1762 inst_env->slot_needed = 0; 1763 inst_env->delay_slot_pc_active = 0; 1764 inst_env->prefix_found = 0; 1765 inst_env->invalid = 0; 1766 inst_env->xflag_found = 0; 1767 inst_env->disable_interrupt = 0; 1768 1769 /* Look for a step target. */ 1770 do 1771 { 1772 /* Read an instruction from the client. */ 1773 insn = read_memory_unsigned_integer (inst_env->reg[PC_REGNUM], 2); 1774 1775 /* If the instruction is not in a delay slot the new content of the 1776 PC is [PC] + 2. If the instruction is in a delay slot it is not 1777 that simple. Since a instruction in a delay slot cannot change 1778 the content of the PC, it does not matter what value PC will have. 1779 Just make sure it is a valid instruction. */ 1780 if (!inst_env->delay_slot_pc_active) 1781 { 1782 inst_env->reg[PC_REGNUM] += 2; 1783 } 1784 else 1785 { 1786 inst_env->delay_slot_pc_active = 0; 1787 inst_env->reg[PC_REGNUM] = inst_env->delay_slot_pc; 1788 } 1789 /* Analyse the present instruction. */ 1790 i = find_cris_op (insn, inst_env); 1791 if (i == -1) 1792 { 1793 inst_env->invalid = 1; 1794 } 1795 else 1796 { 1797 cris_gdb_func (cris_opcodes[i].op, insn, inst_env); 1798 } 1799 } while (!inst_env->invalid 1800 && (inst_env->prefix_found || inst_env->xflag_found 1801 || inst_env->slot_needed)); 1802 return i; 1803} 1804 1805/* There is no hardware single-step support. The function find_step_target 1806 digs through the opcodes in order to find all possible targets. 1807 Either one ordinary target or two targets for branches may be found. */ 1808 1809static void 1810cris_software_single_step (enum target_signal ignore, int insert_breakpoints) 1811{ 1812 inst_env_type inst_env; 1813 1814 if (insert_breakpoints) 1815 { 1816 /* Analyse the present instruction environment and insert 1817 breakpoints. */ 1818 int status = find_step_target (&inst_env); 1819 if (status == -1) 1820 { 1821 /* Could not find a target. FIXME: Should do something. */ 1822 warning ("cris_software_single_step: unable to find step target"); 1823 } 1824 else 1825 { 1826 /* Insert at most two breakpoints. One for the next PC content 1827 and possibly another one for a branch, jump, etc. */ 1828 next_pc = (CORE_ADDR) inst_env.reg[PC_REGNUM]; 1829 target_insert_breakpoint (next_pc, break_mem[0]); 1830 if (inst_env.branch_found 1831 && (CORE_ADDR) inst_env.branch_break_address != next_pc) 1832 { 1833 branch_target_address = 1834 (CORE_ADDR) inst_env.branch_break_address; 1835 target_insert_breakpoint (branch_target_address, break_mem[1]); 1836 branch_break_inserted = 1; 1837 } 1838 } 1839 } 1840 else 1841 { 1842 /* Remove breakpoints. */ 1843 target_remove_breakpoint (next_pc, break_mem[0]); 1844 if (branch_break_inserted) 1845 { 1846 target_remove_breakpoint (branch_target_address, break_mem[1]); 1847 branch_break_inserted = 0; 1848 } 1849 } 1850} 1851 1852/* Calculates the prefix value for quick offset addressing mode. */ 1853 1854static void 1855quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env) 1856{ 1857 /* It's invalid to be in a delay slot. You can't have a prefix to this 1858 instruction (not 100% sure). */ 1859 if (inst_env->slot_needed || inst_env->prefix_found) 1860 { 1861 inst_env->invalid = 1; 1862 return; 1863 } 1864 1865 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; 1866 inst_env->prefix_value += cris_get_bdap_quick_offset (inst); 1867 1868 /* A prefix doesn't change the xflag_found. But the rest of the flags 1869 need updating. */ 1870 inst_env->slot_needed = 0; 1871 inst_env->prefix_found = 1; 1872} 1873 1874/* Updates the autoincrement register. The size of the increment is derived 1875 from the size of the operation. The PC is always kept aligned on even 1876 word addresses. */ 1877 1878static void 1879process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env) 1880{ 1881 if (size == INST_BYTE_SIZE) 1882 { 1883 inst_env->reg[cris_get_operand1 (inst)] += 1; 1884 1885 /* The PC must be word aligned, so increase the PC with one 1886 word even if the size is byte. */ 1887 if (cris_get_operand1 (inst) == REG_PC) 1888 { 1889 inst_env->reg[REG_PC] += 1; 1890 } 1891 } 1892 else if (size == INST_WORD_SIZE) 1893 { 1894 inst_env->reg[cris_get_operand1 (inst)] += 2; 1895 } 1896 else if (size == INST_DWORD_SIZE) 1897 { 1898 inst_env->reg[cris_get_operand1 (inst)] += 4; 1899 } 1900 else 1901 { 1902 /* Invalid size. */ 1903 inst_env->invalid = 1; 1904 } 1905} 1906 1907/* Just a forward declaration. */ 1908 1909static unsigned long get_data_from_address (unsigned short *inst, 1910 CORE_ADDR address); 1911 1912/* Calculates the prefix value for the general case of offset addressing 1913 mode. */ 1914 1915static void 1916bdap_prefix (unsigned short inst, inst_env_type *inst_env) 1917{ 1918 1919 long offset; 1920 1921 /* It's invalid to be in a delay slot. */ 1922 if (inst_env->slot_needed || inst_env->prefix_found) 1923 { 1924 inst_env->invalid = 1; 1925 return; 1926 } 1927 1928 /* The calculation of prefix_value used to be after process_autoincrement, 1929 but that fails for an instruction such as jsr [$r0+12] which is encoded 1930 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it 1931 mustn't be incremented until we have read it and what it points at. */ 1932 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; 1933 1934 /* The offset is an indirection of the contents of the operand1 register. */ 1935 inst_env->prefix_value += 1936 get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)]); 1937 1938 if (cris_get_mode (inst) == AUTOINC_MODE) 1939 { 1940 process_autoincrement (cris_get_size (inst), inst, inst_env); 1941 } 1942 1943 /* A prefix doesn't change the xflag_found. But the rest of the flags 1944 need updating. */ 1945 inst_env->slot_needed = 0; 1946 inst_env->prefix_found = 1; 1947} 1948 1949/* Calculates the prefix value for the index addressing mode. */ 1950 1951static void 1952biap_prefix (unsigned short inst, inst_env_type *inst_env) 1953{ 1954 /* It's invalid to be in a delay slot. I can't see that it's possible to 1955 have a prefix to this instruction. So I will treat this as invalid. */ 1956 if (inst_env->slot_needed || inst_env->prefix_found) 1957 { 1958 inst_env->invalid = 1; 1959 return; 1960 } 1961 1962 inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)]; 1963 1964 /* The offset is the operand2 value shifted the size of the instruction 1965 to the left. */ 1966 inst_env->prefix_value += 1967 inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst); 1968 1969 /* If the PC is operand1 (base) the address used is the address after 1970 the main instruction, i.e. address + 2 (the PC is already compensated 1971 for the prefix operation). */ 1972 if (cris_get_operand1 (inst) == REG_PC) 1973 { 1974 inst_env->prefix_value += 2; 1975 } 1976 1977 /* A prefix doesn't change the xflag_found. But the rest of the flags 1978 need updating. */ 1979 inst_env->slot_needed = 0; 1980 inst_env->xflag_found = 0; 1981 inst_env->prefix_found = 1; 1982} 1983 1984/* Calculates the prefix value for the double indirect addressing mode. */ 1985 1986static void 1987dip_prefix (unsigned short inst, inst_env_type *inst_env) 1988{ 1989 1990 CORE_ADDR address; 1991 1992 /* It's invalid to be in a delay slot. */ 1993 if (inst_env->slot_needed || inst_env->prefix_found) 1994 { 1995 inst_env->invalid = 1; 1996 return; 1997 } 1998 1999 /* The prefix value is one dereference of the contents of the operand1 2000 register. */ 2001 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; 2002 inst_env->prefix_value = read_memory_unsigned_integer (address, 4); 2003 2004 /* Check if the mode is autoincrement. */ 2005 if (cris_get_mode (inst) == AUTOINC_MODE) 2006 { 2007 inst_env->reg[cris_get_operand1 (inst)] += 4; 2008 } 2009 2010 /* A prefix doesn't change the xflag_found. But the rest of the flags 2011 need updating. */ 2012 inst_env->slot_needed = 0; 2013 inst_env->xflag_found = 0; 2014 inst_env->prefix_found = 1; 2015} 2016 2017/* Finds the destination for a branch with 8-bits offset. */ 2018 2019static void 2020eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) 2021{ 2022 2023 short offset; 2024 2025 /* If we have a prefix or are in a delay slot it's bad. */ 2026 if (inst_env->slot_needed || inst_env->prefix_found) 2027 { 2028 inst_env->invalid = 1; 2029 return; 2030 } 2031 2032 /* We have a branch, find out where the branch will land. */ 2033 offset = cris_get_branch_short_offset (inst); 2034 2035 /* Check if the offset is signed. */ 2036 if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK) 2037 { 2038 offset |= 0xFF00; 2039 } 2040 2041 /* The offset ends with the sign bit, set it to zero. The address 2042 should always be word aligned. */ 2043 offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK; 2044 2045 inst_env->branch_found = 1; 2046 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; 2047 2048 inst_env->slot_needed = 1; 2049 inst_env->prefix_found = 0; 2050 inst_env->xflag_found = 0; 2051 inst_env->disable_interrupt = 1; 2052} 2053 2054/* Finds the destination for a branch with 16-bits offset. */ 2055 2056static void 2057sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) 2058{ 2059 short offset; 2060 2061 /* If we have a prefix or is in a delay slot it's bad. */ 2062 if (inst_env->slot_needed || inst_env->prefix_found) 2063 { 2064 inst_env->invalid = 1; 2065 return; 2066 } 2067 2068 /* We have a branch, find out the offset for the branch. */ 2069 offset = read_memory_integer (inst_env->reg[REG_PC], 2); 2070 2071 /* The instruction is one word longer than normal, so add one word 2072 to the PC. */ 2073 inst_env->reg[REG_PC] += 2; 2074 2075 inst_env->branch_found = 1; 2076 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; 2077 2078 2079 inst_env->slot_needed = 1; 2080 inst_env->prefix_found = 0; 2081 inst_env->xflag_found = 0; 2082 inst_env->disable_interrupt = 1; 2083} 2084 2085/* Handles the ABS instruction. */ 2086 2087static void 2088abs_op (unsigned short inst, inst_env_type *inst_env) 2089{ 2090 2091 long value; 2092 2093 /* ABS can't have a prefix, so it's bad if it does. */ 2094 if (inst_env->prefix_found) 2095 { 2096 inst_env->invalid = 1; 2097 return; 2098 } 2099 2100 /* Check if the operation affects the PC. */ 2101 if (cris_get_operand2 (inst) == REG_PC) 2102 { 2103 2104 /* It's invalid to change to the PC if we are in a delay slot. */ 2105 if (inst_env->slot_needed) 2106 { 2107 inst_env->invalid = 1; 2108 return; 2109 } 2110 2111 value = (long) inst_env->reg[REG_PC]; 2112 2113 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */ 2114 if (value != SIGNED_DWORD_MASK) 2115 { 2116 value = -value; 2117 inst_env->reg[REG_PC] = (long) value; 2118 } 2119 } 2120 2121 inst_env->slot_needed = 0; 2122 inst_env->prefix_found = 0; 2123 inst_env->xflag_found = 0; 2124 inst_env->disable_interrupt = 0; 2125} 2126 2127/* Handles the ADDI instruction. */ 2128 2129static void 2130addi_op (unsigned short inst, inst_env_type *inst_env) 2131{ 2132 /* It's invalid to have the PC as base register. And ADDI can't have 2133 a prefix. */ 2134 if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC)) 2135 { 2136 inst_env->invalid = 1; 2137 return; 2138 } 2139 2140 inst_env->slot_needed = 0; 2141 inst_env->prefix_found = 0; 2142 inst_env->xflag_found = 0; 2143 inst_env->disable_interrupt = 0; 2144} 2145 2146/* Handles the ASR instruction. */ 2147 2148static void 2149asr_op (unsigned short inst, inst_env_type *inst_env) 2150{ 2151 int shift_steps; 2152 unsigned long value; 2153 unsigned long signed_extend_mask = 0; 2154 2155 /* ASR can't have a prefix, so check that it doesn't. */ 2156 if (inst_env->prefix_found) 2157 { 2158 inst_env->invalid = 1; 2159 return; 2160 } 2161 2162 /* Check if the PC is the target register. */ 2163 if (cris_get_operand2 (inst) == REG_PC) 2164 { 2165 /* It's invalid to change the PC in a delay slot. */ 2166 if (inst_env->slot_needed) 2167 { 2168 inst_env->invalid = 1; 2169 return; 2170 } 2171 /* Get the number of bits to shift. */ 2172 shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]); 2173 value = inst_env->reg[REG_PC]; 2174 2175 /* Find out how many bits the operation should apply to. */ 2176 if (cris_get_size (inst) == INST_BYTE_SIZE) 2177 { 2178 if (value & SIGNED_BYTE_MASK) 2179 { 2180 signed_extend_mask = 0xFF; 2181 signed_extend_mask = signed_extend_mask >> shift_steps; 2182 signed_extend_mask = ~signed_extend_mask; 2183 } 2184 value = value >> shift_steps; 2185 value |= signed_extend_mask; 2186 value &= 0xFF; 2187 inst_env->reg[REG_PC] &= 0xFFFFFF00; 2188 inst_env->reg[REG_PC] |= value; 2189 } 2190 else if (cris_get_size (inst) == INST_WORD_SIZE) 2191 { 2192 if (value & SIGNED_WORD_MASK) 2193 { 2194 signed_extend_mask = 0xFFFF; 2195 signed_extend_mask = signed_extend_mask >> shift_steps; 2196 signed_extend_mask = ~signed_extend_mask; 2197 } 2198 value = value >> shift_steps; 2199 value |= signed_extend_mask; 2200 value &= 0xFFFF; 2201 inst_env->reg[REG_PC] &= 0xFFFF0000; 2202 inst_env->reg[REG_PC] |= value; 2203 } 2204 else if (cris_get_size (inst) == INST_DWORD_SIZE) 2205 { 2206 if (value & SIGNED_DWORD_MASK) 2207 { 2208 signed_extend_mask = 0xFFFFFFFF; 2209 signed_extend_mask = signed_extend_mask >> shift_steps; 2210 signed_extend_mask = ~signed_extend_mask; 2211 } 2212 value = value >> shift_steps; 2213 value |= signed_extend_mask; 2214 inst_env->reg[REG_PC] = value; 2215 } 2216 } 2217 inst_env->slot_needed = 0; 2218 inst_env->prefix_found = 0; 2219 inst_env->xflag_found = 0; 2220 inst_env->disable_interrupt = 0; 2221} 2222 2223/* Handles the ASRQ instruction. */ 2224 2225static void 2226asrq_op (unsigned short inst, inst_env_type *inst_env) 2227{ 2228 2229 int shift_steps; 2230 unsigned long value; 2231 unsigned long signed_extend_mask = 0; 2232 2233 /* ASRQ can't have a prefix, so check that it doesn't. */ 2234 if (inst_env->prefix_found) 2235 { 2236 inst_env->invalid = 1; 2237 return; 2238 } 2239 2240 /* Check if the PC is the target register. */ 2241 if (cris_get_operand2 (inst) == REG_PC) 2242 { 2243 2244 /* It's invalid to change the PC in a delay slot. */ 2245 if (inst_env->slot_needed) 2246 { 2247 inst_env->invalid = 1; 2248 return; 2249 } 2250 /* The shift size is given as a 5 bit quick value, i.e. we don't 2251 want the the sign bit of the quick value. */ 2252 shift_steps = cris_get_asr_shift_steps (inst); 2253 value = inst_env->reg[REG_PC]; 2254 if (value & SIGNED_DWORD_MASK) 2255 { 2256 signed_extend_mask = 0xFFFFFFFF; 2257 signed_extend_mask = signed_extend_mask >> shift_steps; 2258 signed_extend_mask = ~signed_extend_mask; 2259 } 2260 value = value >> shift_steps; 2261 value |= signed_extend_mask; 2262 inst_env->reg[REG_PC] = value; 2263 } 2264 inst_env->slot_needed = 0; 2265 inst_env->prefix_found = 0; 2266 inst_env->xflag_found = 0; 2267 inst_env->disable_interrupt = 0; 2268} 2269 2270/* Handles the AX, EI and SETF instruction. */ 2271 2272static void 2273ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env) 2274{ 2275 if (inst_env->prefix_found) 2276 { 2277 inst_env->invalid = 1; 2278 return; 2279 } 2280 /* Check if the instruction is setting the X flag. */ 2281 if (cris_is_xflag_bit_on (inst)) 2282 { 2283 inst_env->xflag_found = 1; 2284 } 2285 else 2286 { 2287 inst_env->xflag_found = 0; 2288 } 2289 inst_env->slot_needed = 0; 2290 inst_env->prefix_found = 0; 2291 inst_env->disable_interrupt = 1; 2292} 2293 2294/* Checks if the instruction is in assign mode. If so, it updates the assign 2295 register. Note that check_assign assumes that the caller has checked that 2296 there is a prefix to this instruction. The mode check depends on this. */ 2297 2298static void 2299check_assign (unsigned short inst, inst_env_type *inst_env) 2300{ 2301 /* Check if it's an assign addressing mode. */ 2302 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) 2303 { 2304 /* Assign the prefix value to operand 1. */ 2305 inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value; 2306 } 2307} 2308 2309/* Handles the 2-operand BOUND instruction. */ 2310 2311static void 2312two_operand_bound_op (unsigned short inst, inst_env_type *inst_env) 2313{ 2314 /* It's invalid to have the PC as the index operand. */ 2315 if (cris_get_operand2 (inst) == REG_PC) 2316 { 2317 inst_env->invalid = 1; 2318 return; 2319 } 2320 /* Check if we have a prefix. */ 2321 if (inst_env->prefix_found) 2322 { 2323 check_assign (inst, inst_env); 2324 } 2325 /* Check if this is an autoincrement mode. */ 2326 else if (cris_get_mode (inst) == AUTOINC_MODE) 2327 { 2328 /* It's invalid to change the PC in a delay slot. */ 2329 if (inst_env->slot_needed) 2330 { 2331 inst_env->invalid = 1; 2332 return; 2333 } 2334 process_autoincrement (cris_get_size (inst), inst, inst_env); 2335 } 2336 inst_env->slot_needed = 0; 2337 inst_env->prefix_found = 0; 2338 inst_env->xflag_found = 0; 2339 inst_env->disable_interrupt = 0; 2340} 2341 2342/* Handles the 3-operand BOUND instruction. */ 2343 2344static void 2345three_operand_bound_op (unsigned short inst, inst_env_type *inst_env) 2346{ 2347 /* It's an error if we haven't got a prefix. And it's also an error 2348 if the PC is the destination register. */ 2349 if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC)) 2350 { 2351 inst_env->invalid = 1; 2352 return; 2353 } 2354 inst_env->slot_needed = 0; 2355 inst_env->prefix_found = 0; 2356 inst_env->xflag_found = 0; 2357 inst_env->disable_interrupt = 0; 2358} 2359 2360/* Clears the status flags in inst_env. */ 2361 2362static void 2363btst_nop_op (unsigned short inst, inst_env_type *inst_env) 2364{ 2365 /* It's an error if we have got a prefix. */ 2366 if (inst_env->prefix_found) 2367 { 2368 inst_env->invalid = 1; 2369 return; 2370 } 2371 2372 inst_env->slot_needed = 0; 2373 inst_env->prefix_found = 0; 2374 inst_env->xflag_found = 0; 2375 inst_env->disable_interrupt = 0; 2376} 2377 2378/* Clears the status flags in inst_env. */ 2379 2380static void 2381clearf_di_op (unsigned short inst, inst_env_type *inst_env) 2382{ 2383 /* It's an error if we have got a prefix. */ 2384 if (inst_env->prefix_found) 2385 { 2386 inst_env->invalid = 1; 2387 return; 2388 } 2389 2390 inst_env->slot_needed = 0; 2391 inst_env->prefix_found = 0; 2392 inst_env->xflag_found = 0; 2393 inst_env->disable_interrupt = 1; 2394} 2395 2396/* Handles the CLEAR instruction if it's in register mode. */ 2397 2398static void 2399reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env) 2400{ 2401 /* Check if the target is the PC. */ 2402 if (cris_get_operand2 (inst) == REG_PC) 2403 { 2404 /* The instruction will clear the instruction's size bits. */ 2405 int clear_size = cris_get_clear_size (inst); 2406 if (clear_size == INST_BYTE_SIZE) 2407 { 2408 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00; 2409 } 2410 if (clear_size == INST_WORD_SIZE) 2411 { 2412 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000; 2413 } 2414 if (clear_size == INST_DWORD_SIZE) 2415 { 2416 inst_env->delay_slot_pc = 0x0; 2417 } 2418 /* The jump will be delayed with one delay slot. So we need a delay 2419 slot. */ 2420 inst_env->slot_needed = 1; 2421 inst_env->delay_slot_pc_active = 1; 2422 } 2423 else 2424 { 2425 /* The PC will not change => no delay slot. */ 2426 inst_env->slot_needed = 0; 2427 } 2428 inst_env->prefix_found = 0; 2429 inst_env->xflag_found = 0; 2430 inst_env->disable_interrupt = 0; 2431} 2432 2433/* Handles the TEST instruction if it's in register mode. */ 2434 2435static void 2436reg_mode_test_op (unsigned short inst, inst_env_type *inst_env) 2437{ 2438 /* It's an error if we have got a prefix. */ 2439 if (inst_env->prefix_found) 2440 { 2441 inst_env->invalid = 1; 2442 return; 2443 } 2444 inst_env->slot_needed = 0; 2445 inst_env->prefix_found = 0; 2446 inst_env->xflag_found = 0; 2447 inst_env->disable_interrupt = 0; 2448 2449} 2450 2451/* Handles the CLEAR and TEST instruction if the instruction isn't 2452 in register mode. */ 2453 2454static void 2455none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env) 2456{ 2457 /* Check if we are in a prefix mode. */ 2458 if (inst_env->prefix_found) 2459 { 2460 /* The only way the PC can change is if this instruction is in 2461 assign addressing mode. */ 2462 check_assign (inst, inst_env); 2463 } 2464 /* Indirect mode can't change the PC so just check if the mode is 2465 autoincrement. */ 2466 else if (cris_get_mode (inst) == AUTOINC_MODE) 2467 { 2468 process_autoincrement (cris_get_size (inst), inst, inst_env); 2469 } 2470 inst_env->slot_needed = 0; 2471 inst_env->prefix_found = 0; 2472 inst_env->xflag_found = 0; 2473 inst_env->disable_interrupt = 0; 2474} 2475 2476/* Checks that the PC isn't the destination register or the instructions has 2477 a prefix. */ 2478 2479static void 2480dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env) 2481{ 2482 /* It's invalid to have the PC as the destination. The instruction can't 2483 have a prefix. */ 2484 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) 2485 { 2486 inst_env->invalid = 1; 2487 return; 2488 } 2489 2490 inst_env->slot_needed = 0; 2491 inst_env->prefix_found = 0; 2492 inst_env->xflag_found = 0; 2493 inst_env->disable_interrupt = 0; 2494} 2495 2496/* Checks that the instruction doesn't have a prefix. */ 2497 2498static void 2499break_op (unsigned short inst, inst_env_type *inst_env) 2500{ 2501 /* The instruction can't have a prefix. */ 2502 if (inst_env->prefix_found) 2503 { 2504 inst_env->invalid = 1; 2505 return; 2506 } 2507 2508 inst_env->slot_needed = 0; 2509 inst_env->prefix_found = 0; 2510 inst_env->xflag_found = 0; 2511 inst_env->disable_interrupt = 1; 2512} 2513 2514/* Checks that the PC isn't the destination register and that the instruction 2515 doesn't have a prefix. */ 2516 2517static void 2518scc_op (unsigned short inst, inst_env_type *inst_env) 2519{ 2520 /* It's invalid to have the PC as the destination. The instruction can't 2521 have a prefix. */ 2522 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) 2523 { 2524 inst_env->invalid = 1; 2525 return; 2526 } 2527 2528 inst_env->slot_needed = 0; 2529 inst_env->prefix_found = 0; 2530 inst_env->xflag_found = 0; 2531 inst_env->disable_interrupt = 1; 2532} 2533 2534/* Handles the register mode JUMP instruction. */ 2535 2536static void 2537reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) 2538{ 2539 /* It's invalid to do a JUMP in a delay slot. The mode is register, so 2540 you can't have a prefix. */ 2541 if ((inst_env->slot_needed) || (inst_env->prefix_found)) 2542 { 2543 inst_env->invalid = 1; 2544 return; 2545 } 2546 2547 /* Just change the PC. */ 2548 inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)]; 2549 inst_env->slot_needed = 0; 2550 inst_env->prefix_found = 0; 2551 inst_env->xflag_found = 0; 2552 inst_env->disable_interrupt = 1; 2553} 2554 2555/* Handles the JUMP instruction for all modes except register. */ 2556 2557static void 2558none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) 2559{ 2560 unsigned long newpc; 2561 CORE_ADDR address; 2562 2563 /* It's invalid to do a JUMP in a delay slot. */ 2564 if (inst_env->slot_needed) 2565 { 2566 inst_env->invalid = 1; 2567 } 2568 else 2569 { 2570 /* Check if we have a prefix. */ 2571 if (inst_env->prefix_found) 2572 { 2573 check_assign (inst, inst_env); 2574 2575 /* Get the new value for the the PC. */ 2576 newpc = 2577 read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value, 2578 4); 2579 } 2580 else 2581 { 2582 /* Get the new value for the PC. */ 2583 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; 2584 newpc = read_memory_unsigned_integer (address, 4); 2585 2586 /* Check if we should increment a register. */ 2587 if (cris_get_mode (inst) == AUTOINC_MODE) 2588 { 2589 inst_env->reg[cris_get_operand1 (inst)] += 4; 2590 } 2591 } 2592 inst_env->reg[REG_PC] = newpc; 2593 } 2594 inst_env->slot_needed = 0; 2595 inst_env->prefix_found = 0; 2596 inst_env->xflag_found = 0; 2597 inst_env->disable_interrupt = 1; 2598} 2599 2600/* Handles moves to special registers (aka P-register) for all modes. */ 2601 2602static void 2603move_to_preg_op (unsigned short inst, inst_env_type *inst_env) 2604{ 2605 if (inst_env->prefix_found) 2606 { 2607 /* The instruction has a prefix that means we are only interested if 2608 the instruction is in assign mode. */ 2609 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) 2610 { 2611 /* The prefix handles the problem if we are in a delay slot. */ 2612 if (cris_get_operand1 (inst) == REG_PC) 2613 { 2614 /* Just take care of the assign. */ 2615 check_assign (inst, inst_env); 2616 } 2617 } 2618 } 2619 else if (cris_get_mode (inst) == AUTOINC_MODE) 2620 { 2621 /* The instruction doesn't have a prefix, the only case left that we 2622 are interested in is the autoincrement mode. */ 2623 if (cris_get_operand1 (inst) == REG_PC) 2624 { 2625 /* If the PC is to be incremented it's invalid to be in a 2626 delay slot. */ 2627 if (inst_env->slot_needed) 2628 { 2629 inst_env->invalid = 1; 2630 return; 2631 } 2632 2633 /* The increment depends on the size of the special register. */ 2634 if (cris_register_size (cris_get_operand2 (inst)) == 1) 2635 { 2636 process_autoincrement (INST_BYTE_SIZE, inst, inst_env); 2637 } 2638 else if (cris_register_size (cris_get_operand2 (inst)) == 2) 2639 { 2640 process_autoincrement (INST_WORD_SIZE, inst, inst_env); 2641 } 2642 else 2643 { 2644 process_autoincrement (INST_DWORD_SIZE, inst, inst_env); 2645 } 2646 } 2647 } 2648 inst_env->slot_needed = 0; 2649 inst_env->prefix_found = 0; 2650 inst_env->xflag_found = 0; 2651 inst_env->disable_interrupt = 1; 2652} 2653 2654/* Handles moves from special registers (aka P-register) for all modes 2655 except register. */ 2656 2657static void 2658none_reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) 2659{ 2660 if (inst_env->prefix_found) 2661 { 2662 /* The instruction has a prefix that means we are only interested if 2663 the instruction is in assign mode. */ 2664 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) 2665 { 2666 /* The prefix handles the problem if we are in a delay slot. */ 2667 if (cris_get_operand1 (inst) == REG_PC) 2668 { 2669 /* Just take care of the assign. */ 2670 check_assign (inst, inst_env); 2671 } 2672 } 2673 } 2674 /* The instruction doesn't have a prefix, the only case left that we 2675 are interested in is the autoincrement mode. */ 2676 else if (cris_get_mode (inst) == AUTOINC_MODE) 2677 { 2678 if (cris_get_operand1 (inst) == REG_PC) 2679 { 2680 /* If the PC is to be incremented it's invalid to be in a 2681 delay slot. */ 2682 if (inst_env->slot_needed) 2683 { 2684 inst_env->invalid = 1; 2685 return; 2686 } 2687 2688 /* The increment depends on the size of the special register. */ 2689 if (cris_register_size (cris_get_operand2 (inst)) == 1) 2690 { 2691 process_autoincrement (INST_BYTE_SIZE, inst, inst_env); 2692 } 2693 else if (cris_register_size (cris_get_operand2 (inst)) == 2) 2694 { 2695 process_autoincrement (INST_WORD_SIZE, inst, inst_env); 2696 } 2697 else 2698 { 2699 process_autoincrement (INST_DWORD_SIZE, inst, inst_env); 2700 } 2701 } 2702 } 2703 inst_env->slot_needed = 0; 2704 inst_env->prefix_found = 0; 2705 inst_env->xflag_found = 0; 2706 inst_env->disable_interrupt = 1; 2707} 2708 2709/* Handles moves from special registers (aka P-register) when the mode 2710 is register. */ 2711 2712static void 2713reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) 2714{ 2715 /* Register mode move from special register can't have a prefix. */ 2716 if (inst_env->prefix_found) 2717 { 2718 inst_env->invalid = 1; 2719 return; 2720 } 2721 2722 if (cris_get_operand1 (inst) == REG_PC) 2723 { 2724 /* It's invalid to change the PC in a delay slot. */ 2725 if (inst_env->slot_needed) 2726 { 2727 inst_env->invalid = 1; 2728 return; 2729 } 2730 /* The destination is the PC, the jump will have a delay slot. */ 2731 inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)]; 2732 inst_env->slot_needed = 1; 2733 inst_env->delay_slot_pc_active = 1; 2734 } 2735 else 2736 { 2737 /* If the destination isn't PC, there will be no jump. */ 2738 inst_env->slot_needed = 0; 2739 } 2740 inst_env->prefix_found = 0; 2741 inst_env->xflag_found = 0; 2742 inst_env->disable_interrupt = 1; 2743} 2744 2745/* Handles the MOVEM from memory to general register instruction. */ 2746 2747static void 2748move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env) 2749{ 2750 if (inst_env->prefix_found) 2751 { 2752 /* The prefix handles the problem if we are in a delay slot. Is the 2753 MOVEM instruction going to change the PC? */ 2754 if (cris_get_operand2 (inst) >= REG_PC) 2755 { 2756 inst_env->reg[REG_PC] = 2757 read_memory_unsigned_integer (inst_env->prefix_value, 4); 2758 } 2759 /* The assign value is the value after the increment. Normally, the 2760 assign value is the value before the increment. */ 2761 if ((cris_get_operand1 (inst) == REG_PC) 2762 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) 2763 { 2764 inst_env->reg[REG_PC] = inst_env->prefix_value; 2765 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); 2766 } 2767 } 2768 else 2769 { 2770 /* Is the MOVEM instruction going to change the PC? */ 2771 if (cris_get_operand2 (inst) == REG_PC) 2772 { 2773 /* It's invalid to change the PC in a delay slot. */ 2774 if (inst_env->slot_needed) 2775 { 2776 inst_env->invalid = 1; 2777 return; 2778 } 2779 inst_env->reg[REG_PC] = 2780 read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)], 2781 4); 2782 } 2783 /* The increment is not depending on the size, instead it's depending 2784 on the number of registers loaded from memory. */ 2785 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) 2786 { 2787 /* It's invalid to change the PC in a delay slot. */ 2788 if (inst_env->slot_needed) 2789 { 2790 inst_env->invalid = 1; 2791 return; 2792 } 2793 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); 2794 } 2795 } 2796 inst_env->slot_needed = 0; 2797 inst_env->prefix_found = 0; 2798 inst_env->xflag_found = 0; 2799 inst_env->disable_interrupt = 0; 2800} 2801 2802/* Handles the MOVEM to memory from general register instruction. */ 2803 2804static void 2805move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env) 2806{ 2807 if (inst_env->prefix_found) 2808 { 2809 /* The assign value is the value after the increment. Normally, the 2810 assign value is the value before the increment. */ 2811 if ((cris_get_operand1 (inst) == REG_PC) && 2812 (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) 2813 { 2814 /* The prefix handles the problem if we are in a delay slot. */ 2815 inst_env->reg[REG_PC] = inst_env->prefix_value; 2816 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); 2817 } 2818 } 2819 else 2820 { 2821 /* The increment is not depending on the size, instead it's depending 2822 on the number of registers loaded to memory. */ 2823 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) 2824 { 2825 /* It's invalid to change the PC in a delay slot. */ 2826 if (inst_env->slot_needed) 2827 { 2828 inst_env->invalid = 1; 2829 return; 2830 } 2831 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); 2832 } 2833 } 2834 inst_env->slot_needed = 0; 2835 inst_env->prefix_found = 0; 2836 inst_env->xflag_found = 0; 2837 inst_env->disable_interrupt = 0; 2838} 2839 2840/* Handles the intructions that's not yet implemented, by setting 2841 inst_env->invalid to true. */ 2842 2843static void 2844not_implemented_op (unsigned short inst, inst_env_type *inst_env) 2845{ 2846 inst_env->invalid = 1; 2847} 2848 2849/* Handles the XOR instruction. */ 2850 2851static void 2852xor_op (unsigned short inst, inst_env_type *inst_env) 2853{ 2854 /* XOR can't have a prefix. */ 2855 if (inst_env->prefix_found) 2856 { 2857 inst_env->invalid = 1; 2858 return; 2859 } 2860 2861 /* Check if the PC is the target. */ 2862 if (cris_get_operand2 (inst) == REG_PC) 2863 { 2864 /* It's invalid to change the PC in a delay slot. */ 2865 if (inst_env->slot_needed) 2866 { 2867 inst_env->invalid = 1; 2868 return; 2869 } 2870 inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)]; 2871 } 2872 inst_env->slot_needed = 0; 2873 inst_env->prefix_found = 0; 2874 inst_env->xflag_found = 0; 2875 inst_env->disable_interrupt = 0; 2876} 2877 2878/* Handles the MULS instruction. */ 2879 2880static void 2881muls_op (unsigned short inst, inst_env_type *inst_env) 2882{ 2883 /* MULS/U can't have a prefix. */ 2884 if (inst_env->prefix_found) 2885 { 2886 inst_env->invalid = 1; 2887 return; 2888 } 2889 2890 /* Consider it invalid if the PC is the target. */ 2891 if (cris_get_operand2 (inst) == REG_PC) 2892 { 2893 inst_env->invalid = 1; 2894 return; 2895 } 2896 inst_env->slot_needed = 0; 2897 inst_env->prefix_found = 0; 2898 inst_env->xflag_found = 0; 2899 inst_env->disable_interrupt = 0; 2900} 2901 2902/* Handles the MULU instruction. */ 2903 2904static void 2905mulu_op (unsigned short inst, inst_env_type *inst_env) 2906{ 2907 /* MULS/U can't have a prefix. */ 2908 if (inst_env->prefix_found) 2909 { 2910 inst_env->invalid = 1; 2911 return; 2912 } 2913 2914 /* Consider it invalid if the PC is the target. */ 2915 if (cris_get_operand2 (inst) == REG_PC) 2916 { 2917 inst_env->invalid = 1; 2918 return; 2919 } 2920 inst_env->slot_needed = 0; 2921 inst_env->prefix_found = 0; 2922 inst_env->xflag_found = 0; 2923 inst_env->disable_interrupt = 0; 2924} 2925 2926/* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE. 2927 The MOVE instruction is the move from source to register. */ 2928 2929static void 2930add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env, 2931 unsigned long source1, unsigned long source2) 2932{ 2933 unsigned long pc_mask; 2934 unsigned long operation_mask; 2935 2936 /* Find out how many bits the operation should apply to. */ 2937 if (cris_get_size (inst) == INST_BYTE_SIZE) 2938 { 2939 pc_mask = 0xFFFFFF00; 2940 operation_mask = 0xFF; 2941 } 2942 else if (cris_get_size (inst) == INST_WORD_SIZE) 2943 { 2944 pc_mask = 0xFFFF0000; 2945 operation_mask = 0xFFFF; 2946 } 2947 else if (cris_get_size (inst) == INST_DWORD_SIZE) 2948 { 2949 pc_mask = 0x0; 2950 operation_mask = 0xFFFFFFFF; 2951 } 2952 else 2953 { 2954 /* The size is out of range. */ 2955 inst_env->invalid = 1; 2956 return; 2957 } 2958 2959 /* The instruction just works on uw_operation_mask bits. */ 2960 source2 &= operation_mask; 2961 source1 &= operation_mask; 2962 2963 /* Now calculate the result. The opcode's 3 first bits separates 2964 the different actions. */ 2965 switch (cris_get_opcode (inst) & 7) 2966 { 2967 case 0: /* add */ 2968 source1 += source2; 2969 break; 2970 2971 case 1: /* move */ 2972 source1 = source2; 2973 break; 2974 2975 case 2: /* subtract */ 2976 source1 -= source2; 2977 break; 2978 2979 case 3: /* compare */ 2980 break; 2981 2982 case 4: /* and */ 2983 source1 &= source2; 2984 break; 2985 2986 case 5: /* or */ 2987 source1 |= source2; 2988 break; 2989 2990 default: 2991 inst_env->invalid = 1; 2992 return; 2993 2994 break; 2995 } 2996 2997 /* Make sure that the result doesn't contain more than the instruction 2998 size bits. */ 2999 source2 &= operation_mask; 3000 3001 /* Calculate the new breakpoint address. */ 3002 inst_env->reg[REG_PC] &= pc_mask; 3003 inst_env->reg[REG_PC] |= source1; 3004 3005} 3006 3007/* Extends the value from either byte or word size to a dword. If the mode 3008 is zero extend then the value is extended with zero. If instead the mode 3009 is signed extend the sign bit of the value is taken into consideration. */ 3010 3011static unsigned long 3012do_sign_or_zero_extend (unsigned long value, unsigned short *inst) 3013{ 3014 /* The size can be either byte or word, check which one it is. 3015 Don't check the highest bit, it's indicating if it's a zero 3016 or sign extend. */ 3017 if (cris_get_size (*inst) & INST_WORD_SIZE) 3018 { 3019 /* Word size. */ 3020 value &= 0xFFFF; 3021 3022 /* Check if the instruction is signed extend. If so, check if value has 3023 the sign bit on. */ 3024 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK)) 3025 { 3026 value |= SIGNED_WORD_EXTEND_MASK; 3027 } 3028 } 3029 else 3030 { 3031 /* Byte size. */ 3032 value &= 0xFF; 3033 3034 /* Check if the instruction is signed extend. If so, check if value has 3035 the sign bit on. */ 3036 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK)) 3037 { 3038 value |= SIGNED_BYTE_EXTEND_MASK; 3039 } 3040 } 3041 /* The size should now be dword. */ 3042 cris_set_size_to_dword (inst); 3043 return value; 3044} 3045 3046/* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE 3047 instruction. The MOVE instruction is the move from source to register. */ 3048 3049static void 3050reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, 3051 inst_env_type *inst_env) 3052{ 3053 unsigned long operand1; 3054 unsigned long operand2; 3055 3056 /* It's invalid to have a prefix to the instruction. This is a register 3057 mode instruction and can't have a prefix. */ 3058 if (inst_env->prefix_found) 3059 { 3060 inst_env->invalid = 1; 3061 return; 3062 } 3063 /* Check if the instruction has PC as its target. */ 3064 if (cris_get_operand2 (inst) == REG_PC) 3065 { 3066 if (inst_env->slot_needed) 3067 { 3068 inst_env->invalid = 1; 3069 return; 3070 } 3071 /* The instruction has the PC as its target register. */ 3072 operand1 = inst_env->reg[cris_get_operand1 (inst)]; 3073 operand2 = inst_env->reg[REG_PC]; 3074 3075 /* Check if it's a extend, signed or zero instruction. */ 3076 if (cris_get_opcode (inst) < 4) 3077 { 3078 operand1 = do_sign_or_zero_extend (operand1, &inst); 3079 } 3080 /* Calculate the PC value after the instruction, i.e. where the 3081 breakpoint should be. The order of the udw_operands is vital. */ 3082 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); 3083 } 3084 inst_env->slot_needed = 0; 3085 inst_env->prefix_found = 0; 3086 inst_env->xflag_found = 0; 3087 inst_env->disable_interrupt = 0; 3088} 3089 3090/* Returns the data contained at address. The size of the data is derived from 3091 the size of the operation. If the instruction is a zero or signed 3092 extend instruction, the size field is changed in instruction. */ 3093 3094static unsigned long 3095get_data_from_address (unsigned short *inst, CORE_ADDR address) 3096{ 3097 int size = cris_get_size (*inst); 3098 unsigned long value; 3099 3100 /* If it's an extend instruction we don't want the signed extend bit, 3101 because it influences the size. */ 3102 if (cris_get_opcode (*inst) < 4) 3103 { 3104 size &= ~SIGNED_EXTEND_BIT_MASK; 3105 } 3106 /* Is there a need for checking the size? Size should contain the number of 3107 bytes to read. */ 3108 size = 1 << size; 3109 value = read_memory_unsigned_integer (address, size); 3110 3111 /* Check if it's an extend, signed or zero instruction. */ 3112 if (cris_get_opcode (*inst) < 4) 3113 { 3114 value = do_sign_or_zero_extend (value, inst); 3115 } 3116 return value; 3117} 3118 3119/* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE 3120 instructions. The MOVE instruction is the move from source to register. */ 3121 3122static void 3123handle_prefix_assign_mode_for_aritm_op (unsigned short inst, 3124 inst_env_type *inst_env) 3125{ 3126 unsigned long operand2; 3127 unsigned long operand3; 3128 3129 check_assign (inst, inst_env); 3130 if (cris_get_operand2 (inst) == REG_PC) 3131 { 3132 operand2 = inst_env->reg[REG_PC]; 3133 3134 /* Get the value of the third operand. */ 3135 operand3 = get_data_from_address (&inst, inst_env->prefix_value); 3136 3137 /* Calculate the PC value after the instruction, i.e. where the 3138 breakpoint should be. The order of the udw_operands is vital. */ 3139 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); 3140 } 3141 inst_env->slot_needed = 0; 3142 inst_env->prefix_found = 0; 3143 inst_env->xflag_found = 0; 3144 inst_env->disable_interrupt = 0; 3145} 3146 3147/* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and 3148 OR instructions. Note that for this to work as expected, the calling 3149 function must have made sure that there is a prefix to this instruction. */ 3150 3151static void 3152three_operand_add_sub_cmp_and_or_op (unsigned short inst, 3153 inst_env_type *inst_env) 3154{ 3155 unsigned long operand2; 3156 unsigned long operand3; 3157 3158 if (cris_get_operand1 (inst) == REG_PC) 3159 { 3160 /* The PC will be changed by the instruction. */ 3161 operand2 = inst_env->reg[cris_get_operand2 (inst)]; 3162 3163 /* Get the value of the third operand. */ 3164 operand3 = get_data_from_address (&inst, inst_env->prefix_value); 3165 3166 /* Calculate the PC value after the instruction, i.e. where the 3167 breakpoint should be. */ 3168 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); 3169 } 3170 inst_env->slot_needed = 0; 3171 inst_env->prefix_found = 0; 3172 inst_env->xflag_found = 0; 3173 inst_env->disable_interrupt = 0; 3174} 3175 3176/* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE 3177 instructions. The MOVE instruction is the move from source to register. */ 3178 3179static void 3180handle_prefix_index_mode_for_aritm_op (unsigned short inst, 3181 inst_env_type *inst_env) 3182{ 3183 if (cris_get_operand1 (inst) != cris_get_operand2 (inst)) 3184 { 3185 /* If the instruction is MOVE it's invalid. If the instruction is ADD, 3186 SUB, AND or OR something weird is going on (if everything works these 3187 instructions should end up in the three operand version). */ 3188 inst_env->invalid = 1; 3189 return; 3190 } 3191 else 3192 { 3193 /* three_operand_add_sub_cmp_and_or does the same as we should do here 3194 so use it. */ 3195 three_operand_add_sub_cmp_and_or_op (inst, inst_env); 3196 } 3197 inst_env->slot_needed = 0; 3198 inst_env->prefix_found = 0; 3199 inst_env->xflag_found = 0; 3200 inst_env->disable_interrupt = 0; 3201} 3202 3203/* Handles the autoincrement and indirect addresing mode for the ADD, SUB, 3204 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from 3205 source to register. */ 3206 3207static void 3208handle_inc_and_index_mode_for_aritm_op (unsigned short inst, 3209 inst_env_type *inst_env) 3210{ 3211 unsigned long operand1; 3212 unsigned long operand2; 3213 unsigned long operand3; 3214 int size; 3215 3216 /* The instruction is either an indirect or autoincrement addressing mode. 3217 Check if the destination register is the PC. */ 3218 if (cris_get_operand2 (inst) == REG_PC) 3219 { 3220 /* Must be done here, get_data_from_address may change the size 3221 field. */ 3222 size = cris_get_size (inst); 3223 operand2 = inst_env->reg[REG_PC]; 3224 3225 /* Get the value of the third operand, i.e. the indirect operand. */ 3226 operand1 = inst_env->reg[cris_get_operand1 (inst)]; 3227 operand3 = get_data_from_address (&inst, operand1); 3228 3229 /* Calculate the PC value after the instruction, i.e. where the 3230 breakpoint should be. The order of the udw_operands is vital. */ 3231 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); 3232 } 3233 /* If this is an autoincrement addressing mode, check if the increment 3234 changes the PC. */ 3235 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) 3236 { 3237 /* Get the size field. */ 3238 size = cris_get_size (inst); 3239 3240 /* If it's an extend instruction we don't want the signed extend bit, 3241 because it influences the size. */ 3242 if (cris_get_opcode (inst) < 4) 3243 { 3244 size &= ~SIGNED_EXTEND_BIT_MASK; 3245 } 3246 process_autoincrement (size, inst, inst_env); 3247 } 3248 inst_env->slot_needed = 0; 3249 inst_env->prefix_found = 0; 3250 inst_env->xflag_found = 0; 3251 inst_env->disable_interrupt = 0; 3252} 3253 3254/* Handles the two-operand addressing mode, all modes except register, for 3255 the ADD, SUB CMP, AND and OR instruction. */ 3256 3257static void 3258none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, 3259 inst_env_type *inst_env) 3260{ 3261 if (inst_env->prefix_found) 3262 { 3263 if (cris_get_mode (inst) == PREFIX_INDEX_MODE) 3264 { 3265 handle_prefix_index_mode_for_aritm_op (inst, inst_env); 3266 } 3267 else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) 3268 { 3269 handle_prefix_assign_mode_for_aritm_op (inst, inst_env); 3270 } 3271 else 3272 { 3273 /* The mode is invalid for a prefixed base instruction. */ 3274 inst_env->invalid = 1; 3275 return; 3276 } 3277 } 3278 else 3279 { 3280 handle_inc_and_index_mode_for_aritm_op (inst, inst_env); 3281 } 3282} 3283 3284/* Handles the quick addressing mode for the ADD and SUB instruction. */ 3285 3286static void 3287quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env) 3288{ 3289 unsigned long operand1; 3290 unsigned long operand2; 3291 3292 /* It's a bad idea to be in a prefix instruction now. This is a quick mode 3293 instruction and can't have a prefix. */ 3294 if (inst_env->prefix_found) 3295 { 3296 inst_env->invalid = 1; 3297 return; 3298 } 3299 3300 /* Check if the instruction has PC as its target. */ 3301 if (cris_get_operand2 (inst) == REG_PC) 3302 { 3303 if (inst_env->slot_needed) 3304 { 3305 inst_env->invalid = 1; 3306 return; 3307 } 3308 operand1 = cris_get_quick_value (inst); 3309 operand2 = inst_env->reg[REG_PC]; 3310 3311 /* The size should now be dword. */ 3312 cris_set_size_to_dword (&inst); 3313 3314 /* Calculate the PC value after the instruction, i.e. where the 3315 breakpoint should be. */ 3316 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); 3317 } 3318 inst_env->slot_needed = 0; 3319 inst_env->prefix_found = 0; 3320 inst_env->xflag_found = 0; 3321 inst_env->disable_interrupt = 0; 3322} 3323 3324/* Handles the quick addressing mode for the CMP, AND and OR instruction. */ 3325 3326static void 3327quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env) 3328{ 3329 unsigned long operand1; 3330 unsigned long operand2; 3331 3332 /* It's a bad idea to be in a prefix instruction now. This is a quick mode 3333 instruction and can't have a prefix. */ 3334 if (inst_env->prefix_found) 3335 { 3336 inst_env->invalid = 1; 3337 return; 3338 } 3339 /* Check if the instruction has PC as its target. */ 3340 if (cris_get_operand2 (inst) == REG_PC) 3341 { 3342 if (inst_env->slot_needed) 3343 { 3344 inst_env->invalid = 1; 3345 return; 3346 } 3347 /* The instruction has the PC as its target register. */ 3348 operand1 = cris_get_quick_value (inst); 3349 operand2 = inst_env->reg[REG_PC]; 3350 3351 /* The quick value is signed, so check if we must do a signed extend. */ 3352 if (operand1 & SIGNED_QUICK_VALUE_MASK) 3353 { 3354 /* sign extend */ 3355 operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK; 3356 } 3357 /* The size should now be dword. */ 3358 cris_set_size_to_dword (&inst); 3359 3360 /* Calculate the PC value after the instruction, i.e. where the 3361 breakpoint should be. */ 3362 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); 3363 } 3364 inst_env->slot_needed = 0; 3365 inst_env->prefix_found = 0; 3366 inst_env->xflag_found = 0; 3367 inst_env->disable_interrupt = 0; 3368} 3369 3370/* Translate op_type to a function and call it. */ 3371 3372static void 3373cris_gdb_func (enum cris_op_type op_type, unsigned short inst, 3374 inst_env_type *inst_env) 3375{ 3376 switch (op_type) 3377 { 3378 case cris_not_implemented_op: 3379 not_implemented_op (inst, inst_env); 3380 break; 3381 3382 case cris_abs_op: 3383 abs_op (inst, inst_env); 3384 break; 3385 3386 case cris_addi_op: 3387 addi_op (inst, inst_env); 3388 break; 3389 3390 case cris_asr_op: 3391 asr_op (inst, inst_env); 3392 break; 3393 3394 case cris_asrq_op: 3395 asrq_op (inst, inst_env); 3396 break; 3397 3398 case cris_ax_ei_setf_op: 3399 ax_ei_setf_op (inst, inst_env); 3400 break; 3401 3402 case cris_bdap_prefix: 3403 bdap_prefix (inst, inst_env); 3404 break; 3405 3406 case cris_biap_prefix: 3407 biap_prefix (inst, inst_env); 3408 break; 3409 3410 case cris_break_op: 3411 break_op (inst, inst_env); 3412 break; 3413 3414 case cris_btst_nop_op: 3415 btst_nop_op (inst, inst_env); 3416 break; 3417 3418 case cris_clearf_di_op: 3419 clearf_di_op (inst, inst_env); 3420 break; 3421 3422 case cris_dip_prefix: 3423 dip_prefix (inst, inst_env); 3424 break; 3425 3426 case cris_dstep_logshift_mstep_neg_not_op: 3427 dstep_logshift_mstep_neg_not_op (inst, inst_env); 3428 break; 3429 3430 case cris_eight_bit_offset_branch_op: 3431 eight_bit_offset_branch_op (inst, inst_env); 3432 break; 3433 3434 case cris_move_mem_to_reg_movem_op: 3435 move_mem_to_reg_movem_op (inst, inst_env); 3436 break; 3437 3438 case cris_move_reg_to_mem_movem_op: 3439 move_reg_to_mem_movem_op (inst, inst_env); 3440 break; 3441 3442 case cris_move_to_preg_op: 3443 move_to_preg_op (inst, inst_env); 3444 break; 3445 3446 case cris_muls_op: 3447 muls_op (inst, inst_env); 3448 break; 3449 3450 case cris_mulu_op: 3451 mulu_op (inst, inst_env); 3452 break; 3453 3454 case cris_none_reg_mode_add_sub_cmp_and_or_move_op: 3455 none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); 3456 break; 3457 3458 case cris_none_reg_mode_clear_test_op: 3459 none_reg_mode_clear_test_op (inst, inst_env); 3460 break; 3461 3462 case cris_none_reg_mode_jump_op: 3463 none_reg_mode_jump_op (inst, inst_env); 3464 break; 3465 3466 case cris_none_reg_mode_move_from_preg_op: 3467 none_reg_mode_move_from_preg_op (inst, inst_env); 3468 break; 3469 3470 case cris_quick_mode_add_sub_op: 3471 quick_mode_add_sub_op (inst, inst_env); 3472 break; 3473 3474 case cris_quick_mode_and_cmp_move_or_op: 3475 quick_mode_and_cmp_move_or_op (inst, inst_env); 3476 break; 3477 3478 case cris_quick_mode_bdap_prefix: 3479 quick_mode_bdap_prefix (inst, inst_env); 3480 break; 3481 3482 case cris_reg_mode_add_sub_cmp_and_or_move_op: 3483 reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); 3484 break; 3485 3486 case cris_reg_mode_clear_op: 3487 reg_mode_clear_op (inst, inst_env); 3488 break; 3489 3490 case cris_reg_mode_jump_op: 3491 reg_mode_jump_op (inst, inst_env); 3492 break; 3493 3494 case cris_reg_mode_move_from_preg_op: 3495 reg_mode_move_from_preg_op (inst, inst_env); 3496 break; 3497 3498 case cris_reg_mode_test_op: 3499 reg_mode_test_op (inst, inst_env); 3500 break; 3501 3502 case cris_scc_op: 3503 scc_op (inst, inst_env); 3504 break; 3505 3506 case cris_sixteen_bit_offset_branch_op: 3507 sixteen_bit_offset_branch_op (inst, inst_env); 3508 break; 3509 3510 case cris_three_operand_add_sub_cmp_and_or_op: 3511 three_operand_add_sub_cmp_and_or_op (inst, inst_env); 3512 break; 3513 3514 case cris_three_operand_bound_op: 3515 three_operand_bound_op (inst, inst_env); 3516 break; 3517 3518 case cris_two_operand_bound_op: 3519 two_operand_bound_op (inst, inst_env); 3520 break; 3521 3522 case cris_xor_op: 3523 xor_op (inst, inst_env); 3524 break; 3525 } 3526} 3527 3528/* This wrapper is to avoid cris_get_assembler being called before 3529 exec_bfd has been set. */ 3530 3531static int 3532cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info) 3533{ 3534 int (*print_insn) (bfd_vma addr, struct disassemble_info *info); 3535 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS 3536 disassembler, even when there is no BFD. Does something like 3537 "gdb; target remote; disassmeble *0x123" work? */ 3538 gdb_assert (exec_bfd != NULL); 3539 print_insn = cris_get_disassembler (exec_bfd); 3540 gdb_assert (print_insn != NULL); 3541 return print_insn (addr, info); 3542} 3543 3544/* Copied from <asm/elf.h>. */ 3545typedef unsigned long elf_greg_t; 3546 3547/* Same as user_regs_struct struct in <asm/user.h>. */ 3548typedef elf_greg_t elf_gregset_t[35]; 3549 3550/* Unpack an elf_gregset_t into GDB's register cache. */ 3551 3552static void 3553supply_gregset (elf_gregset_t *gregsetp) 3554{ 3555 int i; 3556 elf_greg_t *regp = *gregsetp; 3557 static char zerobuf[4] = {0}; 3558 3559 /* The kernel dumps all 32 registers as unsigned longs, but supply_register 3560 knows about the actual size of each register so that's no problem. */ 3561 for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++) 3562 { 3563 regcache_raw_supply (current_regcache, i, (char *)®p[i]); 3564 } 3565} 3566 3567/* Use a local version of this function to get the correct types for 3568 regsets, until multi-arch core support is ready. */ 3569 3570static void 3571fetch_core_registers (char *core_reg_sect, unsigned core_reg_size, 3572 int which, CORE_ADDR reg_addr) 3573{ 3574 elf_gregset_t gregset; 3575 3576 switch (which) 3577 { 3578 case 0: 3579 if (core_reg_size != sizeof (gregset)) 3580 { 3581 warning ("wrong size gregset struct in core file"); 3582 } 3583 else 3584 { 3585 memcpy (&gregset, core_reg_sect, sizeof (gregset)); 3586 supply_gregset (&gregset); 3587 } 3588 3589 default: 3590 /* We've covered all the kinds of registers we know about here, 3591 so this must be something we wouldn't know what to do with 3592 anyway. Just ignore it. */ 3593 break; 3594 } 3595} 3596 3597static struct core_fns cris_elf_core_fns = 3598{ 3599 bfd_target_elf_flavour, /* core_flavour */ 3600 default_check_format, /* check_format */ 3601 default_core_sniffer, /* core_sniffer */ 3602 fetch_core_registers, /* core_read_registers */ 3603 NULL /* next */ 3604}; 3605 3606/* Fetch (and possibly build) an appropriate link_map_offsets 3607 structure for native GNU/Linux CRIS targets using the struct 3608 offsets defined in link.h (but without actual reference to that 3609 file). 3610 3611 This makes it possible to access GNU/Linux CRIS shared libraries 3612 from a GDB that was not built on an GNU/Linux CRIS host (for cross 3613 debugging). 3614 3615 See gdb/solib-svr4.h for an explanation of these fields. */ 3616 3617static struct link_map_offsets * 3618cris_linux_svr4_fetch_link_map_offsets (void) 3619{ 3620 static struct link_map_offsets lmo; 3621 static struct link_map_offsets *lmp = NULL; 3622 3623 if (lmp == NULL) 3624 { 3625 lmp = &lmo; 3626 3627 lmo.r_debug_size = 8; /* The actual size is 20 bytes, but 3628 this is all we need. */ 3629 lmo.r_map_offset = 4; 3630 lmo.r_map_size = 4; 3631 3632 lmo.link_map_size = 20; 3633 3634 lmo.l_addr_offset = 0; 3635 lmo.l_addr_size = 4; 3636 3637 lmo.l_name_offset = 4; 3638 lmo.l_name_size = 4; 3639 3640 lmo.l_next_offset = 12; 3641 lmo.l_next_size = 4; 3642 3643 lmo.l_prev_offset = 16; 3644 lmo.l_prev_size = 4; 3645 } 3646 3647 return lmp; 3648} 3649 3650extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */ 3651 3652void 3653_initialize_cris_tdep (void) 3654{ 3655 static struct cmd_list_element *cris_set_cmdlist; 3656 static struct cmd_list_element *cris_show_cmdlist; 3657 3658 struct cmd_list_element *c; 3659 3660 gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep); 3661 3662 /* CRIS-specific user-commands. */ 3663 add_setshow_uinteger_cmd ("cris-version", class_support, 3664 &usr_cmd_cris_version, 3665 "Set the current CRIS version.", 3666 "Show the current CRIS version.", 3667 "Set if autodetection fails.", 3668 "Current CRIS version is %s.", 3669 set_cris_version, NULL, 3670 &setlist, &showlist); 3671 3672 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support, 3673 &usr_cmd_cris_dwarf2_cfi, 3674 "Set the usage of Dwarf-2 CFI for CRIS.", 3675 "Show the usage of Dwarf-2 CFI for CRIS.", 3676 "Set to \"off\" if using gcc-cris < R59.", 3677 "Usage of Dwarf-2 CFI for CRIS is %d.", 3678 set_cris_dwarf2_cfi, NULL, 3679 &setlist, &showlist); 3680 3681 deprecated_add_core_fns (&cris_elf_core_fns); 3682} 3683 3684/* Prints out all target specific values. */ 3685 3686static void 3687cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) 3688{ 3689 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 3690 if (tdep != NULL) 3691 { 3692 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n", 3693 tdep->cris_version); 3694 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n", 3695 tdep->cris_dwarf2_cfi); 3696 } 3697} 3698 3699static void 3700set_cris_version (char *ignore_args, int from_tty, 3701 struct cmd_list_element *c) 3702{ 3703 struct gdbarch_info info; 3704 3705 usr_cmd_cris_version_valid = 1; 3706 3707 /* Update the current architecture, if needed. */ 3708 gdbarch_info_init (&info); 3709 if (!gdbarch_update_p (info)) 3710 internal_error (__FILE__, __LINE__, 3711 "cris_gdbarch_update: failed to update architecture."); 3712} 3713 3714static void 3715set_cris_dwarf2_cfi (char *ignore_args, int from_tty, 3716 struct cmd_list_element *c) 3717{ 3718 struct gdbarch_info info; 3719 3720 /* Update the current architecture, if needed. */ 3721 gdbarch_info_init (&info); 3722 if (!gdbarch_update_p (info)) 3723 internal_error (__FILE__, __LINE__, 3724 "cris_gdbarch_update: failed to update architecture."); 3725} 3726 3727static struct gdbarch * 3728cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 3729{ 3730 struct gdbarch *gdbarch; 3731 struct gdbarch_tdep *tdep; 3732 int cris_version; 3733 3734 if (usr_cmd_cris_version_valid) 3735 { 3736 /* Trust the user's CRIS version setting. */ 3737 cris_version = usr_cmd_cris_version; 3738 } 3739 else 3740 { 3741 /* Assume it's CRIS version 10. */ 3742 cris_version = 10; 3743 } 3744 3745 /* Make the current settings visible to the user. */ 3746 usr_cmd_cris_version = cris_version; 3747 3748 /* Find a candidate among the list of pre-declared architectures. Both 3749 CRIS version and ABI must match. */ 3750 for (arches = gdbarch_list_lookup_by_info (arches, &info); 3751 arches != NULL; 3752 arches = gdbarch_list_lookup_by_info (arches->next, &info)) 3753 { 3754 if ((gdbarch_tdep (arches->gdbarch)->cris_version 3755 == usr_cmd_cris_version) 3756 && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi 3757 == usr_cmd_cris_dwarf2_cfi)) 3758 return arches->gdbarch; 3759 } 3760 3761 /* No matching architecture was found. Create a new one. */ 3762 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); 3763 gdbarch = gdbarch_alloc (&info, tdep); 3764 3765 tdep->cris_version = usr_cmd_cris_version; 3766 tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi; 3767 3768 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */ 3769 switch (info.byte_order) 3770 { 3771 case BFD_ENDIAN_LITTLE: 3772 /* Ok. */ 3773 break; 3774 3775 case BFD_ENDIAN_BIG: 3776 internal_error (__FILE__, __LINE__, "cris_gdbarch_init: big endian byte order in info"); 3777 break; 3778 3779 default: 3780 internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unknown byte order in info"); 3781 } 3782 3783 set_gdbarch_return_value (gdbarch, cris_return_value); 3784 set_gdbarch_deprecated_reg_struct_has_addr (gdbarch, 3785 cris_reg_struct_has_addr); 3786 set_gdbarch_deprecated_use_struct_convention (gdbarch, always_use_struct_convention); 3787 3788 /* There are 32 registers (some of which may not be implemented). */ 3789 set_gdbarch_num_regs (gdbarch, 32); 3790 set_gdbarch_sp_regnum (gdbarch, 14); 3791 set_gdbarch_pc_regnum (gdbarch, 15); 3792 set_gdbarch_register_name (gdbarch, cris_register_name); 3793 3794 set_gdbarch_double_bit (gdbarch, 64); 3795 /* The default definition of a long double is 2 * TARGET_DOUBLE_BIT, 3796 which means we have to set this explicitly. */ 3797 set_gdbarch_long_double_bit (gdbarch, 64); 3798 set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register); 3799 set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register); 3800 3801 /* The total amount of space needed to store (in an array called registers) 3802 GDB's copy of the machine's register state. Note: We can not use 3803 cris_register_size at this point, since it relies on current_gdbarch 3804 being set. */ 3805 switch (tdep->cris_version) 3806 { 3807 case 0: 3808 case 1: 3809 case 2: 3810 case 3: 3811 case 8: 3812 case 9: 3813 /* Old versions; not supported. */ 3814 internal_error (__FILE__, __LINE__, 3815 "cris_gdbarch_init: unsupported CRIS version"); 3816 break; 3817 3818 case 10: 3819 case 11: 3820 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100, 3821 P7 (32 bits), and P15 (32 bits) have been implemented. */ 3822 break; 3823 3824 default: 3825 internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unknown CRIS version"); 3826 } 3827 3828 set_gdbarch_register_type (gdbarch, cris_register_type); 3829 3830 /* Dummy frame functions. */ 3831 set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code); 3832 set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call); 3833 set_gdbarch_frame_align (gdbarch, cris_frame_align); 3834 3835 set_gdbarch_software_single_step (gdbarch, cris_software_single_step); 3836 set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue); 3837 3838 /* The stack grows downward. */ 3839 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 3840 3841 set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc); 3842 3843 set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc); 3844 set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp); 3845 set_gdbarch_unwind_dummy_id (gdbarch, cris_unwind_dummy_id); 3846 3847 if (tdep->cris_dwarf2_cfi == 1) 3848 { 3849 /* Hook in the Dwarf-2 frame sniffer. */ 3850 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum); 3851 dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg); 3852 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); 3853 } 3854 3855 frame_unwind_append_sniffer (gdbarch, cris_sigtramp_frame_sniffer); 3856 3857 frame_unwind_append_sniffer (gdbarch, cris_frame_sniffer); 3858 frame_base_set_default (gdbarch, &cris_frame_base); 3859 3860 /* Use target_specific function to define link map offsets. */ 3861 set_solib_svr4_fetch_link_map_offsets 3862 (gdbarch, cris_linux_svr4_fetch_link_map_offsets); 3863 3864 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS 3865 disassembler, even when there is no BFD. Does something like 3866 "gdb; target remote; disassmeble *0x123" work? */ 3867 set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler); 3868 3869 return gdbarch; 3870} 3871