126219Swpaul/* $FreeBSD$ */ 226219Swpaul 326219Swpaul/*- 426219Swpaul * Copyright (c) 2006 526219Swpaul * Damien Bergamini <damien.bergamini@free.fr> 626219Swpaul * 726219Swpaul * Permission to use, copy, modify, and distribute this software for any 826219Swpaul * purpose with or without fee is hereby granted, provided that the above 926219Swpaul * copyright notice and this permission notice appear in all copies. 1026219Swpaul * 1126219Swpaul * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 1226219Swpaul * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 1326219Swpaul * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 1426219Swpaul * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 1526219Swpaul * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 1626219Swpaul * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 1726219Swpaul * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 1826219Swpaul */ 1926219Swpaul 2026219Swpaul#define RT2661_NOISE_FLOOR -95 2126219Swpaul 2226219Swpaul#define RT2661_TX_RING_COUNT 32 2326219Swpaul#define RT2661_MGT_RING_COUNT 32 2426219Swpaul#define RT2661_RX_RING_COUNT 64 2526219Swpaul 2626219Swpaul#define RT2661_TX_DESC_SIZE (sizeof (struct rt2661_tx_desc)) 2726219Swpaul#define RT2661_TX_DESC_WSIZE (RT2661_TX_DESC_SIZE / 4) 2826219Swpaul#define RT2661_RX_DESC_SIZE (sizeof (struct rt2661_rx_desc)) 2926219Swpaul#define RT2661_RX_DESC_WSIZE (RT2661_RX_DESC_SIZE / 4) 30136581Sobrien 31136581Sobrien#define RT2661_MAX_SCATTER 5 3226219Swpaul 3326219Swpaul/* 3492990Sobrien * Control and status registers. 3592990Sobrien */ 36136581Sobrien#define RT2661_HOST_CMD_CSR 0x0008 3726219Swpaul#define RT2661_MCU_CNTL_CSR 0x000c 3826219Swpaul#define RT2661_SOFT_RESET_CSR 0x0010 3926219Swpaul#define RT2661_MCU_INT_SOURCE_CSR 0x0014 4026219Swpaul#define RT2661_MCU_INT_MASK_CSR 0x0018 4126219Swpaul#define RT2661_PCI_USEC_CSR 0x001c 4226219Swpaul#define RT2661_H2M_MAILBOX_CSR 0x2100 4374462Salfred#define RT2661_M2H_CMD_DONE_CSR 0x2104 4426219Swpaul#define RT2661_HW_BEACON_BASE0 0x2c00 4526219Swpaul#define RT2661_MAC_CSR0 0x3000 4626219Swpaul#define RT2661_MAC_CSR1 0x3004 4726219Swpaul#define RT2661_MAC_CSR2 0x3008 4826219Swpaul#define RT2661_MAC_CSR3 0x300c 4926219Swpaul#define RT2661_MAC_CSR4 0x3010 5026219Swpaul#define RT2661_MAC_CSR5 0x3014 5126219Swpaul#define RT2661_MAC_CSR6 0x3018 5226219Swpaul#define RT2661_MAC_CSR7 0x301c 5326219Swpaul#define RT2661_MAC_CSR8 0x3020 5426219Swpaul#define RT2661_MAC_CSR9 0x3024 5526219Swpaul#define RT2661_MAC_CSR10 0x3028 5626219Swpaul#define RT2661_MAC_CSR11 0x302c 5726219Swpaul#define RT2661_MAC_CSR12 0x3030 5874462Salfred#define RT2661_MAC_CSR13 0x3034 5926219Swpaul#define RT2661_MAC_CSR14 0x3038 6026219Swpaul#define RT2661_MAC_CSR15 0x303c 61137675Sbz#define RT2661_TXRX_CSR0 0x3040 6226219Swpaul#define RT2661_TXRX_CSR1 0x3044 63137675Sbz#define RT2661_TXRX_CSR2 0x3048 6426219Swpaul#define RT2661_TXRX_CSR3 0x304c 6526219Swpaul#define RT2661_TXRX_CSR4 0x3050 6692905Sobrien#define RT2661_TXRX_CSR5 0x3054 6792905Sobrien#define RT2661_TXRX_CSR6 0x3058 6826219Swpaul#define RT2661_TXRX_CSR7 0x305c 6926219Swpaul#define RT2661_TXRX_CSR8 0x3060 7026219Swpaul#define RT2661_TXRX_CSR9 0x3064 7126219Swpaul#define RT2661_TXRX_CSR10 0x3068 7226219Swpaul#define RT2661_TXRX_CSR11 0x306c 7326219Swpaul#define RT2661_TXRX_CSR12 0x3070 7426219Swpaul#define RT2661_TXRX_CSR13 0x3074 7526219Swpaul#define RT2661_TXRX_CSR14 0x3078 7626219Swpaul#define RT2661_TXRX_CSR15 0x307c 7726219Swpaul#define RT2661_PHY_CSR0 0x3080 7826219Swpaul#define RT2661_PHY_CSR1 0x3084 7926219Swpaul#define RT2661_PHY_CSR2 0x3088 8026219Swpaul#define RT2661_PHY_CSR3 0x308c 8126219Swpaul#define RT2661_PHY_CSR4 0x3090 8226219Swpaul#define RT2661_PHY_CSR5 0x3094 8337300Sbde#define RT2661_PHY_CSR6 0x3098 8426219Swpaul#define RT2661_PHY_CSR7 0x309c 8526219Swpaul#define RT2661_SEC_CSR0 0x30a0 8626219Swpaul#define RT2661_SEC_CSR1 0x30a4 8726219Swpaul#define RT2661_SEC_CSR2 0x30a8 8826219Swpaul#define RT2661_SEC_CSR3 0x30ac 8926219Swpaul#define RT2661_SEC_CSR4 0x30b0 9026219Swpaul#define RT2661_SEC_CSR5 0x30b4 9126219Swpaul#define RT2661_STA_CSR0 0x30c0 9265220Sache#define RT2661_STA_CSR1 0x30c4 9365220Sache#define RT2661_STA_CSR2 0x30c8 9465220Sache#define RT2661_STA_CSR3 0x30cc 9526219Swpaul#define RT2661_STA_CSR4 0x30d0 9626219Swpaul#define RT2661_AC0_BASE_CSR 0x3400 9765220Sache#define RT2661_AC1_BASE_CSR 0x3404 9865220Sache#define RT2661_AC2_BASE_CSR 0x3408 9926219Swpaul#define RT2661_AC3_BASE_CSR 0x340c 10026219Swpaul#define RT2661_MGT_BASE_CSR 0x3410 10126219Swpaul#define RT2661_TX_RING_CSR0 0x3418 10265220Sache#define RT2661_TX_RING_CSR1 0x341c 103194498Sbrooks#define RT2661_AIFSN_CSR 0x3420 10465220Sache#define RT2661_CWMIN_CSR 0x3424 10526219Swpaul#define RT2661_CWMAX_CSR 0x3428 10626219Swpaul#define RT2661_TX_DMA_DST_CSR 0x342c 10726219Swpaul#define RT2661_TX_CNTL_CSR 0x3430 10826219Swpaul#define RT2661_LOAD_TX_RING_CSR 0x3434 10926219Swpaul#define RT2661_RX_BASE_CSR 0x3450 11026219Swpaul#define RT2661_RX_RING_CSR 0x3454 11126219Swpaul#define RT2661_RX_CNTL_CSR 0x3458 11226219Swpaul#define RT2661_PCI_CFG_CSR 0x3460 11326219Swpaul#define RT2661_INT_SOURCE_CSR 0x3468 11426219Swpaul#define RT2661_INT_MASK_CSR 0x346c 11526219Swpaul#define RT2661_E2PROM_CSR 0x3470 11626219Swpaul#define RT2661_AC_TXOP_CSR0 0x3474 11726219Swpaul#define RT2661_AC_TXOP_CSR1 0x3478 11826219Swpaul#define RT2661_TEST_MODE_CSR 0x3484 11926219Swpaul#define RT2661_IO_CNTL_CSR 0x3498 12026219Swpaul#define RT2661_MCU_CODE_BASE 0x4000 12126219Swpaul 12226219Swpaul 12326219Swpaul/* possible flags for register HOST_CMD_CSR */ 12426219Swpaul#define RT2661_KICK_CMD (1 << 7) 12526219Swpaul/* Host to MCU (8051) command identifiers */ 12626219Swpaul#define RT2661_MCU_CMD_SLEEP 0x30 12726219Swpaul#define RT2661_MCU_CMD_WAKEUP 0x31 12890271Salfred#define RT2661_MCU_SET_LED 0x50 12926219Swpaul#define RT2661_MCU_SET_RSSI_LED 0x52 13026219Swpaul 13126219Swpaul/* possible flags for register MCU_CNTL_CSR */ 13226219Swpaul#define RT2661_MCU_SEL (1 << 0) 13326219Swpaul#define RT2661_MCU_RESET (1 << 1) 13426219Swpaul#define RT2661_MCU_READY (1 << 2) 13537300Sbde 13626219Swpaul/* possible flags for register MCU_INT_SOURCE_CSR */ 13737300Sbde#define RT2661_MCU_CMD_DONE 0xff 13837300Sbde#define RT2661_MCU_WAKEUP (1 << 8) 13926219Swpaul#define RT2661_MCU_BEACON_EXPIRE (1 << 9) 14026219Swpaul 14126219Swpaul/* possible flags for register H2M_MAILBOX_CSR */ 14226219Swpaul#define RT2661_H2M_BUSY (1 << 24) 14326219Swpaul#define RT2661_TOKEN_NO_INTR 0xff 14426219Swpaul 14526219Swpaul/* possible flags for register MAC_CSR5 */ 14626219Swpaul#define RT2661_ONE_BSSID 3 14726219Swpaul 14826219Swpaul/* possible flags for register TXRX_CSR0 */ 14926219Swpaul/* Tx filter flags are in the low 16 bits */ 15026219Swpaul#define RT2661_AUTO_TX_SEQ (1 << 15) 15126219Swpaul/* Rx filter flags are in the high 16 bits */ 15226219Swpaul#define RT2661_DISABLE_RX (1 << 16) 15326219Swpaul#define RT2661_DROP_CRC_ERROR (1 << 17) 15426219Swpaul#define RT2661_DROP_PHY_ERROR (1 << 18) 15526219Swpaul#define RT2661_DROP_CTL (1 << 19) 156194498Sbrooks#define RT2661_DROP_NOT_TO_ME (1 << 20) 15726219Swpaul#define RT2661_DROP_TODS (1 << 21) 15826219Swpaul#define RT2661_DROP_VER_ERROR (1 << 22) 15992889Sobrien#define RT2661_DROP_MULTICAST (1 << 23) 16092889Sobrien#define RT2661_DROP_BROADCAST (1 << 24) 16192889Sobrien#define RT2661_DROP_ACKCTS (1 << 25) 16226219Swpaul 16326219Swpaul/* possible flags for register TXRX_CSR4 */ 16426219Swpaul#define RT2661_SHORT_PREAMBLE (1 << 19) 16526219Swpaul#define RT2661_MRR_ENABLED (1 << 20) 16626219Swpaul#define RT2661_MRR_CCK_FALLBACK (1 << 23) 16726219Swpaul 168194498Sbrooks/* possible flags for register TXRX_CSR9 */ 16926219Swpaul#define RT2661_TSF_TICKING (1 << 16) 17026219Swpaul#define RT2661_TSF_MODE(x) (((x) & 0x3) << 17) 17126219Swpaul/* TBTT stands for Target Beacon Transmission Time */ 17226219Swpaul#define RT2661_ENABLE_TBTT (1 << 19) 17326219Swpaul#define RT2661_GENERATE_BEACON (1 << 20) 17426219Swpaul 17526219Swpaul/* possible flags for register PHY_CSR0 */ 17626219Swpaul#define RT2661_PA_PE_2GHZ (1 << 16) 17726219Swpaul#define RT2661_PA_PE_5GHZ (1 << 17) 17826219Swpaul 17926219Swpaul/* possible flags for register PHY_CSR3 */ 18026219Swpaul#define RT2661_BBP_READ (1 << 15) 18126219Swpaul#define RT2661_BBP_BUSY (1 << 16) 18226219Swpaul 18326219Swpaul/* possible flags for register PHY_CSR4 */ 18426219Swpaul#define RT2661_RF_21BIT (21 << 24) 18526219Swpaul#define RT2661_RF_BUSY (1 << 31) 18626219Swpaul 18726219Swpaul/* possible values for register STA_CSR4 */ 18826219Swpaul#define RT2661_TX_STAT_VALID (1 << 0) 18926219Swpaul#define RT2661_TX_RESULT(v) (((v) >> 1) & 0x7) 19026219Swpaul#define RT2661_TX_RETRYCNT(v) (((v) >> 4) & 0xf) 19126219Swpaul#define RT2661_TX_QID(v) (((v) >> 8) & 0xf) 19226219Swpaul#define RT2661_TX_SUCCESS 0 19326219Swpaul#define RT2661_TX_RETRY_FAIL 6 19426219Swpaul 19526219Swpaul/* possible flags for register TX_CNTL_CSR */ 19626219Swpaul#define RT2661_KICK_MGT (1 << 4) 19726219Swpaul 19826219Swpaul/* possible flags for register INT_SOURCE_CSR */ 19926219Swpaul#define RT2661_TX_DONE (1 << 0) 20026219Swpaul#define RT2661_RX_DONE (1 << 1) 20126219Swpaul#define RT2661_TX0_DMA_DONE (1 << 16) 20226219Swpaul#define RT2661_TX1_DMA_DONE (1 << 17) 20326219Swpaul#define RT2661_TX2_DMA_DONE (1 << 18) 20426219Swpaul#define RT2661_TX3_DMA_DONE (1 << 19) 20526219Swpaul#define RT2661_MGT_DONE (1 << 20) 20626219Swpaul 20726219Swpaul/* possible flags for register E2PROM_CSR */ 20826219Swpaul#define RT2661_C (1 << 1) 20926219Swpaul#define RT2661_S (1 << 2) 21026219Swpaul#define RT2661_D (1 << 3) 21126219Swpaul#define RT2661_Q (1 << 4) 21226219Swpaul#define RT2661_93C46 (1 << 5) 21326219Swpaul 21426219Swpaul/* Tx descriptor */ 21526219Swpaulstruct rt2661_tx_desc { 21626219Swpaul uint32_t flags; 21726219Swpaul#define RT2661_TX_BUSY (1 << 0) 21826219Swpaul#define RT2661_TX_VALID (1 << 1) 21926219Swpaul#define RT2661_TX_MORE_FRAG (1 << 2) 22026219Swpaul#define RT2661_TX_NEED_ACK (1 << 3) 22126219Swpaul#define RT2661_TX_TIMESTAMP (1 << 4) 22226219Swpaul#define RT2661_TX_OFDM (1 << 5) 22326219Swpaul#define RT2661_TX_IFS (1 << 6) 22426219Swpaul#define RT2661_TX_LONG_RETRY (1 << 7) 22526219Swpaul#define RT2661_TX_BURST (1 << 28) 22626219Swpaul 22726219Swpaul uint16_t wme; 22826219Swpaul#define RT2661_QID(v) (v) 22990271Salfred#define RT2661_AIFSN(v) ((v) << 4) 23026219Swpaul#define RT2661_LOGCWMIN(v) ((v) << 8) 23126219Swpaul#define RT2661_LOGCWMAX(v) ((v) << 12) 23226219Swpaul 23326219Swpaul uint16_t xflags; 23426219Swpaul#define RT2661_TX_HWSEQ (1 << 12) 23526219Swpaul 23626219Swpaul uint8_t plcp_signal; 23726219Swpaul uint8_t plcp_service; 23826219Swpaul#define RT2661_PLCP_LENGEXT 0x80 23926219Swpaul 24026219Swpaul uint8_t plcp_length_lo; 24126219Swpaul uint8_t plcp_length_hi; 24226219Swpaul 24326219Swpaul uint32_t iv; 24426219Swpaul uint32_t eiv; 24526219Swpaul 24626219Swpaul uint8_t offset; 24726219Swpaul uint8_t qid; 24826219Swpaul#define RT2661_QID_MGT 13 24926219Swpaul 25026219Swpaul uint8_t txpower; 25126219Swpaul#define RT2661_DEFAULT_TXPOWER 0 25226219Swpaul 25326219Swpaul uint8_t reserved1; 25426219Swpaul 25526219Swpaul uint32_t addr[RT2661_MAX_SCATTER]; 25626219Swpaul uint16_t len[RT2661_MAX_SCATTER]; 25726219Swpaul 25826219Swpaul uint16_t reserved2; 25926219Swpaul} __packed; 26065220Sache 26126219Swpaul/* Rx descriptor */ 26226219Swpaulstruct rt2661_rx_desc { 26326219Swpaul uint32_t flags; 26426219Swpaul#define RT2661_RX_BUSY (1 << 0) 26526219Swpaul#define RT2661_RX_DROP (1 << 1) 26626219Swpaul#define RT2661_RX_CRC_ERROR (1 << 6) 26726219Swpaul#define RT2661_RX_OFDM (1 << 7) 26826219Swpaul#define RT2661_RX_PHY_ERROR (1 << 8) 26965220Sache#define RT2661_RX_CIPHER_MASK 0x00000600 27026219Swpaul 27165220Sache uint8_t rate; 27265220Sache uint8_t rssi; 27326219Swpaul uint8_t reserved1; 27426219Swpaul uint8_t offset; 27526219Swpaul uint32_t iv; 27626219Swpaul uint32_t eiv; 27726219Swpaul uint32_t reserved2; 27826219Swpaul uint32_t physaddr; 27926219Swpaul uint32_t reserved3[10]; 28026219Swpaul} __packed; 28126219Swpaul 28226219Swpaul#define RAL_RF1 0 28326219Swpaul#define RAL_RF2 2 28426219Swpaul#define RAL_RF3 1 28526219Swpaul#define RAL_RF4 3 28626219Swpaul 28726219Swpaul/* dual-band RF */ 28826219Swpaul#define RT2661_RF_5225 1 28926219Swpaul#define RT2661_RF_5325 2 29026219Swpaul/* single-band RF */ 29126219Swpaul#define RT2661_RF_2527 3 29226219Swpaul#define RT2661_RF_2529 4 29326219Swpaul 29426219Swpaul#define RT2661_RX_DESC_BACK 4 29526219Swpaul 29626219Swpaul#define RT2661_SMART_MODE (1 << 0) 29726583Swpaul 29826583Swpaul#define RT2661_BBPR94_DEFAULT 6 29926219Swpaul 30026219Swpaul#define RT2661_SHIFT_D 3 30126219Swpaul#define RT2661_SHIFT_Q 4 30226219Swpaul 30326219Swpaul#define RT2661_EEPROM_MAC01 0x02 30426219Swpaul#define RT2661_EEPROM_MAC23 0x03 30526219Swpaul#define RT2661_EEPROM_MAC45 0x04 30626219Swpaul#define RT2661_EEPROM_ANTENNA 0x10 30726219Swpaul#define RT2661_EEPROM_CONFIG2 0x11 30826219Swpaul#define RT2661_EEPROM_BBP_BASE 0x13 30965220Sache#define RT2661_EEPROM_TXPOWER 0x23 31026219Swpaul#define RT2661_EEPROM_FREQ_OFFSET 0x2f 31126219Swpaul#define RT2661_EEPROM_RSSI_2GHZ_OFFSET 0x4d 31226219Swpaul#define RT2661_EEPROM_RSSI_5GHZ_OFFSET 0x4e 31326219Swpaul 31426219Swpaul#define RT2661_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 31565220Sache 31665220Sache/* 31765220Sache * control and status registers access macros 31826219Swpaul */ 31926219Swpaul#define RAL_READ(sc, reg) \ 32026219Swpaul bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 32126219Swpaul 32226219Swpaul#define RAL_READ_REGION_4(sc, offset, datap, count) \ 32326219Swpaul bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 32426219Swpaul (datap), (count)) 32526219Swpaul 32626219Swpaul#define RAL_WRITE(sc, reg, val) \ 32726219Swpaul bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 32826219Swpaul 32926219Swpaul#define RAL_WRITE_REGION_1(sc, offset, datap, count) \ 33026219Swpaul bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \ 33126219Swpaul (datap), (count)) 332 333/* 334 * EEPROM access macro 335 */ 336#define RT2661_EEPROM_CTL(sc, val) do { \ 337 RAL_WRITE((sc), RT2661_E2PROM_CSR, (val)); \ 338 DELAY(RT2661_EEPROM_DELAY); \ 339} while (/* CONSTCOND */0) 340 341/* 342 * Default values for MAC registers; values taken from the reference driver. 343 */ 344#define RT2661_DEF_MAC \ 345 { RT2661_TXRX_CSR0, 0x0000b032 }, \ 346 { RT2661_TXRX_CSR1, 0x9eb39eb3 }, \ 347 { RT2661_TXRX_CSR2, 0x8a8b8c8d }, \ 348 { RT2661_TXRX_CSR3, 0x00858687 }, \ 349 { RT2661_TXRX_CSR7, 0x2e31353b }, \ 350 { RT2661_TXRX_CSR8, 0x2a2a2a2c }, \ 351 { RT2661_TXRX_CSR15, 0x0000000f }, \ 352 { RT2661_MAC_CSR6, 0x00000fff }, \ 353 { RT2661_MAC_CSR8, 0x016c030a }, \ 354 { RT2661_MAC_CSR10, 0x00000718 }, \ 355 { RT2661_MAC_CSR12, 0x00000004 }, \ 356 { RT2661_MAC_CSR13, 0x0000e000 }, \ 357 { RT2661_SEC_CSR0, 0x00000000 }, \ 358 { RT2661_SEC_CSR1, 0x00000000 }, \ 359 { RT2661_SEC_CSR5, 0x00000000 }, \ 360 { RT2661_PHY_CSR1, 0x000023b0 }, \ 361 { RT2661_PHY_CSR5, 0x060a100c }, \ 362 { RT2661_PHY_CSR6, 0x00080606 }, \ 363 { RT2661_PHY_CSR7, 0x00000a08 }, \ 364 { RT2661_PCI_CFG_CSR, 0x3cca4808 }, \ 365 { RT2661_AIFSN_CSR, 0x00002273 }, \ 366 { RT2661_CWMIN_CSR, 0x00002344 }, \ 367 { RT2661_CWMAX_CSR, 0x000034aa }, \ 368 { RT2661_TEST_MODE_CSR, 0x00000200 }, \ 369 { RT2661_M2H_CMD_DONE_CSR, 0xffffffff } 370 371/* 372 * Default values for BBP registers; values taken from the reference driver. 373 */ 374#define RT2661_DEF_BBP \ 375 { 3, 0x00 }, \ 376 { 15, 0x30 }, \ 377 { 17, 0x20 }, \ 378 { 21, 0xc8 }, \ 379 { 22, 0x38 }, \ 380 { 23, 0x06 }, \ 381 { 24, 0xfe }, \ 382 { 25, 0x0a }, \ 383 { 26, 0x0d }, \ 384 { 34, 0x12 }, \ 385 { 37, 0x07 }, \ 386 { 39, 0xf8 }, \ 387 { 41, 0x60 }, \ 388 { 53, 0x10 }, \ 389 { 54, 0x18 }, \ 390 { 60, 0x10 }, \ 391 { 61, 0x04 }, \ 392 { 62, 0x04 }, \ 393 { 75, 0xfe }, \ 394 { 86, 0xfe }, \ 395 { 88, 0xfe }, \ 396 { 90, 0x0f }, \ 397 { 99, 0x00 }, \ 398 { 102, 0x16 }, \ 399 { 107, 0x04 } 400 401/* 402 * Default settings for RF registers; values taken from the reference driver. 403 */ 404#define RT2661_RF5225_1 \ 405 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \ 406 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \ 407 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \ 408 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \ 409 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \ 410 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \ 411 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \ 412 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \ 413 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \ 414 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \ 415 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \ 416 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \ 417 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \ 418 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \ 419 \ 420 { 36, 0x00b33, 0x01266, 0x26014, 0x30288 }, \ 421 { 40, 0x00b33, 0x01268, 0x26014, 0x30280 }, \ 422 { 44, 0x00b33, 0x01269, 0x26014, 0x30282 }, \ 423 { 48, 0x00b33, 0x0126a, 0x26014, 0x30284 }, \ 424 { 52, 0x00b33, 0x0126b, 0x26014, 0x30286 }, \ 425 { 56, 0x00b33, 0x0126c, 0x26014, 0x30288 }, \ 426 { 60, 0x00b33, 0x0126e, 0x26014, 0x30280 }, \ 427 { 64, 0x00b33, 0x0126f, 0x26014, 0x30282 }, \ 428 \ 429 { 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 }, \ 430 { 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 }, \ 431 { 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 }, \ 432 { 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 }, \ 433 { 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 }, \ 434 { 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 }, \ 435 { 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 }, \ 436 { 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 }, \ 437 { 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 }, \ 438 { 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 }, \ 439 { 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 }, \ 440 \ 441 { 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 }, \ 442 { 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 }, \ 443 { 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 }, \ 444 { 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 }, \ 445 { 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 } 446 447#define RT2661_RF5225_2 \ 448 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \ 449 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \ 450 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \ 451 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \ 452 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \ 453 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \ 454 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \ 455 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \ 456 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \ 457 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \ 458 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \ 459 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \ 460 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \ 461 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \ 462 \ 463 { 36, 0x00b35, 0x11206, 0x26014, 0x30280 }, \ 464 { 40, 0x00b34, 0x111a0, 0x26014, 0x30280 }, \ 465 { 44, 0x00b34, 0x111a1, 0x26014, 0x30286 }, \ 466 { 48, 0x00b34, 0x111a3, 0x26014, 0x30282 }, \ 467 { 52, 0x00b34, 0x111a4, 0x26014, 0x30288 }, \ 468 { 56, 0x00b34, 0x111a6, 0x26014, 0x30284 }, \ 469 { 60, 0x00b34, 0x111a8, 0x26014, 0x30280 }, \ 470 { 64, 0x00b34, 0x111a9, 0x26014, 0x30286 }, \ 471 \ 472 { 100, 0x00b35, 0x11226, 0x2e014, 0x30280 }, \ 473 { 104, 0x00b35, 0x11228, 0x2e014, 0x30280 }, \ 474 { 108, 0x00b35, 0x1122a, 0x2e014, 0x30280 }, \ 475 { 112, 0x00b35, 0x1122c, 0x2e014, 0x30280 }, \ 476 { 116, 0x00b35, 0x1122e, 0x2e014, 0x30280 }, \ 477 { 120, 0x00b34, 0x111c0, 0x2e014, 0x30280 }, \ 478 { 124, 0x00b34, 0x111c1, 0x2e014, 0x30286 }, \ 479 { 128, 0x00b34, 0x111c3, 0x2e014, 0x30282 }, \ 480 { 132, 0x00b34, 0x111c4, 0x2e014, 0x30288 }, \ 481 { 136, 0x00b34, 0x111c6, 0x2e014, 0x30284 }, \ 482 { 140, 0x00b34, 0x111c8, 0x2e014, 0x30280 }, \ 483 \ 484 { 149, 0x00b34, 0x111cb, 0x2e014, 0x30286 }, \ 485 { 153, 0x00b34, 0x111cd, 0x2e014, 0x30282 }, \ 486 { 157, 0x00b35, 0x11242, 0x2e014, 0x30285 }, \ 487 { 161, 0x00b35, 0x11244, 0x2e014, 0x30285 }, \ 488 { 165, 0x00b35, 0x11246, 0x2e014, 0x30285 } 489