1/* 2 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $ 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD$"); 39 40#include "opt_inet.h" 41#include "opt_bwi.h" 42 43#include <sys/param.h> 44#include <sys/endian.h> 45#include <sys/kernel.h> 46#include <sys/bus.h> 47#include <sys/malloc.h> 48#include <sys/proc.h> 49#include <sys/rman.h> 50#include <sys/socket.h> 51#include <sys/sockio.h> 52#include <sys/sysctl.h> 53#include <sys/systm.h> 54#include <sys/taskqueue.h> 55 56#include <net/if.h> 57#include <net/if_dl.h> 58#include <net/if_media.h> 59#include <net/if_types.h> 60#include <net/if_arp.h> 61#include <net/ethernet.h> 62#include <net/if_llc.h> 63 64#include <net80211/ieee80211_var.h> 65#include <net80211/ieee80211_radiotap.h> 66#include <net80211/ieee80211_regdomain.h> 67#include <net80211/ieee80211_phy.h> 68#include <net80211/ieee80211_ratectl.h> 69 70#include <net/bpf.h> 71 72#ifdef INET 73#include <netinet/in.h> 74#include <netinet/if_ether.h> 75#endif 76 77#include <machine/bus.h> 78 79#include <dev/pci/pcivar.h> 80#include <dev/pci/pcireg.h> 81 82#include <dev/bwi/bitops.h> 83#include <dev/bwi/if_bwireg.h> 84#include <dev/bwi/if_bwivar.h> 85#include <dev/bwi/bwimac.h> 86#include <dev/bwi/bwirf.h> 87 88struct bwi_clock_freq { 89 u_int clkfreq_min; 90 u_int clkfreq_max; 91}; 92 93struct bwi_myaddr_bssid { 94 uint8_t myaddr[IEEE80211_ADDR_LEN]; 95 uint8_t bssid[IEEE80211_ADDR_LEN]; 96} __packed; 97 98static struct ieee80211vap *bwi_vap_create(struct ieee80211com *, 99 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 100 const uint8_t [IEEE80211_ADDR_LEN], 101 const uint8_t [IEEE80211_ADDR_LEN]); 102static void bwi_vap_delete(struct ieee80211vap *); 103static void bwi_init(void *); 104static int bwi_ioctl(struct ifnet *, u_long, caddr_t); 105static void bwi_start(struct ifnet *); 106static void bwi_start_locked(struct ifnet *); 107static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *, 108 const struct ieee80211_bpf_params *); 109static void bwi_watchdog(void *); 110static void bwi_scan_start(struct ieee80211com *); 111static void bwi_set_channel(struct ieee80211com *); 112static void bwi_scan_end(struct ieee80211com *); 113static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int); 114static void bwi_updateslot(struct ifnet *); 115static int bwi_media_change(struct ifnet *); 116 117static void bwi_calibrate(void *); 118 119static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *); 120static int bwi_calc_noise(struct bwi_softc *); 121static __inline uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phytype); 122static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *, 123 struct bwi_rxbuf_hdr *, const void *, int, int, int); 124 125static void bwi_restart(void *, int); 126static void bwi_init_statechg(struct bwi_softc *, int); 127static void bwi_stop(struct bwi_softc *, int); 128static void bwi_stop_locked(struct bwi_softc *, int); 129static int bwi_newbuf(struct bwi_softc *, int, int); 130static int bwi_encap(struct bwi_softc *, int, struct mbuf *, 131 struct ieee80211_node *); 132static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *, 133 struct ieee80211_node *, 134 const struct ieee80211_bpf_params *); 135 136static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t, 137 bus_addr_t, int, int); 138static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t); 139 140static int bwi_init_tx_ring32(struct bwi_softc *, int); 141static int bwi_init_rx_ring32(struct bwi_softc *); 142static int bwi_init_txstats32(struct bwi_softc *); 143static void bwi_free_tx_ring32(struct bwi_softc *, int); 144static void bwi_free_rx_ring32(struct bwi_softc *); 145static void bwi_free_txstats32(struct bwi_softc *); 146static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int); 147static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *, 148 int, bus_addr_t, int); 149static int bwi_rxeof32(struct bwi_softc *); 150static void bwi_start_tx32(struct bwi_softc *, uint32_t, int); 151static void bwi_txeof_status32(struct bwi_softc *); 152 153static int bwi_init_tx_ring64(struct bwi_softc *, int); 154static int bwi_init_rx_ring64(struct bwi_softc *); 155static int bwi_init_txstats64(struct bwi_softc *); 156static void bwi_free_tx_ring64(struct bwi_softc *, int); 157static void bwi_free_rx_ring64(struct bwi_softc *); 158static void bwi_free_txstats64(struct bwi_softc *); 159static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int); 160static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *, 161 int, bus_addr_t, int); 162static int bwi_rxeof64(struct bwi_softc *); 163static void bwi_start_tx64(struct bwi_softc *, uint32_t, int); 164static void bwi_txeof_status64(struct bwi_softc *); 165 166static int bwi_rxeof(struct bwi_softc *, int); 167static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int); 168static void bwi_txeof(struct bwi_softc *); 169static void bwi_txeof_status(struct bwi_softc *, int); 170static void bwi_enable_intrs(struct bwi_softc *, uint32_t); 171static void bwi_disable_intrs(struct bwi_softc *, uint32_t); 172 173static int bwi_dma_alloc(struct bwi_softc *); 174static void bwi_dma_free(struct bwi_softc *); 175static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t, 176 struct bwi_ring_data *, bus_size_t, 177 uint32_t); 178static int bwi_dma_mbuf_create(struct bwi_softc *); 179static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int); 180static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t); 181static void bwi_dma_txstats_free(struct bwi_softc *); 182static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 183static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int, 184 bus_size_t, int); 185 186static void bwi_power_on(struct bwi_softc *, int); 187static int bwi_power_off(struct bwi_softc *, int); 188static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode); 189static int bwi_set_clock_delay(struct bwi_softc *); 190static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *); 191static int bwi_get_pwron_delay(struct bwi_softc *sc); 192static void bwi_set_addr_filter(struct bwi_softc *, uint16_t, 193 const uint8_t *); 194static void bwi_set_bssid(struct bwi_softc *, const uint8_t *); 195 196static void bwi_get_card_flags(struct bwi_softc *); 197static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *); 198 199static int bwi_bus_attach(struct bwi_softc *); 200static int bwi_bbp_attach(struct bwi_softc *); 201static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode); 202static void bwi_bbp_power_off(struct bwi_softc *); 203 204static const char *bwi_regwin_name(const struct bwi_regwin *); 205static uint32_t bwi_regwin_disable_bits(struct bwi_softc *); 206static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *); 207static int bwi_regwin_select(struct bwi_softc *, int); 208 209static void bwi_led_attach(struct bwi_softc *); 210static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state); 211static void bwi_led_event(struct bwi_softc *, int); 212static void bwi_led_blink_start(struct bwi_softc *, int, int); 213static void bwi_led_blink_next(void *); 214static void bwi_led_blink_end(void *); 215 216static const struct { 217 uint16_t did_min; 218 uint16_t did_max; 219 uint16_t bbp_id; 220} bwi_bbpid_map[] = { 221 { 0x4301, 0x4301, 0x4301 }, 222 { 0x4305, 0x4307, 0x4307 }, 223 { 0x4402, 0x4403, 0x4402 }, 224 { 0x4610, 0x4615, 0x4610 }, 225 { 0x4710, 0x4715, 0x4710 }, 226 { 0x4720, 0x4725, 0x4309 } 227}; 228 229static const struct { 230 uint16_t bbp_id; 231 int nregwin; 232} bwi_regwin_count[] = { 233 { 0x4301, 5 }, 234 { 0x4306, 6 }, 235 { 0x4307, 5 }, 236 { 0x4310, 8 }, 237 { 0x4401, 3 }, 238 { 0x4402, 3 }, 239 { 0x4610, 9 }, 240 { 0x4704, 9 }, 241 { 0x4710, 9 }, 242 { 0x5365, 7 } 243}; 244 245#define CLKSRC(src) \ 246[BWI_CLKSRC_ ## src] = { \ 247 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \ 248 .freq_max = BWI_CLKSRC_ ##src## _FMAX \ 249} 250 251static const struct { 252 u_int freq_min; 253 u_int freq_max; 254} bwi_clkfreq[BWI_CLKSRC_MAX] = { 255 CLKSRC(LP_OSC), 256 CLKSRC(CS_OSC), 257 CLKSRC(PCI) 258}; 259 260#undef CLKSRC 261 262#define VENDOR_LED_ACT(vendor) \ 263{ \ 264 .vid = PCI_VENDOR_##vendor, \ 265 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \ 266} 267 268static const struct { 269#define PCI_VENDOR_COMPAQ 0x0e11 270#define PCI_VENDOR_LINKSYS 0x1737 271 uint16_t vid; 272 uint8_t led_act[BWI_LED_MAX]; 273} bwi_vendor_led_act[] = { 274 VENDOR_LED_ACT(COMPAQ), 275 VENDOR_LED_ACT(LINKSYS) 276#undef PCI_VENDOR_LINKSYS 277#undef PCI_VENDOR_COMPAQ 278}; 279 280static const uint8_t bwi_default_led_act[BWI_LED_MAX] = 281 { BWI_VENDOR_LED_ACT_DEFAULT }; 282 283#undef VENDOR_LED_ACT 284 285static const struct { 286 int on_dur; 287 int off_dur; 288} bwi_led_duration[109] = { 289 [0] = { 400, 100 }, 290 [2] = { 150, 75 }, 291 [4] = { 90, 45 }, 292 [11] = { 66, 34 }, 293 [12] = { 53, 26 }, 294 [18] = { 42, 21 }, 295 [22] = { 35, 17 }, 296 [24] = { 32, 16 }, 297 [36] = { 21, 10 }, 298 [48] = { 16, 8 }, 299 [72] = { 11, 5 }, 300 [96] = { 9, 4 }, 301 [108] = { 7, 3 } 302}; 303 304#ifdef BWI_DEBUG 305#ifdef BWI_DEBUG_VERBOSE 306static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER; 307#else 308static uint32_t bwi_debug; 309#endif 310TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug); 311#endif /* BWI_DEBUG */ 312 313static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN]; 314 315uint16_t 316bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs) 317{ 318 return CSR_READ_2(sc, ofs + BWI_SPROM_START); 319} 320 321static __inline void 322bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array, 323 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len, 324 int tx) 325{ 326 struct bwi_desc32 *desc = &desc_array[desc_idx]; 327 uint32_t ctrl, addr, addr_hi, addr_lo; 328 329 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK); 330 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK); 331 332 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) | 333 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK); 334 335 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) | 336 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK); 337 if (desc_idx == ndesc - 1) 338 ctrl |= BWI_DESC32_C_EOR; 339 if (tx) { 340 /* XXX */ 341 ctrl |= BWI_DESC32_C_FRAME_START | 342 BWI_DESC32_C_FRAME_END | 343 BWI_DESC32_C_INTR; 344 } 345 346 desc->addr = htole32(addr); 347 desc->ctrl = htole32(ctrl); 348} 349 350int 351bwi_attach(struct bwi_softc *sc) 352{ 353 struct ieee80211com *ic; 354 device_t dev = sc->sc_dev; 355 struct ifnet *ifp; 356 struct bwi_mac *mac; 357 struct bwi_phy *phy; 358 int i, error; 359 uint8_t bands; 360 uint8_t macaddr[IEEE80211_ADDR_LEN]; 361 362 BWI_LOCK_INIT(sc); 363 364 /* 365 * Initialize taskq and various tasks 366 */ 367 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO, 368 taskqueue_thread_enqueue, &sc->sc_tq); 369 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 370 device_get_nameunit(dev)); 371 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc); 372 373 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0); 374 375 /* 376 * Initialize sysctl variables 377 */ 378 sc->sc_fw_version = BWI_FW_VERSION3; 379 sc->sc_led_idle = (2350 * hz) / 1000; 380 sc->sc_led_blink = 1; 381 sc->sc_txpwr_calib = 1; 382#ifdef BWI_DEBUG 383 sc->sc_debug = bwi_debug; 384#endif 385 bwi_power_on(sc, 1); 386 387 error = bwi_bbp_attach(sc); 388 if (error) 389 goto fail; 390 391 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 392 if (error) 393 goto fail; 394 395 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) { 396 error = bwi_set_clock_delay(sc); 397 if (error) 398 goto fail; 399 400 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST); 401 if (error) 402 goto fail; 403 404 error = bwi_get_pwron_delay(sc); 405 if (error) 406 goto fail; 407 } 408 409 error = bwi_bus_attach(sc); 410 if (error) 411 goto fail; 412 413 bwi_get_card_flags(sc); 414 415 bwi_led_attach(sc); 416 417 for (i = 0; i < sc->sc_nmac; ++i) { 418 struct bwi_regwin *old; 419 420 mac = &sc->sc_mac[i]; 421 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old); 422 if (error) 423 goto fail; 424 425 error = bwi_mac_lateattach(mac); 426 if (error) 427 goto fail; 428 429 error = bwi_regwin_switch(sc, old, NULL); 430 if (error) 431 goto fail; 432 } 433 434 /* 435 * XXX First MAC is known to exist 436 * TODO2 437 */ 438 mac = &sc->sc_mac[0]; 439 phy = &mac->mac_phy; 440 441 bwi_bbp_power_off(sc); 442 443 error = bwi_dma_alloc(sc); 444 if (error) 445 goto fail; 446 447 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 448 if (ifp == NULL) { 449 device_printf(dev, "can not if_alloc()\n"); 450 error = ENOSPC; 451 goto fail; 452 } 453 ic = ifp->if_l2com; 454 455 /* set these up early for if_printf use */ 456 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 457 458 ifp->if_softc = sc; 459 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 460 ifp->if_init = bwi_init; 461 ifp->if_ioctl = bwi_ioctl; 462 ifp->if_start = bwi_start; 463 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 464 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 465 IFQ_SET_READY(&ifp->if_snd); 466 callout_init_mtx(&sc->sc_watchdog_timer, &sc->sc_mtx, 0); 467 468 /* 469 * Setup ratesets, phytype, channels and get MAC address 470 */ 471 bands = 0; 472 if (phy->phy_mode == IEEE80211_MODE_11B || 473 phy->phy_mode == IEEE80211_MODE_11G) { 474 setbit(&bands, IEEE80211_MODE_11B); 475 if (phy->phy_mode == IEEE80211_MODE_11B) { 476 ic->ic_phytype = IEEE80211_T_DS; 477 } else { 478 ic->ic_phytype = IEEE80211_T_OFDM; 479 setbit(&bands, IEEE80211_MODE_11G); 480 } 481 482 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, macaddr); 483 if (IEEE80211_IS_MULTICAST(macaddr)) { 484 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, macaddr); 485 if (IEEE80211_IS_MULTICAST(macaddr)) { 486 device_printf(dev, 487 "invalid MAC address: %6D\n", 488 macaddr, ":"); 489 } 490 } 491 } else if (phy->phy_mode == IEEE80211_MODE_11A) { 492 /* TODO:11A */ 493 setbit(&bands, IEEE80211_MODE_11A); 494 error = ENXIO; 495 goto fail; 496 } else { 497 panic("unknown phymode %d\n", phy->phy_mode); 498 } 499 500 /* Get locale */ 501 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO), 502 BWI_SPROM_CARD_INFO_LOCALE); 503 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale); 504 /* XXX use locale */ 505 ieee80211_init_channels(ic, NULL, &bands); 506 507 ic->ic_ifp = ifp; 508 ic->ic_caps = IEEE80211_C_STA | 509 IEEE80211_C_SHSLOT | 510 IEEE80211_C_SHPREAMBLE | 511 IEEE80211_C_WPA | 512 IEEE80211_C_BGSCAN | 513 IEEE80211_C_MONITOR; 514 ic->ic_opmode = IEEE80211_M_STA; 515 ieee80211_ifattach(ic, macaddr); 516 517 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr); 518 519 /* override default methods */ 520 ic->ic_vap_create = bwi_vap_create; 521 ic->ic_vap_delete = bwi_vap_delete; 522 ic->ic_raw_xmit = bwi_raw_xmit; 523 ic->ic_updateslot = bwi_updateslot; 524 ic->ic_scan_start = bwi_scan_start; 525 ic->ic_scan_end = bwi_scan_end; 526 ic->ic_set_channel = bwi_set_channel; 527 528 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 529 530 ieee80211_radiotap_attach(ic, 531 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 532 BWI_TX_RADIOTAP_PRESENT, 533 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 534 BWI_RX_RADIOTAP_PRESENT); 535 536 /* 537 * Add sysctl nodes 538 */ 539 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 540 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 541 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0, 542 "Firmware version"); 543 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 544 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 545 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0, 546 "# ticks before LED enters idle state"); 547 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 548 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 549 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0, 550 "Allow LED to blink"); 551 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 552 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 553 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0, 554 "Enable software TX power calibration"); 555#ifdef BWI_DEBUG 556 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 557 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 558 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); 559#endif 560 if (bootverbose) 561 ieee80211_announce(ic); 562 563 return (0); 564fail: 565 BWI_LOCK_DESTROY(sc); 566 return (error); 567} 568 569int 570bwi_detach(struct bwi_softc *sc) 571{ 572 struct ifnet *ifp = sc->sc_ifp; 573 struct ieee80211com *ic = ifp->if_l2com; 574 int i; 575 576 bwi_stop(sc, 1); 577 callout_drain(&sc->sc_led_blink_ch); 578 callout_drain(&sc->sc_calib_ch); 579 callout_drain(&sc->sc_watchdog_timer); 580 ieee80211_ifdetach(ic); 581 582 for (i = 0; i < sc->sc_nmac; ++i) 583 bwi_mac_detach(&sc->sc_mac[i]); 584 bwi_dma_free(sc); 585 if_free(ifp); 586 taskqueue_free(sc->sc_tq); 587 588 BWI_LOCK_DESTROY(sc); 589 590 return (0); 591} 592 593static struct ieee80211vap * 594bwi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 595 enum ieee80211_opmode opmode, int flags, 596 const uint8_t bssid[IEEE80211_ADDR_LEN], 597 const uint8_t mac[IEEE80211_ADDR_LEN]) 598{ 599 struct bwi_vap *bvp; 600 struct ieee80211vap *vap; 601 602 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 603 return NULL; 604 bvp = (struct bwi_vap *) malloc(sizeof(struct bwi_vap), 605 M_80211_VAP, M_WAITOK | M_ZERO); 606 if (bvp == NULL) 607 return NULL; 608 vap = &bvp->bv_vap; 609 /* enable s/w bmiss handling for sta mode */ 610 ieee80211_vap_setup(ic, vap, name, unit, opmode, 611 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac); 612 613 /* override default methods */ 614 bvp->bv_newstate = vap->iv_newstate; 615 vap->iv_newstate = bwi_newstate; 616#if 0 617 vap->iv_update_beacon = bwi_beacon_update; 618#endif 619 ieee80211_ratectl_init(vap); 620 621 /* complete setup */ 622 ieee80211_vap_attach(vap, bwi_media_change, ieee80211_media_status); 623 ic->ic_opmode = opmode; 624 return vap; 625} 626 627static void 628bwi_vap_delete(struct ieee80211vap *vap) 629{ 630 struct bwi_vap *bvp = BWI_VAP(vap); 631 632 ieee80211_ratectl_deinit(vap); 633 ieee80211_vap_detach(vap); 634 free(bvp, M_80211_VAP); 635} 636 637void 638bwi_suspend(struct bwi_softc *sc) 639{ 640 bwi_stop(sc, 1); 641} 642 643void 644bwi_resume(struct bwi_softc *sc) 645{ 646 struct ifnet *ifp = sc->sc_ifp; 647 648 if (ifp->if_flags & IFF_UP) 649 bwi_init(sc); 650} 651 652int 653bwi_shutdown(struct bwi_softc *sc) 654{ 655 bwi_stop(sc, 1); 656 return 0; 657} 658 659static void 660bwi_power_on(struct bwi_softc *sc, int with_pll) 661{ 662 uint32_t gpio_in, gpio_out, gpio_en; 663 uint16_t status; 664 665 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); 666 if (gpio_in & BWI_PCIM_GPIO_PWR_ON) 667 goto back; 668 669 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 670 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 671 672 gpio_out |= BWI_PCIM_GPIO_PWR_ON; 673 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 674 if (with_pll) { 675 /* Turn off PLL first */ 676 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 677 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 678 } 679 680 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 681 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 682 DELAY(1000); 683 684 if (with_pll) { 685 /* Turn on PLL */ 686 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF; 687 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 688 DELAY(5000); 689 } 690 691back: 692 /* Clear "Signaled Target Abort" */ 693 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 694 status &= ~PCIM_STATUS_STABORT; 695 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 696} 697 698static int 699bwi_power_off(struct bwi_softc *sc, int with_pll) 700{ 701 uint32_t gpio_out, gpio_en; 702 703 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */ 704 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 705 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 706 707 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON; 708 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 709 if (with_pll) { 710 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 711 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 712 } 713 714 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 715 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 716 return 0; 717} 718 719int 720bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw, 721 struct bwi_regwin **old_rw) 722{ 723 int error; 724 725 if (old_rw != NULL) 726 *old_rw = NULL; 727 728 if (!BWI_REGWIN_EXIST(rw)) 729 return EINVAL; 730 731 if (sc->sc_cur_regwin != rw) { 732 error = bwi_regwin_select(sc, rw->rw_id); 733 if (error) { 734 device_printf(sc->sc_dev, "can't select regwin %d\n", 735 rw->rw_id); 736 return error; 737 } 738 } 739 740 if (old_rw != NULL) 741 *old_rw = sc->sc_cur_regwin; 742 sc->sc_cur_regwin = rw; 743 return 0; 744} 745 746static int 747bwi_regwin_select(struct bwi_softc *sc, int id) 748{ 749 uint32_t win = BWI_PCIM_REGWIN(id); 750 int i; 751 752#define RETRY_MAX 50 753 for (i = 0; i < RETRY_MAX; ++i) { 754 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4); 755 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win) 756 return 0; 757 DELAY(10); 758 } 759#undef RETRY_MAX 760 761 return ENXIO; 762} 763 764static void 765bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev) 766{ 767 uint32_t val; 768 769 val = CSR_READ_4(sc, BWI_ID_HI); 770 *type = BWI_ID_HI_REGWIN_TYPE(val); 771 *rev = BWI_ID_HI_REGWIN_REV(val); 772 773 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, " 774 "vendor 0x%04x\n", *type, *rev, 775 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK)); 776} 777 778static int 779bwi_bbp_attach(struct bwi_softc *sc) 780{ 781#define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 782 uint16_t bbp_id, rw_type; 783 uint8_t rw_rev; 784 uint32_t info; 785 int error, nregwin, i; 786 787 /* 788 * Get 0th regwin information 789 * NOTE: 0th regwin should exist 790 */ 791 error = bwi_regwin_select(sc, 0); 792 if (error) { 793 device_printf(sc->sc_dev, "can't select regwin 0\n"); 794 return error; 795 } 796 bwi_regwin_info(sc, &rw_type, &rw_rev); 797 798 /* 799 * Find out BBP id 800 */ 801 bbp_id = 0; 802 info = 0; 803 if (rw_type == BWI_REGWIN_T_COM) { 804 info = CSR_READ_4(sc, BWI_INFO); 805 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK); 806 807 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev); 808 809 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY); 810 } else { 811 for (i = 0; i < N(bwi_bbpid_map); ++i) { 812 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min && 813 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) { 814 bbp_id = bwi_bbpid_map[i].bbp_id; 815 break; 816 } 817 } 818 if (bbp_id == 0) { 819 device_printf(sc->sc_dev, "no BBP id for device id " 820 "0x%04x\n", sc->sc_pci_did); 821 return ENXIO; 822 } 823 824 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) | 825 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK); 826 } 827 828 /* 829 * Find out number of regwins 830 */ 831 nregwin = 0; 832 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) { 833 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK); 834 } else { 835 for (i = 0; i < N(bwi_regwin_count); ++i) { 836 if (bwi_regwin_count[i].bbp_id == bbp_id) { 837 nregwin = bwi_regwin_count[i].nregwin; 838 break; 839 } 840 } 841 if (nregwin == 0) { 842 device_printf(sc->sc_dev, "no number of win for " 843 "BBP id 0x%04x\n", bbp_id); 844 return ENXIO; 845 } 846 } 847 848 /* Record BBP id/rev for later using */ 849 sc->sc_bbp_id = bbp_id; 850 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK); 851 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK); 852 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n", 853 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg); 854 855 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n", 856 nregwin, sc->sc_cap); 857 858 /* 859 * Create rest of the regwins 860 */ 861 862 /* Don't re-create common regwin, if it is already created */ 863 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0; 864 865 for (; i < nregwin; ++i) { 866 /* 867 * Get regwin information 868 */ 869 error = bwi_regwin_select(sc, i); 870 if (error) { 871 device_printf(sc->sc_dev, 872 "can't select regwin %d\n", i); 873 return error; 874 } 875 bwi_regwin_info(sc, &rw_type, &rw_rev); 876 877 /* 878 * Try attach: 879 * 1) Bus (PCI/PCIE) regwin 880 * 2) MAC regwin 881 * Ignore rest types of regwin 882 */ 883 if (rw_type == BWI_REGWIN_T_BUSPCI || 884 rw_type == BWI_REGWIN_T_BUSPCIE) { 885 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 886 device_printf(sc->sc_dev, 887 "bus regwin already exists\n"); 888 } else { 889 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i, 890 rw_type, rw_rev); 891 } 892 } else if (rw_type == BWI_REGWIN_T_MAC) { 893 /* XXX ignore return value */ 894 bwi_mac_attach(sc, i, rw_rev); 895 } 896 } 897 898 /* At least one MAC shold exist */ 899 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) { 900 device_printf(sc->sc_dev, "no MAC was found\n"); 901 return ENXIO; 902 } 903 KASSERT(sc->sc_nmac > 0, ("no mac's")); 904 905 /* Bus regwin must exist */ 906 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 907 device_printf(sc->sc_dev, "no bus regwin was found\n"); 908 return ENXIO; 909 } 910 911 /* Start with first MAC */ 912 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL); 913 if (error) 914 return error; 915 916 return 0; 917#undef N 918} 919 920int 921bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac) 922{ 923 struct bwi_regwin *old, *bus; 924 uint32_t val; 925 int error; 926 927 bus = &sc->sc_bus_regwin; 928 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin")); 929 930 /* 931 * Tell bus to generate requested interrupts 932 */ 933 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) { 934 /* 935 * NOTE: Read BWI_FLAGS from MAC regwin 936 */ 937 val = CSR_READ_4(sc, BWI_FLAGS); 938 939 error = bwi_regwin_switch(sc, bus, &old); 940 if (error) 941 return error; 942 943 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK)); 944 } else { 945 uint32_t mac_mask; 946 947 mac_mask = 1 << mac->mac_id; 948 949 error = bwi_regwin_switch(sc, bus, &old); 950 if (error) 951 return error; 952 953 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4); 954 val |= mac_mask << 8; 955 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4); 956 } 957 958 if (sc->sc_flags & BWI_F_BUS_INITED) 959 goto back; 960 961 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) { 962 /* 963 * Enable prefetch and burst 964 */ 965 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, 966 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST); 967 968 if (bus->rw_rev < 5) { 969 struct bwi_regwin *com = &sc->sc_com_regwin; 970 971 /* 972 * Configure timeouts for bus operation 973 */ 974 975 /* 976 * Set service timeout and request timeout 977 */ 978 CSR_SETBITS_4(sc, BWI_CONF_LO, 979 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) | 980 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK)); 981 982 /* 983 * If there is common regwin, we switch to that regwin 984 * and switch back to bus regwin once we have done. 985 */ 986 if (BWI_REGWIN_EXIST(com)) { 987 error = bwi_regwin_switch(sc, com, NULL); 988 if (error) 989 return error; 990 } 991 992 /* Let bus know what we have changed */ 993 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC); 994 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */ 995 CSR_WRITE_4(sc, BWI_BUS_DATA, 0); 996 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */ 997 998 if (BWI_REGWIN_EXIST(com)) { 999 error = bwi_regwin_switch(sc, bus, NULL); 1000 if (error) 1001 return error; 1002 } 1003 } else if (bus->rw_rev >= 11) { 1004 /* 1005 * Enable memory read multiple 1006 */ 1007 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM); 1008 } 1009 } else { 1010 /* TODO:PCIE */ 1011 } 1012 1013 sc->sc_flags |= BWI_F_BUS_INITED; 1014back: 1015 return bwi_regwin_switch(sc, old, NULL); 1016} 1017 1018static void 1019bwi_get_card_flags(struct bwi_softc *sc) 1020{ 1021#define PCI_VENDOR_APPLE 0x106b 1022#define PCI_VENDOR_DELL 0x1028 1023 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS); 1024 if (sc->sc_card_flags == 0xffff) 1025 sc->sc_card_flags = 0; 1026 1027 if (sc->sc_pci_subvid == PCI_VENDOR_DELL && 1028 sc->sc_bbp_id == BWI_BBPID_BCM4301 && 1029 sc->sc_pci_revid == 0x74) 1030 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST; 1031 1032 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE && 1033 sc->sc_pci_subdid == 0x4e && /* XXX */ 1034 sc->sc_pci_revid > 0x40) 1035 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9; 1036 1037 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags); 1038#undef PCI_VENDOR_DELL 1039#undef PCI_VENDOR_APPLE 1040} 1041 1042static void 1043bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr) 1044{ 1045 int i; 1046 1047 for (i = 0; i < 3; ++i) { 1048 *((uint16_t *)eaddr + i) = 1049 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i)); 1050 } 1051} 1052 1053static void 1054bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq) 1055{ 1056 struct bwi_regwin *com; 1057 uint32_t val; 1058 u_int div; 1059 int src; 1060 1061 bzero(freq, sizeof(*freq)); 1062 com = &sc->sc_com_regwin; 1063 1064 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist")); 1065 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin")); 1066 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode")); 1067 1068 /* 1069 * Calculate clock frequency 1070 */ 1071 src = -1; 1072 div = 0; 1073 if (com->rw_rev < 6) { 1074 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 1075 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) { 1076 src = BWI_CLKSRC_PCI; 1077 div = 64; 1078 } else { 1079 src = BWI_CLKSRC_CS_OSC; 1080 div = 32; 1081 } 1082 } else if (com->rw_rev < 10) { 1083 val = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1084 1085 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC); 1086 if (src == BWI_CLKSRC_LP_OSC) { 1087 div = 1; 1088 } else { 1089 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2; 1090 1091 /* Unknown source */ 1092 if (src >= BWI_CLKSRC_MAX) 1093 src = BWI_CLKSRC_CS_OSC; 1094 } 1095 } else { 1096 val = CSR_READ_4(sc, BWI_CLOCK_INFO); 1097 1098 src = BWI_CLKSRC_CS_OSC; 1099 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2; 1100 } 1101 1102 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src)); 1103 KASSERT(div != 0, ("div zero")); 1104 1105 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n", 1106 src == BWI_CLKSRC_PCI ? "PCI" : 1107 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC")); 1108 1109 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div; 1110 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div; 1111 1112 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n", 1113 freq->clkfreq_min, freq->clkfreq_max); 1114} 1115 1116static int 1117bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 1118{ 1119 struct bwi_regwin *old, *com; 1120 uint32_t clk_ctrl, clk_src; 1121 int error, pwr_off = 0; 1122 1123 com = &sc->sc_com_regwin; 1124 if (!BWI_REGWIN_EXIST(com)) 1125 return 0; 1126 1127 if (com->rw_rev >= 10 || com->rw_rev < 6) 1128 return 0; 1129 1130 /* 1131 * For common regwin whose rev is [6, 10), the chip 1132 * must be capable to change clock mode. 1133 */ 1134 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 1135 return 0; 1136 1137 error = bwi_regwin_switch(sc, com, &old); 1138 if (error) 1139 return error; 1140 1141 if (clk_mode == BWI_CLOCK_MODE_FAST) 1142 bwi_power_on(sc, 0); /* Don't turn on PLL */ 1143 1144 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1145 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC); 1146 1147 switch (clk_mode) { 1148 case BWI_CLOCK_MODE_FAST: 1149 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW; 1150 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL; 1151 break; 1152 case BWI_CLOCK_MODE_SLOW: 1153 clk_ctrl |= BWI_CLOCK_CTRL_SLOW; 1154 break; 1155 case BWI_CLOCK_MODE_DYN: 1156 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW | 1157 BWI_CLOCK_CTRL_IGNPLL | 1158 BWI_CLOCK_CTRL_NODYN); 1159 if (clk_src != BWI_CLKSRC_CS_OSC) { 1160 clk_ctrl |= BWI_CLOCK_CTRL_NODYN; 1161 pwr_off = 1; 1162 } 1163 break; 1164 } 1165 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl); 1166 1167 if (pwr_off) 1168 bwi_power_off(sc, 0); /* Leave PLL as it is */ 1169 1170 return bwi_regwin_switch(sc, old, NULL); 1171} 1172 1173static int 1174bwi_set_clock_delay(struct bwi_softc *sc) 1175{ 1176 struct bwi_regwin *old, *com; 1177 int error; 1178 1179 com = &sc->sc_com_regwin; 1180 if (!BWI_REGWIN_EXIST(com)) 1181 return 0; 1182 1183 error = bwi_regwin_switch(sc, com, &old); 1184 if (error) 1185 return error; 1186 1187 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) { 1188 if (sc->sc_bbp_rev == 0) 1189 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0); 1190 else if (sc->sc_bbp_rev == 1) 1191 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1); 1192 } 1193 1194 if (sc->sc_cap & BWI_CAP_CLKMODE) { 1195 if (com->rw_rev >= 10) { 1196 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000); 1197 } else { 1198 struct bwi_clock_freq freq; 1199 1200 bwi_get_clock_freq(sc, &freq); 1201 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY, 1202 howmany(freq.clkfreq_max * 150, 1000000)); 1203 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY, 1204 howmany(freq.clkfreq_max * 15, 1000000)); 1205 } 1206 } 1207 1208 return bwi_regwin_switch(sc, old, NULL); 1209} 1210 1211static void 1212bwi_init(void *xsc) 1213{ 1214 struct bwi_softc *sc = xsc; 1215 struct ifnet *ifp = sc->sc_ifp; 1216 struct ieee80211com *ic = ifp->if_l2com; 1217 1218 BWI_LOCK(sc); 1219 bwi_init_statechg(sc, 1); 1220 BWI_UNLOCK(sc); 1221 1222 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1223 ieee80211_start_all(ic); /* start all vap's */ 1224} 1225 1226static void 1227bwi_init_statechg(struct bwi_softc *sc, int statechg) 1228{ 1229 struct ifnet *ifp = sc->sc_ifp; 1230 struct bwi_mac *mac; 1231 int error; 1232 1233 bwi_stop_locked(sc, statechg); 1234 1235 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 1236 1237 /* TODO: 2 MAC */ 1238 1239 mac = &sc->sc_mac[0]; 1240 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL); 1241 if (error) { 1242 if_printf(ifp, "%s: error %d on regwin switch\n", 1243 __func__, error); 1244 goto bad; 1245 } 1246 error = bwi_mac_init(mac); 1247 if (error) { 1248 if_printf(ifp, "%s: error %d on MAC init\n", __func__, error); 1249 goto bad; 1250 } 1251 1252 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN); 1253 1254 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */ 1255 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, IF_LLADDR(ifp)); 1256 1257 bwi_mac_reset_hwkeys(mac); 1258 1259 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) { 1260 int i; 1261 1262#define NRETRY 1000 1263 /* 1264 * Drain any possible pending TX status 1265 */ 1266 for (i = 0; i < NRETRY; ++i) { 1267 if ((CSR_READ_4(sc, BWI_TXSTATUS0) & 1268 BWI_TXSTATUS0_VALID) == 0) 1269 break; 1270 CSR_READ_4(sc, BWI_TXSTATUS1); 1271 } 1272 if (i == NRETRY) 1273 if_printf(ifp, "%s: can't drain TX status\n", __func__); 1274#undef NRETRY 1275 } 1276 1277 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G) 1278 bwi_mac_updateslot(mac, 1); 1279 1280 /* Start MAC */ 1281 error = bwi_mac_start(mac); 1282 if (error) { 1283 if_printf(ifp, "%s: error %d starting MAC\n", __func__, error); 1284 goto bad; 1285 } 1286 1287 /* Clear stop flag before enabling interrupt */ 1288 sc->sc_flags &= ~BWI_F_STOP; 1289 1290 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1291 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1292 1293 /* Enable intrs */ 1294 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1295 return; 1296bad: 1297 bwi_stop_locked(sc, 1); 1298} 1299 1300static int 1301bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1302{ 1303#define IS_RUNNING(ifp) \ 1304 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1305 struct bwi_softc *sc = ifp->if_softc; 1306 struct ieee80211com *ic = ifp->if_l2com; 1307 struct ifreq *ifr = (struct ifreq *) data; 1308 int error = 0, startall = 0; 1309 1310 switch (cmd) { 1311 case SIOCSIFFLAGS: 1312 BWI_LOCK(sc); 1313 if (IS_RUNNING(ifp)) { 1314 struct bwi_mac *mac; 1315 int promisc = -1; 1316 1317 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1318 ("current regwin type %d", 1319 sc->sc_cur_regwin->rw_type)); 1320 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1321 1322 if ((ifp->if_flags & IFF_PROMISC) && 1323 (sc->sc_flags & BWI_F_PROMISC) == 0) { 1324 promisc = 1; 1325 sc->sc_flags |= BWI_F_PROMISC; 1326 } else if ((ifp->if_flags & IFF_PROMISC) == 0 && 1327 (sc->sc_flags & BWI_F_PROMISC)) { 1328 promisc = 0; 1329 sc->sc_flags &= ~BWI_F_PROMISC; 1330 } 1331 1332 if (promisc >= 0) 1333 bwi_mac_set_promisc(mac, promisc); 1334 } 1335 1336 if (ifp->if_flags & IFF_UP) { 1337 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1338 bwi_init_statechg(sc, 1); 1339 startall = 1; 1340 } 1341 } else { 1342 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1343 bwi_stop_locked(sc, 1); 1344 } 1345 BWI_UNLOCK(sc); 1346 if (startall) 1347 ieee80211_start_all(ic); 1348 break; 1349 case SIOCGIFMEDIA: 1350 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1351 break; 1352 case SIOCGIFADDR: 1353 error = ether_ioctl(ifp, cmd, data); 1354 break; 1355 default: 1356 error = EINVAL; 1357 break; 1358 } 1359 return error; 1360#undef IS_RUNNING 1361} 1362 1363static void 1364bwi_start(struct ifnet *ifp) 1365{ 1366 struct bwi_softc *sc = ifp->if_softc; 1367 1368 BWI_LOCK(sc); 1369 bwi_start_locked(ifp); 1370 BWI_UNLOCK(sc); 1371} 1372 1373static void 1374bwi_start_locked(struct ifnet *ifp) 1375{ 1376 struct bwi_softc *sc = ifp->if_softc; 1377 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1378 struct ieee80211_frame *wh; 1379 struct ieee80211_node *ni; 1380 struct ieee80211_key *k; 1381 struct mbuf *m; 1382 int trans, idx; 1383 1384 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1385 return; 1386 1387 trans = 0; 1388 idx = tbd->tbd_idx; 1389 1390 while (tbd->tbd_buf[idx].tb_mbuf == NULL) { 1391 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1392 if (m == NULL) 1393 break; 1394 1395 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1396 wh = mtod(m, struct ieee80211_frame *); 1397 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1398 k = ieee80211_crypto_encap(ni, m); 1399 if (k == NULL) { 1400 ieee80211_free_node(ni); 1401 m_freem(m); 1402 ifp->if_oerrors++; 1403 continue; 1404 } 1405 } 1406 wh = NULL; /* Catch any invalid use */ 1407 1408 if (bwi_encap(sc, idx, m, ni) != 0) { 1409 /* 'm' is freed in bwi_encap() if we reach here */ 1410 if (ni != NULL) 1411 ieee80211_free_node(ni); 1412 ifp->if_oerrors++; 1413 continue; 1414 } 1415 1416 trans = 1; 1417 tbd->tbd_used++; 1418 idx = (idx + 1) % BWI_TX_NDESC; 1419 1420 ifp->if_opackets++; 1421 1422 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) { 1423 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1424 break; 1425 } 1426 } 1427 tbd->tbd_idx = idx; 1428 1429 if (trans) 1430 sc->sc_tx_timer = 5; 1431} 1432 1433static int 1434bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1435 const struct ieee80211_bpf_params *params) 1436{ 1437 struct ieee80211com *ic = ni->ni_ic; 1438 struct ifnet *ifp = ic->ic_ifp; 1439 struct bwi_softc *sc = ifp->if_softc; 1440 /* XXX wme? */ 1441 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1442 int idx, error; 1443 1444 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1445 ieee80211_free_node(ni); 1446 m_freem(m); 1447 return ENETDOWN; 1448 } 1449 1450 BWI_LOCK(sc); 1451 idx = tbd->tbd_idx; 1452 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx)); 1453 if (params == NULL) { 1454 /* 1455 * Legacy path; interpret frame contents to decide 1456 * precisely how to send the frame. 1457 */ 1458 error = bwi_encap(sc, idx, m, ni); 1459 } else { 1460 /* 1461 * Caller supplied explicit parameters to use in 1462 * sending the frame. 1463 */ 1464 error = bwi_encap_raw(sc, idx, m, ni, params); 1465 } 1466 if (error == 0) { 1467 ifp->if_opackets++; 1468 if (++tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) 1469 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1470 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC; 1471 sc->sc_tx_timer = 5; 1472 } else { 1473 /* NB: m is reclaimed on encap failure */ 1474 ieee80211_free_node(ni); 1475 ifp->if_oerrors++; 1476 } 1477 BWI_UNLOCK(sc); 1478 return error; 1479} 1480 1481static void 1482bwi_watchdog(void *arg) 1483{ 1484 struct bwi_softc *sc; 1485 struct ifnet *ifp; 1486 1487 sc = arg; 1488 ifp = sc->sc_ifp; 1489 BWI_ASSERT_LOCKED(sc); 1490 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) { 1491 if_printf(ifp, "watchdog timeout\n"); 1492 ifp->if_oerrors++; 1493 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1494 } 1495 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1496} 1497 1498static void 1499bwi_stop(struct bwi_softc *sc, int statechg) 1500{ 1501 BWI_LOCK(sc); 1502 bwi_stop_locked(sc, statechg); 1503 BWI_UNLOCK(sc); 1504} 1505 1506static void 1507bwi_stop_locked(struct bwi_softc *sc, int statechg) 1508{ 1509 struct ifnet *ifp = sc->sc_ifp; 1510 struct bwi_mac *mac; 1511 int i, error, pwr_off = 0; 1512 1513 BWI_ASSERT_LOCKED(sc); 1514 1515 callout_stop(&sc->sc_calib_ch); 1516 callout_stop(&sc->sc_led_blink_ch); 1517 sc->sc_led_blinking = 0; 1518 sc->sc_flags |= BWI_F_STOP; 1519 1520 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1521 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1522 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1523 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1524 1525 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1526 CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1527 bwi_mac_stop(mac); 1528 } 1529 1530 for (i = 0; i < sc->sc_nmac; ++i) { 1531 struct bwi_regwin *old_rw; 1532 1533 mac = &sc->sc_mac[i]; 1534 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0) 1535 continue; 1536 1537 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw); 1538 if (error) 1539 continue; 1540 1541 bwi_mac_shutdown(mac); 1542 pwr_off = 1; 1543 1544 bwi_regwin_switch(sc, old_rw, NULL); 1545 } 1546 1547 if (pwr_off) 1548 bwi_bbp_power_off(sc); 1549 1550 sc->sc_tx_timer = 0; 1551 callout_stop(&sc->sc_watchdog_timer); 1552 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1553} 1554 1555void 1556bwi_intr(void *xsc) 1557{ 1558 struct bwi_softc *sc = xsc; 1559 struct ifnet *ifp = sc->sc_ifp; 1560 struct bwi_mac *mac; 1561 uint32_t intr_status; 1562 uint32_t txrx_intr_status[BWI_TXRX_NRING]; 1563 int i, txrx_error, tx = 0, rx_data = -1; 1564 1565 BWI_LOCK(sc); 1566 1567#if !defined(__HAIKU__) 1568 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1569 (sc->sc_flags & BWI_F_STOP)) { 1570 BWI_UNLOCK(sc); 1571 return; 1572 } 1573 /* 1574 * Get interrupt status 1575 */ 1576 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); 1577 if (intr_status == 0xffffffff) { /* Not for us */ 1578 BWI_UNLOCK(sc); 1579 return; 1580 } 1581 1582 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status); 1583 1584 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1585 if (intr_status == 0) { /* Nothing is interesting */ 1586 BWI_UNLOCK(sc); 1587 return; 1588 } 1589#else 1590 intr_status = atomic_get((int32 *)&sc->sc_intr_status); 1591#endif 1592 1593 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1594 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1595 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1596 1597 txrx_error = 0; 1598 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr"); 1599 for (i = 0; i < BWI_TXRX_NRING; ++i) { 1600 uint32_t mask; 1601 1602 if (BWI_TXRX_IS_RX(i)) 1603 mask = BWI_TXRX_RX_INTRS; 1604 else 1605 mask = BWI_TXRX_TX_INTRS; 1606 1607 txrx_intr_status[i] = 1608 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask; 1609 1610 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x", 1611 i, txrx_intr_status[i]); 1612 1613 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) { 1614 if_printf(ifp, 1615 "%s: intr fatal TX/RX (%d) error 0x%08x\n", 1616 __func__, i, txrx_intr_status[i]); 1617 txrx_error = 1; 1618 } 1619 } 1620 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", ""); 1621 1622 /* 1623 * Acknowledge interrupt 1624 */ 1625 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status); 1626 1627 for (i = 0; i < BWI_TXRX_NRING; ++i) 1628 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]); 1629 1630#if !defined(__HAIKU__) 1631 /* Disable all interrupts */ 1632 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1633#endif 1634 1635 /* 1636 * http://bcm-specs.sipsolutions.net/Interrupts 1637 * Says for this bit (0x800): 1638 * "Fatal Error 1639 * 1640 * We got this one while testing things when by accident the 1641 * template ram wasn't set to big endian when it should have 1642 * been after writing the initial values. It keeps on being 1643 * triggered, the only way to stop it seems to shut down the 1644 * chip." 1645 * 1646 * Suggesting that we should never get it and if we do we're not 1647 * feeding TX packets into the MAC correctly if we do... Apparently, 1648 * it is valid only on mac version 5 and higher, but I couldn't 1649 * find a reference for that... Since I see them from time to time 1650 * on my card, this suggests an error in the tx path still... 1651 */ 1652 if (intr_status & BWI_INTR_PHY_TXERR) { 1653 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) { 1654 if_printf(ifp, "%s: intr PHY TX error\n", __func__); 1655 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1656 BWI_UNLOCK(sc); 1657 return; 1658 } 1659 } 1660 1661 if (txrx_error) { 1662 /* TODO: reset device */ 1663 } 1664 1665 if (intr_status & BWI_INTR_TBTT) 1666 bwi_mac_config_ps(mac); 1667 1668 if (intr_status & BWI_INTR_EO_ATIM) 1669 if_printf(ifp, "EO_ATIM\n"); 1670 1671 if (intr_status & BWI_INTR_PMQ) { 1672 for (;;) { 1673 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0) 1674 break; 1675 } 1676 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2); 1677 } 1678 1679 if (intr_status & BWI_INTR_NOISE) 1680 if_printf(ifp, "intr noise\n"); 1681 1682 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) { 1683 rx_data = sc->sc_rxeof(sc); 1684 if (sc->sc_flags & BWI_F_STOP) { 1685 BWI_UNLOCK(sc); 1686 return; 1687 } 1688 } 1689 1690 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) { 1691 sc->sc_txeof_status(sc); 1692 tx = 1; 1693 } 1694 1695 if (intr_status & BWI_INTR_TX_DONE) { 1696 bwi_txeof(sc); 1697 tx = 1; 1698 } 1699 1700 /* Re-enable interrupts */ 1701 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1702 1703 if (sc->sc_blink_led != NULL && sc->sc_led_blink) { 1704 int evt = BWI_LED_EVENT_NONE; 1705 1706 if (tx && rx_data > 0) { 1707 if (sc->sc_rx_rate > sc->sc_tx_rate) 1708 evt = BWI_LED_EVENT_RX; 1709 else 1710 evt = BWI_LED_EVENT_TX; 1711 } else if (tx) { 1712 evt = BWI_LED_EVENT_TX; 1713 } else if (rx_data > 0) { 1714 evt = BWI_LED_EVENT_RX; 1715 } else if (rx_data == 0) { 1716 evt = BWI_LED_EVENT_POLL; 1717 } 1718 1719 if (evt != BWI_LED_EVENT_NONE) 1720 bwi_led_event(sc, evt); 1721 } 1722 1723 BWI_UNLOCK(sc); 1724} 1725 1726static void 1727bwi_scan_start(struct ieee80211com *ic) 1728{ 1729 struct bwi_softc *sc = ic->ic_ifp->if_softc; 1730 1731 BWI_LOCK(sc); 1732 /* Enable MAC beacon promiscuity */ 1733 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1734 BWI_UNLOCK(sc); 1735} 1736 1737static void 1738bwi_set_channel(struct ieee80211com *ic) 1739{ 1740 struct bwi_softc *sc = ic->ic_ifp->if_softc; 1741 struct ieee80211_channel *c = ic->ic_curchan; 1742 struct bwi_mac *mac; 1743 1744 BWI_LOCK(sc); 1745 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1746 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1747 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1748 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0); 1749 1750 sc->sc_rates = ieee80211_get_ratetable(c); 1751 1752 /* 1753 * Setup radio tap channel freq and flags 1754 */ 1755 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 1756 htole16(c->ic_freq); 1757 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 1758 htole16(c->ic_flags & 0xffff); 1759 1760 BWI_UNLOCK(sc); 1761} 1762 1763static void 1764bwi_scan_end(struct ieee80211com *ic) 1765{ 1766 struct bwi_softc *sc = ic->ic_ifp->if_softc; 1767 1768 BWI_LOCK(sc); 1769 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1770 BWI_UNLOCK(sc); 1771} 1772 1773static int 1774bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1775{ 1776 struct bwi_vap *bvp = BWI_VAP(vap); 1777 struct ieee80211com *ic= vap->iv_ic; 1778 struct ifnet *ifp = ic->ic_ifp; 1779 enum ieee80211_state ostate = vap->iv_state; 1780 struct bwi_softc *sc = ifp->if_softc; 1781 struct bwi_mac *mac; 1782 int error; 1783 1784 BWI_LOCK(sc); 1785 1786 callout_stop(&sc->sc_calib_ch); 1787 1788 if (nstate == IEEE80211_S_INIT) 1789 sc->sc_txpwrcb_type = BWI_TXPWR_INIT; 1790 1791 bwi_led_newstate(sc, nstate); 1792 1793 error = bvp->bv_newstate(vap, nstate, arg); 1794 if (error != 0) 1795 goto back; 1796 1797 /* 1798 * Clear the BSSID when we stop a STA 1799 */ 1800 if (vap->iv_opmode == IEEE80211_M_STA) { 1801 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) { 1802 /* 1803 * Clear out the BSSID. If we reassociate to 1804 * the same AP, this will reinialize things 1805 * correctly... 1806 */ 1807 if (ic->ic_opmode == IEEE80211_M_STA && 1808 !(sc->sc_flags & BWI_F_STOP)) 1809 bwi_set_bssid(sc, bwi_zero_addr); 1810 } 1811 } 1812 1813 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1814 /* Nothing to do */ 1815 } else if (nstate == IEEE80211_S_RUN) { 1816 bwi_set_bssid(sc, vap->iv_bss->ni_bssid); 1817 1818 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1819 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1820 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1821 1822 /* Initial TX power calibration */ 1823 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT); 1824#ifdef notyet 1825 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE; 1826#else 1827 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 1828#endif 1829 1830 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc); 1831 } 1832back: 1833 BWI_UNLOCK(sc); 1834 1835 return error; 1836} 1837 1838static int 1839bwi_media_change(struct ifnet *ifp) 1840{ 1841 int error = ieee80211_media_change(ifp); 1842 /* NB: only the fixed rate can change and that doesn't need a reset */ 1843 return (error == ENETRESET ? 0 : error); 1844} 1845 1846static int 1847bwi_dma_alloc(struct bwi_softc *sc) 1848{ 1849 int error, i, has_txstats; 1850 bus_addr_t lowaddr = 0; 1851 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0; 1852 uint32_t txrx_ctrl_step = 0; 1853 1854 has_txstats = 0; 1855 for (i = 0; i < sc->sc_nmac; ++i) { 1856 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) { 1857 has_txstats = 1; 1858 break; 1859 } 1860 } 1861 1862 switch (sc->sc_bus_space) { 1863 case BWI_BUS_SPACE_30BIT: 1864 case BWI_BUS_SPACE_32BIT: 1865 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT) 1866 lowaddr = BWI_BUS_SPACE_MAXADDR; 1867 else 1868 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1869 desc_sz = sizeof(struct bwi_desc32); 1870 txrx_ctrl_step = 0x20; 1871 1872 sc->sc_init_tx_ring = bwi_init_tx_ring32; 1873 sc->sc_free_tx_ring = bwi_free_tx_ring32; 1874 sc->sc_init_rx_ring = bwi_init_rx_ring32; 1875 sc->sc_free_rx_ring = bwi_free_rx_ring32; 1876 sc->sc_setup_rxdesc = bwi_setup_rx_desc32; 1877 sc->sc_setup_txdesc = bwi_setup_tx_desc32; 1878 sc->sc_rxeof = bwi_rxeof32; 1879 sc->sc_start_tx = bwi_start_tx32; 1880 if (has_txstats) { 1881 sc->sc_init_txstats = bwi_init_txstats32; 1882 sc->sc_free_txstats = bwi_free_txstats32; 1883 sc->sc_txeof_status = bwi_txeof_status32; 1884 } 1885 break; 1886 1887 case BWI_BUS_SPACE_64BIT: 1888 lowaddr = BUS_SPACE_MAXADDR; /* XXX */ 1889 desc_sz = sizeof(struct bwi_desc64); 1890 txrx_ctrl_step = 0x40; 1891 1892 sc->sc_init_tx_ring = bwi_init_tx_ring64; 1893 sc->sc_free_tx_ring = bwi_free_tx_ring64; 1894 sc->sc_init_rx_ring = bwi_init_rx_ring64; 1895 sc->sc_free_rx_ring = bwi_free_rx_ring64; 1896 sc->sc_setup_rxdesc = bwi_setup_rx_desc64; 1897 sc->sc_setup_txdesc = bwi_setup_tx_desc64; 1898 sc->sc_rxeof = bwi_rxeof64; 1899 sc->sc_start_tx = bwi_start_tx64; 1900 if (has_txstats) { 1901 sc->sc_init_txstats = bwi_init_txstats64; 1902 sc->sc_free_txstats = bwi_free_txstats64; 1903 sc->sc_txeof_status = bwi_txeof_status64; 1904 } 1905 break; 1906 } 1907 1908 KASSERT(lowaddr != 0, ("lowaddr zero")); 1909 KASSERT(desc_sz != 0, ("desc_sz zero")); 1910 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero")); 1911 1912 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN); 1913 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN); 1914 1915 /* 1916 * Create top level DMA tag 1917 */ 1918 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1919 BWI_ALIGN, 0, /* alignment, bounds */ 1920 lowaddr, /* lowaddr */ 1921 BUS_SPACE_MAXADDR, /* highaddr */ 1922 NULL, NULL, /* filter, filterarg */ 1923 MAXBSIZE, /* maxsize */ 1924 BUS_SPACE_UNRESTRICTED, /* nsegments */ 1925 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1926 BUS_DMA_ALLOCNOW, /* flags */ 1927 NULL, NULL, /* lockfunc, lockarg */ 1928 &sc->sc_parent_dtag); 1929 if (error) { 1930 device_printf(sc->sc_dev, "can't create parent DMA tag\n"); 1931 return error; 1932 } 1933 1934#define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step) 1935 1936 /* 1937 * Create TX ring DMA stuffs 1938 */ 1939 error = bus_dma_tag_create(sc->sc_parent_dtag, 1940 BWI_RING_ALIGN, 0, 1941 BUS_SPACE_MAXADDR, 1942 BUS_SPACE_MAXADDR, 1943 NULL, NULL, 1944 tx_ring_sz, 1945 1, 1946 BUS_SPACE_MAXSIZE_32BIT, 1947 BUS_DMA_ALLOCNOW, 1948 NULL, NULL, 1949 &sc->sc_txring_dtag); 1950 if (error) { 1951 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n"); 1952 return error; 1953 } 1954 1955 for (i = 0; i < BWI_TX_NRING; ++i) { 1956 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag, 1957 &sc->sc_tx_rdata[i], tx_ring_sz, 1958 TXRX_CTRL(i)); 1959 if (error) { 1960 device_printf(sc->sc_dev, "%dth TX ring " 1961 "DMA alloc failed\n", i); 1962 return error; 1963 } 1964 } 1965 1966 /* 1967 * Create RX ring DMA stuffs 1968 */ 1969 error = bus_dma_tag_create(sc->sc_parent_dtag, 1970 BWI_RING_ALIGN, 0, 1971 BUS_SPACE_MAXADDR, 1972 BUS_SPACE_MAXADDR, 1973 NULL, NULL, 1974 rx_ring_sz, 1975 1, 1976 BUS_SPACE_MAXSIZE_32BIT, 1977 BUS_DMA_ALLOCNOW, 1978 NULL, NULL, 1979 &sc->sc_rxring_dtag); 1980 if (error) { 1981 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n"); 1982 return error; 1983 } 1984 1985 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata, 1986 rx_ring_sz, TXRX_CTRL(0)); 1987 if (error) { 1988 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n"); 1989 return error; 1990 } 1991 1992 if (has_txstats) { 1993 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz); 1994 if (error) { 1995 device_printf(sc->sc_dev, 1996 "TX stats DMA alloc failed\n"); 1997 return error; 1998 } 1999 } 2000 2001#undef TXRX_CTRL 2002 2003 return bwi_dma_mbuf_create(sc); 2004} 2005 2006static void 2007bwi_dma_free(struct bwi_softc *sc) 2008{ 2009 if (sc->sc_txring_dtag != NULL) { 2010 int i; 2011 2012 for (i = 0; i < BWI_TX_NRING; ++i) { 2013 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i]; 2014 2015 if (rd->rdata_desc != NULL) { 2016 bus_dmamap_unload(sc->sc_txring_dtag, 2017 rd->rdata_dmap); 2018 bus_dmamem_free(sc->sc_txring_dtag, 2019 rd->rdata_desc, 2020 rd->rdata_dmap); 2021 } 2022 } 2023 bus_dma_tag_destroy(sc->sc_txring_dtag); 2024 } 2025 2026 if (sc->sc_rxring_dtag != NULL) { 2027 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2028 2029 if (rd->rdata_desc != NULL) { 2030 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap); 2031 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc, 2032 rd->rdata_dmap); 2033 } 2034 bus_dma_tag_destroy(sc->sc_rxring_dtag); 2035 } 2036 2037 bwi_dma_txstats_free(sc); 2038 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1); 2039 2040 if (sc->sc_parent_dtag != NULL) 2041 bus_dma_tag_destroy(sc->sc_parent_dtag); 2042} 2043 2044static int 2045bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag, 2046 struct bwi_ring_data *rd, bus_size_t size, 2047 uint32_t txrx_ctrl) 2048{ 2049 int error; 2050 2051 error = bus_dmamem_alloc(dtag, &rd->rdata_desc, 2052 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2053 &rd->rdata_dmap); 2054 if (error) { 2055 device_printf(sc->sc_dev, "can't allocate DMA mem\n"); 2056 return error; 2057 } 2058 2059 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size, 2060 bwi_dma_ring_addr, &rd->rdata_paddr, 2061 BUS_DMA_NOWAIT); 2062 if (error) { 2063 device_printf(sc->sc_dev, "can't load DMA mem\n"); 2064 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap); 2065 rd->rdata_desc = NULL; 2066 return error; 2067 } 2068 2069 rd->rdata_txrx_ctrl = txrx_ctrl; 2070 return 0; 2071} 2072 2073static int 2074bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base, 2075 bus_size_t desc_sz) 2076{ 2077 struct bwi_txstats_data *st; 2078 bus_size_t dma_size; 2079 int error; 2080 2081 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO); 2082 if (st == NULL) { 2083 device_printf(sc->sc_dev, "can't allocate txstats data\n"); 2084 return ENOMEM; 2085 } 2086 sc->sc_txstats = st; 2087 2088 /* 2089 * Create TX stats descriptor DMA stuffs 2090 */ 2091 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN); 2092 2093 error = bus_dma_tag_create(sc->sc_parent_dtag, 2094 BWI_RING_ALIGN, 2095 0, 2096 BUS_SPACE_MAXADDR, 2097 BUS_SPACE_MAXADDR, 2098 NULL, NULL, 2099 dma_size, 2100 1, 2101 BUS_SPACE_MAXSIZE_32BIT, 2102 BUS_DMA_ALLOCNOW, 2103 NULL, NULL, 2104 &st->stats_ring_dtag); 2105 if (error) { 2106 device_printf(sc->sc_dev, "can't create txstats ring " 2107 "DMA tag\n"); 2108 return error; 2109 } 2110 2111 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring, 2112 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2113 &st->stats_ring_dmap); 2114 if (error) { 2115 device_printf(sc->sc_dev, "can't allocate txstats ring " 2116 "DMA mem\n"); 2117 bus_dma_tag_destroy(st->stats_ring_dtag); 2118 st->stats_ring_dtag = NULL; 2119 return error; 2120 } 2121 2122 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap, 2123 st->stats_ring, dma_size, 2124 bwi_dma_ring_addr, &st->stats_ring_paddr, 2125 BUS_DMA_NOWAIT); 2126 if (error) { 2127 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n"); 2128 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2129 st->stats_ring_dmap); 2130 bus_dma_tag_destroy(st->stats_ring_dtag); 2131 st->stats_ring_dtag = NULL; 2132 return error; 2133 } 2134 2135 /* 2136 * Create TX stats DMA stuffs 2137 */ 2138 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC, 2139 BWI_ALIGN); 2140 2141 error = bus_dma_tag_create(sc->sc_parent_dtag, 2142 BWI_ALIGN, 2143 0, 2144 BUS_SPACE_MAXADDR, 2145 BUS_SPACE_MAXADDR, 2146 NULL, NULL, 2147 dma_size, 2148 1, 2149 BUS_SPACE_MAXSIZE_32BIT, 2150 BUS_DMA_ALLOCNOW, 2151 NULL, NULL, 2152 &st->stats_dtag); 2153 if (error) { 2154 device_printf(sc->sc_dev, "can't create txstats DMA tag\n"); 2155 return error; 2156 } 2157 2158 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats, 2159 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2160 &st->stats_dmap); 2161 if (error) { 2162 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n"); 2163 bus_dma_tag_destroy(st->stats_dtag); 2164 st->stats_dtag = NULL; 2165 return error; 2166 } 2167 2168 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats, 2169 dma_size, bwi_dma_ring_addr, &st->stats_paddr, 2170 BUS_DMA_NOWAIT); 2171 if (error) { 2172 device_printf(sc->sc_dev, "can't load txstats DMA mem\n"); 2173 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2174 bus_dma_tag_destroy(st->stats_dtag); 2175 st->stats_dtag = NULL; 2176 return error; 2177 } 2178 2179 st->stats_ctrl_base = ctrl_base; 2180 return 0; 2181} 2182 2183static void 2184bwi_dma_txstats_free(struct bwi_softc *sc) 2185{ 2186 struct bwi_txstats_data *st; 2187 2188 if (sc->sc_txstats == NULL) 2189 return; 2190 st = sc->sc_txstats; 2191 2192 if (st->stats_ring_dtag != NULL) { 2193 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap); 2194 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2195 st->stats_ring_dmap); 2196 bus_dma_tag_destroy(st->stats_ring_dtag); 2197 } 2198 2199 if (st->stats_dtag != NULL) { 2200 bus_dmamap_unload(st->stats_dtag, st->stats_dmap); 2201 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2202 bus_dma_tag_destroy(st->stats_dtag); 2203 } 2204 2205 free(st, M_DEVBUF); 2206} 2207 2208static void 2209bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 2210{ 2211 KASSERT(nseg == 1, ("too many segments\n")); 2212 *((bus_addr_t *)arg) = seg->ds_addr; 2213} 2214 2215static int 2216bwi_dma_mbuf_create(struct bwi_softc *sc) 2217{ 2218 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2219 int i, j, k, ntx, error; 2220 2221 /* 2222 * Create TX/RX mbuf DMA tag 2223 */ 2224 error = bus_dma_tag_create(sc->sc_parent_dtag, 2225 1, 2226 0, 2227 BUS_SPACE_MAXADDR, 2228 BUS_SPACE_MAXADDR, 2229 NULL, NULL, 2230 MCLBYTES, 2231 1, 2232 BUS_SPACE_MAXSIZE_32BIT, 2233 BUS_DMA_ALLOCNOW, 2234 NULL, NULL, 2235 &sc->sc_buf_dtag); 2236 if (error) { 2237 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 2238 return error; 2239 } 2240 2241 ntx = 0; 2242 2243 /* 2244 * Create TX mbuf DMA map 2245 */ 2246 for (i = 0; i < BWI_TX_NRING; ++i) { 2247 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2248 2249 for (j = 0; j < BWI_TX_NDESC; ++j) { 2250 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2251 &tbd->tbd_buf[j].tb_dmap); 2252 if (error) { 2253 device_printf(sc->sc_dev, "can't create " 2254 "%dth tbd, %dth DMA map\n", i, j); 2255 2256 ntx = i; 2257 for (k = 0; k < j; ++k) { 2258 bus_dmamap_destroy(sc->sc_buf_dtag, 2259 tbd->tbd_buf[k].tb_dmap); 2260 } 2261 goto fail; 2262 } 2263 } 2264 } 2265 ntx = BWI_TX_NRING; 2266 2267 /* 2268 * Create RX mbuf DMA map and a spare DMA map 2269 */ 2270 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2271 &rbd->rbd_tmp_dmap); 2272 if (error) { 2273 device_printf(sc->sc_dev, 2274 "can't create spare RX buf DMA map\n"); 2275 goto fail; 2276 } 2277 2278 for (j = 0; j < BWI_RX_NDESC; ++j) { 2279 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2280 &rbd->rbd_buf[j].rb_dmap); 2281 if (error) { 2282 device_printf(sc->sc_dev, "can't create %dth " 2283 "RX buf DMA map\n", j); 2284 2285 for (k = 0; k < j; ++k) { 2286 bus_dmamap_destroy(sc->sc_buf_dtag, 2287 rbd->rbd_buf[j].rb_dmap); 2288 } 2289 bus_dmamap_destroy(sc->sc_buf_dtag, 2290 rbd->rbd_tmp_dmap); 2291 goto fail; 2292 } 2293 } 2294 2295 return 0; 2296fail: 2297 bwi_dma_mbuf_destroy(sc, ntx, 0); 2298 return error; 2299} 2300 2301static void 2302bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx) 2303{ 2304 int i, j; 2305 2306 if (sc->sc_buf_dtag == NULL) 2307 return; 2308 2309 for (i = 0; i < ntx; ++i) { 2310 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2311 2312 for (j = 0; j < BWI_TX_NDESC; ++j) { 2313 struct bwi_txbuf *tb = &tbd->tbd_buf[j]; 2314 2315 if (tb->tb_mbuf != NULL) { 2316 bus_dmamap_unload(sc->sc_buf_dtag, 2317 tb->tb_dmap); 2318 m_freem(tb->tb_mbuf); 2319 } 2320 if (tb->tb_ni != NULL) 2321 ieee80211_free_node(tb->tb_ni); 2322 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap); 2323 } 2324 } 2325 2326 if (nrx) { 2327 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2328 2329 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap); 2330 for (j = 0; j < BWI_RX_NDESC; ++j) { 2331 struct bwi_rxbuf *rb = &rbd->rbd_buf[j]; 2332 2333 if (rb->rb_mbuf != NULL) { 2334 bus_dmamap_unload(sc->sc_buf_dtag, 2335 rb->rb_dmap); 2336 m_freem(rb->rb_mbuf); 2337 } 2338 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap); 2339 } 2340 } 2341 2342 bus_dma_tag_destroy(sc->sc_buf_dtag); 2343 sc->sc_buf_dtag = NULL; 2344} 2345 2346static void 2347bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs) 2348{ 2349 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs); 2350} 2351 2352static void 2353bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs) 2354{ 2355 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs); 2356} 2357 2358static int 2359bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx) 2360{ 2361 struct bwi_ring_data *rd; 2362 struct bwi_txbuf_data *tbd; 2363 uint32_t val, addr_hi, addr_lo; 2364 2365 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2366 rd = &sc->sc_tx_rdata[ring_idx]; 2367 tbd = &sc->sc_tx_bdata[ring_idx]; 2368 2369 tbd->tbd_idx = 0; 2370 tbd->tbd_used = 0; 2371 2372 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC); 2373 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 2374 BUS_DMASYNC_PREWRITE); 2375 2376 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2377 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2378 2379 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2380 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2381 BWI_TXRX32_RINGINFO_FUNC_MASK); 2382 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val); 2383 2384 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2385 BWI_TXRX32_CTRL_ENABLE; 2386 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val); 2387 2388 return 0; 2389} 2390 2391static void 2392bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base, 2393 bus_addr_t paddr, int hdr_size, int ndesc) 2394{ 2395 uint32_t val, addr_hi, addr_lo; 2396 2397 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2398 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2399 2400 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2401 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2402 BWI_TXRX32_RINGINFO_FUNC_MASK); 2403 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val); 2404 2405 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) | 2406 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2407 BWI_TXRX32_CTRL_ENABLE; 2408 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val); 2409 2410 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 2411 (ndesc - 1) * sizeof(struct bwi_desc32)); 2412} 2413 2414static int 2415bwi_init_rx_ring32(struct bwi_softc *sc) 2416{ 2417 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2418 int i, error; 2419 2420 sc->sc_rx_bdata.rbd_idx = 0; 2421 2422 for (i = 0; i < BWI_RX_NDESC; ++i) { 2423 error = bwi_newbuf(sc, i, 1); 2424 if (error) { 2425 device_printf(sc->sc_dev, 2426 "can't allocate %dth RX buffer\n", i); 2427 return error; 2428 } 2429 } 2430 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2431 BUS_DMASYNC_PREWRITE); 2432 2433 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr, 2434 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC); 2435 return 0; 2436} 2437 2438static int 2439bwi_init_txstats32(struct bwi_softc *sc) 2440{ 2441 struct bwi_txstats_data *st = sc->sc_txstats; 2442 bus_addr_t stats_paddr; 2443 int i; 2444 2445 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats)); 2446 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE); 2447 2448 st->stats_idx = 0; 2449 2450 stats_paddr = st->stats_paddr; 2451 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) { 2452 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i, 2453 stats_paddr, sizeof(struct bwi_txstats), 0); 2454 stats_paddr += sizeof(struct bwi_txstats); 2455 } 2456 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap, 2457 BUS_DMASYNC_PREWRITE); 2458 2459 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base, 2460 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC); 2461 return 0; 2462} 2463 2464static void 2465bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2466 int buf_len) 2467{ 2468 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2469 2470 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2471 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx, 2472 paddr, buf_len, 0); 2473} 2474 2475static void 2476bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd, 2477 int buf_idx, bus_addr_t paddr, int buf_len) 2478{ 2479 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 2480 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx, 2481 paddr, buf_len, 1); 2482} 2483 2484static int 2485bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx) 2486{ 2487 /* TODO:64 */ 2488 return EOPNOTSUPP; 2489} 2490 2491static int 2492bwi_init_rx_ring64(struct bwi_softc *sc) 2493{ 2494 /* TODO:64 */ 2495 return EOPNOTSUPP; 2496} 2497 2498static int 2499bwi_init_txstats64(struct bwi_softc *sc) 2500{ 2501 /* TODO:64 */ 2502 return EOPNOTSUPP; 2503} 2504 2505static void 2506bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2507 int buf_len) 2508{ 2509 /* TODO:64 */ 2510} 2511 2512static void 2513bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd, 2514 int buf_idx, bus_addr_t paddr, int buf_len) 2515{ 2516 /* TODO:64 */ 2517} 2518 2519static void 2520bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, 2521 bus_size_t mapsz __unused, int error) 2522{ 2523 if (!error) { 2524 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 2525 *((bus_addr_t *)arg) = seg->ds_addr; 2526 } 2527} 2528 2529static int 2530bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init) 2531{ 2532 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2533 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx]; 2534 struct bwi_rxbuf_hdr *hdr; 2535 bus_dmamap_t map; 2536 bus_addr_t paddr; 2537 struct mbuf *m; 2538 int error; 2539 2540 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2541 2542 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2543 if (m == NULL) { 2544 error = ENOBUFS; 2545 2546 /* 2547 * If the NIC is up and running, we need to: 2548 * - Clear RX buffer's header. 2549 * - Restore RX descriptor settings. 2550 */ 2551 if (init) 2552 return error; 2553 else 2554 goto back; 2555 } 2556 m->m_len = m->m_pkthdr.len = MCLBYTES; 2557 2558 /* 2559 * Try to load RX buf into temporary DMA map 2560 */ 2561 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m, 2562 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 2563 if (error) { 2564 m_freem(m); 2565 2566 /* 2567 * See the comment above 2568 */ 2569 if (init) 2570 return error; 2571 else 2572 goto back; 2573 } 2574 2575 if (!init) 2576 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap); 2577 rxbuf->rb_mbuf = m; 2578 rxbuf->rb_paddr = paddr; 2579 2580 /* 2581 * Swap RX buf's DMA map with the loaded temporary one 2582 */ 2583 map = rxbuf->rb_dmap; 2584 rxbuf->rb_dmap = rbd->rbd_tmp_dmap; 2585 rbd->rbd_tmp_dmap = map; 2586 2587back: 2588 /* 2589 * Clear RX buf header 2590 */ 2591 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *); 2592 bzero(hdr, sizeof(*hdr)); 2593 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE); 2594 2595 /* 2596 * Setup RX buf descriptor 2597 */ 2598 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr, 2599 rxbuf->rb_mbuf->m_len - sizeof(*hdr)); 2600 return error; 2601} 2602 2603static void 2604bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs, 2605 const uint8_t *addr) 2606{ 2607 int i; 2608 2609 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL, 2610 BWI_ADDR_FILTER_CTRL_SET | addr_ofs); 2611 2612 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) { 2613 uint16_t addr_val; 2614 2615 addr_val = (uint16_t)addr[i * 2] | 2616 (((uint16_t)addr[(i * 2) + 1]) << 8); 2617 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val); 2618 } 2619} 2620 2621static int 2622bwi_rxeof(struct bwi_softc *sc, int end_idx) 2623{ 2624 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2625 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2626 struct ifnet *ifp = sc->sc_ifp; 2627 struct ieee80211com *ic = ifp->if_l2com; 2628 int idx, rx_data = 0; 2629 2630 idx = rbd->rbd_idx; 2631 while (idx != end_idx) { 2632 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx]; 2633 struct bwi_rxbuf_hdr *hdr; 2634 struct ieee80211_frame_min *wh; 2635 struct ieee80211_node *ni; 2636 struct mbuf *m; 2637 uint32_t plcp; 2638 uint16_t flags2; 2639 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate; 2640 2641 m = rb->rb_mbuf; 2642 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap, 2643 BUS_DMASYNC_POSTREAD); 2644 2645 if (bwi_newbuf(sc, idx, 0)) { 2646 ifp->if_ierrors++; 2647 goto next; 2648 } 2649 2650 hdr = mtod(m, struct bwi_rxbuf_hdr *); 2651 flags2 = le16toh(hdr->rxh_flags2); 2652 2653 hdr_extra = 0; 2654 if (flags2 & BWI_RXH_F2_TYPE2FRAME) 2655 hdr_extra = 2; 2656 wh_ofs = hdr_extra + 6; /* XXX magic number */ 2657 2658 buflen = le16toh(hdr->rxh_buflen); 2659 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) { 2660 if_printf(ifp, "%s: zero length data, hdr_extra %d\n", 2661 __func__, hdr_extra); 2662 ifp->if_ierrors++; 2663 m_freem(m); 2664 goto next; 2665 } 2666 2667 bcopy((uint8_t *)(hdr + 1) + hdr_extra, &plcp, sizeof(plcp)); 2668 rssi = bwi_calc_rssi(sc, hdr); 2669 noise = bwi_calc_noise(sc); 2670 2671 m->m_pkthdr.rcvif = ifp; 2672 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr); 2673 m_adj(m, sizeof(*hdr) + wh_ofs); 2674 2675 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM) 2676 rate = bwi_plcp2rate(plcp, IEEE80211_T_OFDM); 2677 else 2678 rate = bwi_plcp2rate(plcp, IEEE80211_T_CCK); 2679 2680 /* RX radio tap */ 2681 if (ieee80211_radiotap_active(ic)) 2682 bwi_rx_radiotap(sc, m, hdr, &plcp, rate, rssi, noise); 2683 2684 m_adj(m, -IEEE80211_CRC_LEN); 2685 2686 BWI_UNLOCK(sc); 2687 2688 wh = mtod(m, struct ieee80211_frame_min *); 2689 ni = ieee80211_find_rxnode(ic, wh); 2690 if (ni != NULL) { 2691 type = ieee80211_input(ni, m, rssi - noise, noise); 2692 ieee80211_free_node(ni); 2693 } else 2694 type = ieee80211_input_all(ic, m, rssi - noise, noise); 2695 if (type == IEEE80211_FC0_TYPE_DATA) { 2696 rx_data = 1; 2697 sc->sc_rx_rate = rate; 2698 } 2699 2700 BWI_LOCK(sc); 2701next: 2702 idx = (idx + 1) % BWI_RX_NDESC; 2703 2704 if (sc->sc_flags & BWI_F_STOP) { 2705 /* 2706 * Take the fast lane, don't do 2707 * any damage to softc 2708 */ 2709 return -1; 2710 } 2711 } 2712 2713 rbd->rbd_idx = idx; 2714 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2715 BUS_DMASYNC_PREWRITE); 2716 2717 return rx_data; 2718} 2719 2720static int 2721bwi_rxeof32(struct bwi_softc *sc) 2722{ 2723 uint32_t val, rx_ctrl; 2724 int end_idx, rx_data; 2725 2726 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl; 2727 2728 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2729 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 2730 sizeof(struct bwi_desc32); 2731 2732 rx_data = bwi_rxeof(sc, end_idx); 2733 if (rx_data >= 0) { 2734 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX, 2735 end_idx * sizeof(struct bwi_desc32)); 2736 } 2737 return rx_data; 2738} 2739 2740static int 2741bwi_rxeof64(struct bwi_softc *sc) 2742{ 2743 /* TODO:64 */ 2744 return 0; 2745} 2746 2747static void 2748bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl) 2749{ 2750 int i; 2751 2752 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0); 2753 2754#define NRETRY 10 2755 2756 for (i = 0; i < NRETRY; ++i) { 2757 uint32_t status; 2758 2759 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2760 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) == 2761 BWI_RX32_STATUS_STATE_DISABLED) 2762 break; 2763 2764 DELAY(1000); 2765 } 2766 if (i == NRETRY) 2767 device_printf(sc->sc_dev, "reset rx ring timedout\n"); 2768 2769#undef NRETRY 2770 2771 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0); 2772} 2773 2774static void 2775bwi_free_txstats32(struct bwi_softc *sc) 2776{ 2777 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base); 2778} 2779 2780static void 2781bwi_free_rx_ring32(struct bwi_softc *sc) 2782{ 2783 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2784 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2785 int i; 2786 2787 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl); 2788 2789 for (i = 0; i < BWI_RX_NDESC; ++i) { 2790 struct bwi_rxbuf *rb = &rbd->rbd_buf[i]; 2791 2792 if (rb->rb_mbuf != NULL) { 2793 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap); 2794 m_freem(rb->rb_mbuf); 2795 rb->rb_mbuf = NULL; 2796 } 2797 } 2798} 2799 2800static void 2801bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx) 2802{ 2803 struct bwi_ring_data *rd; 2804 struct bwi_txbuf_data *tbd; 2805 struct ifnet *ifp = sc->sc_ifp; 2806 uint32_t state, val; 2807 int i; 2808 2809 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2810 rd = &sc->sc_tx_rdata[ring_idx]; 2811 tbd = &sc->sc_tx_bdata[ring_idx]; 2812 2813#define NRETRY 10 2814 2815 for (i = 0; i < NRETRY; ++i) { 2816 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2817 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2818 if (state == BWI_TX32_STATUS_STATE_DISABLED || 2819 state == BWI_TX32_STATUS_STATE_IDLE || 2820 state == BWI_TX32_STATUS_STATE_STOPPED) 2821 break; 2822 2823 DELAY(1000); 2824 } 2825 if (i == NRETRY) { 2826 if_printf(ifp, "%s: wait for TX ring(%d) stable timed out\n", 2827 __func__, ring_idx); 2828 } 2829 2830 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0); 2831 for (i = 0; i < NRETRY; ++i) { 2832 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2833 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2834 if (state == BWI_TX32_STATUS_STATE_DISABLED) 2835 break; 2836 2837 DELAY(1000); 2838 } 2839 if (i == NRETRY) 2840 if_printf(ifp, "%s: reset TX ring (%d) timed out\n", 2841 __func__, ring_idx); 2842 2843#undef NRETRY 2844 2845 DELAY(1000); 2846 2847 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0); 2848 2849 for (i = 0; i < BWI_TX_NDESC; ++i) { 2850 struct bwi_txbuf *tb = &tbd->tbd_buf[i]; 2851 2852 if (tb->tb_mbuf != NULL) { 2853 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 2854 m_freem(tb->tb_mbuf); 2855 tb->tb_mbuf = NULL; 2856 } 2857 if (tb->tb_ni != NULL) { 2858 ieee80211_free_node(tb->tb_ni); 2859 tb->tb_ni = NULL; 2860 } 2861 } 2862} 2863 2864static void 2865bwi_free_txstats64(struct bwi_softc *sc) 2866{ 2867 /* TODO:64 */ 2868} 2869 2870static void 2871bwi_free_rx_ring64(struct bwi_softc *sc) 2872{ 2873 /* TODO:64 */ 2874} 2875 2876static void 2877bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx) 2878{ 2879 /* TODO:64 */ 2880} 2881 2882/* XXX does not belong here */ 2883#define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0) 2884#define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5) 2885 2886static __inline void 2887bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate) 2888{ 2889 uint32_t plcp; 2890 2891 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM), 2892 IEEE80211_OFDM_PLCP_RATE_MASK) | 2893 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK); 2894 *plcp0 = htole32(plcp); 2895} 2896 2897static __inline void 2898bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len, 2899 uint8_t rate) 2900{ 2901 int len, service, pkt_bitlen; 2902 2903 pkt_bitlen = pkt_len * NBBY; 2904 len = howmany(pkt_bitlen * 2, rate); 2905 2906 service = IEEE80211_PLCP_SERVICE_LOCKED; 2907 if (rate == (11 * 2)) { 2908 int pkt_bitlen1; 2909 2910 /* 2911 * PLCP service field needs to be adjusted, 2912 * if TX rate is 11Mbytes/s 2913 */ 2914 pkt_bitlen1 = len * 11; 2915 if (pkt_bitlen1 - pkt_bitlen >= NBBY) 2916 service |= IEEE80211_PLCP_SERVICE_LENEXT7; 2917 } 2918 2919 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK); 2920 plcp->i_service = service; 2921 plcp->i_length = htole16(len); 2922 /* NOTE: do NOT touch i_crc */ 2923} 2924 2925static __inline void 2926bwi_plcp_header(const struct ieee80211_rate_table *rt, 2927 void *plcp, int pkt_len, uint8_t rate) 2928{ 2929 enum ieee80211_phytype modtype; 2930 2931 /* 2932 * Assume caller has zeroed 'plcp' 2933 */ 2934 modtype = ieee80211_rate2phytype(rt, rate); 2935 if (modtype == IEEE80211_T_OFDM) 2936 bwi_ofdm_plcp_header(plcp, pkt_len, rate); 2937 else if (modtype == IEEE80211_T_DS) 2938 bwi_ds_plcp_header(plcp, pkt_len, rate); 2939 else 2940 panic("unsupport modulation type %u\n", modtype); 2941} 2942 2943static int 2944bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m, 2945 struct ieee80211_node *ni) 2946{ 2947 struct ieee80211vap *vap = ni->ni_vap; 2948 struct ifnet *ifp = sc->sc_ifp; 2949 struct ieee80211com *ic = ifp->if_l2com; 2950 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 2951 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 2952 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 2953 struct bwi_mac *mac; 2954 struct bwi_txbuf_hdr *hdr; 2955 struct ieee80211_frame *wh; 2956 const struct ieee80211_txparam *tp; 2957 uint8_t rate, rate_fb; 2958 uint32_t mac_ctrl; 2959 uint16_t phy_ctrl; 2960 bus_addr_t paddr; 2961 int type, ismcast, pkt_len, error, rix; 2962#if 0 2963 const uint8_t *p; 2964 int i; 2965#endif 2966 2967 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 2968 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 2969 mac = (struct bwi_mac *)sc->sc_cur_regwin; 2970 2971 wh = mtod(m, struct ieee80211_frame *); 2972 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2973 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2974 2975 /* Get 802.11 frame len before prepending TX header */ 2976 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 2977 2978 /* 2979 * Find TX rate 2980 */ 2981 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 2982 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) { 2983 rate = rate_fb = tp->mgmtrate; 2984 } else if (ismcast) { 2985 rate = rate_fb = tp->mcastrate; 2986 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 2987 rate = rate_fb = tp->ucastrate; 2988 } else { 2989 rix = ieee80211_ratectl_rate(ni, NULL, pkt_len); 2990 rate = ni->ni_txrate; 2991 2992 if (rix > 0) { 2993 rate_fb = ni->ni_rates.rs_rates[rix-1] & 2994 IEEE80211_RATE_VAL; 2995 } else { 2996 rate_fb = rate; 2997 } 2998 } 2999 tb->tb_rate[0] = rate; 3000 tb->tb_rate[1] = rate_fb; 3001 sc->sc_tx_rate = rate; 3002 3003 /* 3004 * TX radio tap 3005 */ 3006 if (ieee80211_radiotap_active_vap(vap)) { 3007 sc->sc_tx_th.wt_flags = 0; 3008 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 3009 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3010 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS && 3011 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3012 rate != (1 * 2)) { 3013 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3014 } 3015 sc->sc_tx_th.wt_rate = rate; 3016 3017 ieee80211_radiotap_tx(vap, m); 3018 } 3019 3020 /* 3021 * Setup the embedded TX header 3022 */ 3023 M_PREPEND(m, sizeof(*hdr), M_DONTWAIT); 3024 if (m == NULL) { 3025 if_printf(ifp, "%s: prepend TX header failed\n", __func__); 3026 return ENOBUFS; 3027 } 3028 hdr = mtod(m, struct bwi_txbuf_hdr *); 3029 3030 bzero(hdr, sizeof(*hdr)); 3031 3032 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3033 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3034 3035 if (!ismcast) { 3036 uint16_t dur; 3037 3038 dur = ieee80211_ack_duration(sc->sc_rates, rate, 3039 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE); 3040 3041 hdr->txh_fb_duration = htole16(dur); 3042 } 3043 3044 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3045 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3046 3047 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3048 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3049 3050 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3051 BWI_TXH_PHY_C_ANTMODE_MASK); 3052 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 3053 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3054 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1)) 3055 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3056 3057 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3058 if (!ismcast) 3059 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3060 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM) 3061 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3062 3063 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3064 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3065 3066 /* Catch any further usage */ 3067 hdr = NULL; 3068 wh = NULL; 3069 3070 /* DMA load */ 3071 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3072 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3073 if (error && error != EFBIG) { 3074 if_printf(ifp, "%s: can't load TX buffer (1) %d\n", 3075 __func__, error); 3076 goto back; 3077 } 3078 3079 if (error) { /* error == EFBIG */ 3080 struct mbuf *m_new; 3081 3082 m_new = m_defrag(m, M_DONTWAIT); 3083 if (m_new == NULL) { 3084 if_printf(ifp, "%s: can't defrag TX buffer\n", 3085 __func__); 3086 error = ENOBUFS; 3087 goto back; 3088 } else { 3089 m = m_new; 3090 } 3091 3092 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3093 bwi_dma_buf_addr, &paddr, 3094 BUS_DMA_NOWAIT); 3095 if (error) { 3096 if_printf(ifp, "%s: can't load TX buffer (2) %d\n", 3097 __func__, error); 3098 goto back; 3099 } 3100 } 3101 error = 0; 3102 3103 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3104 3105 tb->tb_mbuf = m; 3106 tb->tb_ni = ni; 3107 3108#if 0 3109 p = mtod(m, const uint8_t *); 3110 for (i = 0; i < m->m_pkthdr.len; ++i) { 3111 if (i != 0 && i % 8 == 0) 3112 printf("\n"); 3113 printf("%02x ", p[i]); 3114 } 3115 printf("\n"); 3116#endif 3117 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3118 idx, pkt_len, m->m_pkthdr.len); 3119 3120 /* Setup TX descriptor */ 3121 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3122 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3123 BUS_DMASYNC_PREWRITE); 3124 3125 /* Kick start */ 3126 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3127 3128back: 3129 if (error) 3130 m_freem(m); 3131 return error; 3132} 3133 3134static int 3135bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m, 3136 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3137{ 3138 struct ifnet *ifp = sc->sc_ifp; 3139 struct ieee80211vap *vap = ni->ni_vap; 3140 struct ieee80211com *ic = ni->ni_ic; 3141 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 3142 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 3143 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 3144 struct bwi_mac *mac; 3145 struct bwi_txbuf_hdr *hdr; 3146 struct ieee80211_frame *wh; 3147 uint8_t rate, rate_fb; 3148 uint32_t mac_ctrl; 3149 uint16_t phy_ctrl; 3150 bus_addr_t paddr; 3151 int ismcast, pkt_len, error; 3152 3153 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3154 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3155 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3156 3157 wh = mtod(m, struct ieee80211_frame *); 3158 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3159 3160 /* Get 802.11 frame len before prepending TX header */ 3161 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 3162 3163 /* 3164 * Find TX rate 3165 */ 3166 rate = params->ibp_rate0; 3167 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3168 /* XXX fall back to mcast/mgmt rate? */ 3169 m_freem(m); 3170 return EINVAL; 3171 } 3172 if (params->ibp_try1 != 0) { 3173 rate_fb = params->ibp_rate1; 3174 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) { 3175 /* XXX fall back to rate0? */ 3176 m_freem(m); 3177 return EINVAL; 3178 } 3179 } else 3180 rate_fb = rate; 3181 tb->tb_rate[0] = rate; 3182 tb->tb_rate[1] = rate_fb; 3183 sc->sc_tx_rate = rate; 3184 3185 /* 3186 * TX radio tap 3187 */ 3188 if (ieee80211_radiotap_active_vap(vap)) { 3189 sc->sc_tx_th.wt_flags = 0; 3190 /* XXX IEEE80211_BPF_CRYPTO */ 3191 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 3192 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3193 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3194 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3195 sc->sc_tx_th.wt_rate = rate; 3196 3197 ieee80211_radiotap_tx(vap, m); 3198 } 3199 3200 /* 3201 * Setup the embedded TX header 3202 */ 3203 M_PREPEND(m, sizeof(*hdr), M_DONTWAIT); 3204 if (m == NULL) { 3205 if_printf(ifp, "%s: prepend TX header failed\n", __func__); 3206 return ENOBUFS; 3207 } 3208 hdr = mtod(m, struct bwi_txbuf_hdr *); 3209 3210 bzero(hdr, sizeof(*hdr)); 3211 3212 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3213 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3214 3215 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3216 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 3217 uint16_t dur; 3218 3219 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0); 3220 3221 hdr->txh_fb_duration = htole16(dur); 3222 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3223 } 3224 3225 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3226 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3227 3228 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3229 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3230 3231 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3232 BWI_TXH_PHY_C_ANTMODE_MASK); 3233 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 3234 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3235 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3236 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3237 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3238 3239 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3240 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3241 3242 /* Catch any further usage */ 3243 hdr = NULL; 3244 wh = NULL; 3245 3246 /* DMA load */ 3247 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3248 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3249 if (error != 0) { 3250 struct mbuf *m_new; 3251 3252 if (error != EFBIG) { 3253 if_printf(ifp, "%s: can't load TX buffer (1) %d\n", 3254 __func__, error); 3255 goto back; 3256 } 3257 m_new = m_defrag(m, M_DONTWAIT); 3258 if (m_new == NULL) { 3259 if_printf(ifp, "%s: can't defrag TX buffer\n", 3260 __func__); 3261 error = ENOBUFS; 3262 goto back; 3263 } 3264 m = m_new; 3265 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3266 bwi_dma_buf_addr, &paddr, 3267 BUS_DMA_NOWAIT); 3268 if (error) { 3269 if_printf(ifp, "%s: can't load TX buffer (2) %d\n", 3270 __func__, error); 3271 goto back; 3272 } 3273 } 3274 3275 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3276 3277 tb->tb_mbuf = m; 3278 tb->tb_ni = ni; 3279 3280 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3281 idx, pkt_len, m->m_pkthdr.len); 3282 3283 /* Setup TX descriptor */ 3284 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3285 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3286 BUS_DMASYNC_PREWRITE); 3287 3288 /* Kick start */ 3289 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3290back: 3291 if (error) 3292 m_freem(m); 3293 return error; 3294} 3295 3296static void 3297bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3298{ 3299 idx = (idx + 1) % BWI_TX_NDESC; 3300 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX, 3301 idx * sizeof(struct bwi_desc32)); 3302} 3303 3304static void 3305bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3306{ 3307 /* TODO:64 */ 3308} 3309 3310static void 3311bwi_txeof_status32(struct bwi_softc *sc) 3312{ 3313 struct ifnet *ifp = sc->sc_ifp; 3314 uint32_t val, ctrl_base; 3315 int end_idx; 3316 3317 ctrl_base = sc->sc_txstats->stats_ctrl_base; 3318 3319 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS); 3320 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 3321 sizeof(struct bwi_desc32); 3322 3323 bwi_txeof_status(sc, end_idx); 3324 3325 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 3326 end_idx * sizeof(struct bwi_desc32)); 3327 3328 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) 3329 ifp->if_start(ifp); 3330} 3331 3332static void 3333bwi_txeof_status64(struct bwi_softc *sc) 3334{ 3335 /* TODO:64 */ 3336} 3337 3338static void 3339_bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt) 3340{ 3341 struct ifnet *ifp = sc->sc_ifp; 3342 struct bwi_txbuf_data *tbd; 3343 struct bwi_txbuf *tb; 3344 int ring_idx, buf_idx; 3345 struct ieee80211_node *ni; 3346 struct ieee80211vap *vap; 3347 3348 if (tx_id == 0) { 3349 if_printf(ifp, "%s: zero tx id\n", __func__); 3350 return; 3351 } 3352 3353 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK); 3354 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK); 3355 3356 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx)); 3357 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 3358 3359 tbd = &sc->sc_tx_bdata[ring_idx]; 3360 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used)); 3361 tbd->tbd_used--; 3362 3363 tb = &tbd->tbd_buf[buf_idx]; 3364 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, " 3365 "acked %d, data_txcnt %d, ni %p\n", 3366 buf_idx, acked, data_txcnt, tb->tb_ni); 3367 3368 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 3369 3370 ni = tb->tb_ni; 3371 if (tb->tb_ni != NULL) { 3372 const struct bwi_txbuf_hdr *hdr = 3373 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *); 3374 vap = ni->ni_vap; 3375 3376 /* NB: update rate control only for unicast frames */ 3377 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) { 3378 /* 3379 * Feed back 'acked and data_txcnt'. Note that the 3380 * generic AMRR code only understands one tx rate 3381 * and the estimator doesn't handle real retry counts 3382 * well so to avoid over-aggressive downshifting we 3383 * treat any number of retries as "1". 3384 */ 3385 ieee80211_ratectl_tx_complete(vap, ni, 3386 (data_txcnt > 1) ? IEEE80211_RATECTL_TX_SUCCESS : 3387 IEEE80211_RATECTL_TX_FAILURE, &acked, NULL); 3388 } 3389 3390 /* 3391 * Do any tx complete callback. Note this must 3392 * be done before releasing the node reference. 3393 */ 3394 if (tb->tb_mbuf->m_flags & M_TXCB) 3395 ieee80211_process_callback(ni, tb->tb_mbuf, !acked); 3396 3397 ieee80211_free_node(tb->tb_ni); 3398 tb->tb_ni = NULL; 3399 } 3400 m_freem(tb->tb_mbuf); 3401 tb->tb_mbuf = NULL; 3402 3403 if (tbd->tbd_used == 0) 3404 sc->sc_tx_timer = 0; 3405 3406 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3407} 3408 3409static void 3410bwi_txeof_status(struct bwi_softc *sc, int end_idx) 3411{ 3412 struct bwi_txstats_data *st = sc->sc_txstats; 3413 int idx; 3414 3415 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD); 3416 3417 idx = st->stats_idx; 3418 while (idx != end_idx) { 3419 const struct bwi_txstats *stats = &st->stats[idx]; 3420 3421 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) { 3422 int data_txcnt; 3423 3424 data_txcnt = __SHIFTOUT(stats->txs_txcnt, 3425 BWI_TXS_TXCNT_DATA); 3426 _bwi_txeof(sc, le16toh(stats->txs_id), 3427 stats->txs_flags & BWI_TXS_F_ACKED, 3428 data_txcnt); 3429 } 3430 idx = (idx + 1) % BWI_TXSTATS_NDESC; 3431 } 3432 st->stats_idx = idx; 3433} 3434 3435static void 3436bwi_txeof(struct bwi_softc *sc) 3437{ 3438 struct ifnet *ifp = sc->sc_ifp; 3439 3440 for (;;) { 3441 uint32_t tx_status0, tx_status1; 3442 uint16_t tx_id; 3443 int data_txcnt; 3444 3445 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0); 3446 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0) 3447 break; 3448 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1); 3449 3450 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK); 3451 data_txcnt = __SHIFTOUT(tx_status0, 3452 BWI_TXSTATUS0_DATA_TXCNT_MASK); 3453 3454 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING)) 3455 continue; 3456 3457 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED, 3458 data_txcnt); 3459 } 3460 3461 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) 3462 ifp->if_start(ifp); 3463} 3464 3465static int 3466bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 3467{ 3468 bwi_power_on(sc, 1); 3469 return bwi_set_clock_mode(sc, clk_mode); 3470} 3471 3472static void 3473bwi_bbp_power_off(struct bwi_softc *sc) 3474{ 3475 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW); 3476 bwi_power_off(sc, 1); 3477} 3478 3479static int 3480bwi_get_pwron_delay(struct bwi_softc *sc) 3481{ 3482 struct bwi_regwin *com, *old; 3483 struct bwi_clock_freq freq; 3484 uint32_t val; 3485 int error; 3486 3487 com = &sc->sc_com_regwin; 3488 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin")); 3489 3490 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 3491 return 0; 3492 3493 error = bwi_regwin_switch(sc, com, &old); 3494 if (error) 3495 return error; 3496 3497 bwi_get_clock_freq(sc, &freq); 3498 3499 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY); 3500 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min); 3501 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay); 3502 3503 return bwi_regwin_switch(sc, old, NULL); 3504} 3505 3506static int 3507bwi_bus_attach(struct bwi_softc *sc) 3508{ 3509 struct bwi_regwin *bus, *old; 3510 int error; 3511 3512 bus = &sc->sc_bus_regwin; 3513 3514 error = bwi_regwin_switch(sc, bus, &old); 3515 if (error) 3516 return error; 3517 3518 if (!bwi_regwin_is_enabled(sc, bus)) 3519 bwi_regwin_enable(sc, bus, 0); 3520 3521 /* Disable interripts */ 3522 CSR_WRITE_4(sc, BWI_INTRVEC, 0); 3523 3524 return bwi_regwin_switch(sc, old, NULL); 3525} 3526 3527static const char * 3528bwi_regwin_name(const struct bwi_regwin *rw) 3529{ 3530 switch (rw->rw_type) { 3531 case BWI_REGWIN_T_COM: 3532 return "COM"; 3533 case BWI_REGWIN_T_BUSPCI: 3534 return "PCI"; 3535 case BWI_REGWIN_T_MAC: 3536 return "MAC"; 3537 case BWI_REGWIN_T_BUSPCIE: 3538 return "PCIE"; 3539 } 3540 panic("unknown regwin type 0x%04x\n", rw->rw_type); 3541 return NULL; 3542} 3543 3544static uint32_t 3545bwi_regwin_disable_bits(struct bwi_softc *sc) 3546{ 3547 uint32_t busrev; 3548 3549 /* XXX cache this */ 3550 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK); 3551 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC, 3552 "bus rev %u\n", busrev); 3553 3554 if (busrev == BWI_BUSREV_0) 3555 return BWI_STATE_LO_DISABLE1; 3556 else if (busrev == BWI_BUSREV_1) 3557 return BWI_STATE_LO_DISABLE2; 3558 else 3559 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2); 3560} 3561 3562int 3563bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw) 3564{ 3565 uint32_t val, disable_bits; 3566 3567 disable_bits = bwi_regwin_disable_bits(sc); 3568 val = CSR_READ_4(sc, BWI_STATE_LO); 3569 3570 if ((val & (BWI_STATE_LO_CLOCK | 3571 BWI_STATE_LO_RESET | 3572 disable_bits)) == BWI_STATE_LO_CLOCK) { 3573 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n", 3574 bwi_regwin_name(rw)); 3575 return 1; 3576 } else { 3577 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n", 3578 bwi_regwin_name(rw)); 3579 return 0; 3580 } 3581} 3582 3583void 3584bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3585{ 3586 uint32_t state_lo, disable_bits; 3587 int i; 3588 3589 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3590 3591 /* 3592 * If current regwin is in 'reset' state, it was already disabled. 3593 */ 3594 if (state_lo & BWI_STATE_LO_RESET) { 3595 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, 3596 "%s was already disabled\n", bwi_regwin_name(rw)); 3597 return; 3598 } 3599 3600 disable_bits = bwi_regwin_disable_bits(sc); 3601 3602 /* 3603 * Disable normal clock 3604 */ 3605 state_lo = BWI_STATE_LO_CLOCK | disable_bits; 3606 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3607 3608 /* 3609 * Wait until normal clock is disabled 3610 */ 3611#define NRETRY 1000 3612 for (i = 0; i < NRETRY; ++i) { 3613 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3614 if (state_lo & disable_bits) 3615 break; 3616 DELAY(10); 3617 } 3618 if (i == NRETRY) { 3619 device_printf(sc->sc_dev, "%s disable clock timeout\n", 3620 bwi_regwin_name(rw)); 3621 } 3622 3623 for (i = 0; i < NRETRY; ++i) { 3624 uint32_t state_hi; 3625 3626 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3627 if ((state_hi & BWI_STATE_HI_BUSY) == 0) 3628 break; 3629 DELAY(10); 3630 } 3631 if (i == NRETRY) { 3632 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n", 3633 bwi_regwin_name(rw)); 3634 } 3635#undef NRETRY 3636 3637 /* 3638 * Reset and disable regwin with gated clock 3639 */ 3640 state_lo = BWI_STATE_LO_RESET | disable_bits | 3641 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK | 3642 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3643 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3644 3645 /* Flush pending bus write */ 3646 CSR_READ_4(sc, BWI_STATE_LO); 3647 DELAY(1); 3648 3649 /* Reset and disable regwin */ 3650 state_lo = BWI_STATE_LO_RESET | disable_bits | 3651 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3652 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3653 3654 /* Flush pending bus write */ 3655 CSR_READ_4(sc, BWI_STATE_LO); 3656 DELAY(1); 3657} 3658 3659void 3660bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3661{ 3662 uint32_t state_lo, state_hi, imstate; 3663 3664 bwi_regwin_disable(sc, rw, flags); 3665 3666 /* Reset regwin with gated clock */ 3667 state_lo = BWI_STATE_LO_RESET | 3668 BWI_STATE_LO_CLOCK | 3669 BWI_STATE_LO_GATED_CLOCK | 3670 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3671 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3672 3673 /* Flush pending bus write */ 3674 CSR_READ_4(sc, BWI_STATE_LO); 3675 DELAY(1); 3676 3677 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3678 if (state_hi & BWI_STATE_HI_SERROR) 3679 CSR_WRITE_4(sc, BWI_STATE_HI, 0); 3680 3681 imstate = CSR_READ_4(sc, BWI_IMSTATE); 3682 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) { 3683 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT); 3684 CSR_WRITE_4(sc, BWI_IMSTATE, imstate); 3685 } 3686 3687 /* Enable regwin with gated clock */ 3688 state_lo = BWI_STATE_LO_CLOCK | 3689 BWI_STATE_LO_GATED_CLOCK | 3690 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3691 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3692 3693 /* Flush pending bus write */ 3694 CSR_READ_4(sc, BWI_STATE_LO); 3695 DELAY(1); 3696 3697 /* Enable regwin with normal clock */ 3698 state_lo = BWI_STATE_LO_CLOCK | 3699 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3700 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3701 3702 /* Flush pending bus write */ 3703 CSR_READ_4(sc, BWI_STATE_LO); 3704 DELAY(1); 3705} 3706 3707static void 3708bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid) 3709{ 3710 struct ifnet *ifp = sc->sc_ifp; 3711 struct bwi_mac *mac; 3712 struct bwi_myaddr_bssid buf; 3713 const uint8_t *p; 3714 uint32_t val; 3715 int n, i; 3716 3717 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3718 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3719 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3720 3721 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid); 3722 3723 bcopy(IF_LLADDR(ifp), buf.myaddr, sizeof(buf.myaddr)); 3724 bcopy(bssid, buf.bssid, sizeof(buf.bssid)); 3725 3726 n = sizeof(buf) / sizeof(val); 3727 p = (const uint8_t *)&buf; 3728 for (i = 0; i < n; ++i) { 3729 int j; 3730 3731 val = 0; 3732 for (j = 0; j < sizeof(val); ++j) 3733 val |= ((uint32_t)(*p++)) << (j * 8); 3734 3735 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val); 3736 } 3737} 3738 3739static void 3740bwi_updateslot(struct ifnet *ifp) 3741{ 3742 struct bwi_softc *sc = ifp->if_softc; 3743 struct ieee80211com *ic = ifp->if_l2com; 3744 struct bwi_mac *mac; 3745 3746 BWI_LOCK(sc); 3747 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3748 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__); 3749 3750 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3751 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3752 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3753 3754 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT)); 3755 } 3756 BWI_UNLOCK(sc); 3757} 3758 3759static void 3760bwi_calibrate(void *xsc) 3761{ 3762 struct bwi_softc *sc = xsc; 3763#ifdef INVARIANTS 3764 struct ifnet *ifp = sc->sc_ifp; 3765 struct ieee80211com *ic = ifp->if_l2com; 3766#endif 3767 struct bwi_mac *mac; 3768 3769 BWI_ASSERT_LOCKED(sc); 3770 3771 KASSERT(ic->ic_opmode != IEEE80211_M_MONITOR, 3772 ("opmode %d", ic->ic_opmode)); 3773 3774 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3775 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3776 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3777 3778 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type); 3779 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 3780 3781 /* XXX 15 seconds */ 3782 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc); 3783} 3784 3785static int 3786bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr) 3787{ 3788 struct bwi_mac *mac; 3789 3790 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3791 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3792 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3793 3794 return bwi_rf_calc_rssi(mac, hdr); 3795} 3796 3797static int 3798bwi_calc_noise(struct bwi_softc *sc) 3799{ 3800 struct bwi_mac *mac; 3801 3802 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3803 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3804 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3805 3806 return bwi_rf_calc_noise(mac); 3807} 3808 3809static __inline uint8_t 3810bwi_plcp2rate(const uint32_t plcp0, enum ieee80211_phytype type) 3811{ 3812 uint32_t plcp = le32toh(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK; 3813 return (ieee80211_plcp2rate(plcp, type)); 3814} 3815 3816static void 3817bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m, 3818 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise) 3819{ 3820 const struct ieee80211_frame_min *wh; 3821 3822 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS; 3823 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE) 3824 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3825 3826 wh = mtod(m, const struct ieee80211_frame_min *); 3827 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 3828 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; 3829 3830 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */ 3831 sc->sc_rx_th.wr_rate = rate; 3832 sc->sc_rx_th.wr_antsignal = rssi; 3833 sc->sc_rx_th.wr_antnoise = noise; 3834} 3835 3836static void 3837bwi_led_attach(struct bwi_softc *sc) 3838{ 3839 const uint8_t *led_act = NULL; 3840 uint16_t gpio, val[BWI_LED_MAX]; 3841 int i; 3842 3843#define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 3844 3845 for (i = 0; i < N(bwi_vendor_led_act); ++i) { 3846 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) { 3847 led_act = bwi_vendor_led_act[i].led_act; 3848 break; 3849 } 3850 } 3851 if (led_act == NULL) 3852 led_act = bwi_default_led_act; 3853 3854#undef N 3855 3856 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01); 3857 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0); 3858 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1); 3859 3860 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23); 3861 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2); 3862 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3); 3863 3864 for (i = 0; i < BWI_LED_MAX; ++i) { 3865 struct bwi_led *led = &sc->sc_leds[i]; 3866 3867 if (val[i] == 0xff) { 3868 led->l_act = led_act[i]; 3869 } else { 3870 if (val[i] & BWI_LED_ACT_LOW) 3871 led->l_flags |= BWI_LED_F_ACTLOW; 3872 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK); 3873 } 3874 led->l_mask = (1 << i); 3875 3876 if (led->l_act == BWI_LED_ACT_BLINK_SLOW || 3877 led->l_act == BWI_LED_ACT_BLINK_POLL || 3878 led->l_act == BWI_LED_ACT_BLINK) { 3879 led->l_flags |= BWI_LED_F_BLINK; 3880 if (led->l_act == BWI_LED_ACT_BLINK_POLL) 3881 led->l_flags |= BWI_LED_F_POLLABLE; 3882 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW) 3883 led->l_flags |= BWI_LED_F_SLOW; 3884 3885 if (sc->sc_blink_led == NULL) { 3886 sc->sc_blink_led = led; 3887 if (led->l_flags & BWI_LED_F_SLOW) 3888 BWI_LED_SLOWDOWN(sc->sc_led_idle); 3889 } 3890 } 3891 3892 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH, 3893 "%dth led, act %d, lowact %d\n", i, 3894 led->l_act, led->l_flags & BWI_LED_F_ACTLOW); 3895 } 3896 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0); 3897} 3898 3899static __inline uint16_t 3900bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on) 3901{ 3902 if (led->l_flags & BWI_LED_F_ACTLOW) 3903 on = !on; 3904 if (on) 3905 val |= led->l_mask; 3906 else 3907 val &= ~led->l_mask; 3908 return val; 3909} 3910 3911static void 3912bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate) 3913{ 3914 struct ifnet *ifp = sc->sc_ifp; 3915 struct ieee80211com *ic = ifp->if_l2com; 3916 uint16_t val; 3917 int i; 3918 3919 if (nstate == IEEE80211_S_INIT) { 3920 callout_stop(&sc->sc_led_blink_ch); 3921 sc->sc_led_blinking = 0; 3922 } 3923 3924 if ((ic->ic_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3925 return; 3926 3927 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3928 for (i = 0; i < BWI_LED_MAX; ++i) { 3929 struct bwi_led *led = &sc->sc_leds[i]; 3930 int on; 3931 3932 if (led->l_act == BWI_LED_ACT_UNKN || 3933 led->l_act == BWI_LED_ACT_NULL) 3934 continue; 3935 3936 if ((led->l_flags & BWI_LED_F_BLINK) && 3937 nstate != IEEE80211_S_INIT) 3938 continue; 3939 3940 switch (led->l_act) { 3941 case BWI_LED_ACT_ON: /* Always on */ 3942 on = 1; 3943 break; 3944 case BWI_LED_ACT_OFF: /* Always off */ 3945 case BWI_LED_ACT_5GHZ: /* TODO: 11A */ 3946 on = 0; 3947 break; 3948 default: 3949 on = 1; 3950 switch (nstate) { 3951 case IEEE80211_S_INIT: 3952 on = 0; 3953 break; 3954 case IEEE80211_S_RUN: 3955 if (led->l_act == BWI_LED_ACT_11G && 3956 ic->ic_curmode != IEEE80211_MODE_11G) 3957 on = 0; 3958 break; 3959 default: 3960 if (led->l_act == BWI_LED_ACT_ASSOC) 3961 on = 0; 3962 break; 3963 } 3964 break; 3965 } 3966 3967 val = bwi_led_onoff(led, val, on); 3968 } 3969 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3970} 3971static void 3972bwi_led_event(struct bwi_softc *sc, int event) 3973{ 3974 struct bwi_led *led = sc->sc_blink_led; 3975 int rate; 3976 3977 if (event == BWI_LED_EVENT_POLL) { 3978 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0) 3979 return; 3980 if (ticks - sc->sc_led_ticks < sc->sc_led_idle) 3981 return; 3982 } 3983 3984 sc->sc_led_ticks = ticks; 3985 if (sc->sc_led_blinking) 3986 return; 3987 3988 switch (event) { 3989 case BWI_LED_EVENT_RX: 3990 rate = sc->sc_rx_rate; 3991 break; 3992 case BWI_LED_EVENT_TX: 3993 rate = sc->sc_tx_rate; 3994 break; 3995 case BWI_LED_EVENT_POLL: 3996 rate = 0; 3997 break; 3998 default: 3999 panic("unknown LED event %d\n", event); 4000 break; 4001 } 4002 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur, 4003 bwi_led_duration[rate].off_dur); 4004} 4005 4006static void 4007bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur) 4008{ 4009 struct bwi_led *led = sc->sc_blink_led; 4010 uint16_t val; 4011 4012 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 4013 val = bwi_led_onoff(led, val, 1); 4014 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 4015 4016 if (led->l_flags & BWI_LED_F_SLOW) { 4017 BWI_LED_SLOWDOWN(on_dur); 4018 BWI_LED_SLOWDOWN(off_dur); 4019 } 4020 4021 sc->sc_led_blinking = 1; 4022 sc->sc_led_blink_offdur = off_dur; 4023 4024 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc); 4025} 4026 4027static void 4028bwi_led_blink_next(void *xsc) 4029{ 4030 struct bwi_softc *sc = xsc; 4031 uint16_t val; 4032 4033 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 4034 val = bwi_led_onoff(sc->sc_blink_led, val, 0); 4035 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 4036 4037 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, 4038 bwi_led_blink_end, sc); 4039} 4040 4041static void 4042bwi_led_blink_end(void *xsc) 4043{ 4044 struct bwi_softc *sc = xsc; 4045 sc->sc_led_blinking = 0; 4046} 4047 4048static void 4049bwi_restart(void *xsc, int pending) 4050{ 4051 struct bwi_softc *sc = xsc; 4052 struct ifnet *ifp = sc->sc_ifp; 4053 4054 if_printf(ifp, "%s begin, help!\n", __func__); 4055 BWI_LOCK(sc); 4056 bwi_init_statechg(xsc, 0); 4057#if 0 4058 bwi_start_locked(ifp); 4059#endif 4060 BWI_UNLOCK(sc); 4061} 4062