1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23 24#include "ar5416/ar5416.h" 25#include "ar5416/ar5416reg.h" 26 27/* 28 * Checks to see if an interrupt is pending on our NIC 29 * 30 * Returns: TRUE if an interrupt is pending 31 * FALSE if not 32 */ 33HAL_BOOL 34ar5416IsInterruptPending(struct ath_hal *ah) 35{ 36 uint32_t isr; 37 38 if (AR_SREV_HOWL(ah)) 39 return AH_TRUE; 40 41 /* 42 * Some platforms trigger our ISR before applying power to 43 * the card, so make sure the INTPEND is really 1, not 0xffffffff. 44 */ 45 isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE); 46 if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_MAC_IRQ) != 0) 47 return AH_TRUE; 48 49 isr = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); 50 if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_SYNC_DEFAULT)) 51 return AH_TRUE; 52 53 return AH_FALSE; 54} 55 56/* 57 * Reads the Interrupt Status Register value from the NIC, thus deasserting 58 * the interrupt line, and returns both the masked and unmasked mapped ISR 59 * values. The value returned is mapped to abstract the hw-specific bit 60 * locations in the Interrupt Status Register. 61 * 62 * (*masked) is cleared on initial call. 63 * 64 * Returns: A hardware-abstracted bitmap of all non-masked-out 65 * interrupts pending, as well as an unmasked value 66 */ 67HAL_BOOL 68ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) 69{ 70 uint32_t isr, isr0, isr1, sync_cause = 0; 71 72 /* 73 * Verify there's a mac interrupt and the RTC is on. 74 */ 75 if (AR_SREV_HOWL(ah)) { 76 *masked = 0; 77 isr = OS_REG_READ(ah, AR_ISR); 78 } else { 79 if ((OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) && 80 (OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON) 81 isr = OS_REG_READ(ah, AR_ISR); 82 else 83 isr = 0; 84 sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); 85 sync_cause &= AR_INTR_SYNC_DEFAULT; 86 *masked = 0; 87 88 if (isr == 0 && sync_cause == 0) 89 return AH_FALSE; 90 } 91 92 if (isr != 0) { 93 struct ath_hal_5212 *ahp = AH5212(ah); 94 uint32_t mask2; 95 96 mask2 = 0; 97 if (isr & AR_ISR_BCNMISC) { 98 uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2); 99 if (isr2 & AR_ISR_S2_TIM) 100 mask2 |= HAL_INT_TIM; 101 if (isr2 & AR_ISR_S2_DTIM) 102 mask2 |= HAL_INT_DTIM; 103 if (isr2 & AR_ISR_S2_DTIMSYNC) 104 mask2 |= HAL_INT_DTIMSYNC; 105 if (isr2 & (AR_ISR_S2_CABEND )) 106 mask2 |= HAL_INT_CABEND; 107 if (isr2 & AR_ISR_S2_GTT) 108 mask2 |= HAL_INT_GTT; 109 if (isr2 & AR_ISR_S2_CST) 110 mask2 |= HAL_INT_CST; 111 if (isr2 & AR_ISR_S2_TSFOOR) 112 mask2 |= HAL_INT_TSFOOR; 113 } 114 115 isr = OS_REG_READ(ah, AR_ISR_RAC); 116 if (isr == 0xffffffff) { 117 *masked = 0; 118 return AH_FALSE; 119 } 120 121 *masked = isr & HAL_INT_COMMON; 122 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) 123 *masked |= HAL_INT_RX; 124 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) { 125 *masked |= HAL_INT_TX; 126 isr0 = OS_REG_READ(ah, AR_ISR_S0_S); 127 ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXOK); 128 ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXDESC); 129 isr1 = OS_REG_READ(ah, AR_ISR_S1_S); 130 ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR); 131 ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL); 132 } 133 134 if (AR_SREV_MERLIN(ah) || AR_SREV_KITE(ah)) { 135 uint32_t isr5; 136 isr5 = OS_REG_READ(ah, AR_ISR_S5_S); 137 if (isr5 & AR_ISR_S5_TIM_TIMER) 138 *masked |= HAL_INT_TIM_TIMER; 139 } 140 141 /* Interrupt Mitigation on AR5416 */ 142#ifdef AH_AR5416_INTERRUPT_MITIGATION 143 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 144 *masked |= HAL_INT_RX; 145 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) 146 *masked |= HAL_INT_TX; 147#endif 148 *masked |= mask2; 149 } 150 151 if (AR_SREV_HOWL(ah)) 152 return AH_TRUE; 153 154 if (sync_cause != 0) { 155 if (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) { 156 *masked |= HAL_INT_FATAL; 157 } 158 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 159 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RADM CPL timeout\n", 160 __func__); 161 OS_REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 162 OS_REG_WRITE(ah, AR_RC, 0); 163 *masked |= HAL_INT_FATAL; 164 } 165 /* 166 * On fatal errors collect ISR state for debugging. 167 */ 168 if (*masked & HAL_INT_FATAL) { 169 AH_PRIVATE(ah)->ah_fatalState[0] = isr; 170 AH_PRIVATE(ah)->ah_fatalState[1] = sync_cause; 171 HALDEBUG(ah, HAL_DEBUG_ANY, 172 "%s: fatal error, ISR_RAC 0x%x SYNC_CAUSE 0x%x\n", 173 __func__, isr, sync_cause); 174 } 175 176 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 177 /* NB: flush write */ 178 (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); 179 } 180 return AH_TRUE; 181} 182 183/* 184 * Atomically enables NIC interrupts. Interrupts are passed in 185 * via the enumerated bitmask in ints. 186 */ 187HAL_INT 188ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints) 189{ 190 struct ath_hal_5212 *ahp = AH5212(ah); 191 uint32_t omask = ahp->ah_maskReg; 192 uint32_t mask, mask2; 193 194 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n", 195 __func__, omask, ints); 196 197 if (omask & HAL_INT_GLOBAL) { 198 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__); 199 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 200 (void) OS_REG_READ(ah, AR_IER); 201 202 if (! AR_SREV_HOWL(ah)) { 203 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); 204 (void) OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE); 205 206 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 207 (void) OS_REG_READ(ah, AR_INTR_SYNC_ENABLE); 208 } 209 } 210 211 mask = ints & HAL_INT_COMMON; 212 mask2 = 0; 213 214#ifdef AH_AR5416_INTERRUPT_MITIGATION 215 /* 216 * Overwrite default mask if Interrupt mitigation 217 * is specified for AR5416 218 */ 219 mask = ints & HAL_INT_COMMON; 220 if (ints & HAL_INT_TX) 221 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM; 222 if (ints & HAL_INT_RX) 223 mask |= AR_IMR_RXERR | AR_IMR_RXMINTR | AR_IMR_RXINTM; 224 if (ints & HAL_INT_TX) { 225 if (ahp->ah_txErrInterruptMask) 226 mask |= AR_IMR_TXERR; 227 if (ahp->ah_txEolInterruptMask) 228 mask |= AR_IMR_TXEOL; 229 } 230#else 231 if (ints & HAL_INT_TX) { 232 if (ahp->ah_txOkInterruptMask) 233 mask |= AR_IMR_TXOK; 234 if (ahp->ah_txErrInterruptMask) 235 mask |= AR_IMR_TXERR; 236 if (ahp->ah_txDescInterruptMask) 237 mask |= AR_IMR_TXDESC; 238 if (ahp->ah_txEolInterruptMask) 239 mask |= AR_IMR_TXEOL; 240 } 241 if (ints & HAL_INT_RX) 242 mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC; 243#endif 244 if (ints & (HAL_INT_BMISC)) { 245 mask |= AR_IMR_BCNMISC; 246 if (ints & HAL_INT_TIM) 247 mask2 |= AR_IMR_S2_TIM; 248 if (ints & HAL_INT_DTIM) 249 mask2 |= AR_IMR_S2_DTIM; 250 if (ints & HAL_INT_DTIMSYNC) 251 mask2 |= AR_IMR_S2_DTIMSYNC; 252 if (ints & HAL_INT_CABEND) 253 mask2 |= (AR_IMR_S2_CABEND ); 254 if (ints & HAL_INT_CST) 255 mask2 |= AR_IMR_S2_CST; 256 if (ints & HAL_INT_TSFOOR) 257 mask2 |= AR_IMR_S2_TSFOOR; 258 } 259 260 if (ints & (HAL_INT_GTT | HAL_INT_CST)) { 261 mask |= AR_IMR_BCNMISC; 262 if (ints & HAL_INT_GTT) 263 mask2 |= AR_IMR_S2_GTT; 264 if (ints & HAL_INT_CST) 265 mask2 |= AR_IMR_S2_CST; 266 } 267 268 /* Write the new IMR and store off our SW copy. */ 269 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask); 270 OS_REG_WRITE(ah, AR_IMR, mask); 271 mask = OS_REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM | 272 AR_IMR_S2_DTIM | 273 AR_IMR_S2_DTIMSYNC | 274 AR_IMR_S2_CABEND | 275 AR_IMR_S2_CABTO | 276 AR_IMR_S2_TSFOOR | 277 AR_IMR_S2_GTT | 278 AR_IMR_S2_CST); 279 OS_REG_WRITE(ah, AR_IMR_S2, mask | mask2); 280 281 ahp->ah_maskReg = ints; 282 283 /* Re-enable interrupts if they were enabled before. */ 284 if (ints & HAL_INT_GLOBAL) { 285 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__); 286 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 287 288 if (! AR_SREV_HOWL(ah)) { 289 mask = AR_INTR_MAC_IRQ; 290 if (ints & HAL_INT_GPIO) 291 mask |= SM(AH5416(ah)->ah_gpioMask, 292 AR_INTR_ASYNC_MASK_GPIO); 293 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, mask); 294 OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, mask); 295 296 mask = AR_INTR_SYNC_DEFAULT; 297 if (ints & HAL_INT_GPIO) 298 mask |= SM(AH5416(ah)->ah_gpioMask, 299 AR_INTR_SYNC_MASK_GPIO); 300 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, mask); 301 OS_REG_WRITE(ah, AR_INTR_SYNC_MASK, mask); 302 } 303 } 304 305 return omask; 306} 307