1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ar5212/ar5212.h" 26#include "ar5212/ar5212reg.h" 27#include "ar5212/ar5212phy.h" 28 29#define AH_5212_COMMON 30#include "ar5212/ar5212.ini" 31 32static void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 33static void ar5212DisablePCIE(struct ath_hal *ah); 34 35static const struct ath_hal_private ar5212hal = {{ 36 .ah_magic = AR5212_MAGIC, 37 38 .ah_getRateTable = ar5212GetRateTable, 39 .ah_detach = ar5212Detach, 40 41 /* Reset Functions */ 42 .ah_reset = ar5212Reset, 43 .ah_phyDisable = ar5212PhyDisable, 44 .ah_disable = ar5212Disable, 45 .ah_configPCIE = ar5212ConfigPCIE, 46 .ah_disablePCIE = ar5212DisablePCIE, 47 .ah_setPCUConfig = ar5212SetPCUConfig, 48 .ah_perCalibration = ar5212PerCalibration, 49 .ah_perCalibrationN = ar5212PerCalibrationN, 50 .ah_resetCalValid = ar5212ResetCalValid, 51 .ah_setTxPowerLimit = ar5212SetTxPowerLimit, 52 .ah_getChanNoise = ath_hal_getChanNoise, 53 54 /* Transmit functions */ 55 .ah_updateTxTrigLevel = ar5212UpdateTxTrigLevel, 56 .ah_setupTxQueue = ar5212SetupTxQueue, 57 .ah_setTxQueueProps = ar5212SetTxQueueProps, 58 .ah_getTxQueueProps = ar5212GetTxQueueProps, 59 .ah_releaseTxQueue = ar5212ReleaseTxQueue, 60 .ah_resetTxQueue = ar5212ResetTxQueue, 61 .ah_getTxDP = ar5212GetTxDP, 62 .ah_setTxDP = ar5212SetTxDP, 63 .ah_numTxPending = ar5212NumTxPending, 64 .ah_startTxDma = ar5212StartTxDma, 65 .ah_stopTxDma = ar5212StopTxDma, 66 .ah_setupTxDesc = ar5212SetupTxDesc, 67 .ah_setupXTxDesc = ar5212SetupXTxDesc, 68 .ah_fillTxDesc = ar5212FillTxDesc, 69 .ah_procTxDesc = ar5212ProcTxDesc, 70 .ah_getTxIntrQueue = ar5212GetTxIntrQueue, 71 .ah_reqTxIntrDesc = ar5212IntrReqTxDesc, 72 .ah_getTxCompletionRates = ar5212GetTxCompletionRates, 73 74 /* RX Functions */ 75 .ah_getRxDP = ar5212GetRxDP, 76 .ah_setRxDP = ar5212SetRxDP, 77 .ah_enableReceive = ar5212EnableReceive, 78 .ah_stopDmaReceive = ar5212StopDmaReceive, 79 .ah_startPcuReceive = ar5212StartPcuReceive, 80 .ah_stopPcuReceive = ar5212StopPcuReceive, 81 .ah_setMulticastFilter = ar5212SetMulticastFilter, 82 .ah_setMulticastFilterIndex = ar5212SetMulticastFilterIndex, 83 .ah_clrMulticastFilterIndex = ar5212ClrMulticastFilterIndex, 84 .ah_getRxFilter = ar5212GetRxFilter, 85 .ah_setRxFilter = ar5212SetRxFilter, 86 .ah_setupRxDesc = ar5212SetupRxDesc, 87 .ah_procRxDesc = ar5212ProcRxDesc, 88 .ah_rxMonitor = ar5212RxMonitor, 89 .ah_aniPoll = ar5212AniPoll, 90 .ah_procMibEvent = ar5212ProcessMibIntr, 91 92 /* Misc Functions */ 93 .ah_getCapability = ar5212GetCapability, 94 .ah_setCapability = ar5212SetCapability, 95 .ah_getDiagState = ar5212GetDiagState, 96 .ah_getMacAddress = ar5212GetMacAddress, 97 .ah_setMacAddress = ar5212SetMacAddress, 98 .ah_getBssIdMask = ar5212GetBssIdMask, 99 .ah_setBssIdMask = ar5212SetBssIdMask, 100 .ah_setRegulatoryDomain = ar5212SetRegulatoryDomain, 101 .ah_setLedState = ar5212SetLedState, 102 .ah_writeAssocid = ar5212WriteAssocid, 103 .ah_gpioCfgInput = ar5212GpioCfgInput, 104 .ah_gpioCfgOutput = ar5212GpioCfgOutput, 105 .ah_gpioGet = ar5212GpioGet, 106 .ah_gpioSet = ar5212GpioSet, 107 .ah_gpioSetIntr = ar5212GpioSetIntr, 108 .ah_getTsf32 = ar5212GetTsf32, 109 .ah_getTsf64 = ar5212GetTsf64, 110 .ah_resetTsf = ar5212ResetTsf, 111 .ah_detectCardPresent = ar5212DetectCardPresent, 112 .ah_updateMibCounters = ar5212UpdateMibCounters, 113 .ah_getRfGain = ar5212GetRfgain, 114 .ah_getDefAntenna = ar5212GetDefAntenna, 115 .ah_setDefAntenna = ar5212SetDefAntenna, 116 .ah_getAntennaSwitch = ar5212GetAntennaSwitch, 117 .ah_setAntennaSwitch = ar5212SetAntennaSwitch, 118 .ah_setSifsTime = ar5212SetSifsTime, 119 .ah_getSifsTime = ar5212GetSifsTime, 120 .ah_setSlotTime = ar5212SetSlotTime, 121 .ah_getSlotTime = ar5212GetSlotTime, 122 .ah_setAckTimeout = ar5212SetAckTimeout, 123 .ah_getAckTimeout = ar5212GetAckTimeout, 124 .ah_setAckCTSRate = ar5212SetAckCTSRate, 125 .ah_getAckCTSRate = ar5212GetAckCTSRate, 126 .ah_setCTSTimeout = ar5212SetCTSTimeout, 127 .ah_getCTSTimeout = ar5212GetCTSTimeout, 128 .ah_setDecompMask = ar5212SetDecompMask, 129 .ah_setCoverageClass = ar5212SetCoverageClass, 130 .ah_setQuiet = ar5212SetQuiet, 131 132 /* DFS Functions */ 133 .ah_enableDfs = ar5212EnableDfs, 134 .ah_getDfsThresh = ar5212GetDfsThresh, 135 .ah_procRadarEvent = ar5212ProcessRadarEvent, 136 .ah_isFastClockEnabled = ar5212IsFastClockEnabled, 137 138 /* Key Cache Functions */ 139 .ah_getKeyCacheSize = ar5212GetKeyCacheSize, 140 .ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry, 141 .ah_isKeyCacheEntryValid = ar5212IsKeyCacheEntryValid, 142 .ah_setKeyCacheEntry = ar5212SetKeyCacheEntry, 143 .ah_setKeyCacheEntryMac = ar5212SetKeyCacheEntryMac, 144 145 /* Power Management Functions */ 146 .ah_setPowerMode = ar5212SetPowerMode, 147 .ah_getPowerMode = ar5212GetPowerMode, 148 149 /* Beacon Functions */ 150 .ah_setBeaconTimers = ar5212SetBeaconTimers, 151 .ah_beaconInit = ar5212BeaconInit, 152 .ah_setStationBeaconTimers = ar5212SetStaBeaconTimers, 153 .ah_resetStationBeaconTimers = ar5212ResetStaBeaconTimers, 154 .ah_getNextTBTT = ar5212GetNextTBTT, 155 156 /* Interrupt Functions */ 157 .ah_isInterruptPending = ar5212IsInterruptPending, 158 .ah_getPendingInterrupts = ar5212GetPendingInterrupts, 159 .ah_getInterrupts = ar5212GetInterrupts, 160 .ah_setInterrupts = ar5212SetInterrupts }, 161 162 .ah_getChannelEdges = ar5212GetChannelEdges, 163 .ah_getWirelessModes = ar5212GetWirelessModes, 164 .ah_eepromRead = ar5212EepromRead, 165#ifdef AH_SUPPORT_WRITE_EEPROM 166 .ah_eepromWrite = ar5212EepromWrite, 167#endif 168 .ah_getChipPowerLimits = ar5212GetChipPowerLimits, 169}; 170 171uint32_t 172ar5212GetRadioRev(struct ath_hal *ah) 173{ 174 uint32_t val; 175 int i; 176 177 /* Read Radio Chip Rev Extract */ 178 OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16); 179 for (i = 0; i < 8; i++) 180 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 181 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 182 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 183 return ath_hal_reverseBits(val, 8); 184} 185 186static void 187ar5212AniSetup(struct ath_hal *ah) 188{ 189 static const struct ar5212AniParams aniparams = { 190 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 191 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 192 .coarseHigh = { -14, -14, -14, -14, -12 }, 193 .coarseLow = { -64, -64, -64, -64, -70 }, 194 .firpwr = { -78, -78, -78, -78, -80 }, 195 .maxSpurImmunityLevel = 2, /* NB: depends on chip rev */ 196 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 197 .maxFirstepLevel = 2, /* levels 0..2 */ 198 .firstep = { 0, 4, 8 }, 199 .ofdmTrigHigh = 500, 200 .ofdmTrigLow = 200, 201 .cckTrigHigh = 200, 202 .cckTrigLow = 100, 203 .rssiThrHigh = 40, 204 .rssiThrLow = 7, 205 .period = 100, 206 }; 207 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) { 208 struct ar5212AniParams tmp; 209 OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams)); 210 tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */ 211 ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE); 212 } else 213 ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 214 215 /* Set overridable ANI methods */ 216 AH5212(ah)->ah_aniControl = ar5212AniControl; 217} 218 219/* 220 * Attach for an AR5212 part. 221 */ 222void 223ar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc, 224 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 225{ 226#define N(a) (sizeof(a)/sizeof(a[0])) 227 static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] = 228 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 229 struct ath_hal *ah; 230 231 ah = &ahp->ah_priv.h; 232 /* set initial values */ 233 OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private)); 234 ah->ah_sc = sc; 235 ah->ah_st = st; 236 ah->ah_sh = sh; 237 238 ah->ah_devid = devid; /* NB: for alq */ 239 AH_PRIVATE(ah)->ah_devid = devid; 240 AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */ 241 242 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 243 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 244 245 ahp->ah_antControl = HAL_ANT_VARIABLE; 246 ahp->ah_diversity = AH_TRUE; 247 ahp->ah_bIQCalibration = AH_FALSE; 248 /* 249 * Enable MIC handling. 250 */ 251 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 252 ahp->ah_rssiThr = INIT_RSSI_THR; 253 ahp->ah_tpcEnabled = AH_FALSE; /* disabled by default */ 254 ahp->ah_phyPowerOn = AH_FALSE; 255 ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK) 256 | SM(MAX_RATE_POWER, AR_TPC_CTS) 257 | SM(MAX_RATE_POWER, AR_TPC_CHIRP); 258 ahp->ah_beaconInterval = 100; /* XXX [20..1000] */ 259 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */ 260 ahp->ah_slottime = (u_int) -1; 261 ahp->ah_acktimeout = (u_int) -1; 262 ahp->ah_ctstimeout = (u_int) -1; 263 ahp->ah_sifstime = (u_int) -1; 264 ahp->ah_txTrigLev = INIT_TX_FIFO_THRESHOLD, 265 ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD, 266 267 OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN); 268#undef N 269} 270 271/* 272 * Validate MAC version and revision. 273 */ 274static HAL_BOOL 275ar5212IsMacSupported(uint8_t macVersion, uint8_t macRev) 276{ 277#define N(a) (sizeof(a)/sizeof(a[0])) 278 static const struct { 279 uint8_t version; 280 uint8_t revMin, revMax; 281 } macs[] = { 282 { AR_SREV_VERSION_VENICE, 283 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 284 { AR_SREV_VERSION_GRIFFIN, 285 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 286 { AR_SREV_5413, 287 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 288 { AR_SREV_5424, 289 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 290 { AR_SREV_2425, 291 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 292 { AR_SREV_2417, 293 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 294 }; 295 int i; 296 297 for (i = 0; i < N(macs); i++) 298 if (macs[i].version == macVersion && 299 macs[i].revMin <= macRev && macRev <= macs[i].revMax) 300 return AH_TRUE; 301 return AH_FALSE; 302#undef N 303} 304 305/* 306 * Attach for an AR5212 part. 307 */ 308static struct ath_hal * 309ar5212Attach(uint16_t devid, HAL_SOFTC sc, 310 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 311 HAL_STATUS *status) 312{ 313#define AH_EEPROM_PROTECT(ah) \ 314 (AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT) 315 struct ath_hal_5212 *ahp; 316 struct ath_hal *ah; 317 struct ath_hal_rf *rf; 318 uint32_t val; 319 uint16_t eeval; 320 HAL_STATUS ecode; 321 322 HALDEBUG_G(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 323 __func__, sc, (void*) st, (void*) sh); 324 325 /* NB: memory is returned zero'd */ 326 ahp = ath_hal_malloc(sizeof (struct ath_hal_5212)); 327 if (ahp == AH_NULL) { 328 HALDEBUG_G(AH_NULL, HAL_DEBUG_ANY, 329 "%s: cannot allocate memory for state block\n", __func__); 330 *status = HAL_ENOMEM; 331 return AH_NULL; 332 } 333 ar5212InitState(ahp, devid, sc, st, sh, status); 334 ah = &ahp->ah_priv.h; 335 336 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 337 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 338 __func__); 339 ecode = HAL_EIO; 340 goto bad; 341 } 342 /* Read Revisions from Chips before taking out of reset */ 343 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 344 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 345 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 346 AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah); 347 348 if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) { 349 HALDEBUG(ah, HAL_DEBUG_ANY, 350 "%s: Mac Chip Rev 0x%02x.%x not supported\n" , 351 __func__, AH_PRIVATE(ah)->ah_macVersion, 352 AH_PRIVATE(ah)->ah_macRev); 353 ecode = HAL_ENOTSUPP; 354 goto bad; 355 } 356 357 /* setup common ini data; rf backends handle remainder */ 358 HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6); 359 HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2); 360 361 if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */ 362 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 363 ecode = HAL_EIO; 364 goto bad; 365 } 366 367 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 368 369 if (AH_PRIVATE(ah)->ah_ispcie) { 370 /* XXX: build flag to disable this? */ 371 ath_hal_configPCIE(ah, AH_FALSE); 372 } 373 374 if (!ar5212ChipTest(ah)) { 375 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 376 __func__); 377 ecode = HAL_ESELFTEST; 378 goto bad; 379 } 380 381 /* Enable PCI core retry fix in software for Hainan and up */ 382 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE) 383 OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN); 384 385 /* 386 * Set correct Baseband to analog shift 387 * setting to access analog chips. 388 */ 389 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 390 391 /* Read Radio Chip Rev Extract */ 392 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 393 394 rf = ath_hal_rfprobe(ah, &ecode); 395 if (rf == AH_NULL) 396 goto bad; 397 398 /* NB: silently accept anything in release code per Atheros */ 399 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 400 case AR_RAD5111_SREV_MAJOR: 401 case AR_RAD5112_SREV_MAJOR: 402 case AR_RAD2112_SREV_MAJOR: 403 case AR_RAD2111_SREV_MAJOR: 404 case AR_RAD2413_SREV_MAJOR: 405 case AR_RAD5413_SREV_MAJOR: 406 case AR_RAD5424_SREV_MAJOR: 407 break; 408 default: 409 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 410 /* 411 * When RF_Silent is used, the 412 * analog chip is reset. So when the system boots 413 * up with the radio switch off we cannot determine 414 * the RF chip rev. To workaround this check the 415 * mac+phy revs and if Hainan, set the radio rev 416 * to Derby. 417 */ 418 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 419 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN && 420 AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) { 421 AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN; 422 break; 423 } 424 if (IS_2413(ah)) { /* Griffin */ 425 AH_PRIVATE(ah)->ah_analog5GhzRev = 426 AR_RAD2413_SREV_MAJOR | 0x1; 427 break; 428 } 429 if (IS_5413(ah)) { /* Eagle */ 430 AH_PRIVATE(ah)->ah_analog5GhzRev = 431 AR_RAD5413_SREV_MAJOR | 0x2; 432 break; 433 } 434 if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */ 435 AH_PRIVATE(ah)->ah_analog5GhzRev = 436 AR_RAD5424_SREV_MAJOR | 0x2; 437 break; 438 } 439 } 440#ifdef AH_DEBUG 441 HALDEBUG(ah, HAL_DEBUG_ANY, 442 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 443 "this driver\n", 444 __func__, AH_PRIVATE(ah)->ah_analog5GhzRev); 445 ecode = HAL_ENOTSUPP; 446 goto bad; 447#endif 448 } 449 if (IS_RAD5112_REV1(ah)) { 450 HALDEBUG(ah, HAL_DEBUG_ANY, 451 "%s: 5112 Rev 1 is not supported by this " 452 "driver (analog5GhzRev 0x%x)\n", __func__, 453 AH_PRIVATE(ah)->ah_analog5GhzRev); 454 ecode = HAL_ENOTSUPP; 455 goto bad; 456 } 457 458 val = OS_REG_READ(ah, AR_PCICFG); 459 val = MS(val, AR_PCICFG_EEPROM_SIZE); 460 if (val == 0) { 461 if (!AH_PRIVATE(ah)->ah_ispcie) { 462 HALDEBUG(ah, HAL_DEBUG_ANY, 463 "%s: unsupported EEPROM size %u (0x%x) found\n", 464 __func__, val, val); 465 ecode = HAL_EESIZE; 466 goto bad; 467 } 468 /* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */ 469 } else if (val != AR_PCICFG_EEPROM_SIZE_16K) { 470 if (AR_PCICFG_EEPROM_SIZE_FAILED == val) { 471 HALDEBUG(ah, HAL_DEBUG_ANY, 472 "%s: unsupported EEPROM size %u (0x%x) found\n", 473 __func__, val, val); 474 ecode = HAL_EESIZE; 475 goto bad; 476 } 477 HALDEBUG(ah, HAL_DEBUG_ANY, 478 "%s: EEPROM size = %d. Must be %d (16k).\n", 479 __func__, val, AR_PCICFG_EEPROM_SIZE_16K); 480 ecode = HAL_EESIZE; 481 goto bad; 482 } 483 ecode = ath_hal_legacyEepromAttach(ah); 484 if (ecode != HAL_OK) { 485 goto bad; 486 } 487 ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON); 488 489 /* 490 * If Bmode and AR5212, verify 2.4 analog exists 491 */ 492 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) && 493 (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) { 494 /* 495 * Set correct Baseband to analog shift 496 * setting to access analog chips. 497 */ 498 OS_REG_WRITE(ah, AR_PHY(0), 0x00004007); 499 OS_DELAY(2000); 500 AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah); 501 502 /* Set baseband for 5GHz chip */ 503 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 504 OS_DELAY(2000); 505 if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) { 506 HALDEBUG(ah, HAL_DEBUG_ANY, 507 "%s: 2G Radio Chip Rev 0x%02X is not " 508 "supported by this driver\n", __func__, 509 AH_PRIVATE(ah)->ah_analog2GhzRev); 510 ecode = HAL_ENOTSUPP; 511 goto bad; 512 } 513 } 514 515 ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval); 516 if (ecode != HAL_OK) { 517 HALDEBUG(ah, HAL_DEBUG_ANY, 518 "%s: cannot read regulatory domain from EEPROM\n", 519 __func__); 520 goto bad; 521 } 522 AH_PRIVATE(ah)->ah_currentRD = eeval; 523 /* XXX record serial number */ 524 525 /* 526 * Got everything we need now to setup the capabilities. 527 */ 528 if (!ar5212FillCapabilityInfo(ah)) { 529 HALDEBUG(ah, HAL_DEBUG_ANY, 530 "%s: failed ar5212FillCapabilityInfo\n", __func__); 531 ecode = HAL_EEREAD; 532 goto bad; 533 } 534 535 if (!rf->attach(ah, &ecode)) { 536 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 537 __func__, ecode); 538 goto bad; 539 } 540 /* 541 * Set noise floor adjust method; we arrange a 542 * direct call instead of thunking. 543 */ 544 AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust; 545 546 /* Initialize gain ladder thermal calibration structure */ 547 ar5212InitializeGainValues(ah); 548 549 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 550 if (ecode != HAL_OK) { 551 HALDEBUG(ah, HAL_DEBUG_ANY, 552 "%s: error getting mac address from EEPROM\n", __func__); 553 goto bad; 554 } 555 556 ar5212AniSetup(ah); 557 /* Setup of Radar/AR structures happens in ath_hal_initchannels*/ 558 ar5212InitNfCalHistBuffer(ah); 559 560 /* XXX EAR stuff goes here */ 561 562 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 563 564 return ah; 565 566bad: 567 if (ahp) 568 ar5212Detach((struct ath_hal *) ahp); 569 if (status) 570 *status = ecode; 571 return AH_NULL; 572#undef AH_EEPROM_PROTECT 573} 574 575void 576ar5212Detach(struct ath_hal *ah) 577{ 578 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 579 580 HALASSERT(ah != AH_NULL); 581 HALASSERT(ah->ah_magic == AR5212_MAGIC); 582 583 ar5212AniDetach(ah); 584 ar5212RfDetach(ah); 585 ar5212Disable(ah); 586 ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 587 588 ath_hal_eepromDetach(ah); 589 ath_hal_free(ah); 590} 591 592HAL_BOOL 593ar5212ChipTest(struct ath_hal *ah) 594{ 595 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; 596 uint32_t regHold[2]; 597 uint32_t patternData[4] = 598 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 599 int i, j; 600 601 /* Test PHY & MAC registers */ 602 for (i = 0; i < 2; i++) { 603 uint32_t addr = regAddr[i]; 604 uint32_t wrData, rdData; 605 606 regHold[i] = OS_REG_READ(ah, addr); 607 for (j = 0; j < 0x100; j++) { 608 wrData = (j << 16) | j; 609 OS_REG_WRITE(ah, addr, wrData); 610 rdData = OS_REG_READ(ah, addr); 611 if (rdData != wrData) { 612 HALDEBUG(ah, HAL_DEBUG_ANY, 613"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 614 __func__, addr, wrData, rdData); 615 return AH_FALSE; 616 } 617 } 618 for (j = 0; j < 4; j++) { 619 wrData = patternData[j]; 620 OS_REG_WRITE(ah, addr, wrData); 621 rdData = OS_REG_READ(ah, addr); 622 if (wrData != rdData) { 623 HALDEBUG(ah, HAL_DEBUG_ANY, 624"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 625 __func__, addr, wrData, rdData); 626 return AH_FALSE; 627 } 628 } 629 OS_REG_WRITE(ah, regAddr[i], regHold[i]); 630 } 631 OS_DELAY(100); 632 return AH_TRUE; 633} 634 635/* 636 * Store the channel edges for the requested operational mode 637 */ 638HAL_BOOL 639ar5212GetChannelEdges(struct ath_hal *ah, 640 uint16_t flags, uint16_t *low, uint16_t *high) 641{ 642 if (flags & IEEE80211_CHAN_5GHZ) { 643 *low = 4915; 644 *high = 6100; 645 return AH_TRUE; 646 } 647 if ((flags & IEEE80211_CHAN_2GHZ) && 648 (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) || 649 ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) { 650 *low = 2312; 651 *high = 2732; 652 return AH_TRUE; 653 } 654 return AH_FALSE; 655} 656 657/* 658 * Disable PLL when in L0s as well as receiver clock when in L1. 659 * This power saving option must be enabled through the Serdes. 660 * 661 * Programming the Serdes must go through the same 288 bit serial shift 662 * register as the other analog registers. Hence the 9 writes. 663 * 664 * XXX Clean up the magic numbers. 665 */ 666static void 667ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 668{ 669 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 670 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 671 672 /* RX shut off when elecidle is asserted */ 673 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 674 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 675 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 676 677 /* Shut off PLL and CLKREQ active in L1 */ 678 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 679 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 680 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 681 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 682 683 /* Load the new settings */ 684 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 685} 686 687static void 688ar5212DisablePCIE(struct ath_hal *ah) 689{ 690 /* NB: fill in for 9100 */ 691} 692 693/* 694 * Fill all software cached or static hardware state information. 695 * Return failure if capabilities are to come from EEPROM and 696 * cannot be read. 697 */ 698HAL_BOOL 699ar5212FillCapabilityInfo(struct ath_hal *ah) 700{ 701#define AR_KEYTABLE_SIZE 128 702#define IS_GRIFFIN_LITE(ah) \ 703 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \ 704 AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE) 705#define IS_COBRA(ah) \ 706 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA) 707#define IS_2112(ah) \ 708 ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR) 709 710 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 711 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 712 uint16_t capField, val; 713 714 /* Read the capability EEPROM location */ 715 if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) { 716 HALDEBUG(ah, HAL_DEBUG_ANY, 717 "%s: unable to read caps from eeprom\n", __func__); 718 return AH_FALSE; 719 } 720 if (IS_2112(ah)) 721 ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE); 722 if (capField == 0 && IS_GRIFFIN_LITE(ah)) { 723 /* 724 * For griffin-lite cards with unprogrammed capabilities. 725 */ 726 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 727 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 728 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 729 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 730 HALDEBUG(ah, HAL_DEBUG_ATTACH, 731 "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n", 732 __func__, capField); 733 } 734 735 /* Modify reg domain on newer cards that need to work with older sw */ 736 if (ahpriv->ah_opmode != HAL_M_HOSTAP && 737 ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { 738 if (ahpriv->ah_currentRD == 0x64 || 739 ahpriv->ah_currentRD == 0x65) 740 ahpriv->ah_currentRD += 5; 741 else if (ahpriv->ah_currentRD == 0x41) 742 ahpriv->ah_currentRD = 0x43; 743 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n", 744 __func__, ahpriv->ah_currentRD); 745 } 746 747 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 || 748 AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) { 749 HALDEBUG(ah, HAL_DEBUG_ATTACH, 750 "%s: enable Bmode and disable turbo for Swan/Nala\n", 751 __func__); 752 ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE); 753 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 754 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 755 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 756 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 757 } 758 759 /* Construct wireless mode from EEPROM */ 760 pCap->halWirelessModes = 0; 761 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 762 pCap->halWirelessModes |= HAL_MODE_11A; 763 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) 764 pCap->halWirelessModes |= HAL_MODE_TURBO; 765 } 766 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) 767 pCap->halWirelessModes |= HAL_MODE_11B; 768 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) && 769 ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) { 770 pCap->halWirelessModes |= HAL_MODE_11G; 771 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE)) 772 pCap->halWirelessModes |= HAL_MODE_108G; 773 } 774 775 pCap->halLow2GhzChan = 2312; 776 /* XXX 2417 too? */ 777 if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah)) 778 pCap->halHigh2GhzChan = 2500; 779 else 780 pCap->halHigh2GhzChan = 2732; 781 782 pCap->halLow5GhzChan = 4915; 783 pCap->halHigh5GhzChan = 6100; 784 785 pCap->halCipherCkipSupport = AH_FALSE; 786 pCap->halCipherTkipSupport = AH_TRUE; 787 pCap->halCipherAesCcmSupport = 788 (ath_hal_eepromGetFlag(ah, AR_EEP_AES) && 789 ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) || 790 ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) && 791 (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU)))); 792 793 pCap->halMicCkipSupport = AH_FALSE; 794 pCap->halMicTkipSupport = AH_TRUE; 795 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 796 /* 797 * Starting with Griffin TX+RX mic keys can be combined 798 * in one key cache slot. 799 */ 800 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN) 801 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 802 else 803 pCap->halTkipMicTxRxKeySupport = AH_FALSE; 804 pCap->halChanSpreadSupport = AH_TRUE; 805 pCap->halSleepAfterBeaconBroken = AH_TRUE; 806 807 if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) { 808 pCap->halCompressSupport = 809 ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) && 810 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 811 pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST); 812 pCap->halFastFramesSupport = 813 ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) && 814 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 815 pCap->halChapTuningSupport = AH_TRUE; 816 pCap->halTurboPrimeSupport = AH_TRUE; 817 } 818 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 819 820 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 821 pCap->halVEOLSupport = AH_TRUE; 822 pCap->halBssIdMaskSupport = AH_TRUE; 823 pCap->halMcastKeySrchSupport = AH_TRUE; 824 if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE && 825 ahpriv->ah_macRev == 8) || 826 ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE) 827 pCap->halTsfAddSupport = AH_TRUE; 828 829 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 830 pCap->halTotalQueues = val; 831 else 832 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 833 834 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 835 pCap->halKeyCacheSize = val; 836 else 837 pCap->halKeyCacheSize = AR_KEYTABLE_SIZE; 838 839 pCap->halChanHalfRate = AH_TRUE; 840 pCap->halChanQuarterRate = AH_TRUE; 841 842 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 843 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 844 /* NB: enabled by default */ 845 ahpriv->ah_rfkillEnabled = AH_TRUE; 846 pCap->halRfSilentSupport = AH_TRUE; 847 } 848 849 /* NB: this is a guess, noone seems to know the answer */ 850 ahpriv->ah_rxornIsFatal = 851 (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE); 852 853 /* enable features that first appeared in Hainan */ 854 if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 855 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) || 856 AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) { 857 /* h/w phy counters */ 858 pCap->halHwPhyCounterSupport = AH_TRUE; 859 /* bssid match disable */ 860 pCap->halBssidMatchSupport = AH_TRUE; 861 } 862 863 pCap->halTstampPrecision = 15; 864 pCap->halIntrMask = HAL_INT_COMMON 865 | HAL_INT_RX 866 | HAL_INT_TX 867 | HAL_INT_FATAL 868 | HAL_INT_BNR 869 | HAL_INT_BMISC 870 ; 871 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) 872 pCap->halIntrMask &= ~HAL_INT_TBTT; 873 874 pCap->hal4kbSplitTransSupport = AH_TRUE; 875 pCap->halHasRxSelfLinkedTail = AH_TRUE; 876 877 return AH_TRUE; 878#undef IS_COBRA 879#undef IS_GRIFFIN_LITE 880#undef AR_KEYTABLE_SIZE 881} 882 883static const char* 884ar5212Probe(uint16_t vendorid, uint16_t devid) 885{ 886 if (vendorid == ATHEROS_VENDOR_ID || 887 vendorid == ATHEROS_3COM_VENDOR_ID || 888 vendorid == ATHEROS_3COM2_VENDOR_ID) { 889 switch (devid) { 890 case AR5212_FPGA: 891 return "Atheros 5212 (FPGA)"; 892 case AR5212_DEVID: 893 case AR5212_DEVID_IBM: 894 case AR5212_DEFAULT: 895 return "Atheros 5212"; 896 case AR5212_AR2413: 897 return "Atheros 2413"; 898 case AR5212_AR2417: 899 return "Atheros 2417"; 900 case AR5212_AR5413: 901 return "Atheros 5413"; 902 case AR5212_AR5424: 903 return "Atheros 5424/2424"; 904 } 905 } 906 return AH_NULL; 907} 908AH_CHIP(AR5212, ar5212Probe, ar5212Attach); 909