1/*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD$
18 */
19#ifndef _ATH_AH_EEPROM_V1_H_
20#define _ATH_AH_EEPROM_V1_H_
21
22#include "ah_eeprom.h"
23
24/*
25 * EEPROM defines for Version 1 Crete EEPROM.
26 *
27 * The EEPROM is segmented into three sections:
28 *
29 *    PCI/Cardbus default configuration settings
30 *    Cardbus CIS tuples and vendor-specific data
31 *    Atheros-specific data
32 *
33 * EEPROM entries are read 32-bits at a time through the PCI bus
34 * interface but are all 16-bit values.
35 *
36 * Access to the Atheros-specific data is controlled by protection
37 * bits and the data is checksum'd.  The driver reads the Atheros
38 * data from the EEPROM at attach and caches it in its private state.
39 * This data includes the local regulatory domain, channel calibration
40 * settings, and phy-related configuration settings.
41 */
42#define	AR_EEPROM_MAC(i)	(0x1f-(i))/* MAC address word */
43#define	AR_EEPROM_MAGIC		0x3d	/* magic number */
44#define AR_EEPROM_PROTECT	0x3f	/* Atheros segment protect register */
45#define	AR_EEPROM_PROTOTECT_WP_128_191	0x80
46#define AR_EEPROM_REG_DOMAIN	0xbf	/* Current regulatory domain register */
47#define AR_EEPROM_ATHEROS_BASE	0xc0	/* Base of Atheros-specific data */
48#define AR_EEPROM_ATHEROS_MAX	64	/* 64x2=128 bytes of EEPROM settings */
49#define	AR_EEPROM_ATHEROS(n)	(AR_EEPROM_ATHEROS_BASE+(n))
50#define	AR_EEPROM_VERSION	AR_EEPROM_ATHEROS(1)
51#define AR_EEPROM_ATHEROS_TP_SETTINGS	0x09	/* Transmit power settings */
52#define AR_REG_DOMAINS_MAX	4	/* # of Regulatory Domains */
53#define AR_CHANNELS_MAX		5	/* # of Channel calibration groups */
54#define AR_TP_SETTINGS_SIZE	11	/* # locations/Channel group */
55#define AR_TP_SCALING_ENTRIES	11	/* # entries in transmit power dBm->pcdac */
56
57/*
58 * NB: we store the rfsilent select+polarity data packed
59 *     with the encoding used in later parts so values
60 *     returned to applications are consistent.
61 */
62#define AR_EEPROM_RFSILENT_GPIO_SEL	0x001c
63#define AR_EEPROM_RFSILENT_GPIO_SEL_S	2
64#define AR_EEPROM_RFSILENT_POLARITY	0x0002
65#define AR_EEPROM_RFSILENT_POLARITY_S	1
66
67#define AR_I2DBM(x)	((uint8_t)((x * 2) + 3))
68
69/*
70 * Transmit power and channel calibration settings.
71 */
72struct tpcMap {
73	uint8_t		pcdac[AR_TP_SCALING_ENTRIES];
74	uint8_t		gainF[AR_TP_SCALING_ENTRIES];
75	uint8_t		rate36;
76	uint8_t		rate48;
77	uint8_t		rate54;
78	uint8_t		regdmn[AR_REG_DOMAINS_MAX];
79};
80
81/*
82 * Information retrieved from EEPROM.
83 */
84typedef struct {
85	uint16_t	ee_version;		/* Version field */
86	uint16_t	ee_protect;		/* EEPROM protect field */
87	uint16_t	ee_antenna;		/* Antenna Settings */
88	uint16_t	ee_biasCurrents;	/* OB, DB */
89	uint8_t		ee_thresh62;		/* thresh62 */
90	uint8_t		ee_xlnaOn;		/* External LNA timing */
91	uint8_t		ee_xpaOff;		/* Extern output stage timing */
92	uint8_t		ee_xpaOn;		/* Extern output stage timing */
93	uint8_t		ee_rfKill;		/* Single low bit signalling if RF Kill is implemented */
94	uint8_t		ee_devType;		/* Type: PCI, miniPCI, CB */
95	uint8_t		ee_regDomain[AR_REG_DOMAINS_MAX];
96						/* calibrated reg domains */
97	struct tpcMap	ee_tpc[AR_CHANNELS_MAX];
98} HAL_EEPROM_v1;
99#endif /* _ATH_AH_EEPROM_V1_H_ */
100