1/****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11/****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48/*- 49 * Copyright (c) 1997, 1998, 1999, 2000 50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by Bill Paul. 63 * 4. Neither the name of the author nor the names of any co-contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77 * THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79/*- 80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 81 * 82 * Permission to use, copy, modify, and distribute this software for any 83 * purpose with or without fee is hereby granted, provided that the above 84 * copyright notice and this permission notice appear in all copies. 85 * 86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 93 */ 94 95/* 96 * Device driver for the Marvell Yukon II Ethernet controller. 97 * Due to lack of documentation, this driver is based on the code from 98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 99 */ 100 101#include <sys/cdefs.h> 102__FBSDID("$FreeBSD$"); 103 104#include <sys/param.h> 105#include <sys/systm.h> 106#include <sys/bus.h> 107#include <sys/endian.h> 108#include <sys/mbuf.h> 109#include <sys/malloc.h> 110#include <sys/kernel.h> 111#include <sys/module.h> 112#include <sys/socket.h> 113#include <sys/sockio.h> 114#include <sys/queue.h> 115#include <sys/sysctl.h> 116 117#include <net/bpf.h> 118#include <net/ethernet.h> 119#include <net/if.h> 120#include <net/if_arp.h> 121#include <net/if_dl.h> 122#include <net/if_media.h> 123#include <net/if_types.h> 124#include <net/if_vlan_var.h> 125 126#include <netinet/in.h> 127#include <netinet/in_systm.h> 128#include <netinet/ip.h> 129#include <netinet/tcp.h> 130#include <netinet/udp.h> 131 132#include <machine/bus.h> 133#include <machine/in_cksum.h> 134#include <machine/resource.h> 135#include <sys/rman.h> 136 137#include <dev/mii/mii.h> 138#include <dev/mii/miivar.h> 139 140#include <dev/pci/pcireg.h> 141#include <dev/pci/pcivar.h> 142 143#include <dev/msk/if_mskreg.h> 144 145MODULE_DEPEND(msk, pci, 1, 1, 1); 146MODULE_DEPEND(msk, ether, 1, 1, 1); 147MODULE_DEPEND(msk, miibus, 1, 1, 1); 148 149/* "device miibus" required. See GENERIC if you get errors here. */ 150#include "miibus_if.h" 151 152/* Tunables. */ 153static int msi_disable = 0; 154TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 155static int legacy_intr = 0; 156TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 157static int jumbo_disable = 0; 158TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable); 159 160#define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 161 162/* 163 * Devices supported by this driver. 164 */ 165static struct msk_product { 166 uint16_t msk_vendorid; 167 uint16_t msk_deviceid; 168 const char *msk_name; 169} msk_products[] = { 170 { VENDORID_SK, DEVICEID_SK_YUKON2, 171 "SK-9Sxx Gigabit Ethernet" }, 172 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 173 "SK-9Exx Gigabit Ethernet"}, 174 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 175 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 176 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 177 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 178 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 179 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 180 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 181 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 182 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 183 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 184 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 185 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 186 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 187 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 188 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 189 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 190 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 191 "Marvell Yukon 88E8035 Fast Ethernet" }, 192 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 193 "Marvell Yukon 88E8036 Fast Ethernet" }, 194 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 195 "Marvell Yukon 88E8038 Fast Ethernet" }, 196 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 197 "Marvell Yukon 88E8039 Fast Ethernet" }, 198 { VENDORID_MARVELL, DEVICEID_MRVL_8040, 199 "Marvell Yukon 88E8040 Fast Ethernet" }, 200 { VENDORID_MARVELL, DEVICEID_MRVL_8040T, 201 "Marvell Yukon 88E8040T Fast Ethernet" }, 202 { VENDORID_MARVELL, DEVICEID_MRVL_8042, 203 "Marvell Yukon 88E8042 Fast Ethernet" }, 204 { VENDORID_MARVELL, DEVICEID_MRVL_8048, 205 "Marvell Yukon 88E8048 Fast Ethernet" }, 206 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 207 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 208 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 209 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 210 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 211 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 212 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 213 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 214 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 215 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 216 { VENDORID_MARVELL, DEVICEID_MRVL_4365, 217 "Marvell Yukon 88E8070 Gigabit Ethernet" }, 218 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 219 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 220 { VENDORID_MARVELL, DEVICEID_MRVL_436B, 221 "Marvell Yukon 88E8071 Gigabit Ethernet" }, 222 { VENDORID_MARVELL, DEVICEID_MRVL_436C, 223 "Marvell Yukon 88E8072 Gigabit Ethernet" }, 224 { VENDORID_MARVELL, DEVICEID_MRVL_436D, 225 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 226 { VENDORID_MARVELL, DEVICEID_MRVL_4370, 227 "Marvell Yukon 88E8075 Gigabit Ethernet" }, 228 { VENDORID_MARVELL, DEVICEID_MRVL_4380, 229 "Marvell Yukon 88E8057 Gigabit Ethernet" }, 230 { VENDORID_MARVELL, DEVICEID_MRVL_4381, 231 "Marvell Yukon 88E8059 Gigabit Ethernet" }, 232 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 233 "D-Link 550SX Gigabit Ethernet" }, 234 { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX, 235 "D-Link 560SX Gigabit Ethernet" }, 236 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 237 "D-Link 560T Gigabit Ethernet" } 238}; 239 240static const char *model_name[] = { 241 "Yukon XL", 242 "Yukon EC Ultra", 243 "Yukon EX", 244 "Yukon EC", 245 "Yukon FE", 246 "Yukon FE+", 247 "Yukon Supreme", 248 "Yukon Ultra 2", 249 "Yukon Unknown", 250 "Yukon Optima", 251}; 252 253static int mskc_probe(device_t); 254static int mskc_attach(device_t); 255static int mskc_detach(device_t); 256static int mskc_shutdown(device_t); 257static int mskc_setup_rambuffer(struct msk_softc *); 258static int mskc_suspend(device_t); 259static int mskc_resume(device_t); 260static void mskc_reset(struct msk_softc *); 261 262static int msk_probe(device_t); 263static int msk_attach(device_t); 264static int msk_detach(device_t); 265 266static void msk_tick(void *); 267static void msk_intr(void *); 268static void msk_intr_phy(struct msk_if_softc *); 269static void msk_intr_gmac(struct msk_if_softc *); 270static __inline void msk_rxput(struct msk_if_softc *); 271static int msk_handle_events(struct msk_softc *); 272static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 273static void msk_intr_hwerr(struct msk_softc *); 274#ifndef __NO_STRICT_ALIGNMENT 275static __inline void msk_fixup_rx(struct mbuf *); 276#endif 277static __inline void msk_rxcsum(struct msk_if_softc *, uint32_t, struct mbuf *); 278static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 279static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 280static void msk_txeof(struct msk_if_softc *, int); 281static int msk_encap(struct msk_if_softc *, struct mbuf **); 282static void msk_start(struct ifnet *); 283static void msk_start_locked(struct ifnet *); 284static int msk_ioctl(struct ifnet *, u_long, caddr_t); 285static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 286static void msk_set_rambuffer(struct msk_if_softc *); 287static void msk_set_tx_stfwd(struct msk_if_softc *); 288static void msk_init(void *); 289static void msk_init_locked(struct msk_if_softc *); 290static void msk_stop(struct msk_if_softc *); 291static void msk_watchdog(struct msk_if_softc *); 292static int msk_mediachange(struct ifnet *); 293static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 294static void msk_phy_power(struct msk_softc *, int); 295static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 296static int msk_status_dma_alloc(struct msk_softc *); 297static void msk_status_dma_free(struct msk_softc *); 298static int msk_txrx_dma_alloc(struct msk_if_softc *); 299static int msk_rx_dma_jalloc(struct msk_if_softc *); 300static void msk_txrx_dma_free(struct msk_if_softc *); 301static void msk_rx_dma_jfree(struct msk_if_softc *); 302static int msk_rx_fill(struct msk_if_softc *, int); 303static int msk_init_rx_ring(struct msk_if_softc *); 304static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 305static void msk_init_tx_ring(struct msk_if_softc *); 306static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 307static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 308static int msk_newbuf(struct msk_if_softc *, int); 309static int msk_jumbo_newbuf(struct msk_if_softc *, int); 310 311static int msk_phy_readreg(struct msk_if_softc *, int, int); 312static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 313static int msk_miibus_readreg(device_t, int, int); 314static int msk_miibus_writereg(device_t, int, int, int); 315static void msk_miibus_statchg(device_t); 316 317static void msk_rxfilter(struct msk_if_softc *); 318static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 319 320static void msk_stats_clear(struct msk_if_softc *); 321static void msk_stats_update(struct msk_if_softc *); 322static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS); 323static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS); 324static void msk_sysctl_node(struct msk_if_softc *); 325static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 326static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 327 328static device_method_t mskc_methods[] = { 329 /* Device interface */ 330 DEVMETHOD(device_probe, mskc_probe), 331 DEVMETHOD(device_attach, mskc_attach), 332 DEVMETHOD(device_detach, mskc_detach), 333 DEVMETHOD(device_suspend, mskc_suspend), 334 DEVMETHOD(device_resume, mskc_resume), 335 DEVMETHOD(device_shutdown, mskc_shutdown), 336 337 DEVMETHOD_END 338}; 339 340static driver_t mskc_driver = { 341 "mskc", 342 mskc_methods, 343 sizeof(struct msk_softc) 344}; 345 346static devclass_t mskc_devclass; 347 348static device_method_t msk_methods[] = { 349 /* Device interface */ 350 DEVMETHOD(device_probe, msk_probe), 351 DEVMETHOD(device_attach, msk_attach), 352 DEVMETHOD(device_detach, msk_detach), 353 DEVMETHOD(device_shutdown, bus_generic_shutdown), 354 355 /* MII interface */ 356 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 357 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 358 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 359 360 DEVMETHOD_END 361}; 362 363static driver_t msk_driver = { 364 "msk", 365 msk_methods, 366 sizeof(struct msk_if_softc) 367}; 368 369static devclass_t msk_devclass; 370 371DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0); 372DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0); 373DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0); 374 375static struct resource_spec msk_res_spec_io[] = { 376 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 377 { -1, 0, 0 } 378}; 379 380static struct resource_spec msk_res_spec_mem[] = { 381 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 382 { -1, 0, 0 } 383}; 384 385static struct resource_spec msk_irq_spec_legacy[] = { 386 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 387 { -1, 0, 0 } 388}; 389 390static struct resource_spec msk_irq_spec_msi[] = { 391 { SYS_RES_IRQ, 1, RF_ACTIVE }, 392 { -1, 0, 0 } 393}; 394 395static int 396msk_miibus_readreg(device_t dev, int phy, int reg) 397{ 398 struct msk_if_softc *sc_if; 399 400 sc_if = device_get_softc(dev); 401 402 return (msk_phy_readreg(sc_if, phy, reg)); 403} 404 405static int 406msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 407{ 408 struct msk_softc *sc; 409 int i, val; 410 411 sc = sc_if->msk_softc; 412 413 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 414 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 415 416 for (i = 0; i < MSK_TIMEOUT; i++) { 417 DELAY(1); 418 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 419 if ((val & GM_SMI_CT_RD_VAL) != 0) { 420 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 421 break; 422 } 423 } 424 425 if (i == MSK_TIMEOUT) { 426 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 427 val = 0; 428 } 429 430 return (val); 431} 432 433static int 434msk_miibus_writereg(device_t dev, int phy, int reg, int val) 435{ 436 struct msk_if_softc *sc_if; 437 438 sc_if = device_get_softc(dev); 439 440 return (msk_phy_writereg(sc_if, phy, reg, val)); 441} 442 443static int 444msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 445{ 446 struct msk_softc *sc; 447 int i; 448 449 sc = sc_if->msk_softc; 450 451 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 452 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 453 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 454 for (i = 0; i < MSK_TIMEOUT; i++) { 455 DELAY(1); 456 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 457 GM_SMI_CT_BUSY) == 0) 458 break; 459 } 460 if (i == MSK_TIMEOUT) 461 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 462 463 return (0); 464} 465 466static void 467msk_miibus_statchg(device_t dev) 468{ 469 struct msk_softc *sc; 470 struct msk_if_softc *sc_if; 471 struct mii_data *mii; 472 struct ifnet *ifp; 473 uint32_t gmac; 474 475 sc_if = device_get_softc(dev); 476 sc = sc_if->msk_softc; 477 478 MSK_IF_LOCK_ASSERT(sc_if); 479 480 mii = device_get_softc(sc_if->msk_miibus); 481 ifp = sc_if->msk_ifp; 482 if (mii == NULL || ifp == NULL || 483 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 484 return; 485 486 sc_if->msk_flags &= ~MSK_FLAG_LINK; 487 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 488 (IFM_AVALID | IFM_ACTIVE)) { 489 switch (IFM_SUBTYPE(mii->mii_media_active)) { 490 case IFM_10_T: 491 case IFM_100_TX: 492 sc_if->msk_flags |= MSK_FLAG_LINK; 493 break; 494 case IFM_1000_T: 495 case IFM_1000_SX: 496 case IFM_1000_LX: 497 case IFM_1000_CX: 498 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) 499 sc_if->msk_flags |= MSK_FLAG_LINK; 500 break; 501 default: 502 break; 503 } 504 } 505 506 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) { 507 /* Enable Tx FIFO Underrun. */ 508 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 509 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 510 /* 511 * Because mii(4) notify msk(4) that it detected link status 512 * change, there is no need to enable automatic 513 * speed/flow-control/duplex updates. 514 */ 515 gmac = GM_GPCR_AU_ALL_DIS; 516 switch (IFM_SUBTYPE(mii->mii_media_active)) { 517 case IFM_1000_SX: 518 case IFM_1000_T: 519 gmac |= GM_GPCR_SPEED_1000; 520 break; 521 case IFM_100_TX: 522 gmac |= GM_GPCR_SPEED_100; 523 break; 524 case IFM_10_T: 525 break; 526 } 527 528 if ((IFM_OPTIONS(mii->mii_media_active) & 529 IFM_ETH_RXPAUSE) == 0) 530 gmac |= GM_GPCR_FC_RX_DIS; 531 if ((IFM_OPTIONS(mii->mii_media_active) & 532 IFM_ETH_TXPAUSE) == 0) 533 gmac |= GM_GPCR_FC_TX_DIS; 534 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 535 gmac |= GM_GPCR_DUP_FULL; 536 else 537 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS; 538 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 539 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 540 /* Read again to ensure writing. */ 541 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 542 gmac = GMC_PAUSE_OFF; 543 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 544 if ((IFM_OPTIONS(mii->mii_media_active) & 545 IFM_ETH_RXPAUSE) != 0) 546 gmac = GMC_PAUSE_ON; 547 } 548 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 549 550 /* Enable PHY interrupt for FIFO underrun/overflow. */ 551 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 552 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 553 } else { 554 /* 555 * Link state changed to down. 556 * Disable PHY interrupts. 557 */ 558 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 559 /* Disable Rx/Tx MAC. */ 560 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 561 if ((gmac & (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)) != 0) { 562 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 563 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 564 /* Read again to ensure writing. */ 565 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 566 } 567 } 568} 569 570static void 571msk_rxfilter(struct msk_if_softc *sc_if) 572{ 573 struct msk_softc *sc; 574 struct ifnet *ifp; 575 struct ifmultiaddr *ifma; 576 uint32_t mchash[2]; 577 uint32_t crc; 578 uint16_t mode; 579 580 sc = sc_if->msk_softc; 581 582 MSK_IF_LOCK_ASSERT(sc_if); 583 584 ifp = sc_if->msk_ifp; 585 586 bzero(mchash, sizeof(mchash)); 587 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 588 if ((ifp->if_flags & IFF_PROMISC) != 0) 589 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 590 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 591 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 592 mchash[0] = 0xffff; 593 mchash[1] = 0xffff; 594 } else { 595 mode |= GM_RXCR_UCF_ENA; 596 if_maddr_rlock(ifp); 597 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 598 if (ifma->ifma_addr->sa_family != AF_LINK) 599 continue; 600 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 601 ifma->ifma_addr), ETHER_ADDR_LEN); 602 /* Just want the 6 least significant bits. */ 603 crc &= 0x3f; 604 /* Set the corresponding bit in the hash table. */ 605 mchash[crc >> 5] |= 1 << (crc & 0x1f); 606 } 607 if_maddr_runlock(ifp); 608 if (mchash[0] != 0 || mchash[1] != 0) 609 mode |= GM_RXCR_MCF_ENA; 610 } 611 612 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 613 mchash[0] & 0xffff); 614 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 615 (mchash[0] >> 16) & 0xffff); 616 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 617 mchash[1] & 0xffff); 618 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 619 (mchash[1] >> 16) & 0xffff); 620 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 621} 622 623static void 624msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 625{ 626 struct msk_softc *sc; 627 628 sc = sc_if->msk_softc; 629 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 630 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 631 RX_VLAN_STRIP_ON); 632 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 633 TX_VLAN_TAG_ON); 634 } else { 635 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 636 RX_VLAN_STRIP_OFF); 637 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 638 TX_VLAN_TAG_OFF); 639 } 640} 641 642static int 643msk_rx_fill(struct msk_if_softc *sc_if, int jumbo) 644{ 645 uint16_t idx; 646 int i; 647 648 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 649 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 650 /* Wait until controller executes OP_TCPSTART command. */ 651 for (i = 10; i > 0; i--) { 652 DELAY(10); 653 idx = CSR_READ_2(sc_if->msk_softc, 654 Y2_PREF_Q_ADDR(sc_if->msk_rxq, 655 PREF_UNIT_GET_IDX_REG)); 656 if (idx != 0) 657 break; 658 } 659 if (i == 0) { 660 device_printf(sc_if->msk_if_dev, 661 "prefetch unit stuck?\n"); 662 return (ETIMEDOUT); 663 } 664 /* 665 * Fill consumed LE with free buffer. This can be done 666 * in Rx handler but we don't want to add special code 667 * in fast handler. 668 */ 669 if (jumbo > 0) { 670 if (msk_jumbo_newbuf(sc_if, 0) != 0) 671 return (ENOBUFS); 672 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 673 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 674 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 675 } else { 676 if (msk_newbuf(sc_if, 0) != 0) 677 return (ENOBUFS); 678 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 679 sc_if->msk_cdata.msk_rx_ring_map, 680 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 681 } 682 sc_if->msk_cdata.msk_rx_prod = 0; 683 CSR_WRITE_2(sc_if->msk_softc, 684 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 685 sc_if->msk_cdata.msk_rx_prod); 686 } 687 return (0); 688} 689 690static int 691msk_init_rx_ring(struct msk_if_softc *sc_if) 692{ 693 struct msk_ring_data *rd; 694 struct msk_rxdesc *rxd; 695 int i, nbuf, prod; 696 697 MSK_IF_LOCK_ASSERT(sc_if); 698 699 sc_if->msk_cdata.msk_rx_cons = 0; 700 sc_if->msk_cdata.msk_rx_prod = 0; 701 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 702 703 rd = &sc_if->msk_rdata; 704 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 705 for (i = prod = 0; i < MSK_RX_RING_CNT; i++) { 706 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 707 rxd->rx_m = NULL; 708 rxd->rx_le = &rd->msk_rx_ring[prod]; 709 MSK_INC(prod, MSK_RX_RING_CNT); 710 } 711 nbuf = MSK_RX_BUF_CNT; 712 prod = 0; 713 /* Have controller know how to compute Rx checksum. */ 714 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 715 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 716#ifdef MSK_64BIT_DMA 717 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 718 rxd->rx_m = NULL; 719 rxd->rx_le = &rd->msk_rx_ring[prod]; 720 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 721 ETHER_HDR_LEN); 722 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 723 MSK_INC(prod, MSK_RX_RING_CNT); 724 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 725#endif 726 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 727 rxd->rx_m = NULL; 728 rxd->rx_le = &rd->msk_rx_ring[prod]; 729 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 730 ETHER_HDR_LEN); 731 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 732 MSK_INC(prod, MSK_RX_RING_CNT); 733 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 734 nbuf--; 735 } 736 for (i = 0; i < nbuf; i++) { 737 if (msk_newbuf(sc_if, prod) != 0) 738 return (ENOBUFS); 739 MSK_RX_INC(prod, MSK_RX_RING_CNT); 740 } 741 742 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 743 sc_if->msk_cdata.msk_rx_ring_map, 744 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 745 746 /* Update prefetch unit. */ 747 sc_if->msk_cdata.msk_rx_prod = prod; 748 CSR_WRITE_2(sc_if->msk_softc, 749 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 750 (sc_if->msk_cdata.msk_rx_prod + MSK_RX_RING_CNT - 1) % 751 MSK_RX_RING_CNT); 752 if (msk_rx_fill(sc_if, 0) != 0) 753 return (ENOBUFS); 754 return (0); 755} 756 757static int 758msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 759{ 760 struct msk_ring_data *rd; 761 struct msk_rxdesc *rxd; 762 int i, nbuf, prod; 763 764 MSK_IF_LOCK_ASSERT(sc_if); 765 766 sc_if->msk_cdata.msk_rx_cons = 0; 767 sc_if->msk_cdata.msk_rx_prod = 0; 768 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 769 770 rd = &sc_if->msk_rdata; 771 bzero(rd->msk_jumbo_rx_ring, 772 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 773 for (i = prod = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 774 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 775 rxd->rx_m = NULL; 776 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 777 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 778 } 779 nbuf = MSK_RX_BUF_CNT; 780 prod = 0; 781 /* Have controller know how to compute Rx checksum. */ 782 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 783 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 784#ifdef MSK_64BIT_DMA 785 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 786 rxd->rx_m = NULL; 787 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 788 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 789 ETHER_HDR_LEN); 790 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 791 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 792 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 793#endif 794 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 795 rxd->rx_m = NULL; 796 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 797 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 798 ETHER_HDR_LEN); 799 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 800 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 801 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 802 nbuf--; 803 } 804 for (i = 0; i < nbuf; i++) { 805 if (msk_jumbo_newbuf(sc_if, prod) != 0) 806 return (ENOBUFS); 807 MSK_RX_INC(prod, MSK_JUMBO_RX_RING_CNT); 808 } 809 810 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 811 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 812 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 813 814 /* Update prefetch unit. */ 815 sc_if->msk_cdata.msk_rx_prod = prod; 816 CSR_WRITE_2(sc_if->msk_softc, 817 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 818 (sc_if->msk_cdata.msk_rx_prod + MSK_JUMBO_RX_RING_CNT - 1) % 819 MSK_JUMBO_RX_RING_CNT); 820 if (msk_rx_fill(sc_if, 1) != 0) 821 return (ENOBUFS); 822 return (0); 823} 824 825static void 826msk_init_tx_ring(struct msk_if_softc *sc_if) 827{ 828 struct msk_ring_data *rd; 829 struct msk_txdesc *txd; 830 int i; 831 832 sc_if->msk_cdata.msk_tso_mtu = 0; 833 sc_if->msk_cdata.msk_last_csum = 0; 834 sc_if->msk_cdata.msk_tx_prod = 0; 835 sc_if->msk_cdata.msk_tx_cons = 0; 836 sc_if->msk_cdata.msk_tx_cnt = 0; 837 sc_if->msk_cdata.msk_tx_high_addr = 0; 838 839 rd = &sc_if->msk_rdata; 840 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 841 for (i = 0; i < MSK_TX_RING_CNT; i++) { 842 txd = &sc_if->msk_cdata.msk_txdesc[i]; 843 txd->tx_m = NULL; 844 txd->tx_le = &rd->msk_tx_ring[i]; 845 } 846 847 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 848 sc_if->msk_cdata.msk_tx_ring_map, 849 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 850} 851 852static __inline void 853msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 854{ 855 struct msk_rx_desc *rx_le; 856 struct msk_rxdesc *rxd; 857 struct mbuf *m; 858 859#ifdef MSK_64BIT_DMA 860 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 861 rx_le = rxd->rx_le; 862 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 863 MSK_INC(idx, MSK_RX_RING_CNT); 864#endif 865 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 866 m = rxd->rx_m; 867 rx_le = rxd->rx_le; 868 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 869} 870 871static __inline void 872msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 873{ 874 struct msk_rx_desc *rx_le; 875 struct msk_rxdesc *rxd; 876 struct mbuf *m; 877 878#ifdef MSK_64BIT_DMA 879 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 880 rx_le = rxd->rx_le; 881 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 882 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT); 883#endif 884 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 885 m = rxd->rx_m; 886 rx_le = rxd->rx_le; 887 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 888} 889 890static int 891msk_newbuf(struct msk_if_softc *sc_if, int idx) 892{ 893 struct msk_rx_desc *rx_le; 894 struct msk_rxdesc *rxd; 895 struct mbuf *m; 896 bus_dma_segment_t segs[1]; 897 bus_dmamap_t map; 898 int nsegs; 899 900 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 901 if (m == NULL) 902 return (ENOBUFS); 903 904 m->m_len = m->m_pkthdr.len = MCLBYTES; 905 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 906 m_adj(m, ETHER_ALIGN); 907#ifndef __NO_STRICT_ALIGNMENT 908 else 909 m_adj(m, MSK_RX_BUF_ALIGN); 910#endif 911 912 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 913 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 914 BUS_DMA_NOWAIT) != 0) { 915 m_freem(m); 916 return (ENOBUFS); 917 } 918 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 919 920 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 921#ifdef MSK_64BIT_DMA 922 rx_le = rxd->rx_le; 923 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr)); 924 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 925 MSK_INC(idx, MSK_RX_RING_CNT); 926 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 927#endif 928 if (rxd->rx_m != NULL) { 929 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 930 BUS_DMASYNC_POSTREAD); 931 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 932 rxd->rx_m = NULL; 933 } 934 map = rxd->rx_dmamap; 935 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 936 sc_if->msk_cdata.msk_rx_sparemap = map; 937 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 938 BUS_DMASYNC_PREREAD); 939 rxd->rx_m = m; 940 rx_le = rxd->rx_le; 941 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 942 rx_le->msk_control = 943 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 944 945 return (0); 946} 947 948static int 949msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 950{ 951 struct msk_rx_desc *rx_le; 952 struct msk_rxdesc *rxd; 953 struct mbuf *m; 954 bus_dma_segment_t segs[1]; 955 bus_dmamap_t map; 956 int nsegs; 957 958 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 959 if (m == NULL) 960 return (ENOBUFS); 961 if ((m->m_flags & M_EXT) == 0) { 962 m_freem(m); 963 return (ENOBUFS); 964 } 965 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 966 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 967 m_adj(m, ETHER_ALIGN); 968#ifndef __NO_STRICT_ALIGNMENT 969 else 970 m_adj(m, MSK_RX_BUF_ALIGN); 971#endif 972 973 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 974 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 975 BUS_DMA_NOWAIT) != 0) { 976 m_freem(m); 977 return (ENOBUFS); 978 } 979 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 980 981 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 982#ifdef MSK_64BIT_DMA 983 rx_le = rxd->rx_le; 984 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr)); 985 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 986 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT); 987 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 988#endif 989 if (rxd->rx_m != NULL) { 990 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 991 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 992 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 993 rxd->rx_dmamap); 994 rxd->rx_m = NULL; 995 } 996 map = rxd->rx_dmamap; 997 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 998 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 999 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 1000 BUS_DMASYNC_PREREAD); 1001 rxd->rx_m = m; 1002 rx_le = rxd->rx_le; 1003 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 1004 rx_le->msk_control = 1005 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 1006 1007 return (0); 1008} 1009 1010/* 1011 * Set media options. 1012 */ 1013static int 1014msk_mediachange(struct ifnet *ifp) 1015{ 1016 struct msk_if_softc *sc_if; 1017 struct mii_data *mii; 1018 int error; 1019 1020 sc_if = ifp->if_softc; 1021 1022 MSK_IF_LOCK(sc_if); 1023 mii = device_get_softc(sc_if->msk_miibus); 1024 error = mii_mediachg(mii); 1025 MSK_IF_UNLOCK(sc_if); 1026 1027 return (error); 1028} 1029 1030/* 1031 * Report current media status. 1032 */ 1033static void 1034msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1035{ 1036 struct msk_if_softc *sc_if; 1037 struct mii_data *mii; 1038 1039 sc_if = ifp->if_softc; 1040 MSK_IF_LOCK(sc_if); 1041 if ((ifp->if_flags & IFF_UP) == 0) { 1042 MSK_IF_UNLOCK(sc_if); 1043 return; 1044 } 1045 mii = device_get_softc(sc_if->msk_miibus); 1046 1047 mii_pollstat(mii); 1048 ifmr->ifm_active = mii->mii_media_active; 1049 ifmr->ifm_status = mii->mii_media_status; 1050 MSK_IF_UNLOCK(sc_if); 1051} 1052 1053static int 1054msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1055{ 1056 struct msk_if_softc *sc_if; 1057 struct ifreq *ifr; 1058 struct mii_data *mii; 1059 int error, mask, reinit; 1060 1061 sc_if = ifp->if_softc; 1062 ifr = (struct ifreq *)data; 1063 error = 0; 1064 1065 switch(command) { 1066 case SIOCSIFMTU: 1067 MSK_IF_LOCK(sc_if); 1068 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) 1069 error = EINVAL; 1070 else if (ifp->if_mtu != ifr->ifr_mtu) { 1071 if (ifr->ifr_mtu > ETHERMTU) { 1072 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 1073 error = EINVAL; 1074 MSK_IF_UNLOCK(sc_if); 1075 break; 1076 } 1077 if ((sc_if->msk_flags & 1078 MSK_FLAG_JUMBO_NOCSUM) != 0) { 1079 ifp->if_hwassist &= 1080 ~(MSK_CSUM_FEATURES | CSUM_TSO); 1081 ifp->if_capenable &= 1082 ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1083 VLAN_CAPABILITIES(ifp); 1084 } 1085 } 1086 ifp->if_mtu = ifr->ifr_mtu; 1087 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1088 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1089 msk_init_locked(sc_if); 1090 } 1091 } 1092 MSK_IF_UNLOCK(sc_if); 1093 break; 1094 case SIOCSIFFLAGS: 1095 MSK_IF_LOCK(sc_if); 1096 if ((ifp->if_flags & IFF_UP) != 0) { 1097 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 1098 ((ifp->if_flags ^ sc_if->msk_if_flags) & 1099 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1100 msk_rxfilter(sc_if); 1101 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0) 1102 msk_init_locked(sc_if); 1103 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1104 msk_stop(sc_if); 1105 sc_if->msk_if_flags = ifp->if_flags; 1106 MSK_IF_UNLOCK(sc_if); 1107 break; 1108 case SIOCADDMULTI: 1109 case SIOCDELMULTI: 1110 MSK_IF_LOCK(sc_if); 1111 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1112 msk_rxfilter(sc_if); 1113 MSK_IF_UNLOCK(sc_if); 1114 break; 1115 case SIOCGIFMEDIA: 1116 case SIOCSIFMEDIA: 1117 mii = device_get_softc(sc_if->msk_miibus); 1118 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1119 break; 1120 case SIOCSIFCAP: 1121 reinit = 0; 1122 MSK_IF_LOCK(sc_if); 1123 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1124 if ((mask & IFCAP_TXCSUM) != 0 && 1125 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1126 ifp->if_capenable ^= IFCAP_TXCSUM; 1127 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1128 ifp->if_hwassist |= MSK_CSUM_FEATURES; 1129 else 1130 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 1131 } 1132 if ((mask & IFCAP_RXCSUM) != 0 && 1133 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) { 1134 ifp->if_capenable ^= IFCAP_RXCSUM; 1135 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0) 1136 reinit = 1; 1137 } 1138 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1139 (IFCAP_VLAN_HWCSUM & ifp->if_capabilities) != 0) 1140 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1141 if ((mask & IFCAP_TSO4) != 0 && 1142 (IFCAP_TSO4 & ifp->if_capabilities) != 0) { 1143 ifp->if_capenable ^= IFCAP_TSO4; 1144 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 1145 ifp->if_hwassist |= CSUM_TSO; 1146 else 1147 ifp->if_hwassist &= ~CSUM_TSO; 1148 } 1149 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1150 (IFCAP_VLAN_HWTSO & ifp->if_capabilities) != 0) 1151 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1152 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1153 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 1154 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1155 if ((IFCAP_VLAN_HWTAGGING & ifp->if_capenable) == 0) 1156 ifp->if_capenable &= 1157 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 1158 msk_setvlan(sc_if, ifp); 1159 } 1160 if (ifp->if_mtu > ETHERMTU && 1161 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 1162 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 1163 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1164 } 1165 VLAN_CAPABILITIES(ifp); 1166 if (reinit > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1167 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1168 msk_init_locked(sc_if); 1169 } 1170 MSK_IF_UNLOCK(sc_if); 1171 break; 1172 default: 1173 error = ether_ioctl(ifp, command, data); 1174 break; 1175 } 1176 1177 return (error); 1178} 1179 1180static int 1181mskc_probe(device_t dev) 1182{ 1183 struct msk_product *mp; 1184 uint16_t vendor, devid; 1185 int i; 1186 1187 vendor = pci_get_vendor(dev); 1188 devid = pci_get_device(dev); 1189 mp = msk_products; 1190 for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]); 1191 i++, mp++) { 1192 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1193 device_set_desc(dev, mp->msk_name); 1194 return (BUS_PROBE_DEFAULT); 1195 } 1196 } 1197 1198 return (ENXIO); 1199} 1200 1201static int 1202mskc_setup_rambuffer(struct msk_softc *sc) 1203{ 1204 int next; 1205 int i; 1206 1207 /* Get adapter SRAM size. */ 1208 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; 1209 if (bootverbose) 1210 device_printf(sc->msk_dev, 1211 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1212 if (sc->msk_ramsize == 0) 1213 return (0); 1214 1215 sc->msk_pflags |= MSK_FLAG_RAMBUF; 1216 /* 1217 * Give receiver 2/3 of memory and round down to the multiple 1218 * of 1024. Tx/Rx RAM buffer size of Yukon II should be multiple 1219 * of 1024. 1220 */ 1221 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1222 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1223 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1224 sc->msk_rxqstart[i] = next; 1225 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1226 next = sc->msk_rxqend[i] + 1; 1227 sc->msk_txqstart[i] = next; 1228 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1229 next = sc->msk_txqend[i] + 1; 1230 if (bootverbose) { 1231 device_printf(sc->msk_dev, 1232 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1233 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1234 sc->msk_rxqend[i]); 1235 device_printf(sc->msk_dev, 1236 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1237 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1238 sc->msk_txqend[i]); 1239 } 1240 } 1241 1242 return (0); 1243} 1244 1245static void 1246msk_phy_power(struct msk_softc *sc, int mode) 1247{ 1248 uint32_t our, val; 1249 int i; 1250 1251 switch (mode) { 1252 case MSK_PHY_POWERUP: 1253 /* Switch power to VCC (WA for VAUX problem). */ 1254 CSR_WRITE_1(sc, B0_POWER_CTRL, 1255 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1256 /* Disable Core Clock Division, set Clock Select to 0. */ 1257 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1258 1259 val = 0; 1260 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1261 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1262 /* Enable bits are inverted. */ 1263 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1264 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1265 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1266 } 1267 /* 1268 * Enable PCI & Core Clock, enable clock gating for both Links. 1269 */ 1270 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1271 1272 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1273 our &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1274 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 1275 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1276 /* Deassert Low Power for 1st PHY. */ 1277 our |= PCI_Y2_PHY1_COMA; 1278 if (sc->msk_num_port > 1) 1279 our |= PCI_Y2_PHY2_COMA; 1280 } 1281 } 1282 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U || 1283 sc->msk_hw_id == CHIP_ID_YUKON_EX || 1284 sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) { 1285 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_4); 1286 val &= (PCI_FORCE_ASPM_REQUEST | 1287 PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY | 1288 PCI_ASPM_CLKRUN_REQUEST); 1289 /* Set all bits to 0 except bits 15..12. */ 1290 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, val); 1291 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_5); 1292 val &= PCI_CTL_TIM_VMAIN_AV_MSK; 1293 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, val); 1294 CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0); 1295 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); 1296 /* 1297 * Disable status race, workaround for 1298 * Yukon EC Ultra & Yukon EX. 1299 */ 1300 val = CSR_READ_4(sc, B2_GP_IO); 1301 val |= GLB_GPIO_STAT_RACE_DIS; 1302 CSR_WRITE_4(sc, B2_GP_IO, val); 1303 CSR_READ_4(sc, B2_GP_IO); 1304 } 1305 /* Release PHY from PowerDown/COMA mode. */ 1306 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, our); 1307 1308 for (i = 0; i < sc->msk_num_port; i++) { 1309 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1310 GMLC_RST_SET); 1311 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1312 GMLC_RST_CLR); 1313 } 1314 break; 1315 case MSK_PHY_POWERDOWN: 1316 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1317 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1318 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1319 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1320 val &= ~PCI_Y2_PHY1_COMA; 1321 if (sc->msk_num_port > 1) 1322 val &= ~PCI_Y2_PHY2_COMA; 1323 } 1324 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1325 1326 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1327 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1328 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1329 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1330 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1331 /* Enable bits are inverted. */ 1332 val = 0; 1333 } 1334 /* 1335 * Disable PCI & Core Clock, disable clock gating for 1336 * both Links. 1337 */ 1338 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1339 CSR_WRITE_1(sc, B0_POWER_CTRL, 1340 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1341 break; 1342 default: 1343 break; 1344 } 1345} 1346 1347static void 1348mskc_reset(struct msk_softc *sc) 1349{ 1350 bus_addr_t addr; 1351 uint16_t status; 1352 uint32_t val; 1353 int i, initram; 1354 1355 /* Disable ASF. */ 1356 if (sc->msk_hw_id >= CHIP_ID_YUKON_XL && 1357 sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) { 1358 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 1359 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 1360 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1361 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR); 1362 /* Clear AHB bridge & microcontroller reset. */ 1363 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | 1364 Y2_ASF_HCU_CCSR_CPU_RST_MODE); 1365 /* Clear ASF microcontroller state. */ 1366 status &= ~Y2_ASF_HCU_CCSR_UC_STATE_MSK; 1367 status &= ~Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK; 1368 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); 1369 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1370 } else 1371 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1372 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1373 /* 1374 * Since we disabled ASF, S/W reset is required for 1375 * Power Management. 1376 */ 1377 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1378 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1379 } 1380 1381 /* Clear all error bits in the PCI status register. */ 1382 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1383 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1384 1385 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1386 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1387 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 1388 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1389 1390 switch (sc->msk_bustype) { 1391 case MSK_PEX_BUS: 1392 /* Clear all PEX errors. */ 1393 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1394 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1395 if ((val & PEX_RX_OV) != 0) { 1396 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1397 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1398 } 1399 break; 1400 case MSK_PCI_BUS: 1401 case MSK_PCIX_BUS: 1402 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1403 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1404 if (val == 0) 1405 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1406 if (sc->msk_bustype == MSK_PCIX_BUS) { 1407 /* Set Cache Line Size opt. */ 1408 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1409 val |= PCI_CLS_OPT; 1410 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1411 } 1412 break; 1413 } 1414 /* Set PHY power state. */ 1415 msk_phy_power(sc, MSK_PHY_POWERUP); 1416 1417 /* Reset GPHY/GMAC Control */ 1418 for (i = 0; i < sc->msk_num_port; i++) { 1419 /* GPHY Control reset. */ 1420 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1421 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1422 /* GMAC Control reset. */ 1423 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1424 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1425 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1426 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 1427 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) 1428 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), 1429 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 1430 GMC_BYP_RETR_ON); 1431 } 1432 1433 if (sc->msk_hw_id == CHIP_ID_YUKON_SUPR && 1434 sc->msk_hw_rev > CHIP_REV_YU_SU_B0) 1435 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, PCI_CLK_MACSEC_DIS); 1436 if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) { 1437 /* Disable PCIe PHY powerdown(reg 0x80, bit7). */ 1438 CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080); 1439 } 1440 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1441 1442 /* LED On. */ 1443 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1444 1445 /* Clear TWSI IRQ. */ 1446 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1447 1448 /* Turn off hardware timer. */ 1449 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1450 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1451 1452 /* Turn off descriptor polling. */ 1453 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1454 1455 /* Turn off time stamps. */ 1456 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1457 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1458 1459 initram = 0; 1460 if (sc->msk_hw_id == CHIP_ID_YUKON_XL || 1461 sc->msk_hw_id == CHIP_ID_YUKON_EC || 1462 sc->msk_hw_id == CHIP_ID_YUKON_FE) 1463 initram++; 1464 1465 /* Configure timeout values. */ 1466 for (i = 0; initram > 0 && i < sc->msk_num_port; i++) { 1467 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1468 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1469 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1470 MSK_RI_TO_53); 1471 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1472 MSK_RI_TO_53); 1473 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1474 MSK_RI_TO_53); 1475 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1476 MSK_RI_TO_53); 1477 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1478 MSK_RI_TO_53); 1479 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1480 MSK_RI_TO_53); 1481 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1482 MSK_RI_TO_53); 1483 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1484 MSK_RI_TO_53); 1485 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1486 MSK_RI_TO_53); 1487 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1488 MSK_RI_TO_53); 1489 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1490 MSK_RI_TO_53); 1491 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1492 MSK_RI_TO_53); 1493 } 1494 1495 /* Disable all interrupts. */ 1496 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1497 CSR_READ_4(sc, B0_HWE_IMSK); 1498 CSR_WRITE_4(sc, B0_IMSK, 0); 1499 CSR_READ_4(sc, B0_IMSK); 1500 1501 /* 1502 * On dual port PCI-X card, there is an problem where status 1503 * can be received out of order due to split transactions. 1504 */ 1505 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) { 1506 uint16_t pcix_cmd; 1507 1508 pcix_cmd = pci_read_config(sc->msk_dev, 1509 sc->msk_pcixcap + PCIXR_COMMAND, 2); 1510 /* Clear Max Outstanding Split Transactions. */ 1511 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS; 1512 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1513 pci_write_config(sc->msk_dev, 1514 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2); 1515 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1516 } 1517 if (sc->msk_expcap != 0) { 1518 /* Change Max. Read Request Size to 2048 bytes. */ 1519 if (pci_get_max_read_req(sc->msk_dev) == 512) 1520 pci_set_max_read_req(sc->msk_dev, 2048); 1521 } 1522 1523 /* Clear status list. */ 1524 bzero(sc->msk_stat_ring, 1525 sizeof(struct msk_stat_desc) * sc->msk_stat_count); 1526 sc->msk_stat_cons = 0; 1527 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1528 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1529 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1530 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1531 /* Set the status list base address. */ 1532 addr = sc->msk_stat_ring_paddr; 1533 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1534 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1535 /* Set the status list last index. */ 1536 CSR_WRITE_2(sc, STAT_LAST_IDX, sc->msk_stat_count - 1); 1537 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1538 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1539 /* WA for dev. #4.3 */ 1540 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1541 /* WA for dev. #4.18 */ 1542 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1543 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1544 } else { 1545 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1546 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1547 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1548 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1549 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1550 else 1551 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1552 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1553 } 1554 /* 1555 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1556 */ 1557 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1558 1559 /* Enable status unit. */ 1560 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1561 1562 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1563 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1564 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1565} 1566 1567static int 1568msk_probe(device_t dev) 1569{ 1570 struct msk_softc *sc; 1571 char desc[100]; 1572 1573 sc = device_get_softc(device_get_parent(dev)); 1574 /* 1575 * Not much to do here. We always know there will be 1576 * at least one GMAC present, and if there are two, 1577 * mskc_attach() will create a second device instance 1578 * for us. 1579 */ 1580 snprintf(desc, sizeof(desc), 1581 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1582 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1583 sc->msk_hw_rev); 1584 device_set_desc_copy(dev, desc); 1585 1586 return (BUS_PROBE_DEFAULT); 1587} 1588 1589static int 1590msk_attach(device_t dev) 1591{ 1592 struct msk_softc *sc; 1593 struct msk_if_softc *sc_if; 1594 struct ifnet *ifp; 1595 struct msk_mii_data *mmd; 1596 int i, port, error; 1597 uint8_t eaddr[6]; 1598 1599 if (dev == NULL) 1600 return (EINVAL); 1601 1602 error = 0; 1603 sc_if = device_get_softc(dev); 1604 sc = device_get_softc(device_get_parent(dev)); 1605 mmd = device_get_ivars(dev); 1606 port = mmd->port; 1607 1608 sc_if->msk_if_dev = dev; 1609 sc_if->msk_port = port; 1610 sc_if->msk_softc = sc; 1611 sc_if->msk_flags = sc->msk_pflags; 1612 sc->msk_if[port] = sc_if; 1613 /* Setup Tx/Rx queue register offsets. */ 1614 if (port == MSK_PORT_A) { 1615 sc_if->msk_txq = Q_XA1; 1616 sc_if->msk_txsq = Q_XS1; 1617 sc_if->msk_rxq = Q_R1; 1618 } else { 1619 sc_if->msk_txq = Q_XA2; 1620 sc_if->msk_txsq = Q_XS2; 1621 sc_if->msk_rxq = Q_R2; 1622 } 1623 1624 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1625 msk_sysctl_node(sc_if); 1626 1627 if ((error = msk_txrx_dma_alloc(sc_if) != 0)) 1628 goto fail; 1629 msk_rx_dma_jalloc(sc_if); 1630 1631 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1632 if (ifp == NULL) { 1633 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1634 error = ENOSPC; 1635 goto fail; 1636 } 1637 ifp->if_softc = sc_if; 1638 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1639 ifp->if_mtu = ETHERMTU; 1640 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1641 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1642 /* 1643 * Enable Rx checksum offloading if controller supports 1644 * new descriptor formant and controller is not Yukon XL. 1645 */ 1646 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 1647 sc->msk_hw_id != CHIP_ID_YUKON_XL) 1648 ifp->if_capabilities |= IFCAP_RXCSUM; 1649 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1650 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1651 ifp->if_capabilities |= IFCAP_RXCSUM; 1652 ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO; 1653 ifp->if_capenable = ifp->if_capabilities; 1654 ifp->if_ioctl = msk_ioctl; 1655 ifp->if_start = msk_start; 1656 ifp->if_init = msk_init; 1657 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1658 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1; 1659 IFQ_SET_READY(&ifp->if_snd); 1660 /* 1661 * Get station address for this interface. Note that 1662 * dual port cards actually come with three station 1663 * addresses: one for each port, plus an extra. The 1664 * extra one is used by the SysKonnect driver software 1665 * as a 'virtual' station address for when both ports 1666 * are operating in failover mode. Currently we don't 1667 * use this extra address. 1668 */ 1669 MSK_IF_LOCK(sc_if); 1670 for (i = 0; i < ETHER_ADDR_LEN; i++) 1671 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1672 1673 /* 1674 * Call MI attach routine. Can't hold locks when calling into ether_*. 1675 */ 1676 MSK_IF_UNLOCK(sc_if); 1677 ether_ifattach(ifp, eaddr); 1678 MSK_IF_LOCK(sc_if); 1679 1680 /* VLAN capability setup */ 1681 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1682 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) { 1683 /* 1684 * Due to Tx checksum offload hardware bugs, msk(4) manually 1685 * computes checksum for short frames. For VLAN tagged frames 1686 * this workaround does not work so disable checksum offload 1687 * for VLAN interface. 1688 */ 1689 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO; 1690 /* 1691 * Enable Rx checksum offloading for VLAN tagged frames 1692 * if controller support new descriptor format. 1693 */ 1694 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1695 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1696 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1697 } 1698 ifp->if_capenable = ifp->if_capabilities; 1699 1700 /* 1701 * Tell the upper layer(s) we support long frames. 1702 * Must appear after the call to ether_ifattach() because 1703 * ether_ifattach() sets ifi_hdrlen to the default value. 1704 */ 1705 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1706 1707 /* 1708 * Do miibus setup. 1709 */ 1710 MSK_IF_UNLOCK(sc_if); 1711 error = mii_attach(dev, &sc_if->msk_miibus, ifp, msk_mediachange, 1712 msk_mediastatus, BMSR_DEFCAPMASK, PHY_ADDR_MARV, MII_OFFSET_ANY, 1713 mmd->mii_flags); 1714 if (error != 0) { 1715 device_printf(sc_if->msk_if_dev, "attaching PHYs failed\n"); 1716 ether_ifdetach(ifp); 1717 error = ENXIO; 1718 goto fail; 1719 } 1720 1721fail: 1722 if (error != 0) { 1723 /* Access should be ok even though lock has been dropped */ 1724 sc->msk_if[port] = NULL; 1725 msk_detach(dev); 1726 } 1727 1728 return (error); 1729} 1730 1731/* 1732 * Attach the interface. Allocate softc structures, do ifmedia 1733 * setup and ethernet/BPF attach. 1734 */ 1735static int 1736mskc_attach(device_t dev) 1737{ 1738 struct msk_softc *sc; 1739 struct msk_mii_data *mmd; 1740 int error, msic, msir, reg; 1741 1742 sc = device_get_softc(dev); 1743 sc->msk_dev = dev; 1744 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1745 MTX_DEF); 1746 1747 /* 1748 * Map control/status registers. 1749 */ 1750 pci_enable_busmaster(dev); 1751 1752 /* Allocate I/O resource */ 1753#ifdef MSK_USEIOSPACE 1754 sc->msk_res_spec = msk_res_spec_io; 1755#else 1756 sc->msk_res_spec = msk_res_spec_mem; 1757#endif 1758 sc->msk_irq_spec = msk_irq_spec_legacy; 1759 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1760 if (error) { 1761 if (sc->msk_res_spec == msk_res_spec_mem) 1762 sc->msk_res_spec = msk_res_spec_io; 1763 else 1764 sc->msk_res_spec = msk_res_spec_mem; 1765 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1766 if (error) { 1767 device_printf(dev, "couldn't allocate %s resources\n", 1768 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1769 "I/O"); 1770 mtx_destroy(&sc->msk_mtx); 1771 return (ENXIO); 1772 } 1773 } 1774 1775 /* Enable all clocks before accessing any registers. */ 1776 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 1777 1778 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1779 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1780 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1781 /* Bail out if chip is not recognized. */ 1782 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1783 sc->msk_hw_id > CHIP_ID_YUKON_OPT || 1784 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) { 1785 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1786 sc->msk_hw_id, sc->msk_hw_rev); 1787 mtx_destroy(&sc->msk_mtx); 1788 return (ENXIO); 1789 } 1790 1791 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1792 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1793 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 1794 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1795 "max number of Rx events to process"); 1796 1797 sc->msk_process_limit = MSK_PROC_DEFAULT; 1798 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1799 "process_limit", &sc->msk_process_limit); 1800 if (error == 0) { 1801 if (sc->msk_process_limit < MSK_PROC_MIN || 1802 sc->msk_process_limit > MSK_PROC_MAX) { 1803 device_printf(dev, "process_limit value out of range; " 1804 "using default: %d\n", MSK_PROC_DEFAULT); 1805 sc->msk_process_limit = MSK_PROC_DEFAULT; 1806 } 1807 } 1808 1809 sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT; 1810 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 1811 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 1812 "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0, 1813 "Maximum number of time to delay interrupts"); 1814 resource_int_value(device_get_name(dev), device_get_unit(dev), 1815 "int_holdoff", &sc->msk_int_holdoff); 1816 1817 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1818 /* Check number of MACs. */ 1819 sc->msk_num_port = 1; 1820 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1821 CFG_DUAL_MAC_MSK) { 1822 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1823 sc->msk_num_port++; 1824 } 1825 1826 /* Check bus type. */ 1827 if (pci_find_cap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) { 1828 sc->msk_bustype = MSK_PEX_BUS; 1829 sc->msk_expcap = reg; 1830 } else if (pci_find_cap(sc->msk_dev, PCIY_PCIX, ®) == 0) { 1831 sc->msk_bustype = MSK_PCIX_BUS; 1832 sc->msk_pcixcap = reg; 1833 } else 1834 sc->msk_bustype = MSK_PCI_BUS; 1835 1836 switch (sc->msk_hw_id) { 1837 case CHIP_ID_YUKON_EC: 1838 sc->msk_clock = 125; /* 125 MHz */ 1839 sc->msk_pflags |= MSK_FLAG_JUMBO; 1840 break; 1841 case CHIP_ID_YUKON_EC_U: 1842 sc->msk_clock = 125; /* 125 MHz */ 1843 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM; 1844 break; 1845 case CHIP_ID_YUKON_EX: 1846 sc->msk_clock = 125; /* 125 MHz */ 1847 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1848 MSK_FLAG_AUTOTX_CSUM; 1849 /* 1850 * Yukon Extreme seems to have silicon bug for 1851 * automatic Tx checksum calculation capability. 1852 */ 1853 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 1854 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM; 1855 /* 1856 * Yukon Extreme A0 could not use store-and-forward 1857 * for jumbo frames, so disable Tx checksum 1858 * offloading for jumbo frames. 1859 */ 1860 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 1861 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM; 1862 break; 1863 case CHIP_ID_YUKON_FE: 1864 sc->msk_clock = 100; /* 100 MHz */ 1865 sc->msk_pflags |= MSK_FLAG_FASTETHER; 1866 break; 1867 case CHIP_ID_YUKON_FE_P: 1868 sc->msk_clock = 50; /* 50 MHz */ 1869 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 | 1870 MSK_FLAG_AUTOTX_CSUM; 1871 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 1872 /* 1873 * XXX 1874 * FE+ A0 has status LE writeback bug so msk(4) 1875 * does not rely on status word of received frame 1876 * in msk_rxeof() which in turn disables all 1877 * hardware assistance bits reported by the status 1878 * word as well as validity of the received frame. 1879 * Just pass received frames to upper stack with 1880 * minimal test and let upper stack handle them. 1881 */ 1882 sc->msk_pflags |= MSK_FLAG_NOHWVLAN | 1883 MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM; 1884 } 1885 break; 1886 case CHIP_ID_YUKON_XL: 1887 sc->msk_clock = 156; /* 156 MHz */ 1888 sc->msk_pflags |= MSK_FLAG_JUMBO; 1889 break; 1890 case CHIP_ID_YUKON_SUPR: 1891 sc->msk_clock = 125; /* 125 MHz */ 1892 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1893 MSK_FLAG_AUTOTX_CSUM; 1894 break; 1895 case CHIP_ID_YUKON_UL_2: 1896 sc->msk_clock = 125; /* 125 MHz */ 1897 sc->msk_pflags |= MSK_FLAG_JUMBO; 1898 break; 1899 case CHIP_ID_YUKON_OPT: 1900 sc->msk_clock = 125; /* 125 MHz */ 1901 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2; 1902 break; 1903 default: 1904 sc->msk_clock = 156; /* 156 MHz */ 1905 break; 1906 } 1907 1908 /* Allocate IRQ resources. */ 1909 msic = pci_msi_count(dev); 1910 if (bootverbose) 1911 device_printf(dev, "MSI count : %d\n", msic); 1912 if (legacy_intr != 0) 1913 msi_disable = 1; 1914 if (msi_disable == 0 && msic > 0) { 1915 msir = 1; 1916 if (pci_alloc_msi(dev, &msir) == 0) { 1917 if (msir == 1) { 1918 sc->msk_pflags |= MSK_FLAG_MSI; 1919 sc->msk_irq_spec = msk_irq_spec_msi; 1920 } else 1921 pci_release_msi(dev); 1922 } 1923 } 1924 1925 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1926 if (error) { 1927 device_printf(dev, "couldn't allocate IRQ resources\n"); 1928 goto fail; 1929 } 1930 1931 if ((error = msk_status_dma_alloc(sc)) != 0) 1932 goto fail; 1933 1934 /* Set base interrupt mask. */ 1935 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1936 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1937 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1938 1939 /* Reset the adapter. */ 1940 mskc_reset(sc); 1941 1942 if ((error = mskc_setup_rambuffer(sc)) != 0) 1943 goto fail; 1944 1945 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1946 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1947 device_printf(dev, "failed to add child for PORT_A\n"); 1948 error = ENXIO; 1949 goto fail; 1950 } 1951 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1952 if (mmd == NULL) { 1953 device_printf(dev, "failed to allocate memory for " 1954 "ivars of PORT_A\n"); 1955 error = ENXIO; 1956 goto fail; 1957 } 1958 mmd->port = MSK_PORT_A; 1959 mmd->pmd = sc->msk_pmd; 1960 mmd->mii_flags |= MIIF_DOPAUSE; 1961 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1962 mmd->mii_flags |= MIIF_HAVEFIBER; 1963 if (sc->msk_pmd == 'P') 1964 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1965 device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd); 1966 1967 if (sc->msk_num_port > 1) { 1968 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1969 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1970 device_printf(dev, "failed to add child for PORT_B\n"); 1971 error = ENXIO; 1972 goto fail; 1973 } 1974 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | 1975 M_ZERO); 1976 if (mmd == NULL) { 1977 device_printf(dev, "failed to allocate memory for " 1978 "ivars of PORT_B\n"); 1979 error = ENXIO; 1980 goto fail; 1981 } 1982 mmd->port = MSK_PORT_B; 1983 mmd->pmd = sc->msk_pmd; 1984 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1985 mmd->mii_flags |= MIIF_HAVEFIBER; 1986 if (sc->msk_pmd == 'P') 1987 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1988 device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd); 1989 } 1990 1991 error = bus_generic_attach(dev); 1992 if (error) { 1993 device_printf(dev, "failed to attach port(s)\n"); 1994 goto fail; 1995 } 1996 1997 /* Hook interrupt last to avoid having to lock softc. */ 1998 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1999 INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand); 2000 if (error != 0) { 2001 device_printf(dev, "couldn't set up interrupt handler\n"); 2002 goto fail; 2003 } 2004fail: 2005 if (error != 0) 2006 mskc_detach(dev); 2007 2008 return (error); 2009} 2010 2011/* 2012 * Shutdown hardware and free up resources. This can be called any 2013 * time after the mutex has been initialized. It is called in both 2014 * the error case in attach and the normal detach case so it needs 2015 * to be careful about only freeing resources that have actually been 2016 * allocated. 2017 */ 2018static int 2019msk_detach(device_t dev) 2020{ 2021 struct msk_softc *sc; 2022 struct msk_if_softc *sc_if; 2023 struct ifnet *ifp; 2024 2025 sc_if = device_get_softc(dev); 2026 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 2027 ("msk mutex not initialized in msk_detach")); 2028 MSK_IF_LOCK(sc_if); 2029 2030 ifp = sc_if->msk_ifp; 2031 if (device_is_attached(dev)) { 2032 /* XXX */ 2033 sc_if->msk_flags |= MSK_FLAG_DETACH; 2034 msk_stop(sc_if); 2035 /* Can't hold locks while calling detach. */ 2036 MSK_IF_UNLOCK(sc_if); 2037 callout_drain(&sc_if->msk_tick_ch); 2038 if (ifp) 2039 ether_ifdetach(ifp); 2040 MSK_IF_LOCK(sc_if); 2041 } 2042 2043 /* 2044 * We're generally called from mskc_detach() which is using 2045 * device_delete_child() to get to here. It's already trashed 2046 * miibus for us, so don't do it here or we'll panic. 2047 * 2048 * if (sc_if->msk_miibus != NULL) { 2049 * device_delete_child(dev, sc_if->msk_miibus); 2050 * sc_if->msk_miibus = NULL; 2051 * } 2052 */ 2053 2054 msk_rx_dma_jfree(sc_if); 2055 msk_txrx_dma_free(sc_if); 2056 bus_generic_detach(dev); 2057 2058 if (ifp) 2059 if_free(ifp); 2060 sc = sc_if->msk_softc; 2061 sc->msk_if[sc_if->msk_port] = NULL; 2062 MSK_IF_UNLOCK(sc_if); 2063 2064 return (0); 2065} 2066 2067static int 2068mskc_detach(device_t dev) 2069{ 2070 struct msk_softc *sc; 2071 2072 sc = device_get_softc(dev); 2073 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 2074 2075 if (device_is_alive(dev)) { 2076 if (sc->msk_devs[MSK_PORT_A] != NULL) { 2077 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 2078 M_DEVBUF); 2079 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 2080 } 2081 if (sc->msk_devs[MSK_PORT_B] != NULL) { 2082 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 2083 M_DEVBUF); 2084 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 2085 } 2086 bus_generic_detach(dev); 2087 } 2088 2089 /* Disable all interrupts. */ 2090 CSR_WRITE_4(sc, B0_IMSK, 0); 2091 CSR_READ_4(sc, B0_IMSK); 2092 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2093 CSR_READ_4(sc, B0_HWE_IMSK); 2094 2095 /* LED Off. */ 2096 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 2097 2098 /* Put hardware reset. */ 2099 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2100 2101 msk_status_dma_free(sc); 2102 2103 if (sc->msk_intrhand) { 2104 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand); 2105 sc->msk_intrhand = NULL; 2106 } 2107 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 2108 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0) 2109 pci_release_msi(dev); 2110 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 2111 mtx_destroy(&sc->msk_mtx); 2112 2113 return (0); 2114} 2115 2116struct msk_dmamap_arg { 2117 bus_addr_t msk_busaddr; 2118}; 2119 2120static void 2121msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2122{ 2123 struct msk_dmamap_arg *ctx; 2124 2125 if (error != 0) 2126 return; 2127 ctx = arg; 2128 ctx->msk_busaddr = segs[0].ds_addr; 2129} 2130 2131/* Create status DMA region. */ 2132static int 2133msk_status_dma_alloc(struct msk_softc *sc) 2134{ 2135 struct msk_dmamap_arg ctx; 2136 bus_size_t stat_sz; 2137 int count, error; 2138 2139 /* 2140 * It seems controller requires number of status LE entries 2141 * is power of 2 and the maximum number of status LE entries 2142 * is 4096. For dual-port controllers, the number of status 2143 * LE entries should be large enough to hold both port's 2144 * status updates. 2145 */ 2146 count = 3 * MSK_RX_RING_CNT + MSK_TX_RING_CNT; 2147#ifdef __HAIKU__ 2148 // TODO check this! 2149 #define imin min 2150#endif 2151 count = imin(4096, roundup2(count, 1024)); 2152 sc->msk_stat_count = count; 2153 stat_sz = count * sizeof(struct msk_stat_desc); 2154 error = bus_dma_tag_create( 2155 bus_get_dma_tag(sc->msk_dev), /* parent */ 2156 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 2157 BUS_SPACE_MAXADDR, /* lowaddr */ 2158 BUS_SPACE_MAXADDR, /* highaddr */ 2159 NULL, NULL, /* filter, filterarg */ 2160 stat_sz, /* maxsize */ 2161 1, /* nsegments */ 2162 stat_sz, /* maxsegsize */ 2163 0, /* flags */ 2164 NULL, NULL, /* lockfunc, lockarg */ 2165 &sc->msk_stat_tag); 2166 if (error != 0) { 2167 device_printf(sc->msk_dev, 2168 "failed to create status DMA tag\n"); 2169 return (error); 2170 } 2171 2172 /* Allocate DMA'able memory and load the DMA map for status ring. */ 2173 error = bus_dmamem_alloc(sc->msk_stat_tag, 2174 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 2175 BUS_DMA_ZERO, &sc->msk_stat_map); 2176 if (error != 0) { 2177 device_printf(sc->msk_dev, 2178 "failed to allocate DMA'able memory for status ring\n"); 2179 return (error); 2180 } 2181 2182 ctx.msk_busaddr = 0; 2183 error = bus_dmamap_load(sc->msk_stat_tag, sc->msk_stat_map, 2184 sc->msk_stat_ring, stat_sz, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2185 if (error != 0) { 2186 device_printf(sc->msk_dev, 2187 "failed to load DMA'able memory for status ring\n"); 2188 return (error); 2189 } 2190 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 2191 2192 return (0); 2193} 2194 2195static void 2196msk_status_dma_free(struct msk_softc *sc) 2197{ 2198 2199 /* Destroy status block. */ 2200 if (sc->msk_stat_tag) { 2201 if (sc->msk_stat_map) { 2202 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 2203 if (sc->msk_stat_ring) { 2204 bus_dmamem_free(sc->msk_stat_tag, 2205 sc->msk_stat_ring, sc->msk_stat_map); 2206 sc->msk_stat_ring = NULL; 2207 } 2208 sc->msk_stat_map = NULL; 2209 } 2210 bus_dma_tag_destroy(sc->msk_stat_tag); 2211 sc->msk_stat_tag = NULL; 2212 } 2213} 2214 2215static int 2216msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 2217{ 2218 struct msk_dmamap_arg ctx; 2219 struct msk_txdesc *txd; 2220 struct msk_rxdesc *rxd; 2221 bus_size_t rxalign; 2222 int error, i; 2223 2224 /* Create parent DMA tag. */ 2225 error = bus_dma_tag_create( 2226 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2227 1, 0, /* alignment, boundary */ 2228 BUS_SPACE_MAXADDR, /* lowaddr */ 2229 BUS_SPACE_MAXADDR, /* highaddr */ 2230 NULL, NULL, /* filter, filterarg */ 2231 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2232 0, /* nsegments */ 2233 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2234 0, /* flags */ 2235 NULL, NULL, /* lockfunc, lockarg */ 2236 &sc_if->msk_cdata.msk_parent_tag); 2237 if (error != 0) { 2238 device_printf(sc_if->msk_if_dev, 2239 "failed to create parent DMA tag\n"); 2240 goto fail; 2241 } 2242 /* Create tag for Tx ring. */ 2243 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2244 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2245 BUS_SPACE_MAXADDR, /* lowaddr */ 2246 BUS_SPACE_MAXADDR, /* highaddr */ 2247 NULL, NULL, /* filter, filterarg */ 2248 MSK_TX_RING_SZ, /* maxsize */ 2249 1, /* nsegments */ 2250 MSK_TX_RING_SZ, /* maxsegsize */ 2251 0, /* flags */ 2252 NULL, NULL, /* lockfunc, lockarg */ 2253 &sc_if->msk_cdata.msk_tx_ring_tag); 2254 if (error != 0) { 2255 device_printf(sc_if->msk_if_dev, 2256 "failed to create Tx ring DMA tag\n"); 2257 goto fail; 2258 } 2259 2260 /* Create tag for Rx ring. */ 2261 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2262 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2263 BUS_SPACE_MAXADDR, /* lowaddr */ 2264 BUS_SPACE_MAXADDR, /* highaddr */ 2265 NULL, NULL, /* filter, filterarg */ 2266 MSK_RX_RING_SZ, /* maxsize */ 2267 1, /* nsegments */ 2268 MSK_RX_RING_SZ, /* maxsegsize */ 2269 0, /* flags */ 2270 NULL, NULL, /* lockfunc, lockarg */ 2271 &sc_if->msk_cdata.msk_rx_ring_tag); 2272 if (error != 0) { 2273 device_printf(sc_if->msk_if_dev, 2274 "failed to create Rx ring DMA tag\n"); 2275 goto fail; 2276 } 2277 2278 /* Create tag for Tx buffers. */ 2279 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2280 1, 0, /* alignment, boundary */ 2281 BUS_SPACE_MAXADDR, /* lowaddr */ 2282 BUS_SPACE_MAXADDR, /* highaddr */ 2283 NULL, NULL, /* filter, filterarg */ 2284 MSK_TSO_MAXSIZE, /* maxsize */ 2285 MSK_MAXTXSEGS, /* nsegments */ 2286 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2287 0, /* flags */ 2288 NULL, NULL, /* lockfunc, lockarg */ 2289 &sc_if->msk_cdata.msk_tx_tag); 2290 if (error != 0) { 2291 device_printf(sc_if->msk_if_dev, 2292 "failed to create Tx DMA tag\n"); 2293 goto fail; 2294 } 2295 2296 rxalign = 1; 2297 /* 2298 * Workaround hardware hang which seems to happen when Rx buffer 2299 * is not aligned on multiple of FIFO word(8 bytes). 2300 */ 2301 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2302 rxalign = MSK_RX_BUF_ALIGN; 2303 /* Create tag for Rx buffers. */ 2304 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2305 rxalign, 0, /* alignment, boundary */ 2306 BUS_SPACE_MAXADDR, /* lowaddr */ 2307 BUS_SPACE_MAXADDR, /* highaddr */ 2308 NULL, NULL, /* filter, filterarg */ 2309 MCLBYTES, /* maxsize */ 2310 1, /* nsegments */ 2311 MCLBYTES, /* maxsegsize */ 2312 0, /* flags */ 2313 NULL, NULL, /* lockfunc, lockarg */ 2314 &sc_if->msk_cdata.msk_rx_tag); 2315 if (error != 0) { 2316 device_printf(sc_if->msk_if_dev, 2317 "failed to create Rx DMA tag\n"); 2318 goto fail; 2319 } 2320 2321 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2322 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2323 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2324 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2325 if (error != 0) { 2326 device_printf(sc_if->msk_if_dev, 2327 "failed to allocate DMA'able memory for Tx ring\n"); 2328 goto fail; 2329 } 2330 2331 ctx.msk_busaddr = 0; 2332 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2333 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2334 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2335 if (error != 0) { 2336 device_printf(sc_if->msk_if_dev, 2337 "failed to load DMA'able memory for Tx ring\n"); 2338 goto fail; 2339 } 2340 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2341 2342 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2343 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2344 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2345 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2346 if (error != 0) { 2347 device_printf(sc_if->msk_if_dev, 2348 "failed to allocate DMA'able memory for Rx ring\n"); 2349 goto fail; 2350 } 2351 2352 ctx.msk_busaddr = 0; 2353 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2354 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2355 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2356 if (error != 0) { 2357 device_printf(sc_if->msk_if_dev, 2358 "failed to load DMA'able memory for Rx ring\n"); 2359 goto fail; 2360 } 2361 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2362 2363 /* Create DMA maps for Tx buffers. */ 2364 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2365 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2366 txd->tx_m = NULL; 2367 txd->tx_dmamap = NULL; 2368 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2369 &txd->tx_dmamap); 2370 if (error != 0) { 2371 device_printf(sc_if->msk_if_dev, 2372 "failed to create Tx dmamap\n"); 2373 goto fail; 2374 } 2375 } 2376 /* Create DMA maps for Rx buffers. */ 2377 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2378 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2379 device_printf(sc_if->msk_if_dev, 2380 "failed to create spare Rx dmamap\n"); 2381 goto fail; 2382 } 2383 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2384 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2385 rxd->rx_m = NULL; 2386 rxd->rx_dmamap = NULL; 2387 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2388 &rxd->rx_dmamap); 2389 if (error != 0) { 2390 device_printf(sc_if->msk_if_dev, 2391 "failed to create Rx dmamap\n"); 2392 goto fail; 2393 } 2394 } 2395 2396fail: 2397 return (error); 2398} 2399 2400static int 2401msk_rx_dma_jalloc(struct msk_if_softc *sc_if) 2402{ 2403 struct msk_dmamap_arg ctx; 2404 struct msk_rxdesc *jrxd; 2405 bus_size_t rxalign; 2406 int error, i; 2407 2408 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 2409 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2410 device_printf(sc_if->msk_if_dev, 2411 "disabling jumbo frame support\n"); 2412 return (0); 2413 } 2414 /* Create tag for jumbo Rx ring. */ 2415 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2416 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2417 BUS_SPACE_MAXADDR, /* lowaddr */ 2418 BUS_SPACE_MAXADDR, /* highaddr */ 2419 NULL, NULL, /* filter, filterarg */ 2420 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2421 1, /* nsegments */ 2422 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2423 0, /* flags */ 2424 NULL, NULL, /* lockfunc, lockarg */ 2425 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2426 if (error != 0) { 2427 device_printf(sc_if->msk_if_dev, 2428 "failed to create jumbo Rx ring DMA tag\n"); 2429 goto jumbo_fail; 2430 } 2431 2432 rxalign = 1; 2433 /* 2434 * Workaround hardware hang which seems to happen when Rx buffer 2435 * is not aligned on multiple of FIFO word(8 bytes). 2436 */ 2437 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2438 rxalign = MSK_RX_BUF_ALIGN; 2439 /* Create tag for jumbo Rx buffers. */ 2440 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2441 rxalign, 0, /* alignment, boundary */ 2442 BUS_SPACE_MAXADDR, /* lowaddr */ 2443 BUS_SPACE_MAXADDR, /* highaddr */ 2444 NULL, NULL, /* filter, filterarg */ 2445 MJUM9BYTES, /* maxsize */ 2446 1, /* nsegments */ 2447 MJUM9BYTES, /* maxsegsize */ 2448 0, /* flags */ 2449 NULL, NULL, /* lockfunc, lockarg */ 2450 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2451 if (error != 0) { 2452 device_printf(sc_if->msk_if_dev, 2453 "failed to create jumbo Rx DMA tag\n"); 2454 goto jumbo_fail; 2455 } 2456 2457 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2458 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2459 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2460 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2461 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2462 if (error != 0) { 2463 device_printf(sc_if->msk_if_dev, 2464 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2465 goto jumbo_fail; 2466 } 2467 2468 ctx.msk_busaddr = 0; 2469 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2470 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2471 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2472 msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2473 if (error != 0) { 2474 device_printf(sc_if->msk_if_dev, 2475 "failed to load DMA'able memory for jumbo Rx ring\n"); 2476 goto jumbo_fail; 2477 } 2478 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2479 2480 /* Create DMA maps for jumbo Rx buffers. */ 2481 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2482 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2483 device_printf(sc_if->msk_if_dev, 2484 "failed to create spare jumbo Rx dmamap\n"); 2485 goto jumbo_fail; 2486 } 2487 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2488 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2489 jrxd->rx_m = NULL; 2490 jrxd->rx_dmamap = NULL; 2491 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2492 &jrxd->rx_dmamap); 2493 if (error != 0) { 2494 device_printf(sc_if->msk_if_dev, 2495 "failed to create jumbo Rx dmamap\n"); 2496 goto jumbo_fail; 2497 } 2498 } 2499 2500 return (0); 2501 2502jumbo_fail: 2503 msk_rx_dma_jfree(sc_if); 2504 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support " 2505 "due to resource shortage\n"); 2506 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2507 return (error); 2508} 2509 2510static void 2511msk_txrx_dma_free(struct msk_if_softc *sc_if) 2512{ 2513 struct msk_txdesc *txd; 2514 struct msk_rxdesc *rxd; 2515 int i; 2516 2517 /* Tx ring. */ 2518 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2519 if (sc_if->msk_cdata.msk_tx_ring_map) 2520 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2521 sc_if->msk_cdata.msk_tx_ring_map); 2522 if (sc_if->msk_cdata.msk_tx_ring_map && 2523 sc_if->msk_rdata.msk_tx_ring) 2524 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2525 sc_if->msk_rdata.msk_tx_ring, 2526 sc_if->msk_cdata.msk_tx_ring_map); 2527 sc_if->msk_rdata.msk_tx_ring = NULL; 2528 sc_if->msk_cdata.msk_tx_ring_map = NULL; 2529 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2530 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2531 } 2532 /* Rx ring. */ 2533 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2534 if (sc_if->msk_cdata.msk_rx_ring_map) 2535 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2536 sc_if->msk_cdata.msk_rx_ring_map); 2537 if (sc_if->msk_cdata.msk_rx_ring_map && 2538 sc_if->msk_rdata.msk_rx_ring) 2539 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2540 sc_if->msk_rdata.msk_rx_ring, 2541 sc_if->msk_cdata.msk_rx_ring_map); 2542 sc_if->msk_rdata.msk_rx_ring = NULL; 2543 sc_if->msk_cdata.msk_rx_ring_map = NULL; 2544 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2545 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2546 } 2547 /* Tx buffers. */ 2548 if (sc_if->msk_cdata.msk_tx_tag) { 2549 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2550 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2551 if (txd->tx_dmamap) { 2552 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2553 txd->tx_dmamap); 2554 txd->tx_dmamap = NULL; 2555 } 2556 } 2557 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2558 sc_if->msk_cdata.msk_tx_tag = NULL; 2559 } 2560 /* Rx buffers. */ 2561 if (sc_if->msk_cdata.msk_rx_tag) { 2562 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2563 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2564 if (rxd->rx_dmamap) { 2565 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2566 rxd->rx_dmamap); 2567 rxd->rx_dmamap = NULL; 2568 } 2569 } 2570 if (sc_if->msk_cdata.msk_rx_sparemap) { 2571 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2572 sc_if->msk_cdata.msk_rx_sparemap); 2573 sc_if->msk_cdata.msk_rx_sparemap = 0; 2574 } 2575 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2576 sc_if->msk_cdata.msk_rx_tag = NULL; 2577 } 2578 if (sc_if->msk_cdata.msk_parent_tag) { 2579 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2580 sc_if->msk_cdata.msk_parent_tag = NULL; 2581 } 2582} 2583 2584static void 2585msk_rx_dma_jfree(struct msk_if_softc *sc_if) 2586{ 2587 struct msk_rxdesc *jrxd; 2588 int i; 2589 2590 /* Jumbo Rx ring. */ 2591 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2592 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map) 2593 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2594 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2595 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map && 2596 sc_if->msk_rdata.msk_jumbo_rx_ring) 2597 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2598 sc_if->msk_rdata.msk_jumbo_rx_ring, 2599 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2600 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2601 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL; 2602 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2603 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2604 } 2605 /* Jumbo Rx buffers. */ 2606 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2607 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2608 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2609 if (jrxd->rx_dmamap) { 2610 bus_dmamap_destroy( 2611 sc_if->msk_cdata.msk_jumbo_rx_tag, 2612 jrxd->rx_dmamap); 2613 jrxd->rx_dmamap = NULL; 2614 } 2615 } 2616 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2617 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2618 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2619 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2620 } 2621 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2622 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2623 } 2624} 2625 2626static int 2627msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2628{ 2629 struct msk_txdesc *txd, *txd_last; 2630 struct msk_tx_desc *tx_le; 2631 struct mbuf *m; 2632 bus_dmamap_t map; 2633 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2634 uint32_t control, csum, prod, si; 2635 uint16_t offset, tcp_offset, tso_mtu; 2636 int error, i, nseg, tso; 2637 2638 MSK_IF_LOCK_ASSERT(sc_if); 2639 2640 tcp_offset = offset = 0; 2641 m = *m_head; 2642 if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2643 (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) || 2644 ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 2645 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) { 2646 /* 2647 * Since mbuf has no protocol specific structure information 2648 * in it we have to inspect protocol information here to 2649 * setup TSO and checksum offload. I don't know why Marvell 2650 * made a such decision in chip design because other GigE 2651 * hardwares normally takes care of all these chores in 2652 * hardware. However, TSO performance of Yukon II is very 2653 * good such that it's worth to implement it. 2654 */ 2655 struct ether_header *eh; 2656 struct ip *ip; 2657 struct tcphdr *tcp; 2658 2659 if (M_WRITABLE(m) == 0) { 2660 /* Get a writable copy. */ 2661 m = m_dup(*m_head, M_DONTWAIT); 2662 m_freem(*m_head); 2663 if (m == NULL) { 2664 *m_head = NULL; 2665 return (ENOBUFS); 2666 } 2667 *m_head = m; 2668 } 2669 2670 offset = sizeof(struct ether_header); 2671 m = m_pullup(m, offset); 2672 if (m == NULL) { 2673 *m_head = NULL; 2674 return (ENOBUFS); 2675 } 2676 eh = mtod(m, struct ether_header *); 2677 /* Check if hardware VLAN insertion is off. */ 2678 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2679 offset = sizeof(struct ether_vlan_header); 2680 m = m_pullup(m, offset); 2681 if (m == NULL) { 2682 *m_head = NULL; 2683 return (ENOBUFS); 2684 } 2685 } 2686 m = m_pullup(m, offset + sizeof(struct ip)); 2687 if (m == NULL) { 2688 *m_head = NULL; 2689 return (ENOBUFS); 2690 } 2691 ip = (struct ip *)(mtod(m, char *) + offset); 2692 offset += (ip->ip_hl << 2); 2693 tcp_offset = offset; 2694 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2695 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2696 if (m == NULL) { 2697 *m_head = NULL; 2698 return (ENOBUFS); 2699 } 2700 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2701 offset += (tcp->th_off << 2); 2702 } else if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2703 (m->m_pkthdr.len < MSK_MIN_FRAMELEN) && 2704 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2705 /* 2706 * It seems that Yukon II has Tx checksum offload bug 2707 * for small TCP packets that's less than 60 bytes in 2708 * size (e.g. TCP window probe packet, pure ACK packet). 2709 * Common work around like padding with zeros to make 2710 * the frame minimum ethernet frame size didn't work at 2711 * all. 2712 * Instead of disabling checksum offload completely we 2713 * resort to S/W checksum routine when we encounter 2714 * short TCP frames. 2715 * Short UDP packets appear to be handled correctly by 2716 * Yukon II. Also I assume this bug does not happen on 2717 * controllers that use newer descriptor format or 2718 * automatic Tx checksum calculation. 2719 */ 2720 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2721 if (m == NULL) { 2722 *m_head = NULL; 2723 return (ENOBUFS); 2724 } 2725 *(uint16_t *)(m->m_data + offset + 2726 m->m_pkthdr.csum_data) = in_cksum_skip(m, 2727 m->m_pkthdr.len, offset); 2728 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2729 } 2730 *m_head = m; 2731 } 2732 2733 prod = sc_if->msk_cdata.msk_tx_prod; 2734 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2735 txd_last = txd; 2736 map = txd->tx_dmamap; 2737 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2738 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2739 if (error == EFBIG) { 2740 m = m_collapse(*m_head, M_DONTWAIT, MSK_MAXTXSEGS); 2741 if (m == NULL) { 2742 m_freem(*m_head); 2743 *m_head = NULL; 2744 return (ENOBUFS); 2745 } 2746 *m_head = m; 2747 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2748 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2749 if (error != 0) { 2750 m_freem(*m_head); 2751 *m_head = NULL; 2752 return (error); 2753 } 2754 } else if (error != 0) 2755 return (error); 2756 if (nseg == 0) { 2757 m_freem(*m_head); 2758 *m_head = NULL; 2759 return (EIO); 2760 } 2761 2762 /* Check number of available descriptors. */ 2763 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2764 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2765 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2766 return (ENOBUFS); 2767 } 2768 2769 control = 0; 2770 tso = 0; 2771 tx_le = NULL; 2772 2773 /* Check TSO support. */ 2774 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2775 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2776 tso_mtu = m->m_pkthdr.tso_segsz; 2777 else 2778 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2779 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2780 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2781 tx_le->msk_addr = htole32(tso_mtu); 2782 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2783 tx_le->msk_control = htole32(OP_MSS | HW_OWNER); 2784 else 2785 tx_le->msk_control = 2786 htole32(OP_LRGLEN | HW_OWNER); 2787 sc_if->msk_cdata.msk_tx_cnt++; 2788 MSK_INC(prod, MSK_TX_RING_CNT); 2789 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2790 } 2791 tso++; 2792 } 2793 /* Check if we have a VLAN tag to insert. */ 2794 if ((m->m_flags & M_VLANTAG) != 0) { 2795 if (tx_le == NULL) { 2796 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2797 tx_le->msk_addr = htole32(0); 2798 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2799 htons(m->m_pkthdr.ether_vtag)); 2800 sc_if->msk_cdata.msk_tx_cnt++; 2801 MSK_INC(prod, MSK_TX_RING_CNT); 2802 } else { 2803 tx_le->msk_control |= htole32(OP_VLAN | 2804 htons(m->m_pkthdr.ether_vtag)); 2805 } 2806 control |= INS_VLAN; 2807 } 2808 /* Check if we have to handle checksum offload. */ 2809 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2810 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0) 2811 control |= CALSUM; 2812 else { 2813 control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2814 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2815 control |= UDPTCP; 2816 /* Checksum write position. */ 2817 csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff; 2818 /* Checksum start position. */ 2819 csum |= (uint32_t)tcp_offset << 16; 2820 if (csum != sc_if->msk_cdata.msk_last_csum) { 2821 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2822 tx_le->msk_addr = htole32(csum); 2823 tx_le->msk_control = htole32(1 << 16 | 2824 (OP_TCPLISW | HW_OWNER)); 2825 sc_if->msk_cdata.msk_tx_cnt++; 2826 MSK_INC(prod, MSK_TX_RING_CNT); 2827 sc_if->msk_cdata.msk_last_csum = csum; 2828 } 2829 } 2830 } 2831 2832#ifdef MSK_64BIT_DMA 2833 if (MSK_ADDR_HI(txsegs[0].ds_addr) != 2834 sc_if->msk_cdata.msk_tx_high_addr) { 2835 sc_if->msk_cdata.msk_tx_high_addr = 2836 MSK_ADDR_HI(txsegs[0].ds_addr); 2837 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2838 tx_le->msk_addr = htole32(MSK_ADDR_HI(txsegs[0].ds_addr)); 2839 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 2840 sc_if->msk_cdata.msk_tx_cnt++; 2841 MSK_INC(prod, MSK_TX_RING_CNT); 2842 } 2843#endif 2844 si = prod; 2845 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2846 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2847 if (tso == 0) 2848 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2849 OP_PACKET); 2850 else 2851 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2852 OP_LARGESEND); 2853 sc_if->msk_cdata.msk_tx_cnt++; 2854 MSK_INC(prod, MSK_TX_RING_CNT); 2855 2856 for (i = 1; i < nseg; i++) { 2857 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2858#ifdef MSK_64BIT_DMA 2859 if (MSK_ADDR_HI(txsegs[i].ds_addr) != 2860 sc_if->msk_cdata.msk_tx_high_addr) { 2861 sc_if->msk_cdata.msk_tx_high_addr = 2862 MSK_ADDR_HI(txsegs[i].ds_addr); 2863 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2864 tx_le->msk_addr = 2865 htole32(MSK_ADDR_HI(txsegs[i].ds_addr)); 2866 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 2867 sc_if->msk_cdata.msk_tx_cnt++; 2868 MSK_INC(prod, MSK_TX_RING_CNT); 2869 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2870 } 2871#endif 2872 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2873 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2874 OP_BUFFER | HW_OWNER); 2875 sc_if->msk_cdata.msk_tx_cnt++; 2876 MSK_INC(prod, MSK_TX_RING_CNT); 2877 } 2878 /* Update producer index. */ 2879 sc_if->msk_cdata.msk_tx_prod = prod; 2880 2881 /* Set EOP on the last descriptor. */ 2882 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2883 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2884 tx_le->msk_control |= htole32(EOP); 2885 2886 /* Turn the first descriptor ownership to hardware. */ 2887 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2888 tx_le->msk_control |= htole32(HW_OWNER); 2889 2890 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2891 map = txd_last->tx_dmamap; 2892 txd_last->tx_dmamap = txd->tx_dmamap; 2893 txd->tx_dmamap = map; 2894 txd->tx_m = m; 2895 2896 /* Sync descriptors. */ 2897 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2898 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2899 sc_if->msk_cdata.msk_tx_ring_map, 2900 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2901 2902 return (0); 2903} 2904 2905static void 2906msk_start(struct ifnet *ifp) 2907{ 2908 struct msk_if_softc *sc_if; 2909 2910 sc_if = ifp->if_softc; 2911 MSK_IF_LOCK(sc_if); 2912 msk_start_locked(ifp); 2913 MSK_IF_UNLOCK(sc_if); 2914} 2915 2916static void 2917msk_start_locked(struct ifnet *ifp) 2918{ 2919 struct msk_if_softc *sc_if; 2920 struct mbuf *m_head; 2921 int enq; 2922 2923 sc_if = ifp->if_softc; 2924 MSK_IF_LOCK_ASSERT(sc_if); 2925 2926 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2927 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0) 2928 return; 2929 2930 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2931 sc_if->msk_cdata.msk_tx_cnt < 2932 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2933 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2934 if (m_head == NULL) 2935 break; 2936 /* 2937 * Pack the data into the transmit ring. If we 2938 * don't have room, set the OACTIVE flag and wait 2939 * for the NIC to drain the ring. 2940 */ 2941 if (msk_encap(sc_if, &m_head) != 0) { 2942 if (m_head == NULL) 2943 break; 2944 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2945 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2946 break; 2947 } 2948 2949 enq++; 2950 /* 2951 * If there's a BPF listener, bounce a copy of this frame 2952 * to him. 2953 */ 2954 ETHER_BPF_MTAP(ifp, m_head); 2955 } 2956 2957 if (enq > 0) { 2958 /* Transmit */ 2959 CSR_WRITE_2(sc_if->msk_softc, 2960 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2961 sc_if->msk_cdata.msk_tx_prod); 2962 2963 /* Set a timeout in case the chip goes out to lunch. */ 2964 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2965 } 2966} 2967 2968static void 2969msk_watchdog(struct msk_if_softc *sc_if) 2970{ 2971 struct ifnet *ifp; 2972 2973 MSK_IF_LOCK_ASSERT(sc_if); 2974 2975 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2976 return; 2977 ifp = sc_if->msk_ifp; 2978 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) { 2979 if (bootverbose) 2980 if_printf(sc_if->msk_ifp, "watchdog timeout " 2981 "(missed link)\n"); 2982 ifp->if_oerrors++; 2983 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2984 msk_init_locked(sc_if); 2985 return; 2986 } 2987 2988 if_printf(ifp, "watchdog timeout\n"); 2989 ifp->if_oerrors++; 2990 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2991 msk_init_locked(sc_if); 2992 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2993 msk_start_locked(ifp); 2994} 2995 2996static int 2997mskc_shutdown(device_t dev) 2998{ 2999 struct msk_softc *sc; 3000 int i; 3001 3002 sc = device_get_softc(dev); 3003 MSK_LOCK(sc); 3004 for (i = 0; i < sc->msk_num_port; i++) { 3005 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 3006 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 3007 IFF_DRV_RUNNING) != 0)) 3008 msk_stop(sc->msk_if[i]); 3009 } 3010 MSK_UNLOCK(sc); 3011 3012 /* Put hardware reset. */ 3013 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 3014 return (0); 3015} 3016 3017static int 3018mskc_suspend(device_t dev) 3019{ 3020 struct msk_softc *sc; 3021 int i; 3022 3023 sc = device_get_softc(dev); 3024 3025 MSK_LOCK(sc); 3026 3027 for (i = 0; i < sc->msk_num_port; i++) { 3028 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 3029 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 3030 IFF_DRV_RUNNING) != 0)) 3031 msk_stop(sc->msk_if[i]); 3032 } 3033 3034 /* Disable all interrupts. */ 3035 CSR_WRITE_4(sc, B0_IMSK, 0); 3036 CSR_READ_4(sc, B0_IMSK); 3037 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 3038 CSR_READ_4(sc, B0_HWE_IMSK); 3039 3040 msk_phy_power(sc, MSK_PHY_POWERDOWN); 3041 3042 /* Put hardware reset. */ 3043 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 3044 sc->msk_pflags |= MSK_FLAG_SUSPEND; 3045 3046 MSK_UNLOCK(sc); 3047 3048 return (0); 3049} 3050 3051static int 3052mskc_resume(device_t dev) 3053{ 3054 struct msk_softc *sc; 3055 int i; 3056 3057 sc = device_get_softc(dev); 3058 3059 MSK_LOCK(sc); 3060 3061 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 3062 mskc_reset(sc); 3063 for (i = 0; i < sc->msk_num_port; i++) { 3064 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 3065 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) { 3066 sc->msk_if[i]->msk_ifp->if_drv_flags &= 3067 ~IFF_DRV_RUNNING; 3068 msk_init_locked(sc->msk_if[i]); 3069 } 3070 } 3071 sc->msk_pflags &= ~MSK_FLAG_SUSPEND; 3072 3073 MSK_UNLOCK(sc); 3074 3075 return (0); 3076} 3077 3078#ifndef __NO_STRICT_ALIGNMENT 3079static __inline void 3080msk_fixup_rx(struct mbuf *m) 3081{ 3082 int i; 3083 uint16_t *src, *dst; 3084 3085 src = mtod(m, uint16_t *); 3086 dst = src - 3; 3087 3088 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3089 *dst++ = *src++; 3090 3091 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN); 3092} 3093#endif 3094 3095static __inline void 3096msk_rxcsum(struct msk_if_softc *sc_if, uint32_t control, struct mbuf *m) 3097{ 3098 struct ether_header *eh; 3099 struct ip *ip; 3100 struct udphdr *uh; 3101 int32_t hlen, len, pktlen, temp32; 3102 uint16_t csum, *opts; 3103 3104 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) { 3105 if ((control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) { 3106 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3107 if ((control & CSS_IPV4_CSUM_OK) != 0) 3108 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3109 if ((control & (CSS_TCP | CSS_UDP)) != 0 && 3110 (control & (CSS_TCPUDP_CSUM_OK)) != 0) { 3111 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3112 CSUM_PSEUDO_HDR; 3113 m->m_pkthdr.csum_data = 0xffff; 3114 } 3115 } 3116 return; 3117 } 3118 /* 3119 * Marvell Yukon controllers that support OP_RXCHKS has known 3120 * to have various Rx checksum offloading bugs. These 3121 * controllers can be configured to compute simple checksum 3122 * at two different positions. So we can compute IP and TCP/UDP 3123 * checksum at the same time. We intentionally have controller 3124 * compute TCP/UDP checksum twice by specifying the same 3125 * checksum start position and compare the result. If the value 3126 * is different it would indicate the hardware logic was wrong. 3127 */ 3128 if ((sc_if->msk_csum & 0xFFFF) != (sc_if->msk_csum >> 16)) { 3129 if (bootverbose) 3130 device_printf(sc_if->msk_if_dev, 3131 "Rx checksum value mismatch!\n"); 3132 return; 3133 } 3134 pktlen = m->m_pkthdr.len; 3135 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 3136 return; 3137 eh = mtod(m, struct ether_header *); 3138 if (eh->ether_type != htons(ETHERTYPE_IP)) 3139 return; 3140 ip = (struct ip *)(eh + 1); 3141 if (ip->ip_v != IPVERSION) 3142 return; 3143 3144 hlen = ip->ip_hl << 2; 3145 pktlen -= sizeof(struct ether_header); 3146 if (hlen < sizeof(struct ip)) 3147 return; 3148 if (ntohs(ip->ip_len) < hlen) 3149 return; 3150 if (ntohs(ip->ip_len) != pktlen) 3151 return; 3152 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 3153 return; /* can't handle fragmented packet. */ 3154 3155 switch (ip->ip_p) { 3156 case IPPROTO_TCP: 3157 if (pktlen < (hlen + sizeof(struct tcphdr))) 3158 return; 3159 break; 3160 case IPPROTO_UDP: 3161 if (pktlen < (hlen + sizeof(struct udphdr))) 3162 return; 3163 uh = (struct udphdr *)((caddr_t)ip + hlen); 3164 if (uh->uh_sum == 0) 3165 return; /* no checksum */ 3166 break; 3167 default: 3168 return; 3169 } 3170 csum = bswap16(sc_if->msk_csum & 0xFFFF); 3171 /* Checksum fixup for IP options. */ 3172 len = hlen - sizeof(struct ip); 3173 if (len > 0) { 3174 opts = (uint16_t *)(ip + 1); 3175 for (; len > 0; len -= sizeof(uint16_t), opts++) { 3176 temp32 = csum - *opts; 3177 temp32 = (temp32 >> 16) + (temp32 & 65535); 3178 csum = temp32 & 65535; 3179 } 3180 } 3181 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 3182 m->m_pkthdr.csum_data = csum; 3183} 3184 3185static void 3186msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3187 int len) 3188{ 3189 struct mbuf *m; 3190 struct ifnet *ifp; 3191 struct msk_rxdesc *rxd; 3192 int cons, rxlen; 3193 3194 ifp = sc_if->msk_ifp; 3195 3196 MSK_IF_LOCK_ASSERT(sc_if); 3197 3198 cons = sc_if->msk_cdata.msk_rx_cons; 3199 do { 3200 rxlen = status >> 16; 3201 if ((status & GMR_FS_VLAN) != 0 && 3202 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3203 rxlen -= ETHER_VLAN_ENCAP_LEN; 3204 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) { 3205 /* 3206 * For controllers that returns bogus status code 3207 * just do minimal check and let upper stack 3208 * handle this frame. 3209 */ 3210 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) { 3211 ifp->if_ierrors++; 3212 msk_discard_rxbuf(sc_if, cons); 3213 break; 3214 } 3215 } else if (len > sc_if->msk_framesize || 3216 ((status & GMR_FS_ANY_ERR) != 0) || 3217 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3218 /* Don't count flow-control packet as errors. */ 3219 if ((status & GMR_FS_GOOD_FC) == 0) 3220 ifp->if_ierrors++; 3221 msk_discard_rxbuf(sc_if, cons); 3222 break; 3223 } 3224#ifdef MSK_64BIT_DMA 3225 rxd = &sc_if->msk_cdata.msk_rxdesc[(cons + 1) % 3226 MSK_RX_RING_CNT]; 3227#else 3228 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 3229#endif 3230 m = rxd->rx_m; 3231 if (msk_newbuf(sc_if, cons) != 0) { 3232 ifp->if_iqdrops++; 3233 /* Reuse old buffer. */ 3234 msk_discard_rxbuf(sc_if, cons); 3235 break; 3236 } 3237 m->m_pkthdr.rcvif = ifp; 3238 m->m_pkthdr.len = m->m_len = len; 3239#ifndef __NO_STRICT_ALIGNMENT 3240 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3241 msk_fixup_rx(m); 3242#endif 3243 ifp->if_ipackets++; 3244 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3245 msk_rxcsum(sc_if, control, m); 3246 /* Check for VLAN tagged packets. */ 3247 if ((status & GMR_FS_VLAN) != 0 && 3248 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3249 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3250 m->m_flags |= M_VLANTAG; 3251 } 3252 MSK_IF_UNLOCK(sc_if); 3253 (*ifp->if_input)(ifp, m); 3254 MSK_IF_LOCK(sc_if); 3255 } while (0); 3256 3257 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 3258 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 3259} 3260 3261static void 3262msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3263 int len) 3264{ 3265 struct mbuf *m; 3266 struct ifnet *ifp; 3267 struct msk_rxdesc *jrxd; 3268 int cons, rxlen; 3269 3270 ifp = sc_if->msk_ifp; 3271 3272 MSK_IF_LOCK_ASSERT(sc_if); 3273 3274 cons = sc_if->msk_cdata.msk_rx_cons; 3275 do { 3276 rxlen = status >> 16; 3277 if ((status & GMR_FS_VLAN) != 0 && 3278 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3279 rxlen -= ETHER_VLAN_ENCAP_LEN; 3280 if (len > sc_if->msk_framesize || 3281 ((status & GMR_FS_ANY_ERR) != 0) || 3282 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3283 /* Don't count flow-control packet as errors. */ 3284 if ((status & GMR_FS_GOOD_FC) == 0) 3285 ifp->if_ierrors++; 3286 msk_discard_jumbo_rxbuf(sc_if, cons); 3287 break; 3288 } 3289#ifdef MSK_64BIT_DMA 3290 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[(cons + 1) % 3291 MSK_JUMBO_RX_RING_CNT]; 3292#else 3293 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 3294#endif 3295 m = jrxd->rx_m; 3296 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 3297 ifp->if_iqdrops++; 3298 /* Reuse old buffer. */ 3299 msk_discard_jumbo_rxbuf(sc_if, cons); 3300 break; 3301 } 3302 m->m_pkthdr.rcvif = ifp; 3303 m->m_pkthdr.len = m->m_len = len; 3304#ifndef __NO_STRICT_ALIGNMENT 3305 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3306 msk_fixup_rx(m); 3307#endif 3308 ifp->if_ipackets++; 3309 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3310 msk_rxcsum(sc_if, control, m); 3311 /* Check for VLAN tagged packets. */ 3312 if ((status & GMR_FS_VLAN) != 0 && 3313 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3314 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3315 m->m_flags |= M_VLANTAG; 3316 } 3317 MSK_IF_UNLOCK(sc_if); 3318 (*ifp->if_input)(ifp, m); 3319 MSK_IF_LOCK(sc_if); 3320 } while (0); 3321 3322 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3323 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3324} 3325 3326static void 3327msk_txeof(struct msk_if_softc *sc_if, int idx) 3328{ 3329 struct msk_txdesc *txd; 3330 struct msk_tx_desc *cur_tx; 3331 struct ifnet *ifp; 3332 uint32_t control; 3333 int cons, prog; 3334 3335 MSK_IF_LOCK_ASSERT(sc_if); 3336 3337 ifp = sc_if->msk_ifp; 3338 3339 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3340 sc_if->msk_cdata.msk_tx_ring_map, 3341 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3342 /* 3343 * Go through our tx ring and free mbufs for those 3344 * frames that have been sent. 3345 */ 3346 cons = sc_if->msk_cdata.msk_tx_cons; 3347 prog = 0; 3348 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3349 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3350 break; 3351 prog++; 3352 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3353 control = le32toh(cur_tx->msk_control); 3354 sc_if->msk_cdata.msk_tx_cnt--; 3355 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3356 if ((control & EOP) == 0) 3357 continue; 3358 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3359 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3360 BUS_DMASYNC_POSTWRITE); 3361 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3362 3363 ifp->if_opackets++; 3364 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3365 __func__)); 3366 m_freem(txd->tx_m); 3367 txd->tx_m = NULL; 3368 } 3369 3370 if (prog > 0) { 3371 sc_if->msk_cdata.msk_tx_cons = cons; 3372 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3373 sc_if->msk_watchdog_timer = 0; 3374 /* No need to sync LEs as we didn't update LEs. */ 3375 } 3376} 3377 3378static void 3379msk_tick(void *xsc_if) 3380{ 3381 struct msk_if_softc *sc_if; 3382 struct mii_data *mii; 3383 3384 sc_if = xsc_if; 3385 3386 MSK_IF_LOCK_ASSERT(sc_if); 3387 3388 mii = device_get_softc(sc_if->msk_miibus); 3389 3390 mii_tick(mii); 3391 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) 3392 msk_miibus_statchg(sc_if->msk_if_dev); 3393 msk_handle_events(sc_if->msk_softc); 3394 msk_watchdog(sc_if); 3395 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3396} 3397 3398static void 3399msk_intr_phy(struct msk_if_softc *sc_if) 3400{ 3401 uint16_t status; 3402 3403 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3404 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3405 /* Handle FIFO Underrun/Overflow? */ 3406 if ((status & PHY_M_IS_FIFO_ERROR)) 3407 device_printf(sc_if->msk_if_dev, 3408 "PHY FIFO underrun/overflow.\n"); 3409} 3410 3411static void 3412msk_intr_gmac(struct msk_if_softc *sc_if) 3413{ 3414 struct msk_softc *sc; 3415 uint8_t status; 3416 3417 sc = sc_if->msk_softc; 3418 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3419 3420 /* GMAC Rx FIFO overrun. */ 3421 if ((status & GM_IS_RX_FF_OR) != 0) 3422 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3423 GMF_CLI_RX_FO); 3424 /* GMAC Tx FIFO underrun. */ 3425 if ((status & GM_IS_TX_FF_UR) != 0) { 3426 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3427 GMF_CLI_TX_FU); 3428 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3429 /* 3430 * XXX 3431 * In case of Tx underrun, we may need to flush/reset 3432 * Tx MAC but that would also require resynchronization 3433 * with status LEs. Reinitializing status LEs would 3434 * affect other port in dual MAC configuration so it 3435 * should be avoided as possible as we can. 3436 * Due to lack of documentation it's all vague guess but 3437 * it needs more investigation. 3438 */ 3439 } 3440} 3441 3442static void 3443msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3444{ 3445 struct msk_softc *sc; 3446 3447 sc = sc_if->msk_softc; 3448 if ((status & Y2_IS_PAR_RD1) != 0) { 3449 device_printf(sc_if->msk_if_dev, 3450 "RAM buffer read parity error\n"); 3451 /* Clear IRQ. */ 3452 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3453 RI_CLR_RD_PERR); 3454 } 3455 if ((status & Y2_IS_PAR_WR1) != 0) { 3456 device_printf(sc_if->msk_if_dev, 3457 "RAM buffer write parity error\n"); 3458 /* Clear IRQ. */ 3459 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3460 RI_CLR_WR_PERR); 3461 } 3462 if ((status & Y2_IS_PAR_MAC1) != 0) { 3463 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3464 /* Clear IRQ. */ 3465 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3466 GMF_CLI_TX_PE); 3467 } 3468 if ((status & Y2_IS_PAR_RX1) != 0) { 3469 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3470 /* Clear IRQ. */ 3471 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3472 } 3473 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3474 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3475 /* Clear IRQ. */ 3476 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3477 } 3478} 3479 3480static void 3481msk_intr_hwerr(struct msk_softc *sc) 3482{ 3483 uint32_t status; 3484 uint32_t tlphead[4]; 3485 3486 status = CSR_READ_4(sc, B0_HWE_ISRC); 3487 /* Time Stamp timer overflow. */ 3488 if ((status & Y2_IS_TIST_OV) != 0) 3489 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3490 if ((status & Y2_IS_PCI_NEXP) != 0) { 3491 /* 3492 * PCI Express Error occured which is not described in PEX 3493 * spec. 3494 * This error is also mapped either to Master Abort( 3495 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3496 * can only be cleared there. 3497 */ 3498 device_printf(sc->msk_dev, 3499 "PCI Express protocol violation error\n"); 3500 } 3501 3502 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3503 uint16_t v16; 3504 3505 if ((status & Y2_IS_MST_ERR) != 0) 3506 device_printf(sc->msk_dev, 3507 "unexpected IRQ Status error\n"); 3508 else 3509 device_printf(sc->msk_dev, 3510 "unexpected IRQ Master error\n"); 3511 /* Reset all bits in the PCI status register. */ 3512 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3513 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3514 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3515 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3516 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 3517 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3518 } 3519 3520 /* Check for PCI Express Uncorrectable Error. */ 3521 if ((status & Y2_IS_PCI_EXP) != 0) { 3522 uint32_t v32; 3523 3524 /* 3525 * On PCI Express bus bridges are called root complexes (RC). 3526 * PCI Express errors are recognized by the root complex too, 3527 * which requests the system to handle the problem. After 3528 * error occurence it may be that no access to the adapter 3529 * may be performed any longer. 3530 */ 3531 3532 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3533 if ((v32 & PEX_UNSUP_REQ) != 0) { 3534 /* Ignore unsupported request error. */ 3535 device_printf(sc->msk_dev, 3536 "Uncorrectable PCI Express error\n"); 3537 } 3538 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3539 int i; 3540 3541 /* Get TLP header form Log Registers. */ 3542 for (i = 0; i < 4; i++) 3543 tlphead[i] = CSR_PCI_READ_4(sc, 3544 PEX_HEADER_LOG + i * 4); 3545 /* Check for vendor defined broadcast message. */ 3546 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3547 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3548 CSR_WRITE_4(sc, B0_HWE_IMSK, 3549 sc->msk_intrhwemask); 3550 CSR_READ_4(sc, B0_HWE_IMSK); 3551 } 3552 } 3553 /* Clear the interrupt. */ 3554 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3555 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3556 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3557 } 3558 3559 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3560 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3561 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3562 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3563} 3564 3565static __inline void 3566msk_rxput(struct msk_if_softc *sc_if) 3567{ 3568 struct msk_softc *sc; 3569 3570 sc = sc_if->msk_softc; 3571 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) 3572 bus_dmamap_sync( 3573 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3574 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3575 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3576 else 3577 bus_dmamap_sync( 3578 sc_if->msk_cdata.msk_rx_ring_tag, 3579 sc_if->msk_cdata.msk_rx_ring_map, 3580 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3581 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3582 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3583} 3584 3585static int 3586msk_handle_events(struct msk_softc *sc) 3587{ 3588 struct msk_if_softc *sc_if; 3589 int rxput[2]; 3590 struct msk_stat_desc *sd; 3591 uint32_t control, status; 3592 int cons, len, port, rxprog; 3593 3594 if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX)) 3595 return (0); 3596 3597 /* Sync status LEs. */ 3598 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3599 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3600 3601 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3602 rxprog = 0; 3603 cons = sc->msk_stat_cons; 3604 for (;;) { 3605 sd = &sc->msk_stat_ring[cons]; 3606 control = le32toh(sd->msk_control); 3607 if ((control & HW_OWNER) == 0) 3608 break; 3609 control &= ~HW_OWNER; 3610 sd->msk_control = htole32(control); 3611 status = le32toh(sd->msk_status); 3612 len = control & STLE_LEN_MASK; 3613 port = (control >> 16) & 0x01; 3614 sc_if = sc->msk_if[port]; 3615 if (sc_if == NULL) { 3616 device_printf(sc->msk_dev, "invalid port opcode " 3617 "0x%08x\n", control & STLE_OP_MASK); 3618 continue; 3619 } 3620 3621 switch (control & STLE_OP_MASK) { 3622 case OP_RXVLAN: 3623 sc_if->msk_vtag = ntohs(len); 3624 break; 3625 case OP_RXCHKSVLAN: 3626 sc_if->msk_vtag = ntohs(len); 3627 /* FALLTHROUGH */ 3628 case OP_RXCHKS: 3629 sc_if->msk_csum = status; 3630 break; 3631 case OP_RXSTAT: 3632 if (!(sc_if->msk_ifp->if_drv_flags & IFF_DRV_RUNNING)) 3633 break; 3634 if (sc_if->msk_framesize > 3635 (MCLBYTES - MSK_RX_BUF_ALIGN)) 3636 msk_jumbo_rxeof(sc_if, status, control, len); 3637 else 3638 msk_rxeof(sc_if, status, control, len); 3639 rxprog++; 3640 /* 3641 * Because there is no way to sync single Rx LE 3642 * put the DMA sync operation off until the end of 3643 * event processing. 3644 */ 3645 rxput[port]++; 3646 /* Update prefetch unit if we've passed water mark. */ 3647 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3648 msk_rxput(sc_if); 3649 rxput[port] = 0; 3650 } 3651 break; 3652 case OP_TXINDEXLE: 3653 if (sc->msk_if[MSK_PORT_A] != NULL) 3654 msk_txeof(sc->msk_if[MSK_PORT_A], 3655 status & STLE_TXA1_MSKL); 3656 if (sc->msk_if[MSK_PORT_B] != NULL) 3657 msk_txeof(sc->msk_if[MSK_PORT_B], 3658 ((status & STLE_TXA2_MSKL) >> 3659 STLE_TXA2_SHIFTL) | 3660 ((len & STLE_TXA2_MSKH) << 3661 STLE_TXA2_SHIFTH)); 3662 break; 3663 default: 3664 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3665 control & STLE_OP_MASK); 3666 break; 3667 } 3668 MSK_INC(cons, sc->msk_stat_count); 3669 if (rxprog > sc->msk_process_limit) 3670 break; 3671 } 3672 3673 sc->msk_stat_cons = cons; 3674 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3675 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3676 3677 if (rxput[MSK_PORT_A] > 0) 3678 msk_rxput(sc->msk_if[MSK_PORT_A]); 3679 if (rxput[MSK_PORT_B] > 0) 3680 msk_rxput(sc->msk_if[MSK_PORT_B]); 3681 3682 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3683} 3684 3685static void 3686msk_intr(void *xsc) 3687{ 3688 struct msk_softc *sc; 3689 struct msk_if_softc *sc_if0, *sc_if1; 3690 struct ifnet *ifp0, *ifp1; 3691 uint32_t status; 3692 int domore; 3693 3694 sc = xsc; 3695 MSK_LOCK(sc); 3696 3697#ifndef __HAIKU__ 3698 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3699 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3700 if (status == 0 || status == 0xffffffff || 3701 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 || 3702 (status & sc->msk_intrmask) == 0) { 3703 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3704 MSK_UNLOCK(sc); 3705 return; 3706 } 3707#else 3708 status = sc->haiku_interrupt_status; 3709#endif 3710 3711 sc_if0 = sc->msk_if[MSK_PORT_A]; 3712 sc_if1 = sc->msk_if[MSK_PORT_B]; 3713 ifp0 = ifp1 = NULL; 3714 if (sc_if0 != NULL) 3715 ifp0 = sc_if0->msk_ifp; 3716 if (sc_if1 != NULL) 3717 ifp1 = sc_if1->msk_ifp; 3718 3719 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3720 msk_intr_phy(sc_if0); 3721 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3722 msk_intr_phy(sc_if1); 3723 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3724 msk_intr_gmac(sc_if0); 3725 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3726 msk_intr_gmac(sc_if1); 3727 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3728 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3729 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3730 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3731 CSR_READ_4(sc, B0_IMSK); 3732 } 3733 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3734 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3735 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3736 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3737 CSR_READ_4(sc, B0_IMSK); 3738 } 3739 if ((status & Y2_IS_HW_ERR) != 0) 3740 msk_intr_hwerr(sc); 3741 3742 domore = msk_handle_events(sc); 3743 if ((status & Y2_IS_STAT_BMU) != 0 && domore == 0) 3744 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3745 3746#ifndef __HAIKU__ 3747 /* Reenable interrupts. */ 3748 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3749#endif 3750 3751 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3752 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3753 msk_start_locked(ifp0); 3754 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3755 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3756 msk_start_locked(ifp1); 3757 3758 MSK_UNLOCK(sc); 3759} 3760 3761static void 3762msk_set_tx_stfwd(struct msk_if_softc *sc_if) 3763{ 3764 struct msk_softc *sc; 3765 struct ifnet *ifp; 3766 3767 ifp = sc_if->msk_ifp; 3768 sc = sc_if->msk_softc; 3769 if ((sc->msk_hw_id == CHIP_ID_YUKON_EX && 3770 sc->msk_hw_rev != CHIP_REV_YU_EX_A0) || 3771 sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) { 3772 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3773 TX_STFW_ENA); 3774 } else { 3775 if (ifp->if_mtu > ETHERMTU) { 3776 /* Set Tx GMAC FIFO Almost Empty Threshold. */ 3777 CSR_WRITE_4(sc, 3778 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3779 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3780 /* Disable Store & Forward mode for Tx. */ 3781 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3782 TX_STFW_DIS); 3783 } else { 3784 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3785 TX_STFW_ENA); 3786 } 3787 } 3788} 3789 3790static void 3791msk_init(void *xsc) 3792{ 3793 struct msk_if_softc *sc_if = xsc; 3794 3795 MSK_IF_LOCK(sc_if); 3796 msk_init_locked(sc_if); 3797 MSK_IF_UNLOCK(sc_if); 3798} 3799 3800static void 3801msk_init_locked(struct msk_if_softc *sc_if) 3802{ 3803 struct msk_softc *sc; 3804 struct ifnet *ifp; 3805 struct mii_data *mii; 3806 uint8_t *eaddr; 3807 uint16_t gmac; 3808 uint32_t reg; 3809 int error; 3810 3811 MSK_IF_LOCK_ASSERT(sc_if); 3812 3813 ifp = sc_if->msk_ifp; 3814 sc = sc_if->msk_softc; 3815 mii = device_get_softc(sc_if->msk_miibus); 3816 3817 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3818 return; 3819 3820 error = 0; 3821 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3822 msk_stop(sc_if); 3823 3824 if (ifp->if_mtu < ETHERMTU) 3825 sc_if->msk_framesize = ETHERMTU; 3826 else 3827 sc_if->msk_framesize = ifp->if_mtu; 3828 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3829 if (ifp->if_mtu > ETHERMTU && 3830 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 3831 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 3832 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 3833 } 3834 3835 /* GMAC Control reset. */ 3836 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); 3837 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); 3838 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); 3839 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 3840 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) 3841 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), 3842 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 3843 GMC_BYP_RETR_ON); 3844 3845 /* 3846 * Initialize GMAC first such that speed/duplex/flow-control 3847 * parameters are renegotiated when interface is brought up. 3848 */ 3849 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0); 3850 3851 /* Dummy read the Interrupt Source Register. */ 3852 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3853 3854 /* Clear MIB stats. */ 3855 msk_stats_clear(sc_if); 3856 3857 /* Disable FCS. */ 3858 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3859 3860 /* Setup Transmit Control Register. */ 3861 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3862 3863 /* Setup Transmit Flow Control Register. */ 3864 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3865 3866 /* Setup Transmit Parameter Register. */ 3867 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3868 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3869 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3870 3871 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3872 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3873 3874 if (ifp->if_mtu > ETHERMTU) 3875 gmac |= GM_SMOD_JUMBO_ENA; 3876 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3877 3878 /* Set station address. */ 3879 eaddr = IF_LLADDR(ifp); 3880 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L, 3881 eaddr[0] | (eaddr[1] << 8)); 3882 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M, 3883 eaddr[2] | (eaddr[3] << 8)); 3884 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H, 3885 eaddr[4] | (eaddr[5] << 8)); 3886 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L, 3887 eaddr[0] | (eaddr[1] << 8)); 3888 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M, 3889 eaddr[2] | (eaddr[3] << 8)); 3890 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H, 3891 eaddr[4] | (eaddr[5] << 8)); 3892 3893 /* Disable interrupts for counter overflows. */ 3894 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3895 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3896 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3897 3898 /* Configure Rx MAC FIFO. */ 3899 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3900 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3901 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 3902 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P || 3903 sc->msk_hw_id == CHIP_ID_YUKON_EX) 3904 reg |= GMF_RX_OVER_ON; 3905 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); 3906 3907 /* Set receive filter. */ 3908 msk_rxfilter(sc_if); 3909 3910 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 3911 /* Clear flush mask - HW bug. */ 3912 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0); 3913 } else { 3914 /* Flush Rx MAC FIFO on any flow control or error. */ 3915 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3916 GMR_FS_ANY_ERR); 3917 } 3918 3919 /* 3920 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word 3921 * due to hardware hang on receipt of pause frames. 3922 */ 3923 reg = RX_GMF_FL_THR_DEF + 1; 3924 /* Another magic for Yukon FE+ - From Linux. */ 3925 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3926 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) 3927 reg = 0x178; 3928 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg); 3929 3930 /* Configure Tx MAC FIFO. */ 3931 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3932 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3933 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3934 3935 /* Configure hardware VLAN tag insertion/stripping. */ 3936 msk_setvlan(sc_if, ifp); 3937 3938 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { 3939 /* Set Rx Pause threshold. */ 3940 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3941 MSK_ECU_LLPP); 3942 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3943 MSK_ECU_ULPP); 3944 /* Configure store-and-forward for Tx. */ 3945 msk_set_tx_stfwd(sc_if); 3946 } 3947 3948 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3949 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 3950 /* Disable dynamic watermark - from Linux. */ 3951 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA)); 3952 reg &= ~0x03; 3953 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); 3954 } 3955 3956 /* 3957 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3958 * arbiter as we don't use Sync Tx queue. 3959 */ 3960 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3961 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3962 /* Enable the RAM Interface Arbiter. */ 3963 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3964 3965 /* Setup RAM buffer. */ 3966 msk_set_rambuffer(sc_if); 3967 3968 /* Disable Tx sync Queue. */ 3969 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3970 3971 /* Setup Tx Queue Bus Memory Interface. */ 3972 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3973 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3974 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3975 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3976 switch (sc->msk_hw_id) { 3977 case CHIP_ID_YUKON_EC_U: 3978 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3979 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3980 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), 3981 MSK_ECU_TXFF_LEV); 3982 } 3983 break; 3984 case CHIP_ID_YUKON_EX: 3985 /* 3986 * Yukon Extreme seems to have silicon bug for 3987 * automatic Tx checksum calculation capability. 3988 */ 3989 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 3990 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F), 3991 F_TX_CHK_AUTO_OFF); 3992 break; 3993 } 3994 3995 /* Setup Rx Queue Bus Memory Interface. */ 3996 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3997 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3998 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3999 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 4000 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 4001 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 4002 /* MAC Rx RAM Read is controlled by hardware. */ 4003 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 4004 } 4005 4006 msk_set_prefetch(sc, sc_if->msk_txq, 4007 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 4008 msk_init_tx_ring(sc_if); 4009 4010 /* Disable Rx checksum offload and RSS hash. */ 4011 reg = BMU_DIS_RX_RSS_HASH; 4012 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 4013 (ifp->if_capenable & IFCAP_RXCSUM) != 0) 4014 reg |= BMU_ENA_RX_CHKSUM; 4015 else 4016 reg |= BMU_DIS_RX_CHKSUM; 4017 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg); 4018 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) { 4019 msk_set_prefetch(sc, sc_if->msk_rxq, 4020 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 4021 MSK_JUMBO_RX_RING_CNT - 1); 4022 error = msk_init_jumbo_rx_ring(sc_if); 4023 } else { 4024 msk_set_prefetch(sc, sc_if->msk_rxq, 4025 sc_if->msk_rdata.msk_rx_ring_paddr, 4026 MSK_RX_RING_CNT - 1); 4027 error = msk_init_rx_ring(sc_if); 4028 } 4029 if (error != 0) { 4030 device_printf(sc_if->msk_if_dev, 4031 "initialization failed: no memory for Rx buffers\n"); 4032 msk_stop(sc_if); 4033 return; 4034 } 4035 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 4036 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 4037 /* Disable flushing of non-ASF packets. */ 4038 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 4039 GMF_RX_MACSEC_FLUSH_OFF); 4040 } 4041 4042 /* Configure interrupt handling. */ 4043 if (sc_if->msk_port == MSK_PORT_A) { 4044 sc->msk_intrmask |= Y2_IS_PORT_A; 4045 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 4046 } else { 4047 sc->msk_intrmask |= Y2_IS_PORT_B; 4048 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 4049 } 4050 /* Configure IRQ moderation mask. */ 4051 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask); 4052 if (sc->msk_int_holdoff > 0) { 4053 /* Configure initial IRQ moderation timer value. */ 4054 CSR_WRITE_4(sc, B2_IRQM_INI, 4055 MSK_USECS(sc, sc->msk_int_holdoff)); 4056 CSR_WRITE_4(sc, B2_IRQM_VAL, 4057 MSK_USECS(sc, sc->msk_int_holdoff)); 4058 /* Start IRQ moderation. */ 4059 CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START); 4060 } 4061 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4062 CSR_READ_4(sc, B0_HWE_IMSK); 4063 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4064 CSR_READ_4(sc, B0_IMSK); 4065 4066 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4067 mii_mediachg(mii); 4068 4069 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4070 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4071 4072 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 4073} 4074 4075static void 4076msk_set_rambuffer(struct msk_if_softc *sc_if) 4077{ 4078 struct msk_softc *sc; 4079 int ltpp, utpp; 4080 4081 sc = sc_if->msk_softc; 4082 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 4083 return; 4084 4085 /* Setup Rx Queue. */ 4086 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 4087 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 4088 sc->msk_rxqstart[sc_if->msk_port] / 8); 4089 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 4090 sc->msk_rxqend[sc_if->msk_port] / 8); 4091 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 4092 sc->msk_rxqstart[sc_if->msk_port] / 8); 4093 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 4094 sc->msk_rxqstart[sc_if->msk_port] / 8); 4095 4096 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 4097 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 4098 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 4099 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 4100 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 4101 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 4102 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 4103 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 4104 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 4105 4106 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 4107 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 4108 4109 /* Setup Tx Queue. */ 4110 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 4111 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 4112 sc->msk_txqstart[sc_if->msk_port] / 8); 4113 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 4114 sc->msk_txqend[sc_if->msk_port] / 8); 4115 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 4116 sc->msk_txqstart[sc_if->msk_port] / 8); 4117 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 4118 sc->msk_txqstart[sc_if->msk_port] / 8); 4119 /* Enable Store & Forward for Tx side. */ 4120 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 4121 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 4122 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 4123} 4124 4125static void 4126msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 4127 uint32_t count) 4128{ 4129 4130 /* Reset the prefetch unit. */ 4131 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4132 PREF_UNIT_RST_SET); 4133 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4134 PREF_UNIT_RST_CLR); 4135 /* Set LE base address. */ 4136 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 4137 MSK_ADDR_LO(addr)); 4138 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 4139 MSK_ADDR_HI(addr)); 4140 /* Set the list last index. */ 4141 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 4142 count); 4143 /* Turn on prefetch unit. */ 4144 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4145 PREF_UNIT_OP_ON); 4146 /* Dummy read to ensure write. */ 4147 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 4148} 4149 4150static void 4151msk_stop(struct msk_if_softc *sc_if) 4152{ 4153 struct msk_softc *sc; 4154 struct msk_txdesc *txd; 4155 struct msk_rxdesc *rxd; 4156 struct msk_rxdesc *jrxd; 4157 struct ifnet *ifp; 4158 uint32_t val; 4159 int i; 4160 4161 MSK_IF_LOCK_ASSERT(sc_if); 4162 sc = sc_if->msk_softc; 4163 ifp = sc_if->msk_ifp; 4164 4165 callout_stop(&sc_if->msk_tick_ch); 4166 sc_if->msk_watchdog_timer = 0; 4167 4168 /* Disable interrupts. */ 4169 if (sc_if->msk_port == MSK_PORT_A) { 4170 sc->msk_intrmask &= ~Y2_IS_PORT_A; 4171 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 4172 } else { 4173 sc->msk_intrmask &= ~Y2_IS_PORT_B; 4174 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 4175 } 4176 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4177 CSR_READ_4(sc, B0_HWE_IMSK); 4178 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4179 CSR_READ_4(sc, B0_IMSK); 4180 4181 /* Disable Tx/Rx MAC. */ 4182 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4183 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 4184 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 4185 /* Read again to ensure writing. */ 4186 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4187 /* Update stats and clear counters. */ 4188 msk_stats_update(sc_if); 4189 4190 /* Stop Tx BMU. */ 4191 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 4192 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4193 for (i = 0; i < MSK_TIMEOUT; i++) { 4194 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 4195 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4196 BMU_STOP); 4197 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4198 } else 4199 break; 4200 DELAY(1); 4201 } 4202 if (i == MSK_TIMEOUT) 4203 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 4204 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 4205 RB_RST_SET | RB_DIS_OP_MD); 4206 4207 /* Disable all GMAC interrupt. */ 4208 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 4209 /* Disable PHY interrupt. */ 4210 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 4211 4212 /* Disable the RAM Interface Arbiter. */ 4213 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 4214 4215 /* Reset the PCI FIFO of the async Tx queue */ 4216 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4217 BMU_RST_SET | BMU_FIFO_RST); 4218 4219 /* Reset the Tx prefetch units. */ 4220 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 4221 PREF_UNIT_RST_SET); 4222 4223 /* Reset the RAM Buffer async Tx queue. */ 4224 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 4225 4226 /* Reset Tx MAC FIFO. */ 4227 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 4228 /* Set Pause Off. */ 4229 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 4230 4231 /* 4232 * The Rx Stop command will not work for Yukon-2 if the BMU does not 4233 * reach the end of packet and since we can't make sure that we have 4234 * incoming data, we must reset the BMU while it is not during a DMA 4235 * transfer. Since it is possible that the Rx path is still active, 4236 * the Rx RAM buffer will be stopped first, so any possible incoming 4237 * data will not trigger a DMA. After the RAM buffer is stopped, the 4238 * BMU is polled until any DMA in progress is ended and only then it 4239 * will be reset. 4240 */ 4241 4242 /* Disable the RAM Buffer receive queue. */ 4243 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 4244 for (i = 0; i < MSK_TIMEOUT; i++) { 4245 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 4246 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 4247 break; 4248 DELAY(1); 4249 } 4250 if (i == MSK_TIMEOUT) 4251 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 4252 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 4253 BMU_RST_SET | BMU_FIFO_RST); 4254 /* Reset the Rx prefetch unit. */ 4255 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 4256 PREF_UNIT_RST_SET); 4257 /* Reset the RAM Buffer receive queue. */ 4258 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 4259 /* Reset Rx MAC FIFO. */ 4260 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 4261 4262 /* Free Rx and Tx mbufs still in the queues. */ 4263 for (i = 0; i < MSK_RX_RING_CNT; i++) { 4264 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 4265 if (rxd->rx_m != NULL) { 4266 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 4267 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4268 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 4269 rxd->rx_dmamap); 4270 m_freem(rxd->rx_m); 4271 rxd->rx_m = NULL; 4272 } 4273 } 4274 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 4275 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 4276 if (jrxd->rx_m != NULL) { 4277 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 4278 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4279 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 4280 jrxd->rx_dmamap); 4281 m_freem(jrxd->rx_m); 4282 jrxd->rx_m = NULL; 4283 } 4284 } 4285 for (i = 0; i < MSK_TX_RING_CNT; i++) { 4286 txd = &sc_if->msk_cdata.msk_txdesc[i]; 4287 if (txd->tx_m != NULL) { 4288 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 4289 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4290 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 4291 txd->tx_dmamap); 4292 m_freem(txd->tx_m); 4293 txd->tx_m = NULL; 4294 } 4295 } 4296 4297 /* 4298 * Mark the interface down. 4299 */ 4300 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4301 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4302} 4303 4304/* 4305 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower 4306 * counter clears high 16 bits of the counter such that accessing 4307 * lower 16 bits should be the last operation. 4308 */ 4309#define MSK_READ_MIB32(x, y) \ 4310 (((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \ 4311 (uint32_t)GMAC_READ_2(sc, x, y) 4312#define MSK_READ_MIB64(x, y) \ 4313 (((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \ 4314 (uint64_t)MSK_READ_MIB32(x, y) 4315 4316static void 4317msk_stats_clear(struct msk_if_softc *sc_if) 4318{ 4319 struct msk_softc *sc; 4320 uint32_t reg; 4321 uint16_t gmac; 4322 int i; 4323 4324 MSK_IF_LOCK_ASSERT(sc_if); 4325 4326 sc = sc_if->msk_softc; 4327 /* Set MIB Clear Counter Mode. */ 4328 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4329 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4330 /* Read all MIB Counters with Clear Mode set. */ 4331 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t)) 4332 reg = MSK_READ_MIB32(sc_if->msk_port, i); 4333 /* Clear MIB Clear Counter Mode. */ 4334 gmac &= ~GM_PAR_MIB_CLR; 4335 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4336} 4337 4338static void 4339msk_stats_update(struct msk_if_softc *sc_if) 4340{ 4341 struct msk_softc *sc; 4342 struct ifnet *ifp; 4343 struct msk_hw_stats *stats; 4344 uint16_t gmac; 4345 uint32_t reg; 4346 4347 MSK_IF_LOCK_ASSERT(sc_if); 4348 4349 ifp = sc_if->msk_ifp; 4350 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 4351 return; 4352 sc = sc_if->msk_softc; 4353 stats = &sc_if->msk_stats; 4354 /* Set MIB Clear Counter Mode. */ 4355 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4356 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4357 4358 /* Rx stats. */ 4359 stats->rx_ucast_frames += 4360 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK); 4361 stats->rx_bcast_frames += 4362 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK); 4363 stats->rx_pause_frames += 4364 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE); 4365 stats->rx_mcast_frames += 4366 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK); 4367 stats->rx_crc_errs += 4368 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR); 4369 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE1); 4370 stats->rx_good_octets += 4371 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO); 4372 stats->rx_bad_octets += 4373 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO); 4374 stats->rx_runts += 4375 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT); 4376 stats->rx_runt_errs += 4377 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG); 4378 stats->rx_pkts_64 += 4379 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B); 4380 stats->rx_pkts_65_127 += 4381 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B); 4382 stats->rx_pkts_128_255 += 4383 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B); 4384 stats->rx_pkts_256_511 += 4385 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B); 4386 stats->rx_pkts_512_1023 += 4387 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B); 4388 stats->rx_pkts_1024_1518 += 4389 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B); 4390 stats->rx_pkts_1519_max += 4391 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ); 4392 stats->rx_pkts_too_long += 4393 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR); 4394 stats->rx_pkts_jabbers += 4395 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT); 4396 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE2); 4397 stats->rx_fifo_oflows += 4398 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV); 4399 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE3); 4400 4401 /* Tx stats. */ 4402 stats->tx_ucast_frames += 4403 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK); 4404 stats->tx_bcast_frames += 4405 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK); 4406 stats->tx_pause_frames += 4407 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE); 4408 stats->tx_mcast_frames += 4409 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK); 4410 stats->tx_octets += 4411 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO); 4412 stats->tx_pkts_64 += 4413 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B); 4414 stats->tx_pkts_65_127 += 4415 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B); 4416 stats->tx_pkts_128_255 += 4417 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B); 4418 stats->tx_pkts_256_511 += 4419 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B); 4420 stats->tx_pkts_512_1023 += 4421 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B); 4422 stats->tx_pkts_1024_1518 += 4423 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B); 4424 stats->tx_pkts_1519_max += 4425 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ); 4426 reg = MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SPARE1); 4427 stats->tx_colls += 4428 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL); 4429 stats->tx_late_colls += 4430 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL); 4431 stats->tx_excess_colls += 4432 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL); 4433 stats->tx_multi_colls += 4434 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL); 4435 stats->tx_single_colls += 4436 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL); 4437 stats->tx_underflows += 4438 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR); 4439 /* Clear MIB Clear Counter Mode. */ 4440 gmac &= ~GM_PAR_MIB_CLR; 4441 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4442} 4443 4444static int 4445msk_sysctl_stat32(SYSCTL_HANDLER_ARGS) 4446{ 4447 struct msk_softc *sc; 4448 struct msk_if_softc *sc_if; 4449 uint32_t result, *stat; 4450 int off; 4451 4452 sc_if = (struct msk_if_softc *)arg1; 4453 sc = sc_if->msk_softc; 4454 off = arg2; 4455 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off); 4456 4457 MSK_IF_LOCK(sc_if); 4458 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4459 result += *stat; 4460 MSK_IF_UNLOCK(sc_if); 4461 4462 return (sysctl_handle_int(oidp, &result, 0, req)); 4463} 4464 4465static int 4466msk_sysctl_stat64(SYSCTL_HANDLER_ARGS) 4467{ 4468 struct msk_softc *sc; 4469 struct msk_if_softc *sc_if; 4470 uint64_t result, *stat; 4471 int off; 4472 4473 sc_if = (struct msk_if_softc *)arg1; 4474 sc = sc_if->msk_softc; 4475 off = arg2; 4476 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off); 4477 4478 MSK_IF_LOCK(sc_if); 4479 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4480 result += *stat; 4481 MSK_IF_UNLOCK(sc_if); 4482 4483 return (sysctl_handle_64(oidp, &result, 0, req)); 4484} 4485 4486#undef MSK_READ_MIB32 4487#undef MSK_READ_MIB64 4488 4489#define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \ 4490 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \ 4491 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \ 4492 "IU", d) 4493#define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \ 4494 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_U64 | CTLFLAG_RD, \ 4495 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \ 4496 "QU", d) 4497 4498static void 4499msk_sysctl_node(struct msk_if_softc *sc_if) 4500{ 4501 struct sysctl_ctx_list *ctx; 4502 struct sysctl_oid_list *child, *schild; 4503 struct sysctl_oid *tree; 4504 4505 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev); 4506 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev)); 4507 4508 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 4509 NULL, "MSK Statistics"); 4510 schild = child = SYSCTL_CHILDREN(tree); 4511 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 4512 NULL, "MSK RX Statistics"); 4513 child = SYSCTL_CHILDREN(tree); 4514 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4515 child, rx_ucast_frames, "Good unicast frames"); 4516 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4517 child, rx_bcast_frames, "Good broadcast frames"); 4518 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4519 child, rx_pause_frames, "Pause frames"); 4520 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4521 child, rx_mcast_frames, "Multicast frames"); 4522 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs", 4523 child, rx_crc_errs, "CRC errors"); 4524 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets", 4525 child, rx_good_octets, "Good octets"); 4526 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets", 4527 child, rx_bad_octets, "Bad octets"); 4528 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4529 child, rx_pkts_64, "64 bytes frames"); 4530 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4531 child, rx_pkts_65_127, "65 to 127 bytes frames"); 4532 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4533 child, rx_pkts_128_255, "128 to 255 bytes frames"); 4534 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4535 child, rx_pkts_256_511, "256 to 511 bytes frames"); 4536 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4537 child, rx_pkts_512_1023, "512 to 1023 bytes frames"); 4538 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4539 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4540 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4541 child, rx_pkts_1519_max, "1519 to max frames"); 4542 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long", 4543 child, rx_pkts_too_long, "frames too long"); 4544 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers", 4545 child, rx_pkts_jabbers, "Jabber errors"); 4546 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows", 4547 child, rx_fifo_oflows, "FIFO overflows"); 4548 4549 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 4550 NULL, "MSK TX Statistics"); 4551 child = SYSCTL_CHILDREN(tree); 4552 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4553 child, tx_ucast_frames, "Unicast frames"); 4554 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4555 child, tx_bcast_frames, "Broadcast frames"); 4556 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4557 child, tx_pause_frames, "Pause frames"); 4558 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4559 child, tx_mcast_frames, "Multicast frames"); 4560 MSK_SYSCTL_STAT64(sc_if, ctx, "octets", 4561 child, tx_octets, "Octets"); 4562 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4563 child, tx_pkts_64, "64 bytes frames"); 4564 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4565 child, tx_pkts_65_127, "65 to 127 bytes frames"); 4566 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4567 child, tx_pkts_128_255, "128 to 255 bytes frames"); 4568 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4569 child, tx_pkts_256_511, "256 to 511 bytes frames"); 4570 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4571 child, tx_pkts_512_1023, "512 to 1023 bytes frames"); 4572 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4573 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4574 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4575 child, tx_pkts_1519_max, "1519 to max frames"); 4576 MSK_SYSCTL_STAT32(sc_if, ctx, "colls", 4577 child, tx_colls, "Collisions"); 4578 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls", 4579 child, tx_late_colls, "Late collisions"); 4580 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls", 4581 child, tx_excess_colls, "Excessive collisions"); 4582 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls", 4583 child, tx_multi_colls, "Multiple collisions"); 4584 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls", 4585 child, tx_single_colls, "Single collisions"); 4586 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows", 4587 child, tx_underflows, "FIFO underflows"); 4588} 4589 4590#undef MSK_SYSCTL_STAT32 4591#undef MSK_SYSCTL_STAT64 4592 4593static int 4594sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4595{ 4596 int error, value; 4597 4598 if (!arg1) 4599 return (EINVAL); 4600 value = *(int *)arg1; 4601 error = sysctl_handle_int(oidp, &value, 0, req); 4602 if (error || !req->newptr) 4603 return (error); 4604 if (value < low || value > high) 4605 return (EINVAL); 4606 *(int *)arg1 = value; 4607 4608 return (0); 4609} 4610 4611static int 4612sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4613{ 4614 4615 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4616 MSK_PROC_MAX)); 4617} 4618