1/****************************************************************************** 2 3 Copyright (c) 2001-2011, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD$*/ 34 35#include "e1000_api.h" 36 37static void e1000_reload_nvm_generic(struct e1000_hw *hw); 38 39/** 40 * e1000_init_nvm_ops_generic - Initialize NVM function pointers 41 * @hw: pointer to the HW structure 42 * 43 * Setups up the function pointers to no-op functions 44 **/ 45void e1000_init_nvm_ops_generic(struct e1000_hw *hw) 46{ 47 struct e1000_nvm_info *nvm = &hw->nvm; 48 DEBUGFUNC("e1000_init_nvm_ops_generic"); 49 50 /* Initialize function pointers */ 51 nvm->ops.init_params = e1000_null_ops_generic; 52 nvm->ops.acquire = e1000_null_ops_generic; 53 nvm->ops.read = e1000_null_read_nvm; 54 nvm->ops.release = e1000_null_nvm_generic; 55 nvm->ops.reload = e1000_reload_nvm_generic; 56 nvm->ops.update = e1000_null_ops_generic; 57 nvm->ops.valid_led_default = e1000_null_led_default; 58 nvm->ops.validate = e1000_null_ops_generic; 59 nvm->ops.write = e1000_null_write_nvm; 60} 61 62/** 63 * e1000_null_nvm_read - No-op function, return 0 64 * @hw: pointer to the HW structure 65 **/ 66s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c) 67{ 68 DEBUGFUNC("e1000_null_read_nvm"); 69 return E1000_SUCCESS; 70} 71 72/** 73 * e1000_null_nvm_generic - No-op function, return void 74 * @hw: pointer to the HW structure 75 **/ 76void e1000_null_nvm_generic(struct e1000_hw *hw) 77{ 78 DEBUGFUNC("e1000_null_nvm_generic"); 79 return; 80} 81 82/** 83 * e1000_null_led_default - No-op function, return 0 84 * @hw: pointer to the HW structure 85 **/ 86s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data) 87{ 88 DEBUGFUNC("e1000_null_led_default"); 89 return E1000_SUCCESS; 90} 91 92/** 93 * e1000_null_write_nvm - No-op function, return 0 94 * @hw: pointer to the HW structure 95 **/ 96s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c) 97{ 98 DEBUGFUNC("e1000_null_write_nvm"); 99 return E1000_SUCCESS; 100} 101 102/** 103 * e1000_raise_eec_clk - Raise EEPROM clock 104 * @hw: pointer to the HW structure 105 * @eecd: pointer to the EEPROM 106 * 107 * Enable/Raise the EEPROM clock bit. 108 **/ 109static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) 110{ 111 *eecd = *eecd | E1000_EECD_SK; 112 E1000_WRITE_REG(hw, E1000_EECD, *eecd); 113 E1000_WRITE_FLUSH(hw); 114 usec_delay(hw->nvm.delay_usec); 115} 116 117/** 118 * e1000_lower_eec_clk - Lower EEPROM clock 119 * @hw: pointer to the HW structure 120 * @eecd: pointer to the EEPROM 121 * 122 * Clear/Lower the EEPROM clock bit. 123 **/ 124static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) 125{ 126 *eecd = *eecd & ~E1000_EECD_SK; 127 E1000_WRITE_REG(hw, E1000_EECD, *eecd); 128 E1000_WRITE_FLUSH(hw); 129 usec_delay(hw->nvm.delay_usec); 130} 131 132/** 133 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM 134 * @hw: pointer to the HW structure 135 * @data: data to send to the EEPROM 136 * @count: number of bits to shift out 137 * 138 * We need to shift 'count' bits out to the EEPROM. So, the value in the 139 * "data" parameter will be shifted out to the EEPROM one bit at a time. 140 * In order to do this, "data" must be broken down into bits. 141 **/ 142static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) 143{ 144 struct e1000_nvm_info *nvm = &hw->nvm; 145 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 146 u32 mask; 147 148 DEBUGFUNC("e1000_shift_out_eec_bits"); 149 150 mask = 0x01 << (count - 1); 151 if (nvm->type == e1000_nvm_eeprom_microwire) 152 eecd &= ~E1000_EECD_DO; 153 else 154 if (nvm->type == e1000_nvm_eeprom_spi) 155 eecd |= E1000_EECD_DO; 156 157 do { 158 eecd &= ~E1000_EECD_DI; 159 160 if (data & mask) 161 eecd |= E1000_EECD_DI; 162 163 E1000_WRITE_REG(hw, E1000_EECD, eecd); 164 E1000_WRITE_FLUSH(hw); 165 166 usec_delay(nvm->delay_usec); 167 168 e1000_raise_eec_clk(hw, &eecd); 169 e1000_lower_eec_clk(hw, &eecd); 170 171 mask >>= 1; 172 } while (mask); 173 174 eecd &= ~E1000_EECD_DI; 175 E1000_WRITE_REG(hw, E1000_EECD, eecd); 176} 177 178/** 179 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM 180 * @hw: pointer to the HW structure 181 * @count: number of bits to shift in 182 * 183 * In order to read a register from the EEPROM, we need to shift 'count' bits 184 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 185 * the EEPROM (setting the SK bit), and then reading the value of the data out 186 * "DO" bit. During this "shifting in" process the data in "DI" bit should 187 * always be clear. 188 **/ 189static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) 190{ 191 u32 eecd; 192 u32 i; 193 u16 data; 194 195 DEBUGFUNC("e1000_shift_in_eec_bits"); 196 197 eecd = E1000_READ_REG(hw, E1000_EECD); 198 199 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 200 data = 0; 201 202 for (i = 0; i < count; i++) { 203 data <<= 1; 204 e1000_raise_eec_clk(hw, &eecd); 205 206 eecd = E1000_READ_REG(hw, E1000_EECD); 207 208 eecd &= ~E1000_EECD_DI; 209 if (eecd & E1000_EECD_DO) 210 data |= 1; 211 212 e1000_lower_eec_clk(hw, &eecd); 213 } 214 215 return data; 216} 217 218/** 219 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion 220 * @hw: pointer to the HW structure 221 * @ee_reg: EEPROM flag for polling 222 * 223 * Polls the EEPROM status bit for either read or write completion based 224 * upon the value of 'ee_reg'. 225 **/ 226s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) 227{ 228 u32 attempts = 100000; 229 u32 i, reg = 0; 230 s32 ret_val = -E1000_ERR_NVM; 231 232 DEBUGFUNC("e1000_poll_eerd_eewr_done"); 233 234 for (i = 0; i < attempts; i++) { 235 if (ee_reg == E1000_NVM_POLL_READ) 236 reg = E1000_READ_REG(hw, E1000_EERD); 237 else 238 reg = E1000_READ_REG(hw, E1000_EEWR); 239 240 if (reg & E1000_NVM_RW_REG_DONE) { 241 ret_val = E1000_SUCCESS; 242 break; 243 } 244 245 usec_delay(5); 246 } 247 248 return ret_val; 249} 250 251/** 252 * e1000_acquire_nvm_generic - Generic request for access to EEPROM 253 * @hw: pointer to the HW structure 254 * 255 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 256 * Return successful if access grant bit set, else clear the request for 257 * EEPROM access and return -E1000_ERR_NVM (-1). 258 **/ 259s32 e1000_acquire_nvm_generic(struct e1000_hw *hw) 260{ 261 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 262 s32 timeout = E1000_NVM_GRANT_ATTEMPTS; 263 s32 ret_val = E1000_SUCCESS; 264 265 DEBUGFUNC("e1000_acquire_nvm_generic"); 266 267 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ); 268 eecd = E1000_READ_REG(hw, E1000_EECD); 269 270 while (timeout) { 271 if (eecd & E1000_EECD_GNT) 272 break; 273 usec_delay(5); 274 eecd = E1000_READ_REG(hw, E1000_EECD); 275 timeout--; 276 } 277 278 if (!timeout) { 279 eecd &= ~E1000_EECD_REQ; 280 E1000_WRITE_REG(hw, E1000_EECD, eecd); 281 DEBUGOUT("Could not acquire NVM grant\n"); 282 ret_val = -E1000_ERR_NVM; 283 } 284 285 return ret_val; 286} 287 288/** 289 * e1000_standby_nvm - Return EEPROM to standby state 290 * @hw: pointer to the HW structure 291 * 292 * Return the EEPROM to a standby state. 293 **/ 294static void e1000_standby_nvm(struct e1000_hw *hw) 295{ 296 struct e1000_nvm_info *nvm = &hw->nvm; 297 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 298 299 DEBUGFUNC("e1000_standby_nvm"); 300 301 if (nvm->type == e1000_nvm_eeprom_microwire) { 302 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 303 E1000_WRITE_REG(hw, E1000_EECD, eecd); 304 E1000_WRITE_FLUSH(hw); 305 usec_delay(nvm->delay_usec); 306 307 e1000_raise_eec_clk(hw, &eecd); 308 309 /* Select EEPROM */ 310 eecd |= E1000_EECD_CS; 311 E1000_WRITE_REG(hw, E1000_EECD, eecd); 312 E1000_WRITE_FLUSH(hw); 313 usec_delay(nvm->delay_usec); 314 315 e1000_lower_eec_clk(hw, &eecd); 316 } else if (nvm->type == e1000_nvm_eeprom_spi) { 317 /* Toggle CS to flush commands */ 318 eecd |= E1000_EECD_CS; 319 E1000_WRITE_REG(hw, E1000_EECD, eecd); 320 E1000_WRITE_FLUSH(hw); 321 usec_delay(nvm->delay_usec); 322 eecd &= ~E1000_EECD_CS; 323 E1000_WRITE_REG(hw, E1000_EECD, eecd); 324 E1000_WRITE_FLUSH(hw); 325 usec_delay(nvm->delay_usec); 326 } 327} 328 329/** 330 * e1000_stop_nvm - Terminate EEPROM command 331 * @hw: pointer to the HW structure 332 * 333 * Terminates the current command by inverting the EEPROM's chip select pin. 334 **/ 335void e1000_stop_nvm(struct e1000_hw *hw) 336{ 337 u32 eecd; 338 339 DEBUGFUNC("e1000_stop_nvm"); 340 341 eecd = E1000_READ_REG(hw, E1000_EECD); 342 if (hw->nvm.type == e1000_nvm_eeprom_spi) { 343 /* Pull CS high */ 344 eecd |= E1000_EECD_CS; 345 e1000_lower_eec_clk(hw, &eecd); 346 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) { 347 /* CS on Microwire is active-high */ 348 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 349 E1000_WRITE_REG(hw, E1000_EECD, eecd); 350 e1000_raise_eec_clk(hw, &eecd); 351 e1000_lower_eec_clk(hw, &eecd); 352 } 353} 354 355/** 356 * e1000_release_nvm_generic - Release exclusive access to EEPROM 357 * @hw: pointer to the HW structure 358 * 359 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 360 **/ 361void e1000_release_nvm_generic(struct e1000_hw *hw) 362{ 363 u32 eecd; 364 365 DEBUGFUNC("e1000_release_nvm_generic"); 366 367 e1000_stop_nvm(hw); 368 369 eecd = E1000_READ_REG(hw, E1000_EECD); 370 eecd &= ~E1000_EECD_REQ; 371 E1000_WRITE_REG(hw, E1000_EECD, eecd); 372} 373 374/** 375 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write 376 * @hw: pointer to the HW structure 377 * 378 * Setups the EEPROM for reading and writing. 379 **/ 380static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) 381{ 382 struct e1000_nvm_info *nvm = &hw->nvm; 383 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 384 s32 ret_val = E1000_SUCCESS; 385 u8 spi_stat_reg; 386 387 DEBUGFUNC("e1000_ready_nvm_eeprom"); 388 389 if (nvm->type == e1000_nvm_eeprom_microwire) { 390 /* Clear SK and DI */ 391 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 392 E1000_WRITE_REG(hw, E1000_EECD, eecd); 393 /* Set CS */ 394 eecd |= E1000_EECD_CS; 395 E1000_WRITE_REG(hw, E1000_EECD, eecd); 396 } else if (nvm->type == e1000_nvm_eeprom_spi) { 397 u16 timeout = NVM_MAX_RETRY_SPI; 398 399 /* Clear SK and CS */ 400 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 401 E1000_WRITE_REG(hw, E1000_EECD, eecd); 402 E1000_WRITE_FLUSH(hw); 403 usec_delay(1); 404 405 /* 406 * Read "Status Register" repeatedly until the LSB is cleared. 407 * The EEPROM will signal that the command has been completed 408 * by clearing bit 0 of the internal status register. If it's 409 * not cleared within 'timeout', then error out. 410 */ 411 while (timeout) { 412 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, 413 hw->nvm.opcode_bits); 414 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); 415 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) 416 break; 417 418 usec_delay(5); 419 e1000_standby_nvm(hw); 420 timeout--; 421 } 422 423 if (!timeout) { 424 DEBUGOUT("SPI NVM Status error\n"); 425 ret_val = -E1000_ERR_NVM; 426 goto out; 427 } 428 } 429 430out: 431 return ret_val; 432} 433 434/** 435 * e1000_read_nvm_spi - Read EEPROM's using SPI 436 * @hw: pointer to the HW structure 437 * @offset: offset of word in the EEPROM to read 438 * @words: number of words to read 439 * @data: word read from the EEPROM 440 * 441 * Reads a 16 bit word from the EEPROM. 442 **/ 443s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 444{ 445 struct e1000_nvm_info *nvm = &hw->nvm; 446 u32 i = 0; 447 s32 ret_val; 448 u16 word_in; 449 u8 read_opcode = NVM_READ_OPCODE_SPI; 450 451 DEBUGFUNC("e1000_read_nvm_spi"); 452 453 /* 454 * A check for invalid values: offset too large, too many words, 455 * and not enough words. 456 */ 457 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 458 (words == 0)) { 459 DEBUGOUT("nvm parameter(s) out of bounds\n"); 460 ret_val = -E1000_ERR_NVM; 461 goto out; 462 } 463 464 ret_val = nvm->ops.acquire(hw); 465 if (ret_val) 466 goto out; 467 468 ret_val = e1000_ready_nvm_eeprom(hw); 469 if (ret_val) 470 goto release; 471 472 e1000_standby_nvm(hw); 473 474 if ((nvm->address_bits == 8) && (offset >= 128)) 475 read_opcode |= NVM_A8_OPCODE_SPI; 476 477 /* Send the READ command (opcode + addr) */ 478 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); 479 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits); 480 481 /* 482 * Read the data. SPI NVMs increment the address with each byte 483 * read and will roll over if reading beyond the end. This allows 484 * us to read the whole NVM from any offset 485 */ 486 for (i = 0; i < words; i++) { 487 word_in = e1000_shift_in_eec_bits(hw, 16); 488 data[i] = (word_in >> 8) | (word_in << 8); 489 } 490 491release: 492 nvm->ops.release(hw); 493 494out: 495 return ret_val; 496} 497 498/** 499 * e1000_read_nvm_microwire - Reads EEPROM's using microwire 500 * @hw: pointer to the HW structure 501 * @offset: offset of word in the EEPROM to read 502 * @words: number of words to read 503 * @data: word read from the EEPROM 504 * 505 * Reads a 16 bit word from the EEPROM. 506 **/ 507s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, 508 u16 *data) 509{ 510 struct e1000_nvm_info *nvm = &hw->nvm; 511 u32 i = 0; 512 s32 ret_val; 513 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE; 514 515 DEBUGFUNC("e1000_read_nvm_microwire"); 516 517 /* 518 * A check for invalid values: offset too large, too many words, 519 * and not enough words. 520 */ 521 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 522 (words == 0)) { 523 DEBUGOUT("nvm parameter(s) out of bounds\n"); 524 ret_val = -E1000_ERR_NVM; 525 goto out; 526 } 527 528 ret_val = nvm->ops.acquire(hw); 529 if (ret_val) 530 goto out; 531 532 ret_val = e1000_ready_nvm_eeprom(hw); 533 if (ret_val) 534 goto release; 535 536 for (i = 0; i < words; i++) { 537 /* Send the READ command (opcode + addr) */ 538 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); 539 e1000_shift_out_eec_bits(hw, (u16)(offset + i), 540 nvm->address_bits); 541 542 /* 543 * Read the data. For microwire, each word requires the 544 * overhead of setup and tear-down. 545 */ 546 data[i] = e1000_shift_in_eec_bits(hw, 16); 547 e1000_standby_nvm(hw); 548 } 549 550release: 551 nvm->ops.release(hw); 552 553out: 554 return ret_val; 555} 556 557/** 558 * e1000_read_nvm_eerd - Reads EEPROM using EERD register 559 * @hw: pointer to the HW structure 560 * @offset: offset of word in the EEPROM to read 561 * @words: number of words to read 562 * @data: word read from the EEPROM 563 * 564 * Reads a 16 bit word from the EEPROM using the EERD register. 565 **/ 566s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 567{ 568 struct e1000_nvm_info *nvm = &hw->nvm; 569 u32 i, eerd = 0; 570 s32 ret_val = E1000_SUCCESS; 571 572 DEBUGFUNC("e1000_read_nvm_eerd"); 573 574 /* 575 * A check for invalid values: offset too large, too many words, 576 * too many words for the offset, and not enough words. 577 */ 578 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 579 (words == 0)) { 580 DEBUGOUT("nvm parameter(s) out of bounds\n"); 581 ret_val = -E1000_ERR_NVM; 582 goto out; 583 } 584 585 for (i = 0; i < words; i++) { 586 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + 587 E1000_NVM_RW_REG_START; 588 589 E1000_WRITE_REG(hw, E1000_EERD, eerd); 590 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); 591 if (ret_val) 592 break; 593 594 data[i] = (E1000_READ_REG(hw, E1000_EERD) >> 595 E1000_NVM_RW_REG_DATA); 596 } 597 598out: 599 return ret_val; 600} 601 602/** 603 * e1000_write_nvm_spi - Write to EEPROM using SPI 604 * @hw: pointer to the HW structure 605 * @offset: offset within the EEPROM to be written to 606 * @words: number of words to write 607 * @data: 16 bit word(s) to be written to the EEPROM 608 * 609 * Writes data to EEPROM at offset using SPI interface. 610 * 611 * If e1000_update_nvm_checksum is not called after this function , the 612 * EEPROM will most likely contain an invalid checksum. 613 **/ 614s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 615{ 616 struct e1000_nvm_info *nvm = &hw->nvm; 617 s32 ret_val; 618 u16 widx = 0; 619 620 DEBUGFUNC("e1000_write_nvm_spi"); 621 622 /* 623 * A check for invalid values: offset too large, too many words, 624 * and not enough words. 625 */ 626 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 627 (words == 0)) { 628 DEBUGOUT("nvm parameter(s) out of bounds\n"); 629 ret_val = -E1000_ERR_NVM; 630 goto out; 631 } 632 633 ret_val = nvm->ops.acquire(hw); 634 if (ret_val) 635 goto out; 636 637 while (widx < words) { 638 u8 write_opcode = NVM_WRITE_OPCODE_SPI; 639 640 ret_val = e1000_ready_nvm_eeprom(hw); 641 if (ret_val) 642 goto release; 643 644 e1000_standby_nvm(hw); 645 646 /* Send the WRITE ENABLE command (8 bit opcode) */ 647 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, 648 nvm->opcode_bits); 649 650 e1000_standby_nvm(hw); 651 652 /* 653 * Some SPI eeproms use the 8th address bit embedded in the 654 * opcode 655 */ 656 if ((nvm->address_bits == 8) && (offset >= 128)) 657 write_opcode |= NVM_A8_OPCODE_SPI; 658 659 /* Send the Write command (8-bit opcode + addr) */ 660 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); 661 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), 662 nvm->address_bits); 663 664 /* Loop to allow for up to whole page write of eeprom */ 665 while (widx < words) { 666 u16 word_out = data[widx]; 667 word_out = (word_out >> 8) | (word_out << 8); 668 e1000_shift_out_eec_bits(hw, word_out, 16); 669 widx++; 670 671 if ((((offset + widx) * 2) % nvm->page_size) == 0) { 672 e1000_standby_nvm(hw); 673 break; 674 } 675 } 676 } 677 678 msec_delay(10); 679release: 680 nvm->ops.release(hw); 681 682out: 683 return ret_val; 684} 685 686/** 687 * e1000_write_nvm_microwire - Writes EEPROM using microwire 688 * @hw: pointer to the HW structure 689 * @offset: offset within the EEPROM to be written to 690 * @words: number of words to write 691 * @data: 16 bit word(s) to be written to the EEPROM 692 * 693 * Writes data to EEPROM at offset using microwire interface. 694 * 695 * If e1000_update_nvm_checksum is not called after this function , the 696 * EEPROM will most likely contain an invalid checksum. 697 **/ 698s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, 699 u16 *data) 700{ 701 struct e1000_nvm_info *nvm = &hw->nvm; 702 s32 ret_val; 703 u32 eecd; 704 u16 words_written = 0; 705 u16 widx = 0; 706 707 DEBUGFUNC("e1000_write_nvm_microwire"); 708 709 /* 710 * A check for invalid values: offset too large, too many words, 711 * and not enough words. 712 */ 713 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 714 (words == 0)) { 715 DEBUGOUT("nvm parameter(s) out of bounds\n"); 716 ret_val = -E1000_ERR_NVM; 717 goto out; 718 } 719 720 ret_val = nvm->ops.acquire(hw); 721 if (ret_val) 722 goto out; 723 724 ret_val = e1000_ready_nvm_eeprom(hw); 725 if (ret_val) 726 goto release; 727 728 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE, 729 (u16)(nvm->opcode_bits + 2)); 730 731 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); 732 733 e1000_standby_nvm(hw); 734 735 while (words_written < words) { 736 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE, 737 nvm->opcode_bits); 738 739 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written), 740 nvm->address_bits); 741 742 e1000_shift_out_eec_bits(hw, data[words_written], 16); 743 744 e1000_standby_nvm(hw); 745 746 for (widx = 0; widx < 200; widx++) { 747 eecd = E1000_READ_REG(hw, E1000_EECD); 748 if (eecd & E1000_EECD_DO) 749 break; 750 usec_delay(50); 751 } 752 753 if (widx == 200) { 754 DEBUGOUT("NVM Write did not complete\n"); 755 ret_val = -E1000_ERR_NVM; 756 goto release; 757 } 758 759 e1000_standby_nvm(hw); 760 761 words_written++; 762 } 763 764 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE, 765 (u16)(nvm->opcode_bits + 2)); 766 767 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); 768 769release: 770 nvm->ops.release(hw); 771 772out: 773 return ret_val; 774} 775 776/** 777 * e1000_read_pba_string_generic - Read device part number 778 * @hw: pointer to the HW structure 779 * @pba_num: pointer to device part number 780 * @pba_num_size: size of part number buffer 781 * 782 * Reads the product board assembly (PBA) number from the EEPROM and stores 783 * the value in pba_num. 784 **/ 785s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, 786 u32 pba_num_size) 787{ 788 s32 ret_val; 789 u16 nvm_data; 790 u16 pba_ptr; 791 u16 offset; 792 u16 length; 793 794 DEBUGFUNC("e1000_read_pba_string_generic"); 795 796 if (pba_num == NULL) { 797 DEBUGOUT("PBA string buffer was null\n"); 798 ret_val = E1000_ERR_INVALID_ARGUMENT; 799 goto out; 800 } 801 802 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 803 if (ret_val) { 804 DEBUGOUT("NVM Read Error\n"); 805 goto out; 806 } 807 808 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); 809 if (ret_val) { 810 DEBUGOUT("NVM Read Error\n"); 811 goto out; 812 } 813 814 /* 815 * if nvm_data is not ptr guard the PBA must be in legacy format which 816 * means pba_ptr is actually our second data word for the PBA number 817 * and we can decode it into an ascii string 818 */ 819 if (nvm_data != NVM_PBA_PTR_GUARD) { 820 DEBUGOUT("NVM PBA number is not stored as string\n"); 821 822 /* we will need 11 characters to store the PBA */ 823 if (pba_num_size < 11) { 824 DEBUGOUT("PBA string buffer too small\n"); 825 return E1000_ERR_NO_SPACE; 826 } 827 828 /* extract hex string from data and pba_ptr */ 829 pba_num[0] = (nvm_data >> 12) & 0xF; 830 pba_num[1] = (nvm_data >> 8) & 0xF; 831 pba_num[2] = (nvm_data >> 4) & 0xF; 832 pba_num[3] = nvm_data & 0xF; 833 pba_num[4] = (pba_ptr >> 12) & 0xF; 834 pba_num[5] = (pba_ptr >> 8) & 0xF; 835 pba_num[6] = '-'; 836 pba_num[7] = 0; 837 pba_num[8] = (pba_ptr >> 4) & 0xF; 838 pba_num[9] = pba_ptr & 0xF; 839 840 /* put a null character on the end of our string */ 841 pba_num[10] = '\0'; 842 843 /* switch all the data but the '-' to hex char */ 844 for (offset = 0; offset < 10; offset++) { 845 if (pba_num[offset] < 0xA) 846 pba_num[offset] += '0'; 847 else if (pba_num[offset] < 0x10) 848 pba_num[offset] += 'A' - 0xA; 849 } 850 851 goto out; 852 } 853 854 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length); 855 if (ret_val) { 856 DEBUGOUT("NVM Read Error\n"); 857 goto out; 858 } 859 860 if (length == 0xFFFF || length == 0) { 861 DEBUGOUT("NVM PBA number section invalid length\n"); 862 ret_val = E1000_ERR_NVM_PBA_SECTION; 863 goto out; 864 } 865 /* check if pba_num buffer is big enough */ 866 if (pba_num_size < (((u32)length * 2) - 1)) { 867 DEBUGOUT("PBA string buffer too small\n"); 868 ret_val = E1000_ERR_NO_SPACE; 869 goto out; 870 } 871 872 /* trim pba length from start of string */ 873 pba_ptr++; 874 length--; 875 876 for (offset = 0; offset < length; offset++) { 877 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data); 878 if (ret_val) { 879 DEBUGOUT("NVM Read Error\n"); 880 goto out; 881 } 882 pba_num[offset * 2] = (u8)(nvm_data >> 8); 883 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); 884 } 885 pba_num[offset * 2] = '\0'; 886 887out: 888 return ret_val; 889} 890 891/** 892 * e1000_read_pba_length_generic - Read device part number length 893 * @hw: pointer to the HW structure 894 * @pba_num_size: size of part number buffer 895 * 896 * Reads the product board assembly (PBA) number length from the EEPROM and 897 * stores the value in pba_num_size. 898 **/ 899s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size) 900{ 901 s32 ret_val; 902 u16 nvm_data; 903 u16 pba_ptr; 904 u16 length; 905 906 DEBUGFUNC("e1000_read_pba_length_generic"); 907 908 if (pba_num_size == NULL) { 909 DEBUGOUT("PBA buffer size was null\n"); 910 ret_val = E1000_ERR_INVALID_ARGUMENT; 911 goto out; 912 } 913 914 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 915 if (ret_val) { 916 DEBUGOUT("NVM Read Error\n"); 917 goto out; 918 } 919 920 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); 921 if (ret_val) { 922 DEBUGOUT("NVM Read Error\n"); 923 goto out; 924 } 925 926 /* if data is not ptr guard the PBA must be in legacy format */ 927 if (nvm_data != NVM_PBA_PTR_GUARD) { 928 *pba_num_size = 11; 929 goto out; 930 } 931 932 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length); 933 if (ret_val) { 934 DEBUGOUT("NVM Read Error\n"); 935 goto out; 936 } 937 938 if (length == 0xFFFF || length == 0) { 939 DEBUGOUT("NVM PBA number section invalid length\n"); 940 ret_val = E1000_ERR_NVM_PBA_SECTION; 941 goto out; 942 } 943 944 /* 945 * Convert from length in u16 values to u8 chars, add 1 for NULL, 946 * and subtract 2 because length field is included in length. 947 */ 948 *pba_num_size = ((u32)length * 2) - 1; 949 950out: 951 return ret_val; 952} 953 954/** 955 * e1000_read_mac_addr_generic - Read device MAC address 956 * @hw: pointer to the HW structure 957 * 958 * Reads the device MAC address from the EEPROM and stores the value. 959 * Since devices with two ports use the same EEPROM, we increment the 960 * last bit in the MAC address for the second port. 961 **/ 962s32 e1000_read_mac_addr_generic(struct e1000_hw *hw) 963{ 964 u32 rar_high; 965 u32 rar_low; 966 u16 i; 967 968 rar_high = E1000_READ_REG(hw, E1000_RAH(0)); 969 rar_low = E1000_READ_REG(hw, E1000_RAL(0)); 970 971 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++) 972 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8)); 973 974 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++) 975 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8)); 976 977 for (i = 0; i < ETH_ADDR_LEN; i++) 978 hw->mac.addr[i] = hw->mac.perm_addr[i]; 979 980 return E1000_SUCCESS; 981} 982 983/** 984 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum 985 * @hw: pointer to the HW structure 986 * 987 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 988 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 989 **/ 990s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) 991{ 992 s32 ret_val = E1000_SUCCESS; 993 u16 checksum = 0; 994 u16 i, nvm_data; 995 996 DEBUGFUNC("e1000_validate_nvm_checksum_generic"); 997 998 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { 999 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 1000 if (ret_val) { 1001 DEBUGOUT("NVM Read Error\n"); 1002 goto out; 1003 } 1004 checksum += nvm_data; 1005 } 1006 1007 if (checksum != (u16) NVM_SUM) { 1008 DEBUGOUT("NVM Checksum Invalid\n"); 1009 ret_val = -E1000_ERR_NVM; 1010 goto out; 1011 } 1012 1013out: 1014 return ret_val; 1015} 1016 1017/** 1018 * e1000_update_nvm_checksum_generic - Update EEPROM checksum 1019 * @hw: pointer to the HW structure 1020 * 1021 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 1022 * up to the checksum. Then calculates the EEPROM checksum and writes the 1023 * value to the EEPROM. 1024 **/ 1025s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw) 1026{ 1027 s32 ret_val; 1028 u16 checksum = 0; 1029 u16 i, nvm_data; 1030 1031 DEBUGFUNC("e1000_update_nvm_checksum"); 1032 1033 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 1034 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 1035 if (ret_val) { 1036 DEBUGOUT("NVM Read Error while updating checksum.\n"); 1037 goto out; 1038 } 1039 checksum += nvm_data; 1040 } 1041 checksum = (u16) NVM_SUM - checksum; 1042 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum); 1043 if (ret_val) 1044 DEBUGOUT("NVM Write Error while updating checksum.\n"); 1045 1046out: 1047 return ret_val; 1048} 1049 1050/** 1051 * e1000_reload_nvm_generic - Reloads EEPROM 1052 * @hw: pointer to the HW structure 1053 * 1054 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the 1055 * extended control register. 1056 **/ 1057static void e1000_reload_nvm_generic(struct e1000_hw *hw) 1058{ 1059 u32 ctrl_ext; 1060 1061 DEBUGFUNC("e1000_reload_nvm_generic"); 1062 1063 usec_delay(10); 1064 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1065 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1066 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1067 E1000_WRITE_FLUSH(hw); 1068} 1069 1070