1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD$"); 32 33/* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37#ifdef HAVE_KERNEL_OPTION_HEADERS 38#include "opt_device_polling.h" 39#endif 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/endian.h> 45#include <sys/kernel.h> 46#include <sys/mbuf.h> 47#include <sys/lock.h> 48#include <sys/module.h> 49#include <sys/mutex.h> 50#include <sys/rman.h> 51#include <sys/socket.h> 52#include <sys/sockio.h> 53#include <sys/sysctl.h> 54 55#include <net/bpf.h> 56#include <net/ethernet.h> 57#include <net/if.h> 58#include <net/if_arp.h> 59#include <net/if_dl.h> 60#include <net/if_media.h> 61#include <net/if_types.h> 62#include <net/if_vlan_var.h> 63 64#include <netinet/in.h> 65#include <netinet/in_systm.h> 66#include <netinet/ip.h> 67#include <netinet/tcp.h> 68#include <netinet/udp.h> 69 70#include <machine/bus.h> 71#include <machine/in_cksum.h> 72#include <machine/resource.h> 73 74#include <dev/pci/pcivar.h> 75#include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 76 77#include <dev/mii/mii.h> 78#include <dev/mii/miivar.h> 79 80#include <dev/fxp/if_fxpreg.h> 81#include <dev/fxp/if_fxpvar.h> 82#include <dev/fxp/rcvbundl.h> 83 84MODULE_DEPEND(fxp, pci, 1, 1, 1); 85MODULE_DEPEND(fxp, ether, 1, 1, 1); 86MODULE_DEPEND(fxp, miibus, 1, 1, 1); 87#include "miibus_if.h" 88 89/* 90 * NOTE! On !x86 we typically have an alignment constraint. The 91 * card DMAs the packet immediately following the RFA. However, 92 * the first thing in the packet is a 14-byte Ethernet header. 93 * This means that the packet is misaligned. To compensate, 94 * we actually offset the RFA 2 bytes into the cluster. This 95 * alignes the packet after the Ethernet header at a 32-bit 96 * boundary. HOWEVER! This means that the RFA is misaligned! 97 */ 98#define RFA_ALIGNMENT_FUDGE 2 99 100/* 101 * Set initial transmit threshold at 64 (512 bytes). This is 102 * increased by 64 (512 bytes) at a time, to maximum of 192 103 * (1536 bytes), if an underrun occurs. 104 */ 105static int tx_threshold = 64; 106 107/* 108 * The configuration byte map has several undefined fields which 109 * must be one or must be zero. Set up a template for these bits. 110 * The actual configuration is performed in fxp_init_body. 111 * 112 * See struct fxp_cb_config for the bit definitions. 113 */ 114static const u_char const fxp_cb_config_template[] = { 115 0x0, 0x0, /* cb_status */ 116 0x0, 0x0, /* cb_command */ 117 0x0, 0x0, 0x0, 0x0, /* link_addr */ 118 0x0, /* 0 */ 119 0x0, /* 1 */ 120 0x0, /* 2 */ 121 0x0, /* 3 */ 122 0x0, /* 4 */ 123 0x0, /* 5 */ 124 0x32, /* 6 */ 125 0x0, /* 7 */ 126 0x0, /* 8 */ 127 0x0, /* 9 */ 128 0x6, /* 10 */ 129 0x0, /* 11 */ 130 0x0, /* 12 */ 131 0x0, /* 13 */ 132 0xf2, /* 14 */ 133 0x48, /* 15 */ 134 0x0, /* 16 */ 135 0x40, /* 17 */ 136 0xf0, /* 18 */ 137 0x0, /* 19 */ 138 0x3f, /* 20 */ 139 0x5, /* 21 */ 140 0x0, /* 22 */ 141 0x0, /* 23 */ 142 0x0, /* 24 */ 143 0x0, /* 25 */ 144 0x0, /* 26 */ 145 0x0, /* 27 */ 146 0x0, /* 28 */ 147 0x0, /* 29 */ 148 0x0, /* 30 */ 149 0x0 /* 31 */ 150}; 151 152/* 153 * Claim various Intel PCI device identifiers for this driver. The 154 * sub-vendor and sub-device field are extensively used to identify 155 * particular variants, but we don't currently differentiate between 156 * them. 157 */ 158static const struct fxp_ident const fxp_ident_table[] = { 159 { 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" }, 160 { 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" }, 161 { 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 162 { 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 163 { 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 164 { 0x1034, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 165 { 0x1035, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 166 { 0x1036, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 167 { 0x1037, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 168 { 0x1038, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 169 { 0x1039, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 170 { 0x103A, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 171 { 0x103B, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 172 { 0x103C, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 173 { 0x103D, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 174 { 0x103E, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 175 { 0x1050, -1, 5, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 176 { 0x1051, -1, 5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 177 { 0x1059, -1, 0, "Intel 82551QM Pro/100 M Mobile Connection" }, 178 { 0x1064, -1, 6, "Intel 82562EZ (ICH6)" }, 179 { 0x1065, -1, 6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, 180 { 0x1068, -1, 6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 181 { 0x1069, -1, 6, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 182 { 0x1091, -1, 7, "Intel 82562GX Pro/100 Ethernet" }, 183 { 0x1092, -1, 7, "Intel Pro/100 VE Network Connection" }, 184 { 0x1093, -1, 7, "Intel Pro/100 VM Network Connection" }, 185 { 0x1094, -1, 7, "Intel Pro/100 946GZ (ICH7) Network Connection" }, 186 { 0x1209, -1, 0, "Intel 82559ER Embedded 10/100 Ethernet" }, 187 { 0x1229, 0x01, 0, "Intel 82557 Pro/100 Ethernet" }, 188 { 0x1229, 0x02, 0, "Intel 82557 Pro/100 Ethernet" }, 189 { 0x1229, 0x03, 0, "Intel 82557 Pro/100 Ethernet" }, 190 { 0x1229, 0x04, 0, "Intel 82558 Pro/100 Ethernet" }, 191 { 0x1229, 0x05, 0, "Intel 82558 Pro/100 Ethernet" }, 192 { 0x1229, 0x06, 0, "Intel 82559 Pro/100 Ethernet" }, 193 { 0x1229, 0x07, 0, "Intel 82559 Pro/100 Ethernet" }, 194 { 0x1229, 0x08, 0, "Intel 82559 Pro/100 Ethernet" }, 195 { 0x1229, 0x09, 0, "Intel 82559ER Pro/100 Ethernet" }, 196 { 0x1229, 0x0c, 0, "Intel 82550 Pro/100 Ethernet" }, 197 { 0x1229, 0x0d, 0, "Intel 82550C Pro/100 Ethernet" }, 198 { 0x1229, 0x0e, 0, "Intel 82550 Pro/100 Ethernet" }, 199 { 0x1229, 0x0f, 0, "Intel 82551 Pro/100 Ethernet" }, 200 { 0x1229, 0x10, 0, "Intel 82551 Pro/100 Ethernet" }, 201 { 0x1229, -1, 0, "Intel 82557/8/9 Pro/100 Ethernet" }, 202 { 0x2449, -1, 2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 203 { 0x27dc, -1, 7, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 204 { 0, -1, 0, NULL }, 205}; 206 207#ifdef FXP_IP_CSUM_WAR 208#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 209#else 210#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 211#endif 212 213static int fxp_probe(device_t dev); 214static int fxp_attach(device_t dev); 215static int fxp_detach(device_t dev); 216static int fxp_shutdown(device_t dev); 217static int fxp_suspend(device_t dev); 218static int fxp_resume(device_t dev); 219 220static const struct fxp_ident *fxp_find_ident(device_t dev); 221static void fxp_intr(void *xsc); 222static void fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, 223 struct mbuf *m, uint16_t status, int pos); 224static int fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 225 uint8_t statack, int count); 226static void fxp_init(void *xsc); 227static void fxp_init_body(struct fxp_softc *sc, int); 228static void fxp_tick(void *xsc); 229static void fxp_start(struct ifnet *ifp); 230static void fxp_start_body(struct ifnet *ifp); 231static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head); 232static void fxp_txeof(struct fxp_softc *sc); 233static void fxp_stop(struct fxp_softc *sc); 234static void fxp_release(struct fxp_softc *sc); 235static int fxp_ioctl(struct ifnet *ifp, u_long command, 236 caddr_t data); 237static void fxp_watchdog(struct fxp_softc *sc); 238static void fxp_add_rfabuf(struct fxp_softc *sc, 239 struct fxp_rx *rxp); 240static void fxp_discard_rfabuf(struct fxp_softc *sc, 241 struct fxp_rx *rxp); 242static int fxp_new_rfabuf(struct fxp_softc *sc, 243 struct fxp_rx *rxp); 244static int fxp_mc_addrs(struct fxp_softc *sc); 245static void fxp_mc_setup(struct fxp_softc *sc); 246static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 247 int autosize); 248static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 249 uint16_t data); 250static void fxp_autosize_eeprom(struct fxp_softc *sc); 251static void fxp_load_eeprom(struct fxp_softc *sc); 252static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 253 int offset, int words); 254static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 255 int offset, int words); 256static int fxp_ifmedia_upd(struct ifnet *ifp); 257static void fxp_ifmedia_sts(struct ifnet *ifp, 258 struct ifmediareq *ifmr); 259static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 260static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 261 struct ifmediareq *ifmr); 262static int fxp_miibus_readreg(device_t dev, int phy, int reg); 263static int fxp_miibus_writereg(device_t dev, int phy, int reg, 264 int value); 265static void fxp_miibus_statchg(device_t dev); 266static void fxp_load_ucode(struct fxp_softc *sc); 267static void fxp_update_stats(struct fxp_softc *sc); 268static void fxp_sysctl_node(struct fxp_softc *sc); 269static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 270 int low, int high); 271static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 272static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 273static void fxp_scb_wait(struct fxp_softc *sc); 274static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 275static void fxp_dma_wait(struct fxp_softc *sc, 276 volatile uint16_t *status, bus_dma_tag_t dmat, 277 bus_dmamap_t map); 278 279static device_method_t fxp_methods[] = { 280 /* Device interface */ 281 DEVMETHOD(device_probe, fxp_probe), 282 DEVMETHOD(device_attach, fxp_attach), 283 DEVMETHOD(device_detach, fxp_detach), 284 DEVMETHOD(device_shutdown, fxp_shutdown), 285 DEVMETHOD(device_suspend, fxp_suspend), 286 DEVMETHOD(device_resume, fxp_resume), 287 288 /* MII interface */ 289 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 290 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 291 DEVMETHOD(miibus_statchg, fxp_miibus_statchg), 292 293 DEVMETHOD_END 294}; 295 296static driver_t fxp_driver = { 297 "fxp", 298 fxp_methods, 299 sizeof(struct fxp_softc), 300}; 301 302static devclass_t fxp_devclass; 303 304DRIVER_MODULE_ORDERED(fxp, pci, fxp_driver, fxp_devclass, NULL, NULL, 305 SI_ORDER_ANY); 306DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, NULL, NULL); 307 308static struct resource_spec fxp_res_spec_mem[] = { 309 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE }, 310 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 311 { -1, 0 } 312}; 313 314static struct resource_spec fxp_res_spec_io[] = { 315 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE }, 316 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 317 { -1, 0 } 318}; 319 320/* 321 * Wait for the previous command to be accepted (but not necessarily 322 * completed). 323 */ 324static void 325fxp_scb_wait(struct fxp_softc *sc) 326{ 327 union { 328 uint16_t w; 329 uint8_t b[2]; 330 } flowctl; 331 int i = 10000; 332 333 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 334 DELAY(2); 335 if (i == 0) { 336 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH); 337 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS); 338 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 339 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 340 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 341 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); 342 } 343} 344 345static void 346fxp_scb_cmd(struct fxp_softc *sc, int cmd) 347{ 348 349 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 350 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 351 fxp_scb_wait(sc); 352 } 353 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 354} 355 356static void 357fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 358 bus_dma_tag_t dmat, bus_dmamap_t map) 359{ 360 int i; 361 362 for (i = 10000; i > 0; i--) { 363 DELAY(2); 364 bus_dmamap_sync(dmat, map, 365 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 366 if ((le16toh(*status) & FXP_CB_STATUS_C) != 0) 367 break; 368 } 369 if (i == 0) 370 device_printf(sc->dev, "DMA timeout\n"); 371} 372 373static const struct fxp_ident * 374fxp_find_ident(device_t dev) 375{ 376 uint16_t devid; 377 uint8_t revid; 378 const struct fxp_ident *ident; 379 380 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 381 devid = pci_get_device(dev); 382 revid = pci_get_revid(dev); 383 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 384 if (ident->devid == devid && 385 (ident->revid == revid || ident->revid == -1)) { 386 return (ident); 387 } 388 } 389 } 390 return (NULL); 391} 392 393/* 394 * Return identification string if this device is ours. 395 */ 396static int 397fxp_probe(device_t dev) 398{ 399 const struct fxp_ident *ident; 400 401 ident = fxp_find_ident(dev); 402 if (ident != NULL) { 403 device_set_desc(dev, ident->name); 404 return (BUS_PROBE_DEFAULT); 405 } 406 return (ENXIO); 407} 408 409static void 410fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 411{ 412 uint32_t *addr; 413 414 if (error) 415 return; 416 417 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 418 addr = arg; 419 *addr = segs->ds_addr; 420} 421 422static int 423fxp_attach(device_t dev) 424{ 425 struct fxp_softc *sc; 426 struct fxp_cb_tx *tcbp; 427 struct fxp_tx *txp; 428 struct fxp_rx *rxp; 429 struct ifnet *ifp; 430 uint32_t val; 431 uint16_t data; 432 u_char eaddr[ETHER_ADDR_LEN]; 433 int error, flags, i, pmc, prefer_iomap; 434 435 error = 0; 436 sc = device_get_softc(dev); 437 sc->dev = dev; 438 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 439 MTX_DEF); 440 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0); 441 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 442 fxp_serial_ifmedia_sts); 443 444 ifp = sc->ifp = if_alloc(IFT_ETHER); 445 if (ifp == NULL) { 446 device_printf(dev, "can not if_alloc()\n"); 447 error = ENOSPC; 448 goto fail; 449 } 450 451 /* 452 * Enable bus mastering. 453 */ 454 pci_enable_busmaster(dev); 455 val = pci_read_config(dev, PCIR_COMMAND, 2); 456 457 /* 458 * Figure out which we should try first - memory mapping or i/o mapping? 459 * We default to memory mapping. Then we accept an override from the 460 * command line. Then we check to see which one is enabled. 461 */ 462 prefer_iomap = 0; 463 resource_int_value(device_get_name(dev), device_get_unit(dev), 464 "prefer_iomap", &prefer_iomap); 465 if (prefer_iomap) 466 sc->fxp_spec = fxp_res_spec_io; 467 else 468 sc->fxp_spec = fxp_res_spec_mem; 469 470 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 471 if (error) { 472 if (sc->fxp_spec == fxp_res_spec_mem) 473 sc->fxp_spec = fxp_res_spec_io; 474 else 475 sc->fxp_spec = fxp_res_spec_mem; 476 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 477 } 478 if (error) { 479 device_printf(dev, "could not allocate resources\n"); 480 error = ENXIO; 481 goto fail; 482 } 483 484 if (bootverbose) { 485 device_printf(dev, "using %s space register mapping\n", 486 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O"); 487 } 488 489 /* 490 * Put CU/RU idle state and prepare full reset. 491 */ 492 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 493 DELAY(10); 494 /* Full reset and disable interrupts. */ 495 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 496 DELAY(10); 497 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 498 499 /* 500 * Find out how large of an SEEPROM we have. 501 */ 502 fxp_autosize_eeprom(sc); 503 fxp_load_eeprom(sc); 504 505 /* 506 * Find out the chip revision; lump all 82557 revs together. 507 */ 508 sc->ident = fxp_find_ident(dev); 509 if (sc->ident->ich > 0) { 510 /* Assume ICH controllers are 82559. */ 511 sc->revision = FXP_REV_82559_A0; 512 } else { 513 data = sc->eeprom[FXP_EEPROM_MAP_CNTR]; 514 if ((data >> 8) == 1) 515 sc->revision = FXP_REV_82557; 516 else 517 sc->revision = pci_get_revid(dev); 518 } 519 520 /* 521 * Check availability of WOL. 82559ER does not support WOL. 522 */ 523 if (sc->revision >= FXP_REV_82558_A4 && 524 sc->revision != FXP_REV_82559S_A) { 525 data = sc->eeprom[FXP_EEPROM_MAP_ID]; 526 if ((data & 0x20) != 0 && 527 pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) 528 sc->flags |= FXP_FLAG_WOLCAP; 529 } 530 531 if (sc->revision == FXP_REV_82550_C) { 532 /* 533 * 82550C with server extension requires microcode to 534 * receive fragmented UDP datagrams. However if the 535 * microcode is used for client-only featured 82550C 536 * it locks up controller. 537 */ 538 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT]; 539 if ((data & 0x0400) == 0) 540 sc->flags |= FXP_FLAG_NO_UCODE; 541 } 542 543 /* Receiver lock-up workaround detection. */ 544 if (sc->revision < FXP_REV_82558_A4) { 545 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT]; 546 if ((data & 0x03) != 0x03) { 547 sc->flags |= FXP_FLAG_RXBUG; 548 device_printf(dev, "Enabling Rx lock-up workaround\n"); 549 } 550 } 551 552 /* 553 * Determine whether we must use the 503 serial interface. 554 */ 555 data = sc->eeprom[FXP_EEPROM_MAP_PRI_PHY]; 556 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 557 && (data & FXP_PHY_SERIAL_ONLY)) 558 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 559 560 fxp_sysctl_node(sc); 561 /* 562 * Enable workarounds for certain chip revision deficiencies. 563 * 564 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 565 * some systems based a normal 82559 design, have a defect where 566 * the chip can cause a PCI protocol violation if it receives 567 * a CU_RESUME command when it is entering the IDLE state. The 568 * workaround is to disable Dynamic Standby Mode, so the chip never 569 * deasserts CLKRUN#, and always remains in an active state. 570 * 571 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 572 */ 573 if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) || 574 (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) { 575 data = sc->eeprom[FXP_EEPROM_MAP_ID]; 576 if (data & 0x02) { /* STB enable */ 577 uint16_t cksum; 578 int i; 579 580 device_printf(dev, 581 "Disabling dynamic standby mode in EEPROM\n"); 582 data &= ~0x02; 583 sc->eeprom[FXP_EEPROM_MAP_ID] = data; 584 fxp_write_eeprom(sc, &data, FXP_EEPROM_MAP_ID, 1); 585 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 586 cksum = 0; 587 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) 588 cksum += sc->eeprom[i]; 589 i = (1 << sc->eeprom_size) - 1; 590 cksum = 0xBABA - cksum; 591 fxp_write_eeprom(sc, &cksum, i, 1); 592 device_printf(dev, 593 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 594 i, sc->eeprom[i], cksum); 595 sc->eeprom[i] = cksum; 596 /* 597 * If the user elects to continue, try the software 598 * workaround, as it is better than nothing. 599 */ 600 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 601 } 602 } 603 604 /* 605 * If we are not a 82557 chip, we can enable extended features. 606 */ 607 if (sc->revision != FXP_REV_82557) { 608 /* 609 * If MWI is enabled in the PCI configuration, and there 610 * is a valid cacheline size (8 or 16 dwords), then tell 611 * the board to turn on MWI. 612 */ 613 if (val & PCIM_CMD_MWRICEN && 614 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 615 sc->flags |= FXP_FLAG_MWI_ENABLE; 616 617 /* turn on the extended TxCB feature */ 618 sc->flags |= FXP_FLAG_EXT_TXCB; 619 620 /* enable reception of long frames for VLAN */ 621 sc->flags |= FXP_FLAG_LONG_PKT_EN; 622 } else { 623 /* a hack to get long VLAN frames on a 82557 */ 624 sc->flags |= FXP_FLAG_SAVE_BAD; 625 } 626 627 /* For 82559 or later chips, Rx checksum offload is supported. */ 628 if (sc->revision >= FXP_REV_82559_A0) { 629 /* 82559ER does not support Rx checksum offloading. */ 630 if (sc->ident->devid != 0x1209) 631 sc->flags |= FXP_FLAG_82559_RXCSUM; 632 } 633 /* 634 * Enable use of extended RFDs and TCBs for 82550 635 * and later chips. Note: we need extended TXCB support 636 * too, but that's already enabled by the code above. 637 * Be careful to do this only on the right devices. 638 */ 639 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 640 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 641 || sc->revision == FXP_REV_82551_10) { 642 sc->rfa_size = sizeof (struct fxp_rfa); 643 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 644 sc->flags |= FXP_FLAG_EXT_RFA; 645 /* Use extended RFA instead of 82559 checksum mode. */ 646 sc->flags &= ~FXP_FLAG_82559_RXCSUM; 647 } else { 648 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 649 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 650 } 651 652 /* 653 * Allocate DMA tags and DMA safe memory. 654 */ 655 sc->maxtxseg = FXP_NTXSEG; 656 sc->maxsegsize = MCLBYTES; 657 if (sc->flags & FXP_FLAG_EXT_RFA) { 658 sc->maxtxseg--; 659 sc->maxsegsize = FXP_TSO_SEGSIZE; 660 } 661 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 662 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 663 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header), 664 sc->maxtxseg, sc->maxsegsize, 0, 665 busdma_lock_mutex, &Giant, &sc->fxp_txmtag); 666 if (error) { 667 device_printf(dev, "could not create TX DMA tag\n"); 668 goto fail; 669 } 670 671 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 672 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 673 MCLBYTES, 1, MCLBYTES, 0, 674 busdma_lock_mutex, &Giant, &sc->fxp_rxmtag); 675 if (error) { 676 device_printf(dev, "could not create RX DMA tag\n"); 677 goto fail; 678 } 679 680 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 681 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 682 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0, 683 busdma_lock_mutex, &Giant, &sc->fxp_stag); 684 if (error) { 685 device_printf(dev, "could not create stats DMA tag\n"); 686 goto fail; 687 } 688 689 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 690 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->fxp_smap); 691 if (error) { 692 device_printf(dev, "could not allocate stats DMA memory\n"); 693 goto fail; 694 } 695 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 696 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 697 BUS_DMA_NOWAIT); 698 if (error) { 699 device_printf(dev, "could not load the stats DMA buffer\n"); 700 goto fail; 701 } 702 703 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 704 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 705 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0, 706 busdma_lock_mutex, &Giant, &sc->cbl_tag); 707 if (error) { 708 device_printf(dev, "could not create TxCB DMA tag\n"); 709 goto fail; 710 } 711 712 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 713 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->cbl_map); 714 if (error) { 715 device_printf(dev, "could not allocate TxCB DMA memory\n"); 716 goto fail; 717 } 718 719 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 720 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 721 &sc->fxp_desc.cbl_addr, BUS_DMA_NOWAIT); 722 if (error) { 723 device_printf(dev, "could not load TxCB DMA buffer\n"); 724 goto fail; 725 } 726 727 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 728 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 729 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0, 730 busdma_lock_mutex, &Giant, &sc->mcs_tag); 731 if (error) { 732 device_printf(dev, 733 "could not create multicast setup DMA tag\n"); 734 goto fail; 735 } 736 737 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 738 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->mcs_map); 739 if (error) { 740 device_printf(dev, 741 "could not allocate multicast setup DMA memory\n"); 742 goto fail; 743 } 744 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 745 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 746 BUS_DMA_NOWAIT); 747 if (error) { 748 device_printf(dev, 749 "can't load the multicast setup DMA buffer\n"); 750 goto fail; 751 } 752 753 /* 754 * Pre-allocate the TX DMA maps and setup the pointers to 755 * the TX command blocks. 756 */ 757 txp = sc->fxp_desc.tx_list; 758 tcbp = sc->fxp_desc.cbl_list; 759 for (i = 0; i < FXP_NTXCB; i++) { 760 txp[i].tx_cb = tcbp + i; 761 error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map); 762 if (error) { 763 device_printf(dev, "can't create DMA map for TX\n"); 764 goto fail; 765 } 766 } 767 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map); 768 if (error) { 769 device_printf(dev, "can't create spare DMA map\n"); 770 goto fail; 771 } 772 773 /* 774 * Pre-allocate our receive buffers. 775 */ 776 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 777 for (i = 0; i < FXP_NRFABUFS; i++) { 778 rxp = &sc->fxp_desc.rx_list[i]; 779 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map); 780 if (error) { 781 device_printf(dev, "can't create DMA map for RX\n"); 782 goto fail; 783 } 784 if (fxp_new_rfabuf(sc, rxp) != 0) { 785 error = ENOMEM; 786 goto fail; 787 } 788 fxp_add_rfabuf(sc, rxp); 789 } 790 791 /* 792 * Read MAC address. 793 */ 794 eaddr[0] = sc->eeprom[FXP_EEPROM_MAP_IA0] & 0xff; 795 eaddr[1] = sc->eeprom[FXP_EEPROM_MAP_IA0] >> 8; 796 eaddr[2] = sc->eeprom[FXP_EEPROM_MAP_IA1] & 0xff; 797 eaddr[3] = sc->eeprom[FXP_EEPROM_MAP_IA1] >> 8; 798 eaddr[4] = sc->eeprom[FXP_EEPROM_MAP_IA2] & 0xff; 799 eaddr[5] = sc->eeprom[FXP_EEPROM_MAP_IA2] >> 8; 800 if (bootverbose) { 801 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 802 pci_get_vendor(dev), pci_get_device(dev), 803 pci_get_subvendor(dev), pci_get_subdevice(dev), 804 pci_get_revid(dev)); 805 device_printf(dev, "Dynamic Standby mode is %s\n", 806 sc->eeprom[FXP_EEPROM_MAP_ID] & 0x02 ? "enabled" : 807 "disabled"); 808 } 809 810 /* 811 * If this is only a 10Mbps device, then there is no MII, and 812 * the PHY will use a serial interface instead. 813 * 814 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 815 * doesn't have a programming interface of any sort. The 816 * media is sensed automatically based on how the link partner 817 * is configured. This is, in essence, manual configuration. 818 */ 819 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 820 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 821 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 822 } else { 823 /* 824 * i82557 wedge when isolating all of their PHYs. 825 */ 826 flags = MIIF_NOISOLATE; 827 if (sc->revision >= FXP_REV_82558_A4) 828 flags |= MIIF_DOPAUSE; 829 error = mii_attach(dev, &sc->miibus, ifp, fxp_ifmedia_upd, 830 fxp_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, 831 MII_OFFSET_ANY, flags); 832 if (error != 0) { 833 device_printf(dev, "attaching PHYs failed\n"); 834 goto fail; 835 } 836 } 837 838 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 839 ifp->if_init = fxp_init; 840 ifp->if_softc = sc; 841 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 842 ifp->if_ioctl = fxp_ioctl; 843 ifp->if_start = fxp_start; 844 845 ifp->if_capabilities = ifp->if_capenable = 0; 846 847 /* Enable checksum offload/TSO for 82550 or better chips */ 848 if (sc->flags & FXP_FLAG_EXT_RFA) { 849 ifp->if_hwassist = FXP_CSUM_FEATURES | CSUM_TSO; 850 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4; 851 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_TSO4; 852 } 853 854 if (sc->flags & FXP_FLAG_82559_RXCSUM) { 855 ifp->if_capabilities |= IFCAP_RXCSUM; 856 ifp->if_capenable |= IFCAP_RXCSUM; 857 } 858 859 if (sc->flags & FXP_FLAG_WOLCAP) { 860 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 861 ifp->if_capenable |= IFCAP_WOL_MAGIC; 862 } 863 864#ifdef DEVICE_POLLING 865 /* Inform the world we support polling. */ 866 ifp->if_capabilities |= IFCAP_POLLING; 867#endif 868 869 /* 870 * Attach the interface. 871 */ 872 ether_ifattach(ifp, eaddr); 873 874 /* 875 * Tell the upper layer(s) we support long frames. 876 * Must appear after the call to ether_ifattach() because 877 * ether_ifattach() sets ifi_hdrlen to the default value. 878 */ 879 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 880 ifp->if_capabilities |= IFCAP_VLAN_MTU; 881 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 882 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) { 883 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | 884 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 885 ifp->if_capenable |= IFCAP_VLAN_HWTAGGING | 886 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 887 } 888 889 /* 890 * Let the system queue as many packets as we have available 891 * TX descriptors. 892 */ 893 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 894 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 895 IFQ_SET_READY(&ifp->if_snd); 896 897 /* 898 * Hook our interrupt after all initialization is complete. 899 */ 900 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE, 901 NULL, fxp_intr, sc, &sc->ih); 902 if (error) { 903 device_printf(dev, "could not setup irq\n"); 904 ether_ifdetach(sc->ifp); 905 goto fail; 906 } 907 908 /* 909 * Configure hardware to reject magic frames otherwise 910 * system will hang on recipt of magic frames. 911 */ 912 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) { 913 FXP_LOCK(sc); 914 /* Clear wakeup events. */ 915 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR)); 916 fxp_init_body(sc, 0); 917 fxp_stop(sc); 918 FXP_UNLOCK(sc); 919 } 920 921fail: 922 if (error) 923 fxp_release(sc); 924 return (error); 925} 926 927/* 928 * Release all resources. The softc lock should not be held and the 929 * interrupt should already be torn down. 930 */ 931static void 932fxp_release(struct fxp_softc *sc) 933{ 934 struct fxp_rx *rxp; 935 struct fxp_tx *txp; 936 int i; 937 938 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 939 KASSERT(sc->ih == NULL, 940 ("fxp_release() called with intr handle still active")); 941 if (sc->miibus) 942 device_delete_child(sc->dev, sc->miibus); 943 bus_generic_detach(sc->dev); 944 ifmedia_removeall(&sc->sc_media); 945 if (sc->fxp_desc.cbl_list) { 946 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 947 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 948 sc->cbl_map); 949 } 950 if (sc->fxp_stats) { 951 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 952 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 953 } 954 if (sc->mcsp) { 955 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 956 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 957 } 958 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res); 959 if (sc->fxp_rxmtag) { 960 for (i = 0; i < FXP_NRFABUFS; i++) { 961 rxp = &sc->fxp_desc.rx_list[i]; 962 if (rxp->rx_mbuf != NULL) { 963 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 964 BUS_DMASYNC_POSTREAD); 965 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map); 966 m_freem(rxp->rx_mbuf); 967 } 968 bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map); 969 } 970 bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map); 971 bus_dma_tag_destroy(sc->fxp_rxmtag); 972 } 973 if (sc->fxp_txmtag) { 974 for (i = 0; i < FXP_NTXCB; i++) { 975 txp = &sc->fxp_desc.tx_list[i]; 976 if (txp->tx_mbuf != NULL) { 977 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, 978 BUS_DMASYNC_POSTWRITE); 979 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map); 980 m_freem(txp->tx_mbuf); 981 } 982 bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map); 983 } 984 bus_dma_tag_destroy(sc->fxp_txmtag); 985 } 986 if (sc->fxp_stag) 987 bus_dma_tag_destroy(sc->fxp_stag); 988 if (sc->cbl_tag) 989 bus_dma_tag_destroy(sc->cbl_tag); 990 if (sc->mcs_tag) 991 bus_dma_tag_destroy(sc->mcs_tag); 992 if (sc->ifp) 993 if_free(sc->ifp); 994 995 mtx_destroy(&sc->sc_mtx); 996} 997 998/* 999 * Detach interface. 1000 */ 1001static int 1002fxp_detach(device_t dev) 1003{ 1004 struct fxp_softc *sc = device_get_softc(dev); 1005 1006#ifdef DEVICE_POLLING 1007 if (sc->ifp->if_capenable & IFCAP_POLLING) 1008 ether_poll_deregister(sc->ifp); 1009#endif 1010 1011 FXP_LOCK(sc); 1012 /* 1013 * Stop DMA and drop transmit queue, but disable interrupts first. 1014 */ 1015 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1016 fxp_stop(sc); 1017 FXP_UNLOCK(sc); 1018 callout_drain(&sc->stat_ch); 1019 1020 /* 1021 * Close down routes etc. 1022 */ 1023 ether_ifdetach(sc->ifp); 1024 1025 /* 1026 * Unhook interrupt before dropping lock. This is to prevent 1027 * races with fxp_intr(). 1028 */ 1029 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih); 1030 sc->ih = NULL; 1031 1032 /* Release our allocated resources. */ 1033 fxp_release(sc); 1034 return (0); 1035} 1036 1037/* 1038 * Device shutdown routine. Called at system shutdown after sync. The 1039 * main purpose of this routine is to shut off receiver DMA so that 1040 * kernel memory doesn't get clobbered during warmboot. 1041 */ 1042static int 1043fxp_shutdown(device_t dev) 1044{ 1045 1046 /* 1047 * Make sure that DMA is disabled prior to reboot. Not doing 1048 * do could allow DMA to corrupt kernel memory during the 1049 * reboot before the driver initializes. 1050 */ 1051 return (fxp_suspend(dev)); 1052} 1053 1054/* 1055 * Device suspend routine. Stop the interface and save some PCI 1056 * settings in case the BIOS doesn't restore them properly on 1057 * resume. 1058 */ 1059static int 1060fxp_suspend(device_t dev) 1061{ 1062 struct fxp_softc *sc = device_get_softc(dev); 1063 struct ifnet *ifp; 1064 int pmc; 1065 uint16_t pmstat; 1066 1067 FXP_LOCK(sc); 1068 1069 ifp = sc->ifp; 1070 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1071 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1072 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1073 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { 1074 /* Request PME. */ 1075 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1076 sc->flags |= FXP_FLAG_WOL; 1077 /* Reconfigure hardware to accept magic frames. */ 1078 fxp_init_body(sc, 1); 1079 } 1080 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1081 } 1082 fxp_stop(sc); 1083 1084 sc->suspended = 1; 1085 1086 FXP_UNLOCK(sc); 1087 return (0); 1088} 1089 1090/* 1091 * Device resume routine. re-enable busmastering, and restart the interface if 1092 * appropriate. 1093 */ 1094static int 1095fxp_resume(device_t dev) 1096{ 1097 struct fxp_softc *sc = device_get_softc(dev); 1098 struct ifnet *ifp = sc->ifp; 1099 int pmc; 1100 uint16_t pmstat; 1101 1102 FXP_LOCK(sc); 1103 1104 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1105 sc->flags &= ~FXP_FLAG_WOL; 1106 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1107 /* Disable PME and clear PME status. */ 1108 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1109 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1110 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) 1111 CSR_WRITE_1(sc, FXP_CSR_PMDR, 1112 CSR_READ_1(sc, FXP_CSR_PMDR)); 1113 } 1114 1115 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1116 DELAY(10); 1117 1118 /* reinitialize interface if necessary */ 1119 if (ifp->if_flags & IFF_UP) 1120 fxp_init_body(sc, 1); 1121 1122 sc->suspended = 0; 1123 1124 FXP_UNLOCK(sc); 1125 return (0); 1126} 1127 1128static void 1129fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1130{ 1131 uint16_t reg; 1132 int x; 1133 1134 /* 1135 * Shift in data. 1136 */ 1137 for (x = 1 << (length - 1); x; x >>= 1) { 1138 if (data & x) 1139 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1140 else 1141 reg = FXP_EEPROM_EECS; 1142 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1143 DELAY(1); 1144 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1145 DELAY(1); 1146 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1147 DELAY(1); 1148 } 1149} 1150 1151/* 1152 * Read from the serial EEPROM. Basically, you manually shift in 1153 * the read opcode (one bit at a time) and then shift in the address, 1154 * and then you shift out the data (all of this one bit at a time). 1155 * The word size is 16 bits, so you have to provide the address for 1156 * every 16 bits of data. 1157 */ 1158static uint16_t 1159fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1160{ 1161 uint16_t reg, data; 1162 int x; 1163 1164 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1165 /* 1166 * Shift in read opcode. 1167 */ 1168 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1169 /* 1170 * Shift in address. 1171 */ 1172 data = 0; 1173 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1174 if (offset & x) 1175 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1176 else 1177 reg = FXP_EEPROM_EECS; 1178 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1179 DELAY(1); 1180 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1181 DELAY(1); 1182 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1183 DELAY(1); 1184 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1185 data++; 1186 if (autosize && reg == 0) { 1187 sc->eeprom_size = data; 1188 break; 1189 } 1190 } 1191 /* 1192 * Shift out data. 1193 */ 1194 data = 0; 1195 reg = FXP_EEPROM_EECS; 1196 for (x = 1 << 15; x; x >>= 1) { 1197 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1198 DELAY(1); 1199 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1200 data |= x; 1201 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1202 DELAY(1); 1203 } 1204 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1205 DELAY(1); 1206 1207 return (data); 1208} 1209 1210static void 1211fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1212{ 1213 int i; 1214 1215 /* 1216 * Erase/write enable. 1217 */ 1218 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1219 fxp_eeprom_shiftin(sc, 0x4, 3); 1220 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1221 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1222 DELAY(1); 1223 /* 1224 * Shift in write opcode, address, data. 1225 */ 1226 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1227 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1228 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1229 fxp_eeprom_shiftin(sc, data, 16); 1230 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1231 DELAY(1); 1232 /* 1233 * Wait for EEPROM to finish up. 1234 */ 1235 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1236 DELAY(1); 1237 for (i = 0; i < 1000; i++) { 1238 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1239 break; 1240 DELAY(50); 1241 } 1242 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1243 DELAY(1); 1244 /* 1245 * Erase/write disable. 1246 */ 1247 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1248 fxp_eeprom_shiftin(sc, 0x4, 3); 1249 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1250 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1251 DELAY(1); 1252} 1253 1254/* 1255 * From NetBSD: 1256 * 1257 * Figure out EEPROM size. 1258 * 1259 * 559's can have either 64-word or 256-word EEPROMs, the 558 1260 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1261 * talks about the existance of 16 to 256 word EEPROMs. 1262 * 1263 * The only known sizes are 64 and 256, where the 256 version is used 1264 * by CardBus cards to store CIS information. 1265 * 1266 * The address is shifted in msb-to-lsb, and after the last 1267 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1268 * after which follows the actual data. We try to detect this zero, by 1269 * probing the data-out bit in the EEPROM control register just after 1270 * having shifted in a bit. If the bit is zero, we assume we've 1271 * shifted enough address bits. The data-out should be tri-state, 1272 * before this, which should translate to a logical one. 1273 */ 1274static void 1275fxp_autosize_eeprom(struct fxp_softc *sc) 1276{ 1277 1278 /* guess maximum size of 256 words */ 1279 sc->eeprom_size = 8; 1280 1281 /* autosize */ 1282 (void) fxp_eeprom_getword(sc, 0, 1); 1283} 1284 1285static void 1286fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1287{ 1288 int i; 1289 1290 for (i = 0; i < words; i++) 1291 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1292} 1293 1294static void 1295fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1296{ 1297 int i; 1298 1299 for (i = 0; i < words; i++) 1300 fxp_eeprom_putword(sc, offset + i, data[i]); 1301} 1302 1303static void 1304fxp_load_eeprom(struct fxp_softc *sc) 1305{ 1306 int i; 1307 uint16_t cksum; 1308 1309 fxp_read_eeprom(sc, sc->eeprom, 0, 1 << sc->eeprom_size); 1310 cksum = 0; 1311 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) 1312 cksum += sc->eeprom[i]; 1313 cksum = 0xBABA - cksum; 1314 if (cksum != sc->eeprom[(1 << sc->eeprom_size) - 1]) 1315 device_printf(sc->dev, 1316 "EEPROM checksum mismatch! (0x%04x -> 0x%04x)\n", 1317 cksum, sc->eeprom[(1 << sc->eeprom_size) - 1]); 1318} 1319 1320/* 1321 * Grab the softc lock and call the real fxp_start_body() routine 1322 */ 1323static void 1324fxp_start(struct ifnet *ifp) 1325{ 1326 struct fxp_softc *sc = ifp->if_softc; 1327 1328 FXP_LOCK(sc); 1329 fxp_start_body(ifp); 1330 FXP_UNLOCK(sc); 1331} 1332 1333/* 1334 * Start packet transmission on the interface. 1335 * This routine must be called with the softc lock held, and is an 1336 * internal entry point only. 1337 */ 1338static void 1339fxp_start_body(struct ifnet *ifp) 1340{ 1341 struct fxp_softc *sc = ifp->if_softc; 1342 struct mbuf *mb_head; 1343 int txqueued; 1344 1345 FXP_LOCK_ASSERT(sc, MA_OWNED); 1346 1347 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1348 IFF_DRV_RUNNING) 1349 return; 1350 1351 if (sc->tx_queued > FXP_NTXCB_HIWAT) 1352 fxp_txeof(sc); 1353 /* 1354 * We're finished if there is nothing more to add to the list or if 1355 * we're all filled up with buffers to transmit. 1356 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1357 * a NOP command when needed. 1358 */ 1359 txqueued = 0; 1360 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1361 sc->tx_queued < FXP_NTXCB - 1) { 1362 1363 /* 1364 * Grab a packet to transmit. 1365 */ 1366 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1367 if (mb_head == NULL) 1368 break; 1369 1370 if (fxp_encap(sc, &mb_head)) { 1371 if (mb_head == NULL) 1372 break; 1373 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head); 1374 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1375 } 1376 txqueued++; 1377 /* 1378 * Pass packet to bpf if there is a listener. 1379 */ 1380 BPF_MTAP(ifp, mb_head); 1381 } 1382 1383 /* 1384 * We're finished. If we added to the list, issue a RESUME to get DMA 1385 * going again if suspended. 1386 */ 1387 if (txqueued > 0) { 1388 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1389 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1390 fxp_scb_wait(sc); 1391 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1392 /* 1393 * Set a 5 second timer just in case we don't hear 1394 * from the card again. 1395 */ 1396 sc->watchdog_timer = 5; 1397 } 1398} 1399 1400static int 1401fxp_encap(struct fxp_softc *sc, struct mbuf **m_head) 1402{ 1403 struct ifnet *ifp; 1404 struct mbuf *m; 1405 struct fxp_tx *txp; 1406 struct fxp_cb_tx *cbp; 1407 struct tcphdr *tcp; 1408 bus_dma_segment_t segs[FXP_NTXSEG]; 1409 int error, i, nseg, tcp_payload; 1410 1411 FXP_LOCK_ASSERT(sc, MA_OWNED); 1412 ifp = sc->ifp; 1413 1414 tcp_payload = 0; 1415 tcp = NULL; 1416 /* 1417 * Get pointer to next available tx desc. 1418 */ 1419 txp = sc->fxp_desc.tx_last->tx_next; 1420 1421 /* 1422 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1423 * Ethernet Controller Family Open Source Software 1424 * Developer Manual says: 1425 * Using software parsing is only allowed with legal 1426 * TCP/IP or UDP/IP packets. 1427 * ... 1428 * For all other datagrams, hardware parsing must 1429 * be used. 1430 * Software parsing appears to truncate ICMP and 1431 * fragmented UDP packets that contain one to three 1432 * bytes in the second (and final) mbuf of the packet. 1433 */ 1434 if (sc->flags & FXP_FLAG_EXT_RFA) 1435 txp->tx_cb->ipcb_ip_activation_high = 1436 FXP_IPCB_HARDWAREPARSING_ENABLE; 1437 1438 m = *m_head; 1439 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1440 /* 1441 * 82550/82551 requires ethernet/IP/TCP headers must be 1442 * contained in the first active transmit buffer. 1443 */ 1444 struct ether_header *eh; 1445 struct ip *ip; 1446 uint32_t ip_off, poff; 1447 1448 if (M_WRITABLE(*m_head) == 0) { 1449 /* Get a writable copy. */ 1450 m = m_dup(*m_head, M_DONTWAIT); 1451 m_freem(*m_head); 1452 if (m == NULL) { 1453 *m_head = NULL; 1454 return (ENOBUFS); 1455 } 1456 *m_head = m; 1457 } 1458 ip_off = sizeof(struct ether_header); 1459 m = m_pullup(*m_head, ip_off); 1460 if (m == NULL) { 1461 *m_head = NULL; 1462 return (ENOBUFS); 1463 } 1464 eh = mtod(m, struct ether_header *); 1465 /* Check the existence of VLAN tag. */ 1466 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1467 ip_off = sizeof(struct ether_vlan_header); 1468 m = m_pullup(m, ip_off); 1469 if (m == NULL) { 1470 *m_head = NULL; 1471 return (ENOBUFS); 1472 } 1473 } 1474 m = m_pullup(m, ip_off + sizeof(struct ip)); 1475 if (m == NULL) { 1476 *m_head = NULL; 1477 return (ENOBUFS); 1478 } 1479 ip = (struct ip *)(mtod(m, char *) + ip_off); 1480 poff = ip_off + (ip->ip_hl << 2); 1481 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1482 if (m == NULL) { 1483 *m_head = NULL; 1484 return (ENOBUFS); 1485 } 1486 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1487 m = m_pullup(m, poff + (tcp->th_off << 2)); 1488 if (m == NULL) { 1489 *m_head = NULL; 1490 return (ENOBUFS); 1491 } 1492 1493 /* 1494 * Since 82550/82551 doesn't modify IP length and pseudo 1495 * checksum in the first frame driver should compute it. 1496 */ 1497 ip = (struct ip *)(mtod(m, char *) + ip_off); 1498 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1499 ip->ip_sum = 0; 1500 ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) + 1501 (tcp->th_off << 2)); 1502 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, 1503 htons(IPPROTO_TCP + (tcp->th_off << 2) + 1504 m->m_pkthdr.tso_segsz)); 1505 /* Compute total TCP payload. */ 1506 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2); 1507 tcp_payload -= tcp->th_off << 2; 1508 *m_head = m; 1509 } else if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) { 1510 /* 1511 * Deal with TCP/IP checksum offload. Note that 1512 * in order for TCP checksum offload to work, 1513 * the pseudo header checksum must have already 1514 * been computed and stored in the checksum field 1515 * in the TCP header. The stack should have 1516 * already done this for us. 1517 */ 1518 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1519 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1520 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET; 1521 1522#ifdef FXP_IP_CSUM_WAR 1523 /* 1524 * XXX The 82550 chip appears to have trouble 1525 * dealing with IP header checksums in very small 1526 * datagrams, namely fragments from 1 to 3 bytes 1527 * in size. For example, say you want to transmit 1528 * a UDP packet of 1473 bytes. The packet will be 1529 * fragmented over two IP datagrams, the latter 1530 * containing only one byte of data. The 82550 will 1531 * botch the header checksum on the 1-byte fragment. 1532 * As long as the datagram contains 4 or more bytes 1533 * of data, you're ok. 1534 * 1535 * The following code attempts to work around this 1536 * problem: if the datagram is less than 38 bytes 1537 * in size (14 bytes ether header, 20 bytes IP header, 1538 * plus 4 bytes of data), we punt and compute the IP 1539 * header checksum by hand. This workaround doesn't 1540 * work very well, however, since it can be fooled 1541 * by things like VLAN tags and IP options that make 1542 * the header sizes/offsets vary. 1543 */ 1544 1545 if (m->m_pkthdr.csum_flags & CSUM_IP) { 1546 if (m->m_pkthdr.len < 38) { 1547 struct ip *ip; 1548 m->m_data += ETHER_HDR_LEN; 1549 ip = mtod(m, struct ip *); 1550 ip->ip_sum = in_cksum(m, ip->ip_hl << 2); 1551 m->m_data -= ETHER_HDR_LEN; 1552 m->m_pkthdr.csum_flags &= ~CSUM_IP; 1553 } else { 1554 txp->tx_cb->ipcb_ip_activation_high = 1555 FXP_IPCB_HARDWAREPARSING_ENABLE; 1556 txp->tx_cb->ipcb_ip_schedule |= 1557 FXP_IPCB_IP_CHECKSUM_ENABLE; 1558 } 1559 } 1560#endif 1561 } 1562 1563 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head, 1564 segs, &nseg, 0); 1565 if (error == EFBIG) { 1566 m = m_collapse(*m_head, M_DONTWAIT, sc->maxtxseg); 1567 if (m == NULL) { 1568 m_freem(*m_head); 1569 *m_head = NULL; 1570 return (ENOMEM); 1571 } 1572 *m_head = m; 1573 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, 1574 *m_head, segs, &nseg, 0); 1575 if (error != 0) { 1576 m_freem(*m_head); 1577 *m_head = NULL; 1578 return (ENOMEM); 1579 } 1580 } else if (error != 0) 1581 return (error); 1582 if (nseg == 0) { 1583 m_freem(*m_head); 1584 *m_head = NULL; 1585 return (EIO); 1586 } 1587 1588 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1589 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1590 1591 cbp = txp->tx_cb; 1592 for (i = 0; i < nseg; i++) { 1593 /* 1594 * If this is an 82550/82551, then we're using extended 1595 * TxCBs _and_ we're using checksum offload. This means 1596 * that the TxCB is really an IPCB. One major difference 1597 * between the two is that with plain extended TxCBs, 1598 * the bottom half of the TxCB contains two entries from 1599 * the TBD array, whereas IPCBs contain just one entry: 1600 * one entry (8 bytes) has been sacrificed for the TCP/IP 1601 * checksum offload control bits. So to make things work 1602 * right, we have to start filling in the TBD array 1603 * starting from a different place depending on whether 1604 * the chip is an 82550/82551 or not. 1605 */ 1606 if (sc->flags & FXP_FLAG_EXT_RFA) { 1607 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1608 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1609 } else { 1610 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1611 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1612 } 1613 } 1614 if (sc->flags & FXP_FLAG_EXT_RFA) { 1615 /* Configure dynamic TBD for 82550/82551. */ 1616 cbp->tbd_number = 0xFF; 1617 cbp->tbd[nseg].tb_size |= htole32(0x8000); 1618 } else 1619 cbp->tbd_number = nseg; 1620 /* Configure TSO. */ 1621 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1622 cbp->tbd[-1].tb_size = htole32(m->m_pkthdr.tso_segsz << 16); 1623 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16); 1624 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE | 1625 FXP_IPCB_IP_CHECKSUM_ENABLE | 1626 FXP_IPCB_TCP_PACKET | 1627 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1628 } 1629 /* Configure VLAN hardware tag insertion. */ 1630 if ((m->m_flags & M_VLANTAG) != 0) { 1631 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag); 1632 txp->tx_cb->ipcb_ip_activation_high |= 1633 FXP_IPCB_INSERTVLAN_ENABLE; 1634 } 1635 1636 txp->tx_mbuf = m; 1637 txp->tx_cb->cb_status = 0; 1638 txp->tx_cb->byte_count = 0; 1639 if (sc->tx_queued != FXP_CXINT_THRESH - 1) 1640 txp->tx_cb->cb_command = 1641 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1642 FXP_CB_COMMAND_S); 1643 else 1644 txp->tx_cb->cb_command = 1645 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1646 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1647 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) 1648 txp->tx_cb->tx_threshold = tx_threshold; 1649 1650 /* 1651 * Advance the end of list forward. 1652 */ 1653 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1654 sc->fxp_desc.tx_last = txp; 1655 1656 /* 1657 * Advance the beginning of the list forward if there are 1658 * no other packets queued (when nothing is queued, tx_first 1659 * sits on the last TxCB that was sent out). 1660 */ 1661 if (sc->tx_queued == 0) 1662 sc->fxp_desc.tx_first = txp; 1663 1664 sc->tx_queued++; 1665 1666 return (0); 1667} 1668 1669#ifdef DEVICE_POLLING 1670static poll_handler_t fxp_poll; 1671 1672static int 1673fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1674{ 1675 struct fxp_softc *sc = ifp->if_softc; 1676 uint8_t statack; 1677 int rx_npkts = 0; 1678 1679 FXP_LOCK(sc); 1680 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1681 FXP_UNLOCK(sc); 1682 return (rx_npkts); 1683 } 1684 1685 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1686 FXP_SCB_STATACK_FR; 1687 if (cmd == POLL_AND_CHECK_STATUS) { 1688 uint8_t tmp; 1689 1690 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1691 if (tmp == 0xff || tmp == 0) { 1692 FXP_UNLOCK(sc); 1693 return (rx_npkts); /* nothing to do */ 1694 } 1695 tmp &= ~statack; 1696 /* ack what we can */ 1697 if (tmp != 0) 1698 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1699 statack |= tmp; 1700 } 1701 rx_npkts = fxp_intr_body(sc, ifp, statack, count); 1702 FXP_UNLOCK(sc); 1703 return (rx_npkts); 1704} 1705#endif /* DEVICE_POLLING */ 1706 1707/* 1708 * Process interface interrupts. 1709 */ 1710static void 1711fxp_intr(void *xsc) 1712{ 1713 struct fxp_softc *sc = xsc; 1714 struct ifnet *ifp = sc->ifp; 1715 uint8_t statack; 1716 1717 FXP_LOCK(sc); 1718 if (sc->suspended) { 1719 FXP_UNLOCK(sc); 1720 return; 1721 } 1722 1723#ifdef DEVICE_POLLING 1724 if (ifp->if_capenable & IFCAP_POLLING) { 1725 FXP_UNLOCK(sc); 1726 return; 1727 } 1728#endif 1729 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1730 /* 1731 * It should not be possible to have all bits set; the 1732 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1733 * all bits are set, this may indicate that the card has 1734 * been physically ejected, so ignore it. 1735 */ 1736 if (statack == 0xff) { 1737 FXP_UNLOCK(sc); 1738 return; 1739 } 1740 1741 /* 1742 * First ACK all the interrupts in this pass. 1743 */ 1744 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1745 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1746 fxp_intr_body(sc, ifp, statack, -1); 1747 } 1748 FXP_UNLOCK(sc); 1749} 1750 1751static void 1752fxp_txeof(struct fxp_softc *sc) 1753{ 1754 struct ifnet *ifp; 1755 struct fxp_tx *txp; 1756 1757 ifp = sc->ifp; 1758 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1759 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1760 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1761 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1762 txp = txp->tx_next) { 1763 if (txp->tx_mbuf != NULL) { 1764 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, 1765 BUS_DMASYNC_POSTWRITE); 1766 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map); 1767 m_freem(txp->tx_mbuf); 1768 txp->tx_mbuf = NULL; 1769 /* clear this to reset csum offload bits */ 1770 txp->tx_cb->tbd[0].tb_addr = 0; 1771 } 1772 sc->tx_queued--; 1773 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1774 } 1775 sc->fxp_desc.tx_first = txp; 1776 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1777 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1778 if (sc->tx_queued == 0) 1779 sc->watchdog_timer = 0; 1780} 1781 1782static void 1783fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, struct mbuf *m, 1784 uint16_t status, int pos) 1785{ 1786 struct ether_header *eh; 1787 struct ip *ip; 1788 struct udphdr *uh; 1789 int32_t hlen, len, pktlen, temp32; 1790 uint16_t csum, *opts; 1791 1792 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) { 1793 if ((status & FXP_RFA_STATUS_PARSE) != 0) { 1794 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1795 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1796 if (status & FXP_RFDX_CS_IP_CSUM_VALID) 1797 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1798 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1799 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1800 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 1801 CSUM_PSEUDO_HDR; 1802 m->m_pkthdr.csum_data = 0xffff; 1803 } 1804 } 1805 return; 1806 } 1807 1808 pktlen = m->m_pkthdr.len; 1809 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 1810 return; 1811 eh = mtod(m, struct ether_header *); 1812 if (eh->ether_type != htons(ETHERTYPE_IP)) 1813 return; 1814 ip = (struct ip *)(eh + 1); 1815 if (ip->ip_v != IPVERSION) 1816 return; 1817 1818 hlen = ip->ip_hl << 2; 1819 pktlen -= sizeof(struct ether_header); 1820 if (hlen < sizeof(struct ip)) 1821 return; 1822 if (ntohs(ip->ip_len) < hlen) 1823 return; 1824 if (ntohs(ip->ip_len) != pktlen) 1825 return; 1826 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 1827 return; /* can't handle fragmented packet */ 1828 1829 switch (ip->ip_p) { 1830 case IPPROTO_TCP: 1831 if (pktlen < (hlen + sizeof(struct tcphdr))) 1832 return; 1833 break; 1834 case IPPROTO_UDP: 1835 if (pktlen < (hlen + sizeof(struct udphdr))) 1836 return; 1837 uh = (struct udphdr *)((caddr_t)ip + hlen); 1838 if (uh->uh_sum == 0) 1839 return; /* no checksum */ 1840 break; 1841 default: 1842 return; 1843 } 1844 /* Extract computed checksum. */ 1845 csum = be16dec(mtod(m, char *) + pos); 1846 /* checksum fixup for IP options */ 1847 len = hlen - sizeof(struct ip); 1848 if (len > 0) { 1849 opts = (uint16_t *)(ip + 1); 1850 for (; len > 0; len -= sizeof(uint16_t), opts++) { 1851 temp32 = csum - *opts; 1852 temp32 = (temp32 >> 16) + (temp32 & 65535); 1853 csum = temp32 & 65535; 1854 } 1855 } 1856 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1857 m->m_pkthdr.csum_data = csum; 1858} 1859 1860static int 1861fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, 1862 int count) 1863{ 1864 struct mbuf *m; 1865 struct fxp_rx *rxp; 1866 struct fxp_rfa *rfa; 1867 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1868 int rx_npkts; 1869 uint16_t status; 1870 1871 rx_npkts = 0; 1872 FXP_LOCK_ASSERT(sc, MA_OWNED); 1873 1874 if (rnr) 1875 sc->rnr++; 1876#ifdef DEVICE_POLLING 1877 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1878 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1879 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1880 rnr = 1; 1881 } 1882#endif 1883 1884 /* 1885 * Free any finished transmit mbuf chains. 1886 * 1887 * Handle the CNA event likt a CXTNO event. It used to 1888 * be that this event (control unit not ready) was not 1889 * encountered, but it is now with the SMPng modifications. 1890 * The exact sequence of events that occur when the interface 1891 * is brought up are different now, and if this event 1892 * goes unhandled, the configuration/rxfilter setup sequence 1893 * can stall for several seconds. The result is that no 1894 * packets go out onto the wire for about 5 to 10 seconds 1895 * after the interface is ifconfig'ed for the first time. 1896 */ 1897 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) 1898 fxp_txeof(sc); 1899 1900 /* 1901 * Try to start more packets transmitting. 1902 */ 1903 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1904 fxp_start_body(ifp); 1905 1906 /* 1907 * Just return if nothing happened on the receive side. 1908 */ 1909 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1910 return (rx_npkts); 1911 1912 /* 1913 * Process receiver interrupts. If a no-resource (RNR) 1914 * condition exists, get whatever packets we can and 1915 * re-start the receiver. 1916 * 1917 * When using polling, we do not process the list to completion, 1918 * so when we get an RNR interrupt we must defer the restart 1919 * until we hit the last buffer with the C bit set. 1920 * If we run out of cycles and rfa_headm has the C bit set, 1921 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1922 * that the info will be used in the subsequent polling cycle. 1923 */ 1924 for (;;) { 1925 rxp = sc->fxp_desc.rx_head; 1926 m = rxp->rx_mbuf; 1927 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1928 RFA_ALIGNMENT_FUDGE); 1929 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 1930 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1931 1932#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1933 if (count >= 0 && count-- == 0) { 1934 if (rnr) { 1935 /* Defer RNR processing until the next time. */ 1936 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1937 rnr = 0; 1938 } 1939 break; 1940 } 1941#endif /* DEVICE_POLLING */ 1942 1943 status = le16toh(rfa->rfa_status); 1944 if ((status & FXP_RFA_STATUS_C) == 0) 1945 break; 1946 1947 if ((status & FXP_RFA_STATUS_RNR) != 0) 1948 rnr++; 1949 /* 1950 * Advance head forward. 1951 */ 1952 sc->fxp_desc.rx_head = rxp->rx_next; 1953 1954 /* 1955 * Add a new buffer to the receive chain. 1956 * If this fails, the old buffer is recycled 1957 * instead. 1958 */ 1959 if (fxp_new_rfabuf(sc, rxp) == 0) { 1960 int total_len; 1961 1962 /* 1963 * Fetch packet length (the top 2 bits of 1964 * actual_size are flags set by the controller 1965 * upon completion), and drop the packet in case 1966 * of bogus length or CRC errors. 1967 */ 1968 total_len = le16toh(rfa->actual_size) & 0x3fff; 1969 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 1970 (ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1971 /* Adjust for appended checksum bytes. */ 1972 total_len -= 2; 1973 } 1974 if (total_len < (int)sizeof(struct ether_header) || 1975 total_len > (MCLBYTES - RFA_ALIGNMENT_FUDGE - 1976 sc->rfa_size) || 1977 status & (FXP_RFA_STATUS_CRC | 1978 FXP_RFA_STATUS_ALIGN | FXP_RFA_STATUS_OVERRUN)) { 1979 m_freem(m); 1980 fxp_add_rfabuf(sc, rxp); 1981 continue; 1982 } 1983 1984 m->m_pkthdr.len = m->m_len = total_len; 1985 m->m_pkthdr.rcvif = ifp; 1986 1987 /* Do IP checksum checking. */ 1988 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1989 fxp_rxcsum(sc, ifp, m, status, total_len); 1990 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 1991 (status & FXP_RFA_STATUS_VLAN) != 0) { 1992 m->m_pkthdr.ether_vtag = 1993 ntohs(rfa->rfax_vlan_id); 1994 m->m_flags |= M_VLANTAG; 1995 } 1996 /* 1997 * Drop locks before calling if_input() since it 1998 * may re-enter fxp_start() in the netisr case. 1999 * This would result in a lock reversal. Better 2000 * performance might be obtained by chaining all 2001 * packets received, dropping the lock, and then 2002 * calling if_input() on each one. 2003 */ 2004 FXP_UNLOCK(sc); 2005 (*ifp->if_input)(ifp, m); 2006 FXP_LOCK(sc); 2007 rx_npkts++; 2008 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2009 return (rx_npkts); 2010 } else { 2011 /* Reuse RFA and loaded DMA map. */ 2012 ifp->if_iqdrops++; 2013 fxp_discard_rfabuf(sc, rxp); 2014 } 2015 fxp_add_rfabuf(sc, rxp); 2016 } 2017 if (rnr) { 2018 fxp_scb_wait(sc); 2019 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 2020 sc->fxp_desc.rx_head->rx_addr); 2021 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2022 } 2023 return (rx_npkts); 2024} 2025 2026static void 2027fxp_update_stats(struct fxp_softc *sc) 2028{ 2029 struct ifnet *ifp = sc->ifp; 2030 struct fxp_stats *sp = sc->fxp_stats; 2031 struct fxp_hwstats *hsp; 2032 uint32_t *status; 2033 2034 FXP_LOCK_ASSERT(sc, MA_OWNED); 2035 2036 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2037 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2038 /* Update statistical counters. */ 2039 if (sc->revision >= FXP_REV_82559_A0) 2040 status = &sp->completion_status; 2041 else if (sc->revision >= FXP_REV_82558_A4) 2042 status = (uint32_t *)&sp->tx_tco; 2043 else 2044 status = &sp->tx_pause; 2045 if (*status == htole32(FXP_STATS_DR_COMPLETE)) { 2046 hsp = &sc->fxp_hwstats; 2047 hsp->tx_good += le32toh(sp->tx_good); 2048 hsp->tx_maxcols += le32toh(sp->tx_maxcols); 2049 hsp->tx_latecols += le32toh(sp->tx_latecols); 2050 hsp->tx_underruns += le32toh(sp->tx_underruns); 2051 hsp->tx_lostcrs += le32toh(sp->tx_lostcrs); 2052 hsp->tx_deffered += le32toh(sp->tx_deffered); 2053 hsp->tx_single_collisions += le32toh(sp->tx_single_collisions); 2054 hsp->tx_multiple_collisions += 2055 le32toh(sp->tx_multiple_collisions); 2056 hsp->tx_total_collisions += le32toh(sp->tx_total_collisions); 2057 hsp->rx_good += le32toh(sp->rx_good); 2058 hsp->rx_crc_errors += le32toh(sp->rx_crc_errors); 2059 hsp->rx_alignment_errors += le32toh(sp->rx_alignment_errors); 2060 hsp->rx_rnr_errors += le32toh(sp->rx_rnr_errors); 2061 hsp->rx_overrun_errors += le32toh(sp->rx_overrun_errors); 2062 hsp->rx_cdt_errors += le32toh(sp->rx_cdt_errors); 2063 hsp->rx_shortframes += le32toh(sp->rx_shortframes); 2064 hsp->tx_pause += le32toh(sp->tx_pause); 2065 hsp->rx_pause += le32toh(sp->rx_pause); 2066 hsp->rx_controls += le32toh(sp->rx_controls); 2067 hsp->tx_tco += le16toh(sp->tx_tco); 2068 hsp->rx_tco += le16toh(sp->rx_tco); 2069 2070 ifp->if_opackets += le32toh(sp->tx_good); 2071 ifp->if_collisions += le32toh(sp->tx_total_collisions); 2072 if (sp->rx_good) { 2073 ifp->if_ipackets += le32toh(sp->rx_good); 2074 sc->rx_idle_secs = 0; 2075 } else if (sc->flags & FXP_FLAG_RXBUG) { 2076 /* 2077 * Receiver's been idle for another second. 2078 */ 2079 sc->rx_idle_secs++; 2080 } 2081 ifp->if_ierrors += 2082 le32toh(sp->rx_crc_errors) + 2083 le32toh(sp->rx_alignment_errors) + 2084 le32toh(sp->rx_rnr_errors) + 2085 le32toh(sp->rx_overrun_errors); 2086 /* 2087 * If any transmit underruns occured, bump up the transmit 2088 * threshold by another 512 bytes (64 * 8). 2089 */ 2090 if (sp->tx_underruns) { 2091 ifp->if_oerrors += le32toh(sp->tx_underruns); 2092 if (tx_threshold < 192) 2093 tx_threshold += 64; 2094 } 2095 *status = 0; 2096 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2097 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2098 } 2099} 2100 2101/* 2102 * Update packet in/out/collision statistics. The i82557 doesn't 2103 * allow you to access these counters without doing a fairly 2104 * expensive DMA to get _all_ of the statistics it maintains, so 2105 * we do this operation here only once per second. The statistics 2106 * counters in the kernel are updated from the previous dump-stats 2107 * DMA and then a new dump-stats DMA is started. The on-chip 2108 * counters are zeroed when the DMA completes. If we can't start 2109 * the DMA immediately, we don't wait - we just prepare to read 2110 * them again next time. 2111 */ 2112static void 2113fxp_tick(void *xsc) 2114{ 2115 struct fxp_softc *sc = xsc; 2116 struct ifnet *ifp = sc->ifp; 2117 2118 FXP_LOCK_ASSERT(sc, MA_OWNED); 2119 2120 /* Update statistical counters. */ 2121 fxp_update_stats(sc); 2122 2123 /* 2124 * Release any xmit buffers that have completed DMA. This isn't 2125 * strictly necessary to do here, but it's advantagous for mbufs 2126 * with external storage to be released in a timely manner rather 2127 * than being defered for a potentially long time. This limits 2128 * the delay to a maximum of one second. 2129 */ 2130 fxp_txeof(sc); 2131 2132 /* 2133 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 2134 * then assume the receiver has locked up and attempt to clear 2135 * the condition by reprogramming the multicast filter. This is 2136 * a work-around for a bug in the 82557 where the receiver locks 2137 * up if it gets certain types of garbage in the syncronization 2138 * bits prior to the packet header. This bug is supposed to only 2139 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 2140 * mode as well (perhaps due to a 10/100 speed transition). 2141 */ 2142 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 2143 sc->rx_idle_secs = 0; 2144 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2145 fxp_init_body(sc, 1); 2146 return; 2147 } 2148 /* 2149 * If there is no pending command, start another stats 2150 * dump. Otherwise punt for now. 2151 */ 2152 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 2153 /* 2154 * Start another stats dump. 2155 */ 2156 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 2157 } 2158 if (sc->miibus != NULL) 2159 mii_tick(device_get_softc(sc->miibus)); 2160 2161 /* 2162 * Check that chip hasn't hung. 2163 */ 2164 fxp_watchdog(sc); 2165 2166 /* 2167 * Schedule another timeout one second from now. 2168 */ 2169 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2170} 2171 2172/* 2173 * Stop the interface. Cancels the statistics updater and resets 2174 * the interface. 2175 */ 2176static void 2177fxp_stop(struct fxp_softc *sc) 2178{ 2179 struct ifnet *ifp = sc->ifp; 2180 struct fxp_tx *txp; 2181 int i; 2182 2183 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2184 sc->watchdog_timer = 0; 2185 2186 /* 2187 * Cancel stats updater. 2188 */ 2189 callout_stop(&sc->stat_ch); 2190 2191 /* 2192 * Preserve PCI configuration, configure, IA/multicast 2193 * setup and put RU and CU into idle state. 2194 */ 2195 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 2196 DELAY(50); 2197 /* Disable interrupts. */ 2198 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2199 2200 fxp_update_stats(sc); 2201 2202 /* 2203 * Release any xmit buffers. 2204 */ 2205 txp = sc->fxp_desc.tx_list; 2206 if (txp != NULL) { 2207 for (i = 0; i < FXP_NTXCB; i++) { 2208 if (txp[i].tx_mbuf != NULL) { 2209 bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map, 2210 BUS_DMASYNC_POSTWRITE); 2211 bus_dmamap_unload(sc->fxp_txmtag, 2212 txp[i].tx_map); 2213 m_freem(txp[i].tx_mbuf); 2214 txp[i].tx_mbuf = NULL; 2215 /* clear this to reset csum offload bits */ 2216 txp[i].tx_cb->tbd[0].tb_addr = 0; 2217 } 2218 } 2219 } 2220 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2221 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2222 sc->tx_queued = 0; 2223} 2224 2225/* 2226 * Watchdog/transmission transmit timeout handler. Called when a 2227 * transmission is started on the interface, but no interrupt is 2228 * received before the timeout. This usually indicates that the 2229 * card has wedged for some reason. 2230 */ 2231static void 2232fxp_watchdog(struct fxp_softc *sc) 2233{ 2234 2235 FXP_LOCK_ASSERT(sc, MA_OWNED); 2236 2237 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 2238 return; 2239 2240 device_printf(sc->dev, "device timeout\n"); 2241 sc->ifp->if_oerrors++; 2242 2243 fxp_init_body(sc, 1); 2244} 2245 2246/* 2247 * Acquire locks and then call the real initialization function. This 2248 * is necessary because ether_ioctl() calls if_init() and this would 2249 * result in mutex recursion if the mutex was held. 2250 */ 2251static void 2252fxp_init(void *xsc) 2253{ 2254 struct fxp_softc *sc = xsc; 2255 2256 FXP_LOCK(sc); 2257 fxp_init_body(sc, 1); 2258 FXP_UNLOCK(sc); 2259} 2260 2261/* 2262 * Perform device initialization. This routine must be called with the 2263 * softc lock held. 2264 */ 2265static void 2266fxp_init_body(struct fxp_softc *sc, int setmedia) 2267{ 2268 struct ifnet *ifp = sc->ifp; 2269 struct mii_data *mii; 2270 struct fxp_cb_config *cbp; 2271 struct fxp_cb_ias *cb_ias; 2272 struct fxp_cb_tx *tcbp; 2273 struct fxp_tx *txp; 2274 int i, prm; 2275 2276 FXP_LOCK_ASSERT(sc, MA_OWNED); 2277 /* 2278 * Cancel any pending I/O 2279 */ 2280 fxp_stop(sc); 2281 2282 /* 2283 * Issue software reset, which also unloads the microcode. 2284 */ 2285 sc->flags &= ~FXP_FLAG_UCODE; 2286 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 2287 DELAY(50); 2288 2289 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 2290 2291 /* 2292 * Initialize base of CBL and RFA memory. Loading with zero 2293 * sets it up for regular linear addressing. 2294 */ 2295 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2296 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2297 2298 fxp_scb_wait(sc); 2299 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2300 2301 /* 2302 * Initialize base of dump-stats buffer. 2303 */ 2304 fxp_scb_wait(sc); 2305 bzero(sc->fxp_stats, sizeof(struct fxp_stats)); 2306 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2307 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2308 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2309 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2310 2311 /* 2312 * Attempt to load microcode if requested. 2313 * For ICH based controllers do not load microcode. 2314 */ 2315 if (sc->ident->ich == 0) { 2316 if (ifp->if_flags & IFF_LINK0 && 2317 (sc->flags & FXP_FLAG_UCODE) == 0) 2318 fxp_load_ucode(sc); 2319 } 2320 2321 /* 2322 * Set IFF_ALLMULTI status. It's needed in configure action 2323 * command. 2324 */ 2325 fxp_mc_addrs(sc); 2326 2327 /* 2328 * We temporarily use memory that contains the TxCB list to 2329 * construct the config CB. The TxCB list memory is rebuilt 2330 * later. 2331 */ 2332 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2333 2334 /* 2335 * This bcopy is kind of disgusting, but there are a bunch of must be 2336 * zero and must be one bits in this structure and this is the easiest 2337 * way to initialize them all to proper values. 2338 */ 2339 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2340 2341 cbp->cb_status = 0; 2342 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2343 FXP_CB_COMMAND_EL); 2344 cbp->link_addr = 0xffffffff; /* (no) next command */ 2345 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2346 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2347 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2348 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2349 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2350 cbp->type_enable = 0; /* actually reserved */ 2351 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2352 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2353 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2354 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2355 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2356 cbp->late_scb = 0; /* (don't) defer SCB update */ 2357 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2358 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2359 cbp->ci_int = 1; /* interrupt on CU idle */ 2360 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2361 cbp->ext_stats_dis = 1; /* disable extended counters */ 2362 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2363 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2364 cbp->disc_short_rx = !prm; /* discard short packets */ 2365 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2366 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2367 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2368 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2369 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2370 cbp->csma_dis = 0; /* (don't) disable link */ 2371 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 2372 (ifp->if_capenable & IFCAP_RXCSUM) != 0) ? 1 : 0; 2373 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2374 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2375 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2376 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2377 cbp->nsai = 1; /* (don't) disable source addr insert */ 2378 cbp->preamble_length = 2; /* (7 byte) preamble */ 2379 cbp->loopback = 0; /* (don't) loopback */ 2380 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2381 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2382 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2383 cbp->promiscuous = prm; /* promiscuous mode */ 2384 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2385 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2386 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2387 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2388 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2389 2390 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2391 cbp->padding = 1; /* (do) pad short tx packets */ 2392 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2393 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2394 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2395 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1; 2396 cbp->force_fdx = 0; /* (don't) force full duplex */ 2397 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2398 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2399 cbp->mc_all = ifp->if_flags & IFF_ALLMULTI ? 1 : prm; 2400 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2401 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 && 2402 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0; 2403 2404 if (sc->revision == FXP_REV_82557) { 2405 /* 2406 * The 82557 has no hardware flow control, the values 2407 * below are the defaults for the chip. 2408 */ 2409 cbp->fc_delay_lsb = 0; 2410 cbp->fc_delay_msb = 0x40; 2411 cbp->pri_fc_thresh = 3; 2412 cbp->tx_fc_dis = 0; 2413 cbp->rx_fc_restop = 0; 2414 cbp->rx_fc_restart = 0; 2415 cbp->fc_filter = 0; 2416 cbp->pri_fc_loc = 1; 2417 } else { 2418 /* Set pause RX FIFO threshold to 1KB. */ 2419 CSR_WRITE_1(sc, FXP_CSR_FC_THRESH, 1); 2420 /* Set pause time. */ 2421 cbp->fc_delay_lsb = 0xff; 2422 cbp->fc_delay_msb = 0xff; 2423 cbp->pri_fc_thresh = 3; 2424 mii = device_get_softc(sc->miibus); 2425 if ((IFM_OPTIONS(mii->mii_media_active) & 2426 IFM_ETH_TXPAUSE) != 0) 2427 /* enable transmit FC */ 2428 cbp->tx_fc_dis = 0; 2429 else 2430 /* disable transmit FC */ 2431 cbp->tx_fc_dis = 1; 2432 if ((IFM_OPTIONS(mii->mii_media_active) & 2433 IFM_ETH_RXPAUSE) != 0) { 2434 /* enable FC restart/restop frames */ 2435 cbp->rx_fc_restart = 1; 2436 cbp->rx_fc_restop = 1; 2437 } else { 2438 /* disable FC restart/restop frames */ 2439 cbp->rx_fc_restart = 0; 2440 cbp->rx_fc_restop = 0; 2441 } 2442 cbp->fc_filter = !prm; /* drop FC frames to host */ 2443 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2444 } 2445 2446 /* Enable 82558 and 82559 extended statistics functionality. */ 2447 if (sc->revision >= FXP_REV_82558_A4) { 2448 if (sc->revision >= FXP_REV_82559_A0) { 2449 /* 2450 * Extend configuration table size to 32 2451 * to include TCO configuration. 2452 */ 2453 cbp->byte_count = 32; 2454 cbp->ext_stats_dis = 1; 2455 /* Enable TCO stats. */ 2456 cbp->tno_int_or_tco_en = 1; 2457 cbp->gamla_rx = 1; 2458 } else 2459 cbp->ext_stats_dis = 0; 2460 } 2461 2462 /* 2463 * Start the config command/DMA. 2464 */ 2465 fxp_scb_wait(sc); 2466 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2467 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2468 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2469 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2470 /* ...and wait for it to complete. */ 2471 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2472 2473 /* 2474 * Now initialize the station address. Temporarily use the TxCB 2475 * memory area like we did above for the config CB. 2476 */ 2477 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2478 cb_ias->cb_status = 0; 2479 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2480 cb_ias->link_addr = 0xffffffff; 2481 bcopy(IF_LLADDR(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN); 2482 2483 /* 2484 * Start the IAS (Individual Address Setup) command/DMA. 2485 */ 2486 fxp_scb_wait(sc); 2487 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2488 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2489 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2490 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2491 /* ...and wait for it to complete. */ 2492 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2493 2494 /* 2495 * Initialize the multicast address list. 2496 */ 2497 fxp_mc_setup(sc); 2498 2499 /* 2500 * Initialize transmit control block (TxCB) list. 2501 */ 2502 txp = sc->fxp_desc.tx_list; 2503 tcbp = sc->fxp_desc.cbl_list; 2504 bzero(tcbp, FXP_TXCB_SZ); 2505 for (i = 0; i < FXP_NTXCB; i++) { 2506 txp[i].tx_mbuf = NULL; 2507 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2508 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2509 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2510 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2511 if (sc->flags & FXP_FLAG_EXT_TXCB) 2512 tcbp[i].tbd_array_addr = 2513 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2514 else 2515 tcbp[i].tbd_array_addr = 2516 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2517 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2518 } 2519 /* 2520 * Set the suspend flag on the first TxCB and start the control 2521 * unit. It will execute the NOP and then suspend. 2522 */ 2523 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2524 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2525 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2526 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2527 sc->tx_queued = 1; 2528 2529 fxp_scb_wait(sc); 2530 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2531 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2532 2533 /* 2534 * Initialize receiver buffer area - RFA. 2535 */ 2536 fxp_scb_wait(sc); 2537 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2538 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2539 2540 if (sc->miibus != NULL && setmedia != 0) 2541 mii_mediachg(device_get_softc(sc->miibus)); 2542 2543 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2544 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2545 2546 /* 2547 * Enable interrupts. 2548 */ 2549#ifdef DEVICE_POLLING 2550 /* 2551 * ... but only do that if we are not polling. And because (presumably) 2552 * the default is interrupts on, we need to disable them explicitly! 2553 */ 2554 if (ifp->if_capenable & IFCAP_POLLING ) 2555 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2556 else 2557#endif /* DEVICE_POLLING */ 2558 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2559 2560 /* 2561 * Start stats updater. 2562 */ 2563 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2564} 2565 2566static int 2567fxp_serial_ifmedia_upd(struct ifnet *ifp) 2568{ 2569 2570 return (0); 2571} 2572 2573static void 2574fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2575{ 2576 2577 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2578} 2579 2580/* 2581 * Change media according to request. 2582 */ 2583static int 2584fxp_ifmedia_upd(struct ifnet *ifp) 2585{ 2586 struct fxp_softc *sc = ifp->if_softc; 2587 struct mii_data *mii; 2588 struct mii_softc *miisc; 2589 2590 mii = device_get_softc(sc->miibus); 2591 FXP_LOCK(sc); 2592 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2593 PHY_RESET(miisc); 2594 mii_mediachg(mii); 2595 FXP_UNLOCK(sc); 2596 return (0); 2597} 2598 2599/* 2600 * Notify the world which media we're using. 2601 */ 2602static void 2603fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2604{ 2605 struct fxp_softc *sc = ifp->if_softc; 2606 struct mii_data *mii; 2607 2608 mii = device_get_softc(sc->miibus); 2609 FXP_LOCK(sc); 2610 mii_pollstat(mii); 2611 ifmr->ifm_active = mii->mii_media_active; 2612 ifmr->ifm_status = mii->mii_media_status; 2613 FXP_UNLOCK(sc); 2614} 2615 2616/* 2617 * Add a buffer to the end of the RFA buffer list. 2618 * Return 0 if successful, 1 for failure. A failure results in 2619 * reusing the RFA buffer. 2620 * The RFA struct is stuck at the beginning of mbuf cluster and the 2621 * data pointer is fixed up to point just past it. 2622 */ 2623static int 2624fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2625{ 2626 struct mbuf *m; 2627 struct fxp_rfa *rfa; 2628 bus_dmamap_t tmp_map; 2629 int error; 2630 2631 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2632 if (m == NULL) 2633 return (ENOBUFS); 2634 2635 /* 2636 * Move the data pointer up so that the incoming data packet 2637 * will be 32-bit aligned. 2638 */ 2639 m->m_data += RFA_ALIGNMENT_FUDGE; 2640 2641 /* 2642 * Get a pointer to the base of the mbuf cluster and move 2643 * data start past it. 2644 */ 2645 rfa = mtod(m, struct fxp_rfa *); 2646 m->m_data += sc->rfa_size; 2647 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2648 2649 rfa->rfa_status = 0; 2650 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2651 rfa->actual_size = 0; 2652 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE - 2653 sc->rfa_size; 2654 2655 /* 2656 * Initialize the rest of the RFA. Note that since the RFA 2657 * is misaligned, we cannot store values directly. We're thus 2658 * using the le32enc() function which handles endianness and 2659 * is also alignment-safe. 2660 */ 2661 le32enc(&rfa->link_addr, 0xffffffff); 2662 le32enc(&rfa->rbd_addr, 0xffffffff); 2663 2664 /* Map the RFA into DMA memory. */ 2665 error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa, 2666 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2667 &rxp->rx_addr, BUS_DMA_NOWAIT); 2668 if (error) { 2669 m_freem(m); 2670 return (error); 2671 } 2672 2673 if (rxp->rx_mbuf != NULL) 2674 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map); 2675 tmp_map = sc->spare_map; 2676 sc->spare_map = rxp->rx_map; 2677 rxp->rx_map = tmp_map; 2678 rxp->rx_mbuf = m; 2679 2680 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 2681 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2682 return (0); 2683} 2684 2685static void 2686fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2687{ 2688 struct fxp_rfa *p_rfa; 2689 struct fxp_rx *p_rx; 2690 2691 /* 2692 * If there are other buffers already on the list, attach this 2693 * one to the end by fixing up the tail to point to this one. 2694 */ 2695 if (sc->fxp_desc.rx_head != NULL) { 2696 p_rx = sc->fxp_desc.rx_tail; 2697 p_rfa = (struct fxp_rfa *) 2698 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2699 p_rx->rx_next = rxp; 2700 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2701 p_rfa->rfa_control = 0; 2702 bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map, 2703 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2704 } else { 2705 rxp->rx_next = NULL; 2706 sc->fxp_desc.rx_head = rxp; 2707 } 2708 sc->fxp_desc.rx_tail = rxp; 2709} 2710 2711static void 2712fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2713{ 2714 struct mbuf *m; 2715 struct fxp_rfa *rfa; 2716 2717 m = rxp->rx_mbuf; 2718 m->m_data = m->m_ext.ext_buf; 2719 /* 2720 * Move the data pointer up so that the incoming data packet 2721 * will be 32-bit aligned. 2722 */ 2723 m->m_data += RFA_ALIGNMENT_FUDGE; 2724 2725 /* 2726 * Get a pointer to the base of the mbuf cluster and move 2727 * data start past it. 2728 */ 2729 rfa = mtod(m, struct fxp_rfa *); 2730 m->m_data += sc->rfa_size; 2731 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2732 2733 rfa->rfa_status = 0; 2734 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2735 rfa->actual_size = 0; 2736 2737 /* 2738 * Initialize the rest of the RFA. Note that since the RFA 2739 * is misaligned, we cannot store values directly. We're thus 2740 * using the le32enc() function which handles endianness and 2741 * is also alignment-safe. 2742 */ 2743 le32enc(&rfa->link_addr, 0xffffffff); 2744 le32enc(&rfa->rbd_addr, 0xffffffff); 2745 2746 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 2747 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2748} 2749 2750static int 2751fxp_miibus_readreg(device_t dev, int phy, int reg) 2752{ 2753 struct fxp_softc *sc = device_get_softc(dev); 2754 int count = 10000; 2755 int value; 2756 2757 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2758 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2759 2760 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2761 && count--) 2762 DELAY(10); 2763 2764 if (count <= 0) 2765 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2766 2767 return (value & 0xffff); 2768} 2769 2770static int 2771fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2772{ 2773 struct fxp_softc *sc = device_get_softc(dev); 2774 int count = 10000; 2775 2776 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2777 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2778 (value & 0xffff)); 2779 2780 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2781 count--) 2782 DELAY(10); 2783 2784 if (count <= 0) 2785 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2786 return (0); 2787} 2788 2789static void 2790fxp_miibus_statchg(device_t dev) 2791{ 2792 struct fxp_softc *sc; 2793 struct mii_data *mii; 2794 struct ifnet *ifp; 2795 2796 sc = device_get_softc(dev); 2797 mii = device_get_softc(sc->miibus); 2798 ifp = sc->ifp; 2799 if (mii == NULL || ifp == NULL || 2800 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 2801 (mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) != 2802 (IFM_AVALID | IFM_ACTIVE)) 2803 return; 2804 2805 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T && 2806 sc->flags & FXP_FLAG_CU_RESUME_BUG) 2807 sc->cu_resume_bug = 1; 2808 else 2809 sc->cu_resume_bug = 0; 2810 /* 2811 * Call fxp_init_body in order to adjust the flow control settings. 2812 * Note that the 82557 doesn't support hardware flow control. 2813 */ 2814 if (sc->revision == FXP_REV_82557) 2815 return; 2816 fxp_init_body(sc, 0); 2817} 2818 2819static int 2820fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2821{ 2822 struct fxp_softc *sc = ifp->if_softc; 2823 struct ifreq *ifr = (struct ifreq *)data; 2824 struct mii_data *mii; 2825 int flag, mask, error = 0, reinit; 2826 2827 switch (command) { 2828 case SIOCSIFFLAGS: 2829 FXP_LOCK(sc); 2830 /* 2831 * If interface is marked up and not running, then start it. 2832 * If it is marked down and running, stop it. 2833 * XXX If it's up then re-initialize it. This is so flags 2834 * such as IFF_PROMISC are handled. 2835 */ 2836 if (ifp->if_flags & IFF_UP) { 2837 if (((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) && 2838 ((ifp->if_flags ^ sc->if_flags) & 2839 (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0) 2840 fxp_init_body(sc, 0); 2841 else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2842 fxp_init_body(sc, 1); 2843 } else { 2844 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2845 fxp_stop(sc); 2846 } 2847 sc->if_flags = ifp->if_flags; 2848 FXP_UNLOCK(sc); 2849 break; 2850 2851 case SIOCADDMULTI: 2852 case SIOCDELMULTI: 2853 FXP_LOCK(sc); 2854 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2855 fxp_init_body(sc, 0); 2856 FXP_UNLOCK(sc); 2857 break; 2858 2859 case SIOCSIFMEDIA: 2860 case SIOCGIFMEDIA: 2861 if (sc->miibus != NULL) { 2862 mii = device_get_softc(sc->miibus); 2863 error = ifmedia_ioctl(ifp, ifr, 2864 &mii->mii_media, command); 2865 } else { 2866 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2867 } 2868 break; 2869 2870 case SIOCSIFCAP: 2871 reinit = 0; 2872 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2873#ifdef DEVICE_POLLING 2874 if (mask & IFCAP_POLLING) { 2875 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2876 error = ether_poll_register(fxp_poll, ifp); 2877 if (error) 2878 return(error); 2879 FXP_LOCK(sc); 2880 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 2881 FXP_SCB_INTR_DISABLE); 2882 ifp->if_capenable |= IFCAP_POLLING; 2883 FXP_UNLOCK(sc); 2884 } else { 2885 error = ether_poll_deregister(ifp); 2886 /* Enable interrupts in any case */ 2887 FXP_LOCK(sc); 2888 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2889 ifp->if_capenable &= ~IFCAP_POLLING; 2890 FXP_UNLOCK(sc); 2891 } 2892 } 2893#endif 2894 FXP_LOCK(sc); 2895 if ((mask & IFCAP_TXCSUM) != 0 && 2896 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2897 ifp->if_capenable ^= IFCAP_TXCSUM; 2898 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2899 ifp->if_hwassist |= FXP_CSUM_FEATURES; 2900 else 2901 ifp->if_hwassist &= ~FXP_CSUM_FEATURES; 2902 } 2903 if ((mask & IFCAP_RXCSUM) != 0 && 2904 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 2905 ifp->if_capenable ^= IFCAP_RXCSUM; 2906 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0) 2907 reinit++; 2908 } 2909 if ((mask & IFCAP_TSO4) != 0 && 2910 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2911 ifp->if_capenable ^= IFCAP_TSO4; 2912 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 2913 ifp->if_hwassist |= CSUM_TSO; 2914 else 2915 ifp->if_hwassist &= ~CSUM_TSO; 2916 } 2917 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2918 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2919 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2920 if ((mask & IFCAP_VLAN_MTU) != 0 && 2921 (ifp->if_capabilities & IFCAP_VLAN_MTU) != 0) { 2922 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2923 if (sc->revision != FXP_REV_82557) 2924 flag = FXP_FLAG_LONG_PKT_EN; 2925 else /* a hack to get long frames on the old chip */ 2926 flag = FXP_FLAG_SAVE_BAD; 2927 sc->flags ^= flag; 2928 if (ifp->if_flags & IFF_UP) 2929 reinit++; 2930 } 2931 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2932 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2933 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2934 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2935 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2936 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2937 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2938 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2939 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2940 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2941 ifp->if_capenable &= 2942 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 2943 reinit++; 2944 } 2945 if (reinit > 0 && ifp->if_flags & IFF_UP) 2946 fxp_init_body(sc, 0); 2947 FXP_UNLOCK(sc); 2948 VLAN_CAPABILITIES(ifp); 2949 break; 2950 2951 default: 2952 error = ether_ioctl(ifp, command, data); 2953 } 2954 return (error); 2955} 2956 2957/* 2958 * Fill in the multicast address list and return number of entries. 2959 */ 2960static int 2961fxp_mc_addrs(struct fxp_softc *sc) 2962{ 2963 struct fxp_cb_mcs *mcsp = sc->mcsp; 2964 struct ifnet *ifp = sc->ifp; 2965 struct ifmultiaddr *ifma; 2966 int nmcasts; 2967 2968 nmcasts = 0; 2969 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2970 if_maddr_rlock(ifp); 2971 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2972 if (ifma->ifma_addr->sa_family != AF_LINK) 2973 continue; 2974 if (nmcasts >= MAXMCADDR) { 2975 ifp->if_flags |= IFF_ALLMULTI; 2976 nmcasts = 0; 2977 break; 2978 } 2979 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2980 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2981 nmcasts++; 2982 } 2983 if_maddr_runlock(ifp); 2984 } 2985 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2986 return (nmcasts); 2987} 2988 2989/* 2990 * Program the multicast filter. 2991 * 2992 * We have an artificial restriction that the multicast setup command 2993 * must be the first command in the chain, so we take steps to ensure 2994 * this. By requiring this, it allows us to keep up the performance of 2995 * the pre-initialized command ring (esp. link pointers) by not actually 2996 * inserting the mcsetup command in the ring - i.e. its link pointer 2997 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2998 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2999 * lead into the regular TxCB ring when it completes. 3000 */ 3001static void 3002fxp_mc_setup(struct fxp_softc *sc) 3003{ 3004 struct fxp_cb_mcs *mcsp; 3005 int count; 3006 3007 FXP_LOCK_ASSERT(sc, MA_OWNED); 3008 3009 mcsp = sc->mcsp; 3010 mcsp->cb_status = 0; 3011 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 3012 mcsp->link_addr = 0xffffffff; 3013 fxp_mc_addrs(sc); 3014 3015 /* 3016 * Wait until command unit is idle. This should never be the 3017 * case when nothing is queued, but make sure anyway. 3018 */ 3019 count = 100; 3020 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) != 3021 FXP_SCB_CUS_IDLE && --count) 3022 DELAY(10); 3023 if (count == 0) { 3024 device_printf(sc->dev, "command queue timeout\n"); 3025 return; 3026 } 3027 3028 /* 3029 * Start the multicast setup command. 3030 */ 3031 fxp_scb_wait(sc); 3032 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 3033 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3034 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 3035 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 3036 /* ...and wait for it to complete. */ 3037 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 3038} 3039 3040static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 3041static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 3042static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 3043static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 3044static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 3045static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 3046static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 3047 3048#define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 3049 3050static const struct ucode { 3051 uint32_t revision; 3052 uint32_t *ucode; 3053 int length; 3054 u_short int_delay_offset; 3055 u_short bundle_max_offset; 3056} const ucode_table[] = { 3057 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 3058 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 3059 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 3060 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 3061 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 3062 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 3063 { FXP_REV_82550, UCODE(fxp_ucode_d102), 3064 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 3065 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 3066 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 3067 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 3068 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 3069 { FXP_REV_82551_10, UCODE(fxp_ucode_d102e), 3070 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 3071 { 0, NULL, 0, 0, 0 } 3072}; 3073 3074static void 3075fxp_load_ucode(struct fxp_softc *sc) 3076{ 3077 const struct ucode *uc; 3078 struct fxp_cb_ucode *cbp; 3079 int i; 3080 3081 if (sc->flags & FXP_FLAG_NO_UCODE) 3082 return; 3083 3084 for (uc = ucode_table; uc->ucode != NULL; uc++) 3085 if (sc->revision == uc->revision) 3086 break; 3087 if (uc->ucode == NULL) 3088 return; 3089 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 3090 cbp->cb_status = 0; 3091 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 3092 cbp->link_addr = 0xffffffff; /* (no) next command */ 3093 for (i = 0; i < uc->length; i++) 3094 cbp->ucode[i] = htole32(uc->ucode[i]); 3095 if (uc->int_delay_offset) 3096 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 3097 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 3098 if (uc->bundle_max_offset) 3099 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 3100 htole16(sc->tunable_bundle_max); 3101 /* 3102 * Download the ucode to the chip. 3103 */ 3104 fxp_scb_wait(sc); 3105 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 3106 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3107 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 3108 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 3109 /* ...and wait for it to complete. */ 3110 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 3111 device_printf(sc->dev, 3112 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 3113 sc->tunable_int_delay, 3114 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 3115 sc->flags |= FXP_FLAG_UCODE; 3116 bzero(cbp, FXP_TXCB_SZ); 3117} 3118 3119#define FXP_SYSCTL_STAT_ADD(c, h, n, p, d) \ 3120 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 3121 3122static void 3123fxp_sysctl_node(struct fxp_softc *sc) 3124{ 3125 struct sysctl_ctx_list *ctx; 3126 struct sysctl_oid_list *child, *parent; 3127 struct sysctl_oid *tree; 3128 struct fxp_hwstats *hsp; 3129 3130 ctx = device_get_sysctl_ctx(sc->dev); 3131 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 3132 3133 SYSCTL_ADD_PROC(ctx, child, 3134 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 3135 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 3136 "FXP driver receive interrupt microcode bundling delay"); 3137 SYSCTL_ADD_PROC(ctx, child, 3138 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 3139 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 3140 "FXP driver receive interrupt microcode bundle size limit"); 3141 SYSCTL_ADD_INT(ctx, child,OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 3142 "FXP RNR events"); 3143 3144 /* 3145 * Pull in device tunables. 3146 */ 3147 sc->tunable_int_delay = TUNABLE_INT_DELAY; 3148 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 3149 (void) resource_int_value(device_get_name(sc->dev), 3150 device_get_unit(sc->dev), "int_delay", &sc->tunable_int_delay); 3151 (void) resource_int_value(device_get_name(sc->dev), 3152 device_get_unit(sc->dev), "bundle_max", &sc->tunable_bundle_max); 3153 sc->rnr = 0; 3154 3155 hsp = &sc->fxp_hwstats; 3156 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 3157 NULL, "FXP statistics"); 3158 parent = SYSCTL_CHILDREN(tree); 3159 3160 /* Rx MAC statistics. */ 3161 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 3162 NULL, "Rx MAC statistics"); 3163 child = SYSCTL_CHILDREN(tree); 3164 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames", 3165 &hsp->rx_good, "Good frames"); 3166 FXP_SYSCTL_STAT_ADD(ctx, child, "crc_errors", 3167 &hsp->rx_crc_errors, "CRC errors"); 3168 FXP_SYSCTL_STAT_ADD(ctx, child, "alignment_errors", 3169 &hsp->rx_alignment_errors, "Alignment errors"); 3170 FXP_SYSCTL_STAT_ADD(ctx, child, "rnr_errors", 3171 &hsp->rx_rnr_errors, "RNR errors"); 3172 FXP_SYSCTL_STAT_ADD(ctx, child, "overrun_errors", 3173 &hsp->rx_overrun_errors, "Overrun errors"); 3174 FXP_SYSCTL_STAT_ADD(ctx, child, "cdt_errors", 3175 &hsp->rx_cdt_errors, "Collision detect errors"); 3176 FXP_SYSCTL_STAT_ADD(ctx, child, "shortframes", 3177 &hsp->rx_shortframes, "Short frame errors"); 3178 if (sc->revision >= FXP_REV_82558_A4) { 3179 FXP_SYSCTL_STAT_ADD(ctx, child, "pause", 3180 &hsp->rx_pause, "Pause frames"); 3181 FXP_SYSCTL_STAT_ADD(ctx, child, "controls", 3182 &hsp->rx_controls, "Unsupported control frames"); 3183 } 3184 if (sc->revision >= FXP_REV_82559_A0) 3185 FXP_SYSCTL_STAT_ADD(ctx, child, "tco", 3186 &hsp->rx_tco, "TCO frames"); 3187 3188 /* Tx MAC statistics. */ 3189 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 3190 NULL, "Tx MAC statistics"); 3191 child = SYSCTL_CHILDREN(tree); 3192 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames", 3193 &hsp->tx_good, "Good frames"); 3194 FXP_SYSCTL_STAT_ADD(ctx, child, "maxcols", 3195 &hsp->tx_maxcols, "Maximum collisions errors"); 3196 FXP_SYSCTL_STAT_ADD(ctx, child, "latecols", 3197 &hsp->tx_latecols, "Late collisions errors"); 3198 FXP_SYSCTL_STAT_ADD(ctx, child, "underruns", 3199 &hsp->tx_underruns, "Underrun errors"); 3200 FXP_SYSCTL_STAT_ADD(ctx, child, "lostcrs", 3201 &hsp->tx_lostcrs, "Lost carrier sense"); 3202 FXP_SYSCTL_STAT_ADD(ctx, child, "deffered", 3203 &hsp->tx_deffered, "Deferred"); 3204 FXP_SYSCTL_STAT_ADD(ctx, child, "single_collisions", 3205 &hsp->tx_single_collisions, "Single collisions"); 3206 FXP_SYSCTL_STAT_ADD(ctx, child, "multiple_collisions", 3207 &hsp->tx_multiple_collisions, "Multiple collisions"); 3208 FXP_SYSCTL_STAT_ADD(ctx, child, "total_collisions", 3209 &hsp->tx_total_collisions, "Total collisions"); 3210 if (sc->revision >= FXP_REV_82558_A4) 3211 FXP_SYSCTL_STAT_ADD(ctx, child, "pause", 3212 &hsp->tx_pause, "Pause frames"); 3213 if (sc->revision >= FXP_REV_82559_A0) 3214 FXP_SYSCTL_STAT_ADD(ctx, child, "tco", 3215 &hsp->tx_tco, "TCO frames"); 3216} 3217 3218#undef FXP_SYSCTL_STAT_ADD 3219 3220static int 3221sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3222{ 3223 int error, value; 3224 3225 value = *(int *)arg1; 3226 error = sysctl_handle_int(oidp, &value, 0, req); 3227 if (error || !req->newptr) 3228 return (error); 3229 if (value < low || value > high) 3230 return (EINVAL); 3231 *(int *)arg1 = value; 3232 return (0); 3233} 3234 3235/* 3236 * Interrupt delay is expressed in microseconds, a multiplier is used 3237 * to convert this to the appropriate clock ticks before using. 3238 */ 3239static int 3240sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 3241{ 3242 3243 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 3244} 3245 3246static int 3247sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 3248{ 3249 3250 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 3251} 3252