1/******************************************************************************/ 2/* */ 3/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2003 Broadcom */ 4/* Corporation. */ 5/* All rights reserved. */ 6/* */ 7/* This program is free software; you can redistribute it and/or modify */ 8/* it under the terms of the GNU General Public License as published by */ 9/* the Free Software Foundation, located in the file LICENSE. */ 10/* */ 11/* History: */ 12/* */ 13/******************************************************************************/ 14 15#ifndef TIGON3_H 16#define TIGON3_H 17 18#include "lm.h" 19#if INCLUDE_TBI_SUPPORT 20#include "autoneg.h" 21#endif 22 23 24 25/******************************************************************************/ 26/* Constants. */ 27/******************************************************************************/ 28 29/* Maxim number of packet descriptors used for sending packets. */ 30#define MAX_TX_PACKET_DESC_COUNT T3_SEND_RCB_ENTRY_COUNT 31#define DEFAULT_TX_PACKET_DESC_COUNT 120 32 33/* Maximum number of packet descriptors used for receiving packets. */ 34#if T3_JUMBO_RCB_ENTRY_COUNT 35#define MAX_RX_PACKET_DESC_COUNT \ 36 (T3_STD_RCV_RCB_ENTRY_COUNT + T3_JUMBO_RCV_RCB_ENTRY_COUNT) 37#else 38#define MAX_RX_PACKET_DESC_COUNT T3_STD_RCV_RCB_ENTRY_COUNT 39#endif 40#define DEFAULT_RX_PACKET_DESC_COUNT 200 41 42/* Threshhold for double copying small tx packets. 0 will disable double */ 43/* copying of small Tx packets. */ 44#define DEFAULT_TX_COPY_BUFFER_SIZE 0 45#define MIN_TX_COPY_BUFFER_SIZE 64 46#define MAX_TX_COPY_BUFFER_SIZE 512 47 48/* Cache line. */ 49#define COMMON_CACHE_LINE_SIZE 0x20 50#define COMMON_CACHE_LINE_MASK (COMMON_CACHE_LINE_SIZE-1) 51 52/* Maximum number of fragment we can handle. */ 53#ifndef MAX_FRAGMENT_COUNT 54#define MAX_FRAGMENT_COUNT 32 55#endif 56 57/* B0 bug. */ 58#define BCM5700_BX_MIN_FRAG_SIZE 10 59#define BCM5700_BX_MIN_FRAG_BUF_SIZE 16 /* nice aligned size. */ 60#define BCM5700_BX_MIN_FRAG_BUF_SIZE_MASK (BCM5700_BX_MIN_FRAG_BUF_SIZE-1) 61#define BCM5700_BX_TX_COPY_BUF_SIZE (BCM5700_BX_MIN_FRAG_BUF_SIZE * \ 62 MAX_FRAGMENT_COUNT) 63 64/* MAGIC number. */ 65//#define T3_MAGIC_NUM 'KevT' 66#define T3_FIRMWARE_MAILBOX 0x0b50 67#define T3_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4B657654 68#define T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b 69 70#define T3_NIC_DATA_SIG_ADDR 0x0b54 71#define T3_NIC_DATA_SIG 0x4b657654 72 73#define T3_NIC_DATA_NIC_CFG_ADDR 0x0b58 74#define T3_NIC_CFG_LED_MAC_MODE BIT_NONE 75#define T3_NIC_CFG_LED_PHY_MODE_1 BIT_2 76#define T3_NIC_CFG_LED_PHY_MODE_2 BIT_3 77#define T3_NIC_CFG_LED_MODE_MASK (BIT_2 | BIT_3) 78#define T3_NIC_CFG_PHY_TYPE_UNKNOWN BIT_NONE 79#define T3_NIC_CFG_PHY_TYPE_COPPER BIT_4 80#define T3_NIC_CFG_PHY_TYPE_FIBER BIT_5 81#define T3_NIC_CFG_PHY_TYPE_MASK (BIT_4 | BIT_5) 82#define T3_NIC_CFG_ENABLE_WOL BIT_6 83#define T3_NIC_CFG_ENABLE_ASF BIT_7 84#define T3_NIC_EEPROM_WP BIT_8 85#define T3_NIC_WOL_LIMIT_10 BIT_10 86#define T3_NIC_MINI_PCI BIT_12 87#define T3_NIC_FIBER_WOL_CAPABLE BIT_14 88 89#define T3_NIC_DATA_PHY_ID_ADDR 0x0b74 90#define T3_NIC_PHY_ID1_MASK 0xffff0000 91#define T3_NIC_PHY_ID2_MASK 0x0000ffff 92 93#define T3_CMD_MAILBOX 0x0b78 94#define T3_CMD_NICDRV_ALIVE 0x01 95#define T3_CMD_NICDRV_PAUSE_FW 0x02 96#define T3_CMD_NICDRV_IPV4ADDR_CHANGE 0x03 97#define T3_CMD_NICDRV_IPV6ADDR_CHANGE 0x04 98#define T3_CMD_5703A0_FIX_DMAFW_DMAR 0x05 99#define T3_CMD_5703A0_FIX_DMAFW_DMAW 0x06 100 101#define T3_CMD_LENGTH_MAILBOX 0x0b7c 102#define T3_CMD_DATA_MAILBOX 0x0b80 103 104#define T3_ASF_FW_STATUS_MAILBOX 0x0c00 105 106#define T3_DRV_STATE_MAILBOX 0x0c04 107#define T3_DRV_STATE_START 0x01 108#define T3_DRV_STATE_START_DONE 0x80000001 109#define T3_DRV_STATE_UNLOAD 0x02 110#define T3_DRV_STATE_UNLOAD_DONE 0x80000002 111#define T3_DRV_STATE_WOL 0x03 112#define T3_DRV_STATE_SUSPEND 0x04 113 114#define T3_FW_RESET_TYPE_MAILBOX 0x0c08 115 116#define T3_MAC_ADDR_HIGH_MAILBOX 0x0c14 117#define T3_MAC_ADDR_LOW_MAILBOX 0x0c18 118 119#define DRV_WOL_MAILBOX 0xd30 120#define DRV_WOL_SIGNATURE 0x474c0000 121 122#define DRV_DOWN_STATE_SHUTDOWN 0x1 123 124#define DRV_WOL_SET_MAGIC_PKT BIT_2 125 126#define T3_NIC_DATA_NIC_CFG_ADDR2 0x0d38 /* bit 2-3 are same as in */ 127 /* 0xb58 */ 128#define T3_SHASTA_EXT_LED_MODE_MASK (BIT_15 | BIT_16) 129#define T3_SHASTA_EXT_LED_LEGACY_MODE BIT_NONE 130#define T3_SHASTA_EXT_LED_SHARED_TRAFFIC_LINK_MODE BIT_15 131#define T3_SHASTA_EXT_LED_MAC_MODE BIT_16 132#define T3_SHASTA_EXT_LED_WIRELESS_COMBO_MODE (BIT_15 | BIT_16) 133 134/******************************************************************************/ 135/* Hardware constants. */ 136/******************************************************************************/ 137 138/* Number of entries in the send ring: must be 512. */ 139#define T3_SEND_RCB_ENTRY_COUNT 512 140#define T3_SEND_RCB_ENTRY_COUNT_MASK (T3_SEND_RCB_ENTRY_COUNT-1) 141 142/* Number of send RCBs. May be 1-16 but for now, only support one. */ 143#define T3_MAX_SEND_RCB_COUNT 16 144 145/* Number of entries in the Standard Receive RCB. Must be 512 entries. */ 146#define T3_STD_RCV_RCB_ENTRY_COUNT 512 147#define T3_STD_RCV_RCB_ENTRY_COUNT_MASK (T3_STD_RCV_RCB_ENTRY_COUNT-1) 148#define DEFAULT_STD_RCV_DESC_COUNT 200 /* Must be < 512. */ 149#define MAX_STD_RCV_BUFFER_SIZE 0x600 150 151/* Number of entries in the Mini Receive RCB. This value can either be */ 152/* 0, 1024. Currently Mini Receive RCB is disabled. */ 153#ifndef T3_MINI_RCV_RCB_ENTRY_COUNT 154#define T3_MINI_RCV_RCB_ENTRY_COUNT 0 155#endif /* T3_MINI_RCV_RCB_ENTRY_COUNT */ 156#define T3_MINI_RCV_RCB_ENTRY_COUNT_MASK (T3_MINI_RCV_RCB_ENTRY_COUNT-1) 157#define MAX_MINI_RCV_BUFFER_SIZE 512 158#define DEFAULT_MINI_RCV_BUFFER_SIZE 64 159#define DEFAULT_MINI_RCV_DESC_COUNT 100 /* Must be < 1024. */ 160 161/* Number of entries in the Jumbo Receive RCB. This value must 256 or 0. */ 162/* Currently, Jumbo Receive RCB is disabled. */ 163#ifndef T3_JUMBO_RCV_RCB_ENTRY_COUNT 164#define T3_JUMBO_RCV_RCB_ENTRY_COUNT 0 165#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ 166#define T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK (T3_JUMBO_RCV_RCB_ENTRY_COUNT-1) 167 168#define MAX_JUMBO_RCV_BUFFER_SIZE (10 * 1024) /* > 1514 */ 169#define DEFAULT_JUMBO_RCV_BUFFER_SIZE (4 * 1024) /* > 1514 */ 170#define DEFAULT_JUMBO_RCV_DESC_COUNT 128 /* Must be < 256. */ 171 172#define MAX_JUMBO_TX_BUFFER_SIZE (8 * 1024) /* > 1514 */ 173#define DEFAULT_JUMBO_TX_BUFFER_SIZE (4 * 1024) /* > 1514 */ 174 175/* Number of receive return RCBs. Maybe 1-16 but for now, only support one. */ 176#define T3_MAX_RCV_RETURN_RCB_COUNT 16 177 178/* Number of entries in a Receive Return ring. This value is either 1024 */ 179/* or 2048. */ 180#ifndef T3_RCV_RETURN_RCB_ENTRY_COUNT 181#define T3_RCV_RETURN_RCB_ENTRY_COUNT 1024 182#endif /* T3_RCV_RETURN_RCB_ENTRY_COUNT */ 183#define T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK (T3_RCV_RETURN_RCB_ENTRY_COUNT-1) 184 185 186/* Default coalescing parameters. */ 187#ifdef BCM_NAPI_RXPOLL 188#define DEFAULT_RX_COALESCING_TICKS 18 189#define DEFAULT_RX_MAX_COALESCED_FRAMES 6 190#else 191#define DEFAULT_RX_COALESCING_TICKS 60 192#define DEFAULT_RX_MAX_COALESCED_FRAMES 15 193#endif 194 195#define DEFAULT_TX_COALESCING_TICKS 200 196#define DEFAULT_TX_MAX_COALESCED_FRAMES 35 197 198#define MAX_RX_COALESCING_TICKS 500 199#define MAX_TX_COALESCING_TICKS 500 200#define MAX_RX_MAX_COALESCED_FRAMES 100 201#define MAX_TX_MAX_COALESCED_FRAMES 100 202 203#define ADAPTIVE_LO_RX_MAX_COALESCED_FRAMES 5 204#define ADAPTIVE_HI_RX_MAX_COALESCED_FRAMES 48 205#define ADAPTIVE_LO_RX_COALESCING_TICKS 25 206#define ADAPTIVE_HI_RX_COALESCING_TICKS 120 207#define ADAPTIVE_LO_PKT_THRESH 52000 208#define ADAPTIVE_HI_PKT_THRESH 112000 209#define ADAPTIVE_LO_TX_MAX_COALESCED_FRAMES 20 210#define ADAPTIVE_HI_TX_MAX_COALESCED_FRAMES 75 211 212#ifdef BCM_NAPI_RXPOLL 213#define DEFAULT_RX_COALESCING_TICKS_DURING_INT 18 214#define DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT 6 215#else 216#define DEFAULT_RX_COALESCING_TICKS_DURING_INT 25 217#define DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT 2 218#endif 219#define DEFAULT_TX_COALESCING_TICKS_DURING_INT 25 220#define ADAPTIVE_LO_RX_MAX_COALESCED_FRAMES_DURING_INT 1 221#define ADAPTIVE_HI_RX_MAX_COALESCED_FRAMES_DURING_INT 5 222#define DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT 5 223 224#define BAD_DEFAULT_VALUE 0xffffffff 225 226#define DEFAULT_STATS_COALESCING_TICKS 1000000 227#define MIN_STATS_COALESCING_TICKS 100 228#define MAX_STATS_COALESCING_TICKS 3600000000U 229 230 231/* Receive BD Replenish thresholds. */ 232#define DEFAULT_RCV_STD_BD_REPLENISH_THRESHOLD 4 233#define DEFAULT_RCV_JUMBO_BD_REPLENISH_THRESHOLD 4 234 235/* Maximum physical fragment size. */ 236#define MAX_FRAGMENT_SIZE (64 * 1024) 237 238 239/* Standard view. */ 240#define T3_STD_VIEW_SIZE (64 * 1024) 241#define T3_FLAT_VIEW_SIZE (32 * 1024 * 1024) 242 243 244/* Buffer descriptor base address on the NIC's memory. */ 245 246#define T3_NIC_SND_BUFFER_DESC_ADDR 0x4000 247#define T3_NIC_STD_RCV_BUFFER_DESC_ADDR 0x6000 248#define T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR 0x7000 249 250#define T3_NIC_STD_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xc000 251#define T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xd000 252#define T3_NIC_MINI_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xe000 253 254#define T3_NIC_SND_BUFFER_DESC_SIZE (T3_SEND_RCB_ENTRY_COUNT * \ 255 sizeof(T3_SND_BD) / 4) 256 257#define T3_NIC_STD_RCV_BUFFER_DESC_SIZE (T3_STD_RCV_RCB_ENTRY_COUNT * \ 258 sizeof(T3_RCV_BD) / 4) 259 260#define T3_NIC_JUMBO_RCV_BUFFER_DESC_SIZE (T3_JUMBO_RCV_RCB_ENTRY_COUNT * \ 261 sizeof(T3_EXT_RCV_BD) / 4) 262 263 264/* MBUF pool. */ 265#define T3_NIC_MBUF_POOL_ADDR 0x8000 266#define T3_NIC_MBUF_POOL_SIZE96 0x18000 267#define T3_NIC_MBUF_POOL_SIZE64 0x10000 268 269#define T3_NIC_MBUF_POOL_ADDR_EXT_MEM 0x20000 270 271#define T3_NIC_BCM5705_MBUF_POOL_ADDR 0x10000 272#define T3_NIC_BCM5705_MBUF_POOL_SIZE 0xe000 273 274/* DMA descriptor pool */ 275#define T3_NIC_DMA_DESC_POOL_ADDR 0x2000 276#define T3_NIC_DMA_DESC_POOL_SIZE 0x2000 /* 8KB. */ 277 278#define T3_DEF_DMA_MBUF_LOW_WMARK 0x50 279#define T3_DEF_RX_MAC_MBUF_LOW_WMARK 0x20 280#define T3_DEF_MBUF_HIGH_WMARK 0x60 281 282#define T3_DEF_DMA_MBUF_LOW_WMARK_5705 0x0 283#define T3_DEF_RX_MAC_MBUF_LOW_WMARK_5705 0x10 284#define T3_DEF_MBUF_HIGH_WMARK_5705 0x60 285 286#define T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO 304 287#define T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO 152 288#define T3_DEF_MBUF_HIGH_WMARK_JUMBO 380 289 290#define T3_DEF_DMA_DESC_LOW_WMARK 5 291#define T3_DEF_DMA_DESC_HIGH_WMARK 10 292 293/* Maximum size of giant TCP packet can be sent */ 294#define T3_TCP_SEG_MAX_OFFLOAD_SIZE 64*1000 295#define T3_TCP_SEG_MIN_NUM_SEG 20 296 297#define T3_RX_CPU_ID 0x1 298#define T3_TX_CPU_ID 0x2 299#define T3_RX_CPU_SPAD_ADDR 0x30000 300#define T3_RX_CPU_SPAD_SIZE 0x4000 301#define T3_TX_CPU_SPAD_ADDR 0x34000 302#define T3_TX_CPU_SPAD_SIZE 0x4000 303 304typedef struct T3_DIR_ENTRY 305{ 306 PLM_UINT8 Buffer; 307 LM_UINT32 Offset; 308 LM_UINT32 Length; 309} T3_DIR_ENTRY,*PT3_DIR_ENTRY; 310 311typedef struct T3_FWIMG_INFO 312{ 313 LM_UINT32 StartAddress; 314 T3_DIR_ENTRY Text; 315 T3_DIR_ENTRY ROnlyData; 316 T3_DIR_ENTRY Data; 317 T3_DIR_ENTRY Sbss; 318 T3_DIR_ENTRY Bss; 319} T3_FWIMG_INFO, *PT3_FWIMG_INFO; 320 321 322 323/******************************************************************************/ 324/* Tigon3 PCI Registers. */ 325/******************************************************************************/ 326#define T3_PCI_ID_BCM5700 0x164414e4 327#define T3_PCI_ID_BCM5701 0x164514e4 328#define T3_PCI_ID_BCM5702 0x164614e4 329#define T3_PCI_ID_BCM5702x 0x16A614e4 330#define T3_PCI_ID_BCM5703 0x164714e4 331#define T3_PCI_ID_BCM5703x 0x16A714e4 332#define T3_PCI_ID_BCM5702FE 0x164D14e4 333#define T3_PCI_ID_BCM5704 0x164814e4 334#define T3_PCI_ID_BCM5705 0x165314e4 335#define T3_PCI_ID_BCM5705M 0x165D14e4 336#define T3_PCI_ID_BCM5705F 0x166E14e4 337#define T3_PCI_ID_BCM5901 0x170D14e4 338#define T3_PCI_ID_BCM5901A2 0x170E14e4 339#define T3_PCI_ID_BCM5751F 0x167E14e4 340 341#define T3_PCI_VENDOR_ID(x) ((x) & 0xffff) 342#define T3_PCI_DEVICE_ID(x) ((x) >> 16) 343 344#define T3_PCI_MISC_HOST_CTRL_REG 0x68 345 346/* The most significant 16bit of register 0x68. */ 347/* ChipId:4, ChipRev:4, MetalRev:8 */ 348#define T3_CHIP_ID_5700_A0 0x7000 349#define T3_CHIP_ID_5700_A1 0x7001 350#define T3_CHIP_ID_5700_B0 0x7100 351#define T3_CHIP_ID_5700_B1 0x7101 352#define T3_CHIP_ID_5700_C0 0x7200 353 354#define T3_CHIP_ID_5701_A0 0x0000 355#define T3_CHIP_ID_5701_B0 0x0100 356#define T3_CHIP_ID_5701_B2 0x0102 357#define T3_CHIP_ID_5701_B5 0x0105 358 359#define T3_CHIP_ID_5703_A0 0x1000 360#define T3_CHIP_ID_5703_A1 0x1001 361#define T3_CHIP_ID_5703_A2 0x1002 362#define T3_CHIP_ID_5703_A3 0x1003 363 364#define T3_CHIP_ID_5704_A0 0x2000 365#define T3_CHIP_ID_5704_A1 0x2001 366#define T3_CHIP_ID_5704_A2 0x2002 367 368#define T3_CHIP_ID_5705_A0 0x3000 369#define T3_CHIP_ID_5705_A1 0x3001 370#define T3_CHIP_ID_5705_A2 0x3002 371#define T3_CHIP_ID_5705_A3 0x3003 372 373#define T3_CHIP_ID_5750_A0 0x4000 374#define T3_CHIP_ID_5750_A1 0x4001 375#define T3_CHIP_ID_5750_A3 0x4003 376 377/* Chip Id. */ 378#define T3_ASIC_REV(_ChipRevId) ((_ChipRevId) >> 12) 379#define T3_ASIC_REV_5700 0x07 380#define T3_ASIC_REV_5701 0x00 381#define T3_ASIC_REV_5703 0x01 382#define T3_ASIC_REV_5704 0x02 383#define T3_ASIC_REV_5705 0x03 384#define T3_ASIC_REV_5750 0x04 385 386#define T3_ASIC_5705_OR_5750(_ChipRevId) \ 387 ((T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5705) || \ 388 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5750)) 389 390/* Chip id and revision. */ 391#define T3_CHIP_REV(_ChipRevId) ((_ChipRevId) >> 8) 392#define T3_CHIP_REV_5700_AX 0x70 393#define T3_CHIP_REV_5700_BX 0x71 394#define T3_CHIP_REV_5700_CX 0x72 395#define T3_CHIP_REV_5701_AX 0x00 396#define T3_CHIP_REV_5703_AX 0x10 397#define T3_CHIP_REV_5704_AX 0x20 398#define T3_CHIP_REV_5704_BX 0x21 399 400/* Metal revision. */ 401#define T3_METAL_REV(_ChipRevId) ((_ChipRevId) & 0xff) 402#define T3_METAL_REV_A0 0x00 403#define T3_METAL_REV_A1 0x01 404#define T3_METAL_REV_B0 0x00 405#define T3_METAL_REV_B1 0x01 406#define T3_METAL_REV_B2 0x02 407 408#define T3_PCI_REG_CLOCK_CTRL 0x74 409 410#define T3_PCI_DISABLE_RX_CLOCK BIT_10 411#define T3_PCI_DISABLE_TX_CLOCK BIT_11 412#define T3_PCI_SELECT_ALTERNATE_CLOCK BIT_12 413#define T3_PCI_POWER_DOWN_PCI_PLL133 BIT_15 414#define T3_PCI_44MHZ_CORE_CLOCK BIT_18 415#define T3_PCI_625_CORE_CLOCK BIT_20 416#define T3_PCI_FORCE_CLKRUN BIT_21 417#define T3_PCI_CLKRUN_OUTPUT_EN BIT_22 418 419 420#define T3_PCI_REG_ADDR_REG 0x78 421#define T3_PCI_REG_DATA_REG 0x80 422 423#define T3_PCI_MEM_WIN_ADDR_REG 0x7c 424#define T3_PCI_MEM_WIN_DATA_REG 0x84 425 426#define T3_PCI_PM_CAP_REG 0x48 427 428#define T3_PCI_PM_CAP_PME_D3COLD BIT_31 429#define T3_PCI_PM_CAP_PME_D3HOT BIT_30 430 431#define T3_PCI_PM_STATUS_CTRL_REG 0x4c 432 433#define T3_PM_POWER_STATE_MASK (BIT_0 | BIT_1) 434#define T3_PM_POWER_STATE_D0 BIT_NONE 435#define T3_PM_POWER_STATE_D1 BIT_0 436#define T3_PM_POWER_STATE_D2 BIT_1 437#define T3_PM_POWER_STATE_D3 (BIT_0 | BIT_1) 438 439#define T3_PM_PME_ENABLE BIT_8 440#define T3_PM_PME_ASSERTED BIT_15 441 442#define T3_MSI_CAPABILITY_ID_REG 0x58 443#define T3_MSI_NEXT_CAPABILITY_PTR 0x59 444 445/* PCI state register. */ 446#define T3_PCI_STATE_REG 0x70 447 448#define T3_PCI_STATE_FORCE_RESET BIT_0 449#define T3_PCI_STATE_INT_NOT_ACTIVE BIT_1 450#define T3_PCI_STATE_CONVENTIONAL_PCI_MODE BIT_2 451#define T3_PCI_STATE_BUS_SPEED_HIGH BIT_3 452#define T3_PCI_STATE_32BIT_PCI_BUS BIT_4 453 454 455/* Broadcom subsystem/subvendor IDs. */ 456#define T3_SVID_BROADCOM 0x14e4 457 458#define T3_SSID_BROADCOM_BCM95700A6 0x1644 459#define T3_SSID_BROADCOM_BCM95701A5 0x0001 460#define T3_SSID_BROADCOM_BCM95700T6 0x0002 /* BCM8002 */ 461#define T3_SSID_BROADCOM_BCM95700A9 0x0003 /* Agilent */ 462#define T3_SSID_BROADCOM_BCM95701T1 0x0005 463#define T3_SSID_BROADCOM_BCM95701T8 0x0006 464#define T3_SSID_BROADCOM_BCM95701A7 0x0007 /* Agilent */ 465#define T3_SSID_BROADCOM_BCM95701A10 0x0008 466#define T3_SSID_BROADCOM_BCM95701A12 0x8008 467#define T3_SSID_BROADCOM_BCM95703Ax1 0x0009 468#define T3_SSID_BROADCOM_BCM95703Ax2 0x8009 469 470/* 3COM subsystem/subvendor IDs. */ 471#define T3_SVID_3COM 0x10b7 472 473#define T3_SSID_3COM_3C996T 0x1000 474#define T3_SSID_3COM_3C996BT 0x1006 475#define T3_SSID_3COM_3C996CT 0x1002 476#define T3_SSID_3COM_3C997T 0x1003 477#define T3_SSID_3COM_3C1000T 0x1007 478#define T3_SSID_3COM_3C940BR01 0x1008 479 480/* Fiber boards. */ 481#define T3_SSID_3COM_3C996SX 0x1004 482#define T3_SSID_3COM_3C997SX 0x1005 483 484 485/* Dell subsystem/subvendor IDs. */ 486 487#define T3_SVID_DELL 0x1028 488 489#define T3_SSID_DELL_VIPER 0x00d1 490#define T3_SSID_DELL_JAGUAR 0x0106 491#define T3_SSID_DELL_MERLOT 0x0109 492#define T3_SSID_DELL_SLIM_MERLOT 0x010a 493 494/* Compaq subsystem/subvendor IDs */ 495 496#define T3_SVID_COMPAQ 0x0e11 497 498#define T3_SSID_COMPAQ_BANSHEE 0x007c 499#define T3_SSID_COMPAQ_BANSHEE_2 0x009a 500#define T3_SSID_COMPAQ_CHANGELING 0x007d 501#define T3_SSID_COMPAQ_NC7780 0x0085 502#define T3_SSID_COMPAQ_NC7780_2 0x0099 503 504#define T3_PCIE_CAPABILITY_ID_REG 0xD0 505#define T3_PCIE_CAPABILITY_ID 0x10 506 507#define T3_PCIE_CAPABILITY_REG 0xD2 508 509/******************************************************************************/ 510/* MII registers. */ 511/******************************************************************************/ 512 513/* Control register. */ 514#define PHY_CTRL_REG 0x00 515 516#define PHY_CTRL_SPEED_MASK (BIT_6 | BIT_13) 517#define PHY_CTRL_SPEED_SELECT_10MBPS BIT_NONE 518#define PHY_CTRL_SPEED_SELECT_100MBPS BIT_13 519#define PHY_CTRL_SPEED_SELECT_1000MBPS BIT_6 520#define PHY_CTRL_COLLISION_TEST_ENABLE BIT_7 521#define PHY_CTRL_FULL_DUPLEX_MODE BIT_8 522#define PHY_CTRL_RESTART_AUTO_NEG BIT_9 523#define PHY_CTRL_ISOLATE_PHY BIT_10 524#define PHY_CTRL_LOWER_POWER_MODE BIT_11 525#define PHY_CTRL_AUTO_NEG_ENABLE BIT_12 526#define PHY_CTRL_LOOPBACK_MODE BIT_14 527#define PHY_CTRL_PHY_RESET BIT_15 528 529 530/* Status register. */ 531#define PHY_STATUS_REG 0x01 532 533#define PHY_STATUS_LINK_PASS BIT_2 534#define PHY_STATUS_AUTO_NEG_COMPLETE BIT_5 535 536 537/* Phy Id registers. */ 538#define PHY_ID1_REG 0x02 539#define PHY_ID1_OUI_MASK 0xffff 540 541#define PHY_ID2_REG 0x03 542#define PHY_ID2_REV_MASK 0x000f 543#define PHY_ID2_MODEL_MASK 0x03f0 544#define PHY_ID2_OUI_MASK 0xfc00 545 546 547/* Auto-negotiation advertisement register. */ 548#define PHY_AN_AD_REG 0x04 549 550#define PHY_AN_AD_ASYM_PAUSE BIT_11 551#define PHY_AN_AD_PAUSE_CAPABLE BIT_10 552#define PHY_AN_AD_10BASET_HALF BIT_5 553#define PHY_AN_AD_10BASET_FULL BIT_6 554#define PHY_AN_AD_100BASETX_HALF BIT_7 555#define PHY_AN_AD_100BASETX_FULL BIT_8 556#define PHY_AN_AD_PROTOCOL_802_3_CSMA_CD 0x01 557 558#define PHY_AN_AD_ALL_SPEEDS (PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL |\ 559 PHY_AN_AD_100BASETX_HALF | PHY_AN_AD_100BASETX_FULL) 560 561/* Auto-negotiation Link Partner Ability register. */ 562#define PHY_LINK_PARTNER_ABILITY_REG 0x05 563 564#define PHY_LINK_PARTNER_ASYM_PAUSE BIT_11 565#define PHY_LINK_PARTNER_PAUSE_CAPABLE BIT_10 566 567 568/* Auto-negotiation expansion register. */ 569#define PHY_AN_EXPANSION_REG 0x06 570 571 572 573/******************************************************************************/ 574/* BCM5400 and BCM5401 phy info. */ 575/******************************************************************************/ 576 577#define PHY_DEVICE_ID 1 578 579/* OUI: bit 31-10; Model#: bit 9-4; Rev# bit 3-0. */ 580#define PHY_UNKNOWN_PHY 0x00000000 581#define PHY_BCM5400_PHY_ID 0x60008040 582#define PHY_BCM5401_PHY_ID 0x60008050 583#define PHY_BCM5411_PHY_ID 0x60008070 584#define PHY_BCM5701_PHY_ID 0x60008110 585#define PHY_BCM5703_PHY_ID 0x60008160 586#define PHY_BCM5704_PHY_ID 0x60008190 587#define PHY_BCM5705_PHY_ID 0x600081a0 588#define PHY_BCM5750_PHY_ID 0x60008180 589#define PHY_BCM8002_PHY_ID 0x60010140 590 591#define PHY_BCM5401_B0_REV 0x1 592#define PHY_BCM5401_B2_REV 0x3 593#define PHY_BCM5401_C0_REV 0x6 594 595#define PHY_ID_OUI_MASK 0xfffffc00 596#define PHY_ID_MODEL_MASK 0x000003f0 597#define PHY_ID_REV_MASK 0x0000000f 598#define PHY_ID_MASK (PHY_ID_OUI_MASK | \ 599 PHY_ID_MODEL_MASK) 600 601 602#define UNKNOWN_PHY_ID(x) ((((x) & PHY_ID_MASK) != PHY_BCM5400_PHY_ID) && \ 603 (((x) & PHY_ID_MASK) != PHY_BCM5401_PHY_ID) && \ 604 (((x) & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) && \ 605 (((x) & PHY_ID_MASK) != PHY_BCM5701_PHY_ID) && \ 606 (((x) & PHY_ID_MASK) != PHY_BCM5703_PHY_ID) && \ 607 (((x) & PHY_ID_MASK) != PHY_BCM5704_PHY_ID) && \ 608 (((x) & PHY_ID_MASK) != PHY_BCM5705_PHY_ID) && \ 609 (((x) & PHY_ID_MASK) != PHY_BCM5750_PHY_ID) && \ 610 (((x) & PHY_ID_MASK) != PHY_BCM8002_PHY_ID)) 611 612 613 614/* 1000Base-T control register. */ 615#define BCM540X_1000BASET_CTRL_REG 0x09 616 617#define BCM540X_AN_AD_1000BASET_HALF BIT_8 618#define BCM540X_AN_AD_1000BASET_FULL BIT_9 619#define BCM540X_CONFIG_AS_MASTER BIT_11 620#define BCM540X_ENABLE_CONFIG_AS_MASTER BIT_12 621 622#define BCM540X_AN_AD_ALL_1G_SPEEDS (BCM540X_AN_AD_1000BASET_HALF | \ 623 BCM540X_AN_AD_1000BASET_FULL) 624 625/* Extended control register. */ 626#define BCM540X_EXT_CTRL_REG 0x10 627 628#define BCM540X_EXT_CTRL_LINK3_LED_MODE BIT_1 629#define BCM540X_EXT_CTRL_FORCE_LED_OFF BIT_3 630#define BCM540X_EXT_CTRL_TBI BIT_15 631 632/* PHY extended status register. */ 633#define BCM540X_EXT_STATUS_REG 0x11 634 635#define BCM540X_EXT_STATUS_LINK_PASS BIT_8 636 637 638/* DSP Coefficient Read/Write Port. */ 639#define BCM540X_DSP_RW_PORT 0x15 640 641 642/* DSP Coeficient Address Register. */ 643#define BCM540X_DSP_ADDRESS_REG 0x17 644 645#define BCM540X_DSP_TAP_NUMBER_MASK 0x00 646#define BCM540X_DSP_AGC_A 0x00 647#define BCM540X_DSP_AGC_B 0x01 648#define BCM540X_DSP_MSE_PAIR_STATUS 0x02 649#define BCM540X_DSP_SOFT_DECISION 0x03 650#define BCM540X_DSP_PHASE_REG 0x04 651#define BCM540X_DSP_SKEW 0x05 652#define BCM540X_DSP_POWER_SAVER_UPPER_BOUND 0x06 653#define BCM540X_DSP_POWER_SAVER_LOWER_BOUND 0x07 654#define BCM540X_DSP_LAST_ECHO 0x08 655#define BCM540X_DSP_FREQUENCY 0x09 656#define BCM540X_DSP_PLL_BANDWIDTH 0x0a 657#define BCM540X_DSP_PLL_PHASE_OFFSET 0x0b 658 659#define BCM540X_DSP_FILTER_DCOFFSET (BIT_10 | BIT_11) 660#define BCM540X_DSP_FILTER_FEXT3 (BIT_8 | BIT_9 | BIT_11) 661#define BCM540X_DSP_FILTER_FEXT2 (BIT_9 | BIT_11) 662#define BCM540X_DSP_FILTER_FEXT1 (BIT_8 | BIT_11) 663#define BCM540X_DSP_FILTER_FEXT0 BIT_11 664#define BCM540X_DSP_FILTER_NEXT3 (BIT_8 | BIT_9 | BIT_10) 665#define BCM540X_DSP_FILTER_NEXT2 (BIT_9 | BIT_10) 666#define BCM540X_DSP_FILTER_NEXT1 (BIT_8 | BIT_10) 667#define BCM540X_DSP_FILTER_NEXT0 BIT_10 668#define BCM540X_DSP_FILTER_ECHO (BIT_8 | BIT_9) 669#define BCM540X_DSP_FILTER_DFE BIT_9 670#define BCM540X_DSP_FILTER_FFE BIT_8 671 672#define BCM540X_DSP_CONTROL_ALL_FILTERS BIT_12 673 674#define BCM540X_DSP_SEL_CH_0 BIT_NONE 675#define BCM540X_DSP_SEL_CH_1 BIT_13 676#define BCM540X_DSP_SEL_CH_2 BIT_14 677#define BCM540X_DSP_SEL_CH_3 (BIT_13 | BIT_14) 678 679#define BCM540X_CONTROL_ALL_CHANNELS BIT_15 680 681 682/* Auxilliary Control Register (Shadow Register) */ 683#define BCM5401_AUX_CTRL 0x18 684 685#define BCM5401_SHADOW_SEL_MASK 0x7 686#define BCM5401_SHADOW_SEL_NORMAL 0x00 687#define BCM5401_SHADOW_SEL_10BASET 0x01 688#define BCM5401_SHADOW_SEL_POWER_CONTROL 0x02 689#define BCM5401_SHADOW_SEL_IP_PHONE 0x03 690#define BCM5401_SHADOW_SEL_MISC_TEST1 0x04 691#define BCM5401_SHADOW_SEL_MISC_TEST2 0x05 692#define BCM5401_SHADOW_SEL_IP_PHONE_SEED 0x06 693 694 695/* Shadow register selector == '000' */ 696#define BCM5401_SHDW_NORMAL_DIAG_MODE BIT_3 697#define BCM5401_SHDW_NORMAL_DISABLE_MBP BIT_4 698#define BCM5401_SHDW_NORMAL_DISABLE_LOW_PWR BIT_5 699#define BCM5401_SHDW_NORMAL_DISABLE_INV_PRF BIT_6 700#define BCM5401_SHDW_NORMAL_DISABLE_PRF BIT_7 701#define BCM5401_SHDW_NORMAL_RX_SLICING_NORMAL BIT_NONE 702#define BCM5401_SHDW_NORMAL_RX_SLICING_4D BIT_8 703#define BCM5401_SHDW_NORMAL_RX_SLICING_3LVL_1D BIT_9 704#define BCM5401_SHDW_NORMAL_RX_SLICING_5LVL_1D (BIT_8 | BIT_9) 705#define BCM5401_SHDW_NORMAL_TX_6DB_CODING BIT_10 706#define BCM5401_SHDW_NORMAL_ENABLE_SM_DSP_CLOCK BIT_11 707#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_4NS BIT_NONE 708#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_5NS BIT_12 709#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_3NS BIT_13 710#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_0NS (BIT_12 | BIT_13) 711#define BCM5401_SHDW_NORMAL_EXT_PACKET_LENGTH BIT_14 712#define BCM5401_SHDW_NORMAL_EXTERNAL_LOOPBACK BIT_15 713 714 715/* Auxilliary status summary. */ 716#define BCM540X_AUX_STATUS_REG 0x19 717 718#define BCM540X_AUX_LINK_PASS BIT_2 719#define BCM540X_AUX_SPEED_MASK (BIT_8 | BIT_9 | BIT_10) 720#define BCM540X_AUX_10BASET_HD BIT_8 721#define BCM540X_AUX_10BASET_FD BIT_9 722#define BCM540X_AUX_100BASETX_HD (BIT_8 | BIT_9) 723#define BCM540X_AUX_100BASET4 BIT_10 724#define BCM540X_AUX_100BASETX_FD (BIT_8 | BIT_10) 725#define BCM540X_AUX_100BASET_HD (BIT_9 | BIT_10) 726#define BCM540X_AUX_100BASET_FD (BIT_8 | BIT_9 | BIT_10) 727 728 729/* Interrupt status. */ 730#define BCM540X_INT_STATUS_REG 0x1a 731 732#define BCM540X_INT_LINK_CHANGE BIT_1 733#define BCM540X_INT_SPEED_CHANGE BIT_2 734#define BCM540X_INT_DUPLEX_CHANGE BIT_3 735#define BCM540X_INT_AUTO_NEG_PAGE_RX BIT_10 736 737 738/* Interrupt mask register. */ 739#define BCM540X_INT_MASK_REG 0x1b 740 741 742 743/******************************************************************************/ 744/* Register definitions. */ 745/******************************************************************************/ 746 747typedef volatile LM_UINT8 T3_8BIT_REGISTER, *PT3_8BIT_REGISTER; 748typedef volatile LM_UINT16 T3_16BIT_REGISTER, *PT3_16BIT_REGISTER; 749typedef volatile LM_UINT32 T3_32BIT_REGISTER, *PT3_32BIT_REGISTER; 750 751typedef struct { 752 /* Big endian format. */ 753 T3_32BIT_REGISTER High; 754 T3_32BIT_REGISTER Low; 755} T3_64BIT_REGISTER, *PT3_64BIT_REGISTER; 756 757typedef T3_64BIT_REGISTER T3_64BIT_HOST_ADDR, *PT3_64BIT_HOST_ADDR; 758 759#define T3_NUM_OF_DMA_DESC 256 760#define T3_NUM_OF_MBUF 768 761 762typedef struct 763{ 764 T3_64BIT_REGISTER host_addr; 765 T3_32BIT_REGISTER nic_mbuf; 766 T3_16BIT_REGISTER len; 767 T3_16BIT_REGISTER cqid_sqid; 768 T3_32BIT_REGISTER flags; 769 T3_32BIT_REGISTER opaque1; 770 T3_32BIT_REGISTER opaque2; 771 T3_32BIT_REGISTER opaque3; 772}T3_DMA_DESC, *PT3_DMA_DESC; 773 774 775 776/******************************************************************************/ 777/* Ring control block. */ 778/******************************************************************************/ 779 780typedef struct { 781 T3_64BIT_REGISTER HostRingAddr; 782 783 union { 784 struct { 785#ifdef BIG_ENDIAN_HOST 786 T3_16BIT_REGISTER MaxLen; 787 T3_16BIT_REGISTER Flags; 788#else /* BIG_ENDIAN_HOST */ 789 T3_16BIT_REGISTER Flags; 790 T3_16BIT_REGISTER MaxLen; 791#endif 792 } s; 793 794 T3_32BIT_REGISTER MaxLen_Flags; 795 } u; 796 797 T3_32BIT_REGISTER NicRingAddr; 798} T3_RCB, *PT3_RCB; 799 800#define T3_RCB_FLAG_USE_EXT_RECV_BD BIT_0 801#define T3_RCB_FLAG_RING_DISABLED BIT_1 802 803 804 805/******************************************************************************/ 806/* Status block. */ 807/******************************************************************************/ 808 809/* 810 * Size of status block is actually 0x50 bytes. Use 0x80 bytes for 811 * cache line alignment. 812 */ 813#define T3_STATUS_BLOCK_SIZE 0x80 814 815typedef struct { 816 volatile LM_UINT32 Status; 817 #define STATUS_BLOCK_UPDATED BIT_0 818 #define STATUS_BLOCK_LINK_CHANGED_STATUS BIT_1 819 #define STATUS_BLOCK_ERROR BIT_2 820 821 volatile LM_UINT32 StatusTag; 822 823#ifdef BIG_ENDIAN_HOST 824 volatile LM_UINT16 RcvStdConIdx; 825 volatile LM_UINT16 RcvJumboConIdx; 826 827 volatile LM_UINT16 Reserved2; 828 volatile LM_UINT16 RcvMiniConIdx; 829 830 struct { 831 volatile LM_UINT16 SendConIdx; /* Send consumer index. */ 832 volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ 833 } Idx[16]; 834#else /* BIG_ENDIAN_HOST */ 835 volatile LM_UINT16 RcvJumboConIdx; 836 volatile LM_UINT16 RcvStdConIdx; 837 838 volatile LM_UINT16 RcvMiniConIdx; 839 volatile LM_UINT16 Reserved2; 840 841 struct { 842 volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ 843 volatile LM_UINT16 SendConIdx; /* Send consumer index. */ 844 } Idx[16]; 845#endif 846} T3_STATUS_BLOCK, *PT3_STATUS_BLOCK; 847 848 849 850/******************************************************************************/ 851/* Receive buffer descriptors. */ 852/******************************************************************************/ 853 854typedef struct { 855 T3_64BIT_HOST_ADDR HostAddr; 856 857#ifdef BIG_ENDIAN_HOST 858 volatile LM_UINT16 Index; 859 volatile LM_UINT16 Len; 860 861 volatile LM_UINT16 Type; 862 volatile LM_UINT16 Flags; 863 864 volatile LM_UINT16 IpCksum; 865 volatile LM_UINT16 TcpUdpCksum; 866 867 volatile LM_UINT16 ErrorFlag; 868 volatile LM_UINT16 VlanTag; 869#else /* BIG_ENDIAN_HOST */ 870 volatile LM_UINT16 Len; 871 volatile LM_UINT16 Index; 872 873 volatile LM_UINT16 Flags; 874 volatile LM_UINT16 Type; 875 876 volatile LM_UINT16 TcpUdpCksum; 877 volatile LM_UINT16 IpCksum; 878 879 volatile LM_UINT16 VlanTag; 880 volatile LM_UINT16 ErrorFlag; 881#endif 882 883 volatile LM_UINT32 Reserved; 884 volatile LM_UINT32 Opaque; 885} T3_RCV_BD, *PT3_RCV_BD; 886 887 888typedef struct { 889 T3_64BIT_HOST_ADDR HostAddr[3]; 890 891#ifdef BIG_ENDIAN_HOST 892 LM_UINT16 Len1; 893 LM_UINT16 Len2; 894 895 LM_UINT16 Len3; 896 LM_UINT16 Reserved1; 897#else /* BIG_ENDIAN_HOST */ 898 LM_UINT16 Len2; 899 LM_UINT16 Len1; 900 901 LM_UINT16 Reserved1; 902 LM_UINT16 Len3; 903#endif 904 905 T3_RCV_BD StdRcvBd; 906} T3_EXT_RCV_BD, *PT3_EXT_RCV_BD; 907 908 909/* Error flags. */ 910#define RCV_BD_ERR_BAD_CRC 0x0001 911#define RCV_BD_ERR_COLL_DETECT 0x0002 912#define RCV_BD_ERR_LINK_LOST_DURING_PKT 0x0004 913#define RCV_BD_ERR_PHY_DECODE_ERR 0x0008 914#define RCV_BD_ERR_ODD_NIBBLED_RCVD_MII 0x0010 915#define RCV_BD_ERR_MAC_ABORT 0x0020 916#define RCV_BD_ERR_LEN_LT_64 0x0040 917#define RCV_BD_ERR_TRUNC_NO_RESOURCES 0x0080 918#define RCV_BD_ERR_GIANT_FRAME_RCVD 0x0100 919 920 921/* Buffer descriptor flags. */ 922#define RCV_BD_FLAG_END 0x0004 923#define RCV_BD_FLAG_JUMBO_RING 0x0020 924#define RCV_BD_FLAG_VLAN_TAG 0x0040 925#define RCV_BD_FLAG_FRAME_HAS_ERROR 0x0400 926#define RCV_BD_FLAG_MINI_RING 0x0800 927#define RCV_BD_FLAG_IP_CHKSUM_FIELD 0x1000 928#define RCV_BD_FLAG_TCP_UDP_CHKSUM_FIELD 0x2000 929#define RCV_BD_FLAG_TCP_PACKET 0x4000 930 931 932 933/******************************************************************************/ 934/* Send buffer descriptor. */ 935/******************************************************************************/ 936 937typedef struct { 938 T3_64BIT_HOST_ADDR HostAddr; 939 940 union { 941 struct { 942#ifdef BIG_ENDIAN_HOST 943 LM_UINT16 Len; 944 LM_UINT16 Flags; 945#else /* BIG_ENDIAN_HOST */ 946 LM_UINT16 Flags; 947 LM_UINT16 Len; 948#endif 949 } s1; 950 951 LM_UINT32 Len_Flags; 952 } u1; 953 954 union { 955 struct { 956#ifdef BIG_ENDIAN_HOST 957 LM_UINT16 Reserved; 958 LM_UINT16 VlanTag; 959#else /* BIG_ENDIAN_HOST */ 960 LM_UINT16 VlanTag; 961 LM_UINT16 Reserved; 962#endif 963 } s2; 964 965 LM_UINT32 VlanTag; 966 } u2; 967} T3_SND_BD, *PT3_SND_BD; 968 969 970/* Send buffer descriptor flags. */ 971#define SND_BD_FLAG_TCP_UDP_CKSUM 0x0001 972#define SND_BD_FLAG_IP_CKSUM 0x0002 973#define SND_BD_FLAG_END 0x0004 974#define SND_BD_FLAG_IP_FRAG 0x0008 975#define SND_BD_FLAG_IP_FRAG_END 0x0010 976#define SND_BD_FLAG_VLAN_TAG 0x0040 977#define SND_BD_FLAG_COAL_NOW 0x0080 978#define SND_BD_FLAG_CPU_PRE_DMA 0x0100 979#define SND_BD_FLAG_CPU_POST_DMA 0x0200 980#define SND_BD_FLAG_INSERT_SRC_ADDR 0x1000 981#define SND_BD_FLAG_CHOOSE_SRC_ADDR 0x6000 982#define SND_BD_FLAG_DONT_GEN_CRC 0x8000 983 984/* MBUFs */ 985typedef struct T3_MBUF_FRAME_DESC { 986#ifdef BIG_ENDIAN_HOST 987 LM_UINT32 status_control; 988 union { 989 struct { 990 LM_UINT8 cqid; 991 LM_UINT8 reserved1; 992 LM_UINT16 length; 993 }s1; 994 LM_UINT32 word; 995 }u1; 996 union { 997 struct 998 { 999 LM_UINT16 ip_hdr_start; 1000 LM_UINT16 tcp_udp_hdr_start; 1001 }s2; 1002 1003 LM_UINT32 word; 1004 }u2; 1005 1006 union { 1007 struct { 1008 LM_UINT16 data_start; 1009 LM_UINT16 vlan_id; 1010 }s3; 1011 1012 LM_UINT32 word; 1013 }u3; 1014 1015 union { 1016 struct { 1017 LM_UINT16 ip_checksum; 1018 LM_UINT16 tcp_udp_checksum; 1019 }s4; 1020 1021 LM_UINT32 word; 1022 }u4; 1023 1024 union { 1025 struct { 1026 LM_UINT16 pseudo_checksum; 1027 LM_UINT16 checksum_status; 1028 }s5; 1029 1030 LM_UINT32 word; 1031 }u5; 1032 1033 union { 1034 struct { 1035 LM_UINT16 rule_match; 1036 LM_UINT8 class; 1037 LM_UINT8 rupt; 1038 }s6; 1039 1040 LM_UINT32 word; 1041 }u6; 1042 1043 union { 1044 struct { 1045 LM_UINT16 reserved2; 1046 LM_UINT16 mbuf_num; 1047 }s7; 1048 1049 LM_UINT32 word; 1050 }u7; 1051 1052 LM_UINT32 reserved3; 1053 LM_UINT32 reserved4; 1054#else 1055 LM_UINT32 status_control; 1056 union { 1057 struct { 1058 LM_UINT16 length; 1059 LM_UINT8 reserved1; 1060 LM_UINT8 cqid; 1061 }s1; 1062 LM_UINT32 word; 1063 }u1; 1064 union { 1065 struct 1066 { 1067 LM_UINT16 tcp_udp_hdr_start; 1068 LM_UINT16 ip_hdr_start; 1069 }s2; 1070 1071 LM_UINT32 word; 1072 }u2; 1073 1074 union { 1075 struct { 1076 LM_UINT16 vlan_id; 1077 LM_UINT16 data_start; 1078 }s3; 1079 1080 LM_UINT32 word; 1081 }u3; 1082 1083 union { 1084 struct { 1085 LM_UINT16 tcp_udp_checksum; 1086 LM_UINT16 ip_checksum; 1087 }s4; 1088 1089 LM_UINT32 word; 1090 }u4; 1091 1092 union { 1093 struct { 1094 LM_UINT16 checksum_status; 1095 LM_UINT16 pseudo_checksum; 1096 }s5; 1097 1098 LM_UINT32 word; 1099 }u5; 1100 1101 union { 1102 struct { 1103 LM_UINT8 rupt; 1104 LM_UINT8 class; 1105 LM_UINT16 rule_match; 1106 }s6; 1107 1108 LM_UINT32 word; 1109 }u6; 1110 1111 union { 1112 struct { 1113 LM_UINT16 mbuf_num; 1114 LM_UINT16 reserved2; 1115 }s7; 1116 1117 LM_UINT32 word; 1118 }u7; 1119 1120 LM_UINT32 reserved3; 1121 LM_UINT32 reserved4; 1122#endif 1123}T3_MBUF_FRAME_DESC,*PT3_MBUF_FRAME_DESC; 1124 1125typedef struct T3_MBUF_HDR { 1126 union { 1127 struct { 1128 unsigned int C:1; 1129 unsigned int F:1; 1130 unsigned int reserved1:7; 1131 unsigned int next_mbuf:16; 1132 unsigned int length:7; 1133 }s1; 1134 1135 LM_UINT32 word; 1136 }u1; 1137 1138 LM_UINT32 next_frame_ptr; 1139}T3_MBUF_HDR, *PT3_MBUF_HDR; 1140 1141typedef struct T3_MBUF 1142{ 1143 T3_MBUF_HDR hdr; 1144 union 1145 { 1146 struct { 1147 T3_MBUF_FRAME_DESC frame_hdr; 1148 LM_UINT32 data[20]; 1149 }s1; 1150 1151 struct { 1152 LM_UINT32 data[30]; 1153 }s2; 1154 }body; 1155}T3_MBUF, *PT3_MBUF; 1156 1157#define T3_MBUF_BASE (T3_NIC_MBUF_POOL_ADDR >> 7) 1158#define T3_MBUF_END ((T3_NIC_MBUF_POOL_ADDR + T3_NIC_MBUF_POOL_SIZE) >> 7) 1159 1160 1161 1162/******************************************************************************/ 1163/* Statistics block. */ 1164/******************************************************************************/ 1165 1166typedef struct { 1167 LM_UINT8 Reserved0[0x400-0x300]; 1168 1169 /* Statistics maintained by Receive MAC. */ 1170 T3_64BIT_REGISTER ifHCInOctets; 1171 T3_64BIT_REGISTER Reserved1; 1172 T3_64BIT_REGISTER etherStatsFragments; 1173 T3_64BIT_REGISTER ifHCInUcastPkts; 1174 T3_64BIT_REGISTER ifHCInMulticastPkts; 1175 T3_64BIT_REGISTER ifHCInBroadcastPkts; 1176 T3_64BIT_REGISTER dot3StatsFCSErrors; 1177 T3_64BIT_REGISTER dot3StatsAlignmentErrors; 1178 T3_64BIT_REGISTER xonPauseFramesReceived; 1179 T3_64BIT_REGISTER xoffPauseFramesReceived; 1180 T3_64BIT_REGISTER macControlFramesReceived; 1181 T3_64BIT_REGISTER xoffStateEntered; 1182 T3_64BIT_REGISTER dot3StatsFramesTooLong; 1183 T3_64BIT_REGISTER etherStatsJabbers; 1184 T3_64BIT_REGISTER etherStatsUndersizePkts; 1185 T3_64BIT_REGISTER inRangeLengthError; 1186 T3_64BIT_REGISTER outRangeLengthError; 1187 T3_64BIT_REGISTER etherStatsPkts64Octets; 1188 T3_64BIT_REGISTER etherStatsPkts65Octetsto127Octets; 1189 T3_64BIT_REGISTER etherStatsPkts128Octetsto255Octets; 1190 T3_64BIT_REGISTER etherStatsPkts256Octetsto511Octets; 1191 T3_64BIT_REGISTER etherStatsPkts512Octetsto1023Octets; 1192 T3_64BIT_REGISTER etherStatsPkts1024Octetsto1522Octets; 1193 T3_64BIT_REGISTER etherStatsPkts1523Octetsto2047Octets; 1194 T3_64BIT_REGISTER etherStatsPkts2048Octetsto4095Octets; 1195 T3_64BIT_REGISTER etherStatsPkts4096Octetsto8191Octets; 1196 T3_64BIT_REGISTER etherStatsPkts8192Octetsto9022Octets; 1197 1198 T3_64BIT_REGISTER Unused1[37]; 1199 1200 /* Statistics maintained by Transmit MAC. */ 1201 T3_64BIT_REGISTER ifHCOutOctets; 1202 T3_64BIT_REGISTER Reserved2; 1203 T3_64BIT_REGISTER etherStatsCollisions; 1204 T3_64BIT_REGISTER outXonSent; 1205 T3_64BIT_REGISTER outXoffSent; 1206 T3_64BIT_REGISTER flowControlDone; 1207 T3_64BIT_REGISTER dot3StatsInternalMacTransmitErrors; 1208 T3_64BIT_REGISTER dot3StatsSingleCollisionFrames; 1209 T3_64BIT_REGISTER dot3StatsMultipleCollisionFrames; 1210 T3_64BIT_REGISTER dot3StatsDeferredTransmissions; 1211 T3_64BIT_REGISTER Reserved3; 1212 T3_64BIT_REGISTER dot3StatsExcessiveCollisions; 1213 T3_64BIT_REGISTER dot3StatsLateCollisions; 1214 T3_64BIT_REGISTER dot3Collided2Times; 1215 T3_64BIT_REGISTER dot3Collided3Times; 1216 T3_64BIT_REGISTER dot3Collided4Times; 1217 T3_64BIT_REGISTER dot3Collided5Times; 1218 T3_64BIT_REGISTER dot3Collided6Times; 1219 T3_64BIT_REGISTER dot3Collided7Times; 1220 T3_64BIT_REGISTER dot3Collided8Times; 1221 T3_64BIT_REGISTER dot3Collided9Times; 1222 T3_64BIT_REGISTER dot3Collided10Times; 1223 T3_64BIT_REGISTER dot3Collided11Times; 1224 T3_64BIT_REGISTER dot3Collided12Times; 1225 T3_64BIT_REGISTER dot3Collided13Times; 1226 T3_64BIT_REGISTER dot3Collided14Times; 1227 T3_64BIT_REGISTER dot3Collided15Times; 1228 T3_64BIT_REGISTER ifHCOutUcastPkts; 1229 T3_64BIT_REGISTER ifHCOutMulticastPkts; 1230 T3_64BIT_REGISTER ifHCOutBroadcastPkts; 1231 T3_64BIT_REGISTER dot3StatsCarrierSenseErrors; 1232 T3_64BIT_REGISTER ifOutDiscards; 1233 T3_64BIT_REGISTER ifOutErrors; 1234 1235 T3_64BIT_REGISTER Unused2[31]; 1236 1237 /* Statistics maintained by Receive List Placement. */ 1238 T3_64BIT_REGISTER COSIfHCInPkts[16]; 1239 T3_64BIT_REGISTER COSFramesDroppedDueToFilters; 1240 T3_64BIT_REGISTER nicDmaWriteQueueFull; 1241 T3_64BIT_REGISTER nicDmaWriteHighPriQueueFull; 1242 T3_64BIT_REGISTER nicNoMoreRxBDs; 1243 T3_64BIT_REGISTER ifInDiscards; 1244 T3_64BIT_REGISTER ifInErrors; 1245 T3_64BIT_REGISTER nicRecvThresholdHit; 1246 1247 T3_64BIT_REGISTER Unused3[9]; 1248 1249 /* Statistics maintained by Send Data Initiator. */ 1250 T3_64BIT_REGISTER COSIfHCOutPkts[16]; 1251 T3_64BIT_REGISTER nicDmaReadQueueFull; 1252 T3_64BIT_REGISTER nicDmaReadHighPriQueueFull; 1253 T3_64BIT_REGISTER nicSendDataCompQueueFull; 1254 1255 /* Statistics maintained by Host Coalescing. */ 1256 T3_64BIT_REGISTER nicRingSetSendProdIndex; 1257 T3_64BIT_REGISTER nicRingStatusUpdate; 1258 T3_64BIT_REGISTER nicInterrupts; 1259 T3_64BIT_REGISTER nicAvoidedInterrupts; 1260 T3_64BIT_REGISTER nicSendThresholdHit; 1261 1262 LM_UINT8 Reserved4[0xb00-0x9c0]; 1263} T3_STATS_BLOCK, *PT3_STATS_BLOCK; 1264 1265 1266 1267/******************************************************************************/ 1268/* PCI configuration registers. */ 1269/******************************************************************************/ 1270 1271typedef struct { 1272 T3_16BIT_REGISTER VendorId; 1273 T3_16BIT_REGISTER DeviceId; 1274 1275 T3_16BIT_REGISTER Command; 1276 T3_16BIT_REGISTER Status; 1277 1278 T3_32BIT_REGISTER ClassCodeRevId; 1279 1280 T3_8BIT_REGISTER CacheLineSize; 1281 T3_8BIT_REGISTER LatencyTimer; 1282 T3_8BIT_REGISTER HeaderType; 1283 T3_8BIT_REGISTER Bist; 1284 1285 T3_32BIT_REGISTER MemBaseAddrLow; 1286 T3_32BIT_REGISTER MemBaseAddrHigh; 1287 1288 LM_UINT8 Unused1[20]; 1289 1290 T3_16BIT_REGISTER SubsystemVendorId; 1291 T3_16BIT_REGISTER SubsystemId; 1292 1293 T3_32BIT_REGISTER RomBaseAddr; 1294 1295 T3_8BIT_REGISTER PciXCapiblityPtr; 1296 LM_UINT8 Unused2[7]; 1297 1298 T3_8BIT_REGISTER IntLine; 1299 T3_8BIT_REGISTER IntPin; 1300 T3_8BIT_REGISTER MinGnt; 1301 T3_8BIT_REGISTER MaxLat; 1302 1303 T3_8BIT_REGISTER PciXCapabilities; 1304 T3_8BIT_REGISTER PmCapabilityPtr; 1305 T3_16BIT_REGISTER PciXCommand; 1306 1307 T3_32BIT_REGISTER PciXStatus; 1308 1309 T3_8BIT_REGISTER PmCapabilityId; 1310 T3_8BIT_REGISTER VpdCapabilityPtr; 1311 T3_16BIT_REGISTER PmCapabilities; 1312 1313 T3_16BIT_REGISTER PmCtrlStatus; 1314 #define PM_CTRL_PME_STATUS BIT_15 1315 #define PM_CTRL_PME_ENABLE BIT_8 1316 #define PM_CTRL_PME_POWER_STATE_D0 0 1317 #define PM_CTRL_PME_POWER_STATE_D1 1 1318 #define PM_CTRL_PME_POWER_STATE_D2 2 1319 #define PM_CTRL_PME_POWER_STATE_D3H 3 1320 1321 T3_8BIT_REGISTER BridgeSupportExt; 1322 T3_8BIT_REGISTER PmData; 1323 1324 T3_8BIT_REGISTER VpdCapabilityId; 1325 T3_8BIT_REGISTER MsiCapabilityPtr; 1326 T3_16BIT_REGISTER VpdAddrFlag; 1327 #define VPD_FLAG_WRITE (1 << 15) 1328 #define VPD_FLAG_RW_MASK (1 << 15) 1329 #define VPD_FLAG_READ 0 1330 1331 1332 T3_32BIT_REGISTER VpdData; 1333 1334 T3_8BIT_REGISTER MsiCapabilityId; 1335 T3_8BIT_REGISTER NextCapabilityPtr; 1336 T3_16BIT_REGISTER MsiCtrl; 1337 #define MSI_CTRL_64BIT_CAP (1 << 7) 1338 #define MSI_CTRL_MSG_ENABLE(x) (x << 4) 1339 #define MSI_CTRL_MSG_CAP(x) (x << 1) 1340 #define MSI_CTRL_ENABLE (1 << 0) 1341 1342 1343 T3_32BIT_REGISTER MsiAddrLow; 1344 T3_32BIT_REGISTER MsiAddrHigh; 1345 1346 T3_16BIT_REGISTER MsiData; 1347 T3_16BIT_REGISTER Unused3; 1348 1349 T3_32BIT_REGISTER MiscHostCtrl; 1350 #define MISC_HOST_CTRL_CLEAR_INT BIT_0 1351 #define MISC_HOST_CTRL_MASK_PCI_INT BIT_1 1352 #define MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP BIT_2 1353 #define MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP BIT_3 1354 #define MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW BIT_4 1355 #define MISC_HOST_CTRL_ENABLE_CLK_REG_RW BIT_5 1356 #define MISC_HOST_CTRL_ENABLE_REG_WORD_SWAP BIT_6 1357 #define MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS BIT_7 1358 #define MISC_HOST_CTRL_ENABLE_INT_MASK_MODE BIT_8 1359 #define MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE BIT_9 1360 1361 T3_32BIT_REGISTER DmaReadWriteCtrl; 1362 #define DMA_CTRL_WRITE_CMD 0x70000000 1363 #define DMA_CTRL_WRITE_BOUNDARY_64_PCIE 0x10000000 1364 #define DMA_CTRL_WRITE_BOUNDARY_128_PCIE 0x30000000 1365 #define DMA_CTRL_WRITE_BOUNDARY_DISABLE_PCIE 0x70000000 1366 #define DMA_CTRL_READ_CMD 0x06000000 1367 1368 #define DMA_CTRL_WRITE_BOUNDARY_MASK (BIT_11 | BIT_12 | BIT_13) 1369 #define DMA_CTRL_WRITE_BOUNDARY_DISABLE 0 1370 #define DMA_CTRL_WRITE_BOUNDARY_16 BIT_11 1371 #define DMA_CTRL_WRITE_BOUNDARY_128_PCIX BIT_11 1372 #define DMA_CTRL_WRITE_BOUNDARY_32 BIT_12 1373 #define DMA_CTRL_WRITE_BOUNDARY_256_PCIX BIT_12 1374 #define DMA_CTRL_WRITE_BOUNDARY_64 (BIT_12 | BIT_11) 1375 #define DMA_CTRL_WRITE_BOUNDARY_384_PCIX (BIT_12 | BIT_11) 1376 #define DMA_CTRL_WRITE_BOUNDARY_128 BIT_13 1377 #define DMA_CTRL_WRITE_BOUNDARY_256 (BIT_13 | BIT_11) 1378 #define DMA_CTRL_WRITE_BOUNDARY_512 (BIT_13 | BIT_12) 1379 #define DMA_CTRL_WRITE_BOUNDARY_1024 (BIT_13 | BIT_12 | BIT_11) 1380 #define DMA_CTRL_WRITE_ONE_DMA_AT_ONCE BIT_14 1381 1382 #define DMA_CTRL_READ_BOUNDARY_MASK (BIT_10 | BIT_9 | BIT_8) 1383 #define DMA_CTRL_READ_BOUNDARY_DISABLE 0 1384 #define DMA_CTRL_READ_BOUNDARY_16 BIT_8 1385 #define DMA_CTRL_READ_BOUNDARY_128_PCIX BIT_8 1386 #define DMA_CTRL_READ_BOUNDARY_32 BIT_9 1387 #define DMA_CTRL_READ_BOUNDARY_256_PCIX BIT_9 1388 #define DMA_CTRL_READ_BOUNDARY_64 (BIT_9 | BIT_8) 1389 #define DMA_CTRL_READ_BOUNDARY_384_PCIX (BIT_9 | BIT_8) 1390 #define DMA_CTRL_READ_BOUNDARY_128 BIT_10 1391 #define DMA_CTRL_READ_BOUNDARY_256 (BIT_10 | BIT_8) 1392 #define DMA_CTRL_READ_BOUNDARY_512 (BIT_10 | BIT_9) 1393 #define DMA_CTRL_READ_BOUNDARY_1024 (BIT_10 | BIT_9 | BIT_8) 1394 1395 T3_32BIT_REGISTER PciState; 1396 #define T3_PCI_STATE_FORCE_PCI_RESET BIT_0 1397 #define T3_PCI_STATE_INTERRUPT_NOT_ACTIVE BIT_1 1398 #define T3_PCI_STATE_NOT_PCI_X_BUS BIT_2 1399 #define T3_PCI_STATE_HIGH_BUS_SPEED BIT_3 1400 #define T3_PCI_STATE_32BIT_PCI_BUS BIT_4 1401 #define T3_PCI_STATE_PCI_ROM_ENABLE BIT_5 1402 #define T3_PCI_STATE_PCI_ROM_RETRY_ENABLE BIT_6 1403 #define T3_PCI_STATE_FLAT_VIEW BIT_8 1404 #define T3_PCI_STATE_RETRY_SAME_DMA BIT_13 1405 1406 T3_32BIT_REGISTER ClockCtrl; 1407 #define T3_PCI_CLKCTRL_TXCPU_CLK_DISABLE BIT_11 1408 #define T3_PCI_CLKCTRL_RXCPU_CLK_DISABLE BIT_10 1409 #define T3_PCI_CLKCTRL_CORE_CLK_DISABLE BIT_9 1410 1411 T3_32BIT_REGISTER RegBaseAddr; 1412 1413 T3_32BIT_REGISTER MemWindowBaseAddr; 1414 1415#ifdef NIC_CPU_VIEW 1416 /* These registers are ONLY visible to NIC CPU */ 1417 T3_32BIT_REGISTER PowerConsumed; 1418 T3_32BIT_REGISTER PowerDissipated; 1419#else /* NIC_CPU_VIEW */ 1420 T3_32BIT_REGISTER RegData; 1421 T3_32BIT_REGISTER MemWindowData; 1422#endif /* !NIC_CPU_VIEW */ 1423 1424 T3_32BIT_REGISTER ModeCtrl; 1425 1426 T3_32BIT_REGISTER MiscCfg; 1427 1428 T3_32BIT_REGISTER MiscLocalCtrl; 1429 1430 T3_32BIT_REGISTER Unused4; 1431 1432 /* NOTE: Big/Little-endian clarification needed. Are these register */ 1433 /* in big or little endian formate. */ 1434 T3_64BIT_REGISTER StdRingProdIdx; 1435 T3_64BIT_REGISTER RcvRetRingConIdx; 1436 T3_64BIT_REGISTER SndProdIdx; 1437 1438 T3_32BIT_REGISTER Unused5[2]; 1439 1440 T3_32BIT_REGISTER DualMacCtrl; 1441 #define T3_DUAL_MAC_CH_CTRL_MASK (BIT_1 | BIT_0) 1442 #define T3_DUAL_MAC_ID BIT_2 1443 1444 LM_UINT8 Unused6[68]; 1445 1446} T3_PCI_CONFIGURATION, *PT3_PCI_CONFIGURATION; 1447 1448#define PCIX_CMD_MAX_SPLIT_MASK 0x00700000 1449#define PCIX_CMD_MAX_SPLIT_SHL 20 1450#define PCIX_CMD_MAX_BURST_MASK 0x000c0000 1451#define PCIX_CMD_MAX_BURST_SHL 18 1452#define PCIX_CMD_MAX_BURST_CPIOB 2 1453 1454/******************************************************************************/ 1455/* Mac control registers. */ 1456/******************************************************************************/ 1457 1458typedef struct { 1459 /* MAC mode control. */ 1460 T3_32BIT_REGISTER Mode; 1461 #define MAC_MODE_GLOBAL_RESET BIT_0 1462 #define MAC_MODE_HALF_DUPLEX BIT_1 1463 #define MAC_MODE_PORT_MODE_MASK (BIT_2 | BIT_3) 1464 #define MAC_MODE_PORT_MODE_TBI (BIT_2 | BIT_3) 1465 #define MAC_MODE_PORT_MODE_GMII BIT_3 1466 #define MAC_MODE_PORT_MODE_MII BIT_2 1467 #define MAC_MODE_PORT_MODE_NONE BIT_NONE 1468 #define MAC_MODE_PORT_INTERNAL_LOOPBACK BIT_4 1469 #define MAC_MODE_TAGGED_MAC_CONTROL BIT_7 1470 #define MAC_MODE_TX_BURSTING BIT_8 1471 #define MAC_MODE_MAX_DEFER BIT_9 1472 #define MAC_MODE_LINK_POLARITY BIT_10 1473 #define MAC_MODE_ENABLE_RX_STATISTICS BIT_11 1474 #define MAC_MODE_CLEAR_RX_STATISTICS BIT_12 1475 #define MAC_MODE_FLUSH_RX_STATISTICS BIT_13 1476 #define MAC_MODE_ENABLE_TX_STATISTICS BIT_14 1477 #define MAC_MODE_CLEAR_TX_STATISTICS BIT_15 1478 #define MAC_MODE_FLUSH_TX_STATISTICS BIT_16 1479 #define MAC_MODE_SEND_CONFIGS BIT_17 1480 #define MAC_MODE_DETECT_MAGIC_PACKET_ENABLE BIT_18 1481 #define MAC_MODE_ACPI_POWER_ON_ENABLE BIT_19 1482 #define MAC_MODE_ENABLE_MIP BIT_20 1483 #define MAC_MODE_ENABLE_TDE BIT_21 1484 #define MAC_MODE_ENABLE_RDE BIT_22 1485 #define MAC_MODE_ENABLE_FHDE BIT_23 1486 1487 /* MAC status */ 1488 T3_32BIT_REGISTER Status; 1489 #define MAC_STATUS_PCS_SYNCED BIT_0 1490 #define MAC_STATUS_SIGNAL_DETECTED BIT_1 1491 #define MAC_STATUS_RECEIVING_CFG BIT_2 1492 #define MAC_STATUS_CFG_CHANGED BIT_3 1493 #define MAC_STATUS_SYNC_CHANGED BIT_4 1494 #define MAC_STATUS_PORT_DECODE_ERROR BIT_10 1495 #define MAC_STATUS_LINK_STATE_CHANGED BIT_12 1496 #define MAC_STATUS_MI_COMPLETION BIT_22 1497 #define MAC_STATUS_MI_INTERRUPT BIT_23 1498 #define MAC_STATUS_AP_ERROR BIT_24 1499 #define MAC_STATUS_ODI_ERROR BIT_25 1500 #define MAC_STATUS_RX_STATS_OVERRUN BIT_26 1501 #define MAC_STATUS_TX_STATS_OVERRUN BIT_27 1502 1503 /* Event Enable */ 1504 T3_32BIT_REGISTER MacEvent; 1505 #define MAC_EVENT_ENABLE_PORT_DECODE_ERR BIT_10 1506 #define MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN BIT_12 1507 #define MAC_EVENT_ENABLE_MI_COMPLETION BIT_22 1508 #define MAC_EVENT_ENABLE_MI_INTERRUPT BIT_23 1509 #define MAC_EVENT_ENABLE_AP_ERROR BIT_24 1510 #define MAC_EVENT_ENABLE_ODI_ERROR BIT_25 1511 #define MAC_EVENT_ENABLE_RX_STATS_OVERRUN BIT_26 1512 #define MAC_EVENT_ENABLE_TX_STATS_OVERRUN BIT_27 1513 1514 /* Led control. */ 1515 T3_32BIT_REGISTER LedCtrl; 1516 #define LED_CTRL_OVERRIDE_LINK_LED BIT_0 1517 #define LED_CTRL_1000MBPS_LED_ON BIT_1 1518 #define LED_CTRL_100MBPS_LED_ON BIT_2 1519 #define LED_CTRL_10MBPS_LED_ON BIT_3 1520 #define LED_CTRL_OVERRIDE_TRAFFIC_LED BIT_4 1521 #define LED_CTRL_BLINK_TRAFFIC_LED BIT_5 1522 #define LED_CTRL_TRAFFIC_LED BIT_6 1523 #define LED_CTRL_1000MBPS_LED_STATUS BIT_7 1524 #define LED_CTRL_100MBPS_LED_STATUS BIT_8 1525 #define LED_CTRL_10MBPS_LED_STATUS BIT_9 1526 #define LED_CTRL_TRAFFIC_LED_STATUS BIT_10 1527 #define LED_CTRL_MAC_MODE BIT_NONE 1528 #define LED_CTRL_PHY_MODE_1 BIT_11 1529 #define LED_CTRL_PHY_MODE_2 BIT_12 1530 #define LED_CTRL_SHASTA_MAC_MODE BIT_13 1531 #define LED_CTRL_SHARED_TRAFFIC_LINK BIT_14 1532 #define LED_CTRL_WIRELESS_COMBO BIT_15 1533 #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 1534 #define LED_CTRL_OVERRIDE_BLINK_PERIOD BIT_19 1535 #define LED_CTRL_OVERRIDE_BLINK_RATE BIT_31 1536 1537 /* MAC addresses. */ 1538 struct { 1539 T3_32BIT_REGISTER High; /* Upper 2 bytes. */ 1540 T3_32BIT_REGISTER Low; /* Lower 4 bytes. */ 1541 } MacAddr[4]; 1542 1543 /* ACPI Mbuf pointer. */ 1544 T3_32BIT_REGISTER AcpiMbufPtr; 1545 1546 /* ACPI Length and Offset. */ 1547 T3_32BIT_REGISTER AcpiLengthOffset; 1548 #define ACPI_LENGTH_MASK 0xffff 1549 #define ACPI_OFFSET_MASK 0x0fff0000 1550 #define ACPI_LENGTH(x) x 1551 #define ACPI_OFFSET(x) ((x) << 16) 1552 1553 /* Transmit random backoff. */ 1554 T3_32BIT_REGISTER TxBackoffSeed; 1555 #define MAC_TX_BACKOFF_SEED_MASK 0x3ff 1556 1557 /* Receive MTU */ 1558 T3_32BIT_REGISTER MtuSize; 1559 #define MAC_RX_MTU_MASK 0xffff 1560 1561 /* Gigabit PCS Test. */ 1562 T3_32BIT_REGISTER PcsTest; 1563 #define MAC_PCS_TEST_DATA_PATTERN_MASK 0x0fffff 1564 #define MAC_PCS_TEST_ENABLE BIT_20 1565 1566 /* Transmit Gigabit Auto-Negotiation. */ 1567 T3_32BIT_REGISTER TxAutoNeg; 1568 #define MAC_AN_TX_AN_DATA_MASK 0xffff 1569 1570 /* Receive Gigabit Auto-Negotiation. */ 1571 T3_32BIT_REGISTER RxAutoNeg; 1572 #define MAC_AN_RX_AN_DATA_MASK 0xffff 1573 1574 /* MI Communication. */ 1575 T3_32BIT_REGISTER MiCom; 1576 #define MI_COM_CMD_MASK (BIT_26 | BIT_27) 1577 #define MI_COM_CMD_WRITE BIT_26 1578 #define MI_COM_CMD_READ BIT_27 1579 #define MI_COM_READ_FAILED BIT_28 1580 #define MI_COM_START BIT_29 1581 #define MI_COM_BUSY BIT_29 1582 1583 #define MI_COM_PHY_ADDR_MASK 0x1f 1584 #define MI_COM_FIRST_PHY_ADDR_BIT 21 1585 1586 #define MI_COM_PHY_REG_ADDR_MASK 0x1f 1587 #define MI_COM_FIRST_PHY_REG_ADDR_BIT 16 1588 1589 #define MI_COM_PHY_DATA_MASK 0xffff 1590 1591 /* MI Status. */ 1592 T3_32BIT_REGISTER MiStatus; 1593 #define MI_STATUS_ENABLE_LINK_STATUS_ATTN BIT_0 1594 #define MI_STATUS_10MBPS BIT_1 1595 1596 /* MI Mode. */ 1597 T3_32BIT_REGISTER MiMode; 1598 #define MI_MODE_CLOCK_SPEED_10MHZ BIT_0 1599 #define MI_MODE_USE_SHORT_PREAMBLE BIT_1 1600 #define MI_MODE_AUTO_POLLING_ENABLE BIT_4 1601 #define MI_MODE_CORE_CLOCK_SPEED_62MHZ BIT_15 1602 1603 /* Auto-polling status. */ 1604 T3_32BIT_REGISTER AutoPollStatus; 1605 #define AUTO_POLL_ERROR BIT_0 1606 1607 /* Transmit MAC mode. */ 1608 T3_32BIT_REGISTER TxMode; 1609 #define TX_MODE_RESET BIT_0 1610 #define TX_MODE_ENABLE BIT_1 1611 #define TX_MODE_ENABLE_FLOW_CONTROL BIT_4 1612 #define TX_MODE_ENABLE_BIG_BACKOFF BIT_5 1613 #define TX_MODE_ENABLE_LONG_PAUSE BIT_6 1614 1615 /* Transmit MAC status. */ 1616 T3_32BIT_REGISTER TxStatus; 1617 #define TX_STATUS_RX_CURRENTLY_XOFFED BIT_0 1618 #define TX_STATUS_SENT_XOFF BIT_1 1619 #define TX_STATUS_SENT_XON BIT_2 1620 #define TX_STATUS_LINK_UP BIT_3 1621 #define TX_STATUS_ODI_UNDERRUN BIT_4 1622 #define TX_STATUS_ODI_OVERRUN BIT_5 1623 1624 /* Transmit MAC length. */ 1625 T3_32BIT_REGISTER TxLengths; 1626 #define TX_LEN_SLOT_TIME_MASK 0xff 1627 #define TX_LEN_IPG_MASK 0x0f00 1628 #define TX_LEN_IPG_CRS_MASK (BIT_12 | BIT_13) 1629 1630 /* Receive MAC mode. */ 1631 T3_32BIT_REGISTER RxMode; 1632 #define RX_MODE_RESET BIT_0 1633 #define RX_MODE_ENABLE BIT_1 1634 #define RX_MODE_ENABLE_FLOW_CONTROL BIT_2 1635 #define RX_MODE_KEEP_MAC_CONTROL BIT_3 1636 #define RX_MODE_KEEP_PAUSE BIT_4 1637 #define RX_MODE_ACCEPT_OVERSIZED BIT_5 1638 #define RX_MODE_ACCEPT_RUNTS BIT_6 1639 #define RX_MODE_LENGTH_CHECK BIT_7 1640 #define RX_MODE_PROMISCUOUS_MODE BIT_8 1641 #define RX_MODE_NO_CRC_CHECK BIT_9 1642 #define RX_MODE_KEEP_VLAN_TAG BIT_10 1643 1644 /* Receive MAC status. */ 1645 T3_32BIT_REGISTER RxStatus; 1646 #define RX_STATUS_REMOTE_TRANSMITTER_XOFFED BIT_0 1647 #define RX_STATUS_XOFF_RECEIVED BIT_1 1648 #define RX_STATUS_XON_RECEIVED BIT_2 1649 1650 /* Hash registers. */ 1651 T3_32BIT_REGISTER HashReg[4]; 1652 1653 /* Receive placement rules registers. */ 1654 struct { 1655 T3_32BIT_REGISTER Rule; 1656 T3_32BIT_REGISTER Value; 1657 } RcvRules[16]; 1658 1659 #define RCV_DISABLE_RULE_MASK 0x7fffffff 1660 1661 #define RCV_RULE1_REJECT_BROADCAST_IDX 0x00 1662 #define REJECT_BROADCAST_RULE1_RULE 0xc2000000 1663 #define REJECT_BROADCAST_RULE1_VALUE 0xffffffff 1664 1665 #define RCV_RULE2_REJECT_BROADCAST_IDX 0x01 1666 #define REJECT_BROADCAST_RULE2_RULE 0x86000004 1667 #define REJECT_BROADCAST_RULE2_VALUE 0xffffffff 1668 1669#if INCLUDE_5701_AX_FIX 1670 #define RCV_LAST_RULE_IDX 0x04 1671#else 1672 #define RCV_LAST_RULE_IDX 0x02 1673#endif 1674 1675 T3_32BIT_REGISTER RcvRuleCfg; 1676 #define RX_RULE_DEFAULT_CLASS (1 << 3) 1677 1678 T3_32BIT_REGISTER LowWaterMarkMaxRxFrame; 1679 1680 LM_UINT8 Reserved1[24]; 1681 1682 T3_32BIT_REGISTER HashRegU[4]; 1683 1684 struct { 1685 T3_32BIT_REGISTER High; 1686 T3_32BIT_REGISTER Low; 1687 } MacAddrExt[12]; 1688 1689 T3_32BIT_REGISTER SerdesCfg; 1690 T3_32BIT_REGISTER SerdesStatus; 1691 1692 LM_UINT8 Reserved2[24]; 1693 1694 T3_32BIT_REGISTER SgDigControl; 1695 T3_32BIT_REGISTER SgDigStatus; 1696 1697 LM_UINT8 Reserved3[72]; 1698 1699 volatile LM_UINT8 TxMacState[16]; 1700 volatile LM_UINT8 RxMacState[20]; 1701 1702 LM_UINT8 Reserved4[476]; 1703 1704 T3_32BIT_REGISTER ifHCOutOctets; 1705 T3_32BIT_REGISTER Reserved5; 1706 T3_32BIT_REGISTER etherStatsCollisions; 1707 T3_32BIT_REGISTER outXonSent; 1708 T3_32BIT_REGISTER outXoffSent; 1709 T3_32BIT_REGISTER Reserved6; 1710 T3_32BIT_REGISTER dot3StatsInternalMacTransmitErrors; 1711 T3_32BIT_REGISTER dot3StatsSingleCollisionFrames; 1712 T3_32BIT_REGISTER dot3StatsMultipleCollisionFrames; 1713 T3_32BIT_REGISTER dot3StatsDeferredTransmissions; 1714 T3_32BIT_REGISTER Reserved7; 1715 T3_32BIT_REGISTER dot3StatsExcessiveCollisions; 1716 T3_32BIT_REGISTER dot3StatsLateCollisions; 1717 T3_32BIT_REGISTER Reserved8[14]; 1718 T3_32BIT_REGISTER ifHCOutUcastPkts; 1719 T3_32BIT_REGISTER ifHCOutMulticastPkts; 1720 T3_32BIT_REGISTER ifHCOutBroadcastPkts; 1721 T3_32BIT_REGISTER Reserved9[2]; 1722 T3_32BIT_REGISTER ifHCInOctets; 1723 T3_32BIT_REGISTER Reserved10; 1724 T3_32BIT_REGISTER etherStatsFragments; 1725 T3_32BIT_REGISTER ifHCInUcastPkts; 1726 T3_32BIT_REGISTER ifHCInMulticastPkts; 1727 T3_32BIT_REGISTER ifHCInBroadcastPkts; 1728 T3_32BIT_REGISTER dot3StatsFCSErrors; 1729 T3_32BIT_REGISTER dot3StatsAlignmentErrors; 1730 T3_32BIT_REGISTER xonPauseFramesReceived; 1731 T3_32BIT_REGISTER xoffPauseFramesReceived; 1732 T3_32BIT_REGISTER macControlFramesReceived; 1733 T3_32BIT_REGISTER xoffStateEntered; 1734 T3_32BIT_REGISTER dot3StatsFramesTooLong; 1735 T3_32BIT_REGISTER etherStatsJabbers; 1736 T3_32BIT_REGISTER etherStatsUndersizePkts; 1737 1738 T3_32BIT_REGISTER Reserved11[209]; 1739 1740} T3_MAC_CONTROL, *PT3_MAC_CONTROL; 1741 1742 1743 1744/******************************************************************************/ 1745/* Send data initiator control registers. */ 1746/******************************************************************************/ 1747 1748typedef struct { 1749 T3_32BIT_REGISTER Mode; 1750 #define T3_SND_DATA_IN_MODE_RESET BIT_0 1751 #define T3_SND_DATA_IN_MODE_ENABLE BIT_1 1752 #define T3_SND_DATA_IN_MODE_STATS_OFLW_ATTN_ENABLE BIT_2 1753 1754 T3_32BIT_REGISTER Status; 1755 #define T3_SND_DATA_IN_STATUS_STATS_OFLW_ATTN BIT_2 1756 1757 T3_32BIT_REGISTER StatsCtrl; 1758 #define T3_SND_DATA_IN_STATS_CTRL_ENABLE BIT_0 1759 #define T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE BIT_1 1760 #define T3_SND_DATA_IN_STATS_CTRL_CLEAR BIT_2 1761 #define T3_SND_DATA_IN_STATS_CTRL_FLUSH BIT_3 1762 #define T3_SND_DATA_IN_STATS_CTRL_FORCE_ZERO BIT_4 1763 1764 T3_32BIT_REGISTER StatsEnableMask; 1765 1766 T3_32BIT_REGISTER StatsIncMask; 1767 1768 LM_UINT8 Reserved[108]; 1769 1770 T3_32BIT_REGISTER ClassOfServCnt[16]; 1771 T3_32BIT_REGISTER DmaReadQFullCnt; 1772 T3_32BIT_REGISTER DmaPriorityReadQFullCnt; 1773 T3_32BIT_REGISTER SdcQFullCnt; 1774 1775 T3_32BIT_REGISTER NicRingSetSendProdIdxCnt; 1776 T3_32BIT_REGISTER StatusUpdatedCnt; 1777 T3_32BIT_REGISTER InterruptsCnt; 1778 T3_32BIT_REGISTER AvoidInterruptsCnt; 1779 T3_32BIT_REGISTER SendThresholdHitCnt; 1780 1781 /* Unused space. */ 1782 LM_UINT8 Unused[800]; 1783} T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR; 1784 1785 1786 1787/******************************************************************************/ 1788/* Send data completion control registers. */ 1789/******************************************************************************/ 1790 1791typedef struct { 1792 T3_32BIT_REGISTER Mode; 1793 #define SND_DATA_COMP_MODE_RESET BIT_0 1794 #define SND_DATA_COMP_MODE_ENABLE BIT_1 1795 1796 /* Unused space. */ 1797 LM_UINT8 Unused[1020]; 1798} T3_SEND_DATA_COMPLETION, *PT3_SEND_DATA_COMPLETION; 1799 1800 1801 1802/******************************************************************************/ 1803/* Send BD Ring Selector Control Registers. */ 1804/******************************************************************************/ 1805 1806typedef struct { 1807 T3_32BIT_REGISTER Mode; 1808 #define SND_BD_SEL_MODE_RESET BIT_0 1809 #define SND_BD_SEL_MODE_ENABLE BIT_1 1810 #define SND_BD_SEL_MODE_ATTN_ENABLE BIT_2 1811 1812 T3_32BIT_REGISTER Status; 1813 #define SND_BD_SEL_STATUS_ERROR_ATTN BIT_2 1814 1815 T3_32BIT_REGISTER HwDiag; 1816 1817 /* Unused space. */ 1818 LM_UINT8 Unused1[52]; 1819 1820 /* Send BD Ring Selector Local NIC Send BD Consumer Index. */ 1821 T3_32BIT_REGISTER NicSendBdSelConIdx[16]; 1822 1823 /* Unused space. */ 1824 LM_UINT8 Unused2[896]; 1825} T3_SEND_BD_SELECTOR, *PT3_SEND_BD_SELECTOR; 1826 1827 1828 1829/******************************************************************************/ 1830/* Send BD initiator control registers. */ 1831/******************************************************************************/ 1832 1833typedef struct { 1834 T3_32BIT_REGISTER Mode; 1835 #define SND_BD_IN_MODE_RESET BIT_0 1836 #define SND_BD_IN_MODE_ENABLE BIT_1 1837 #define SND_BD_IN_MODE_ATTN_ENABLE BIT_2 1838 1839 T3_32BIT_REGISTER Status; 1840 #define SND_BD_IN_STATUS_ERROR_ATTN BIT_2 1841 1842 /* Send BD initiator local NIC send BD producer index. */ 1843 T3_32BIT_REGISTER NicSendBdInProdIdx[16]; 1844 1845 /* Unused space. */ 1846 LM_UINT8 Unused2[952]; 1847} T3_SEND_BD_INITIATOR, *PT3_SEND_BD_INITIATOR; 1848 1849 1850 1851/******************************************************************************/ 1852/* Send BD Completion Control. */ 1853/******************************************************************************/ 1854 1855typedef struct { 1856 T3_32BIT_REGISTER Mode; 1857 #define SND_BD_COMP_MODE_RESET BIT_0 1858 #define SND_BD_COMP_MODE_ENABLE BIT_1 1859 #define SND_BD_COMP_MODE_ATTN_ENABLE BIT_2 1860 1861 /* Unused space. */ 1862 LM_UINT8 Unused2[1020]; 1863} T3_SEND_BD_COMPLETION, *PT3_SEND_BD_COMPLETION; 1864 1865 1866 1867/******************************************************************************/ 1868/* Receive list placement control registers. */ 1869/******************************************************************************/ 1870 1871typedef struct { 1872 /* Mode. */ 1873 T3_32BIT_REGISTER Mode; 1874 #define RCV_LIST_PLMT_MODE_RESET BIT_0 1875 #define RCV_LIST_PLMT_MODE_ENABLE BIT_1 1876 #define RCV_LIST_PLMT_MODE_CLASS0_ATTN_ENABLE BIT_2 1877 #define RCV_LIST_PLMT_MODE_MAPPING_OOR_ATTN_ENABLE BIT_3 1878 #define RCV_LIST_PLMT_MODE_STATS_OFLOW_ATTN_ENABLE BIT_4 1879 1880 /* Status. */ 1881 T3_32BIT_REGISTER Status; 1882 #define RCV_LIST_PLMT_STATUS_CLASS0_ATTN BIT_2 1883 #define RCV_LIST_PLMT_STATUS_MAPPING_ATTN BIT_3 1884 #define RCV_LIST_PLMT_STATUS_STATS_OFLOW_ATTN BIT_4 1885 1886 /* Receive selector list lock register. */ 1887 T3_32BIT_REGISTER Lock; 1888 #define RCV_LIST_SEL_LOCK_REQUEST_MASK 0xffff 1889 #define RCV_LIST_SEL_LOCK_GRANT_MASK 0xffff0000 1890 1891 /* Selector non-empty bits. */ 1892 T3_32BIT_REGISTER NonEmptyBits; 1893 #define RCV_LIST_SEL_NON_EMPTY_MASK 0xffff 1894 1895 /* Receive list placement configuration register. */ 1896 T3_32BIT_REGISTER Config; 1897 1898 /* Receive List Placement statistics Control. */ 1899 T3_32BIT_REGISTER StatsCtrl; 1900#define RCV_LIST_STATS_ENABLE BIT_0 1901#define RCV_LIST_STATS_FAST_UPDATE BIT_1 1902 1903 /* Receive List Placement statistics Enable Mask. */ 1904 T3_32BIT_REGISTER StatsEnableMask; 1905 #define T3_DISABLE_LONG_BURST_READ_DYN_FIX BIT_22 1906 1907 /* Receive List Placement statistics Increment Mask. */ 1908 T3_32BIT_REGISTER StatsIncMask; 1909 1910 /* Unused space. */ 1911 LM_UINT8 Unused1[224]; 1912 1913 struct { 1914 T3_32BIT_REGISTER Head; 1915 T3_32BIT_REGISTER Tail; 1916 T3_32BIT_REGISTER Count; 1917 1918 /* Unused space. */ 1919 LM_UINT8 Unused[4]; 1920 } RcvSelectorList[16]; 1921 1922 /* Local statistics counter. */ 1923 T3_32BIT_REGISTER ClassOfServCnt[16]; 1924 1925 T3_32BIT_REGISTER DropDueToFilterCnt; 1926 T3_32BIT_REGISTER DmaWriteQFullCnt; 1927 T3_32BIT_REGISTER DmaHighPriorityWriteQFullCnt; 1928 T3_32BIT_REGISTER NoMoreReceiveBdCnt; 1929 T3_32BIT_REGISTER IfInDiscardsCnt; 1930 T3_32BIT_REGISTER IfInErrorsCnt; 1931 T3_32BIT_REGISTER RcvThresholdHitCnt; 1932 1933 /* Another unused space. */ 1934 LM_UINT8 Unused2[420]; 1935} T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT; 1936 1937 1938 1939/******************************************************************************/ 1940/* Receive Data and Receive BD Initiator Control. */ 1941/******************************************************************************/ 1942 1943typedef struct { 1944 /* Mode. */ 1945 T3_32BIT_REGISTER Mode; 1946 #define RCV_DATA_BD_IN_MODE_RESET BIT_0 1947 #define RCV_DATA_BD_IN_MODE_ENABLE BIT_1 1948 #define RCV_DATA_BD_IN_MODE_JUMBO_BD_NEEDED BIT_2 1949 #define RCV_DATA_BD_IN_MODE_FRAME_TOO_BIG BIT_3 1950 #define RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE BIT_4 1951 1952 /* Status. */ 1953 T3_32BIT_REGISTER Status; 1954 #define RCV_DATA_BD_IN_STATUS_JUMBO_BD_NEEDED BIT_2 1955 #define RCV_DATA_BD_IN_STATUS_FRAME_TOO_BIG BIT_3 1956 #define RCV_DATA_BD_IN_STATUS_INVALID_RING_SIZE BIT_4 1957 1958 /* Split frame minium size. */ 1959 T3_32BIT_REGISTER SplitFrameMinSize; 1960 1961 /* Unused space. */ 1962 LM_UINT8 Unused1[0x2440-0x240c]; 1963 1964 /* Receive RCBs. */ 1965 T3_RCB JumboRcvRcb; 1966 T3_RCB StdRcvRcb; 1967 T3_RCB MiniRcvRcb; 1968 1969 /* Receive Data and Receive BD Ring Initiator Local NIC Receive */ 1970 /* BD Consumber Index. */ 1971 T3_32BIT_REGISTER NicJumboConIdx; 1972 T3_32BIT_REGISTER NicStdConIdx; 1973 T3_32BIT_REGISTER NicMiniConIdx; 1974 1975 /* Unused space. */ 1976 LM_UINT8 Unused2[4]; 1977 1978 /* Receive Data and Receive BD Initiator Local Receive Return ProdIdx. */ 1979 T3_32BIT_REGISTER RcvDataBdProdIdx[16]; 1980 1981 /* Receive Data and Receive BD Initiator Hardware Diagnostic. */ 1982 T3_32BIT_REGISTER HwDiag; 1983 1984 /* Unused space. */ 1985 LM_UINT8 Unused3[828]; 1986} T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR; 1987 1988 1989 1990/******************************************************************************/ 1991/* Receive Data Completion Control Registes. */ 1992/******************************************************************************/ 1993 1994typedef struct { 1995 T3_32BIT_REGISTER Mode; 1996 #define RCV_DATA_COMP_MODE_RESET BIT_0 1997 #define RCV_DATA_COMP_MODE_ENABLE BIT_1 1998 #define RCV_DATA_COMP_MODE_ATTN_ENABLE BIT_2 1999 2000 /* Unused spaced. */ 2001 LM_UINT8 Unused[1020]; 2002} T3_RCV_DATA_COMPLETION, *PT3_RCV_DATA_COMPLETION; 2003 2004 2005 2006/******************************************************************************/ 2007/* Receive BD Initiator Control. */ 2008/******************************************************************************/ 2009 2010typedef struct { 2011 T3_32BIT_REGISTER Mode; 2012 #define RCV_BD_IN_MODE_RESET BIT_0 2013 #define RCV_BD_IN_MODE_ENABLE BIT_1 2014 #define RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE BIT_2 2015 2016 T3_32BIT_REGISTER Status; 2017 #define RCV_BD_IN_STATUS_BD_IN_DIABLED_RCB_ATTN BIT_2 2018 2019 T3_32BIT_REGISTER NicJumboRcvProdIdx; 2020 T3_32BIT_REGISTER NicStdRcvProdIdx; 2021 T3_32BIT_REGISTER NicMiniRcvProdIdx; 2022 2023 T3_32BIT_REGISTER MiniRcvThreshold; 2024 T3_32BIT_REGISTER StdRcvThreshold; 2025 T3_32BIT_REGISTER JumboRcvThreshold; 2026 2027 /* Unused space. */ 2028 LM_UINT8 Unused[992]; 2029} T3_RCV_BD_INITIATOR, *PT3_RCV_BD_INITIATOR; 2030 2031 2032 2033/******************************************************************************/ 2034/* Receive BD Completion Control Registers. */ 2035/******************************************************************************/ 2036 2037typedef struct { 2038 T3_32BIT_REGISTER Mode; 2039 #define RCV_BD_COMP_MODE_RESET BIT_0 2040 #define RCV_BD_COMP_MODE_ENABLE BIT_1 2041 #define RCV_BD_COMP_MODE_ATTN_ENABLE BIT_2 2042 2043 T3_32BIT_REGISTER Status; 2044 #define RCV_BD_COMP_STATUS_ERROR_ATTN BIT_2 2045 2046 T3_32BIT_REGISTER NicJumboRcvBdProdIdx; 2047 T3_32BIT_REGISTER NicStdRcvBdProdIdx; 2048 T3_32BIT_REGISTER NicMiniRcvBdProdIdx; 2049 2050 /* Unused space. */ 2051 LM_UINT8 Unused[1004]; 2052} T3_RCV_BD_COMPLETION, *PT3_RCV_BD_COMPLETION; 2053 2054 2055 2056/******************************************************************************/ 2057/* Receive list selector control register. */ 2058/******************************************************************************/ 2059 2060typedef struct { 2061 T3_32BIT_REGISTER Mode; 2062 #define RCV_LIST_SEL_MODE_RESET BIT_0 2063 #define RCV_LIST_SEL_MODE_ENABLE BIT_1 2064 #define RCV_LIST_SEL_MODE_ATTN_ENABLE BIT_2 2065 2066 T3_32BIT_REGISTER Status; 2067 #define RCV_LIST_SEL_STATUS_ERROR_ATTN BIT_2 2068 2069 /* Unused space. */ 2070 LM_UINT8 Unused[1016]; 2071} T3_RCV_LIST_SELECTOR, *PT3_RCV_LIST_SELECTOR; 2072 2073 2074 2075/******************************************************************************/ 2076/* Mbuf cluster free registers. */ 2077/******************************************************************************/ 2078 2079typedef struct { 2080 T3_32BIT_REGISTER Mode; 2081#define MBUF_CLUSTER_FREE_MODE_RESET BIT_0 2082#define MBUF_CLUSTER_FREE_MODE_ENABLE BIT_1 2083 2084 T3_32BIT_REGISTER Status; 2085 2086 /* Unused space. */ 2087 LM_UINT8 Unused[1016]; 2088} T3_MBUF_CLUSTER_FREE, *PT3_MBUF_CLUSTER_FREE; 2089 2090 2091 2092/******************************************************************************/ 2093/* Host coalescing control registers. */ 2094/******************************************************************************/ 2095 2096typedef struct { 2097 /* Mode. */ 2098 T3_32BIT_REGISTER Mode; 2099 #define HOST_COALESCE_RESET BIT_0 2100 #define HOST_COALESCE_ENABLE BIT_1 2101 #define HOST_COALESCE_ATTN BIT_2 2102 #define HOST_COALESCE_NOW BIT_3 2103 #define HOST_COALESCE_FULL_STATUS_MODE BIT_NONE 2104 #define HOST_COALESCE_64_BYTE_STATUS_MODE BIT_7 2105 #define HOST_COALESCE_32_BYTE_STATUS_MODE BIT_8 2106 #define HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT BIT_9 2107 #define HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT BIT_10 2108 #define HOST_COALESCE_NO_INT_ON_COALESCE_NOW_MODE BIT_11 2109 #define HOST_COALESCE_NO_INT_ON_FORCE_DMAD_MODE BIT_12 2110 2111 /* Status. */ 2112 T3_32BIT_REGISTER Status; 2113 #define HOST_COALESCE_ERROR_ATTN BIT_2 2114 2115 /* Receive coalescing ticks. */ 2116 T3_32BIT_REGISTER RxCoalescingTicks; 2117 2118 /* Send coalescing ticks. */ 2119 T3_32BIT_REGISTER TxCoalescingTicks; 2120 2121 /* Receive max coalesced frames. */ 2122 T3_32BIT_REGISTER RxMaxCoalescedFrames; 2123 2124 /* Send max coalesced frames. */ 2125 T3_32BIT_REGISTER TxMaxCoalescedFrames; 2126 2127 /* Receive coalescing ticks during interrupt. */ 2128 T3_32BIT_REGISTER RxCoalescedTickDuringInt; 2129 2130 /* Send coalescing ticks during interrupt. */ 2131 T3_32BIT_REGISTER TxCoalescedTickDuringInt; 2132 2133 /* Receive max coalesced frames during interrupt. */ 2134 T3_32BIT_REGISTER RxMaxCoalescedFramesDuringInt; 2135 2136 /* Send max coalesced frames during interrupt. */ 2137 T3_32BIT_REGISTER TxMaxCoalescedFramesDuringInt; 2138 2139 /* Statistics tick. */ 2140 T3_32BIT_REGISTER StatsCoalescingTicks; 2141 2142 /* Unused space. */ 2143 LM_UINT8 Unused2[4]; 2144 2145 /* Statistics host address. */ 2146 T3_64BIT_REGISTER StatsBlkHostAddr; 2147 2148 /* Status block host address.*/ 2149 T3_64BIT_REGISTER StatusBlkHostAddr; 2150 2151 /* Statistics NIC address. */ 2152 T3_32BIT_REGISTER StatsBlkNicAddr; 2153 2154 /* Statust block NIC address. */ 2155 T3_32BIT_REGISTER StatusBlkNicAddr; 2156 2157 /* Flow attention registers. */ 2158 T3_32BIT_REGISTER FlowAttn; 2159 2160 /* Unused space. */ 2161 LM_UINT8 Unused3[4]; 2162 2163 T3_32BIT_REGISTER NicJumboRcvBdConIdx; 2164 T3_32BIT_REGISTER NicStdRcvBdConIdx; 2165 T3_32BIT_REGISTER NicMiniRcvBdConIdx; 2166 2167 /* Unused space. */ 2168 LM_UINT8 Unused4[36]; 2169 2170 T3_32BIT_REGISTER NicRetProdIdx[16]; 2171 T3_32BIT_REGISTER NicSndBdConIdx[16]; 2172 2173 /* Unused space. */ 2174 LM_UINT8 Unused5[768]; 2175} T3_HOST_COALESCING, *PT3_HOST_COALESCING; 2176 2177 2178 2179/******************************************************************************/ 2180/* Memory arbiter registers. */ 2181/******************************************************************************/ 2182 2183typedef struct { 2184 T3_32BIT_REGISTER Mode; 2185#define T3_MEM_ARBITER_MODE_RESET BIT_0 2186#define T3_MEM_ARBITER_MODE_ENABLE BIT_1 2187 2188 T3_32BIT_REGISTER Status; 2189 2190 T3_32BIT_REGISTER ArbTrapAddrLow; 2191 T3_32BIT_REGISTER ArbTrapAddrHigh; 2192 2193 /* Unused space. */ 2194 LM_UINT8 Unused[1008]; 2195} T3_MEM_ARBITER, *PT3_MEM_ARBITER; 2196 2197 2198 2199/******************************************************************************/ 2200/* Buffer manager control register. */ 2201/******************************************************************************/ 2202 2203typedef struct { 2204 T3_32BIT_REGISTER Mode; 2205 #define BUFMGR_MODE_RESET BIT_0 2206 #define BUFMGR_MODE_ENABLE BIT_1 2207 #define BUFMGR_MODE_ATTN_ENABLE BIT_2 2208 #define BUFMGR_MODE_BM_TEST BIT_3 2209 #define BUFMGR_MODE_MBUF_LOW_ATTN_ENABLE BIT_4 2210 2211 T3_32BIT_REGISTER Status; 2212 #define BUFMGR_STATUS_ERROR BIT_2 2213 #define BUFMGR_STATUS_MBUF_LOW BIT_4 2214 2215 T3_32BIT_REGISTER MbufPoolAddr; 2216 T3_32BIT_REGISTER MbufPoolSize; 2217 T3_32BIT_REGISTER MbufReadDmaLowWaterMark; 2218 T3_32BIT_REGISTER MbufMacRxLowWaterMark; 2219 T3_32BIT_REGISTER MbufHighWaterMark; 2220 2221 T3_32BIT_REGISTER RxCpuMbufAllocReq; 2222 #define BUFMGR_MBUF_ALLOC_BIT BIT_31 2223 T3_32BIT_REGISTER RxCpuMbufAllocResp; 2224 T3_32BIT_REGISTER TxCpuMbufAllocReq; 2225 T3_32BIT_REGISTER TxCpuMbufAllocResp; 2226 2227 T3_32BIT_REGISTER DmaDescPoolAddr; 2228 T3_32BIT_REGISTER DmaDescPoolSize; 2229 T3_32BIT_REGISTER DmaLowWaterMark; 2230 T3_32BIT_REGISTER DmaHighWaterMark; 2231 2232 T3_32BIT_REGISTER RxCpuDmaAllocReq; 2233 T3_32BIT_REGISTER RxCpuDmaAllocResp; 2234 T3_32BIT_REGISTER TxCpuDmaAllocReq; 2235 T3_32BIT_REGISTER TxCpuDmaAllocResp; 2236 2237 T3_32BIT_REGISTER Hwdiag[3]; 2238 2239 /* Unused space. */ 2240 LM_UINT8 Unused[936]; 2241} T3_BUFFER_MANAGER, *PT3_BUFFER_MANAGER; 2242 2243 2244 2245/******************************************************************************/ 2246/* Read DMA control registers. */ 2247/******************************************************************************/ 2248 2249typedef struct { 2250 T3_32BIT_REGISTER Mode; 2251 #define DMA_READ_MODE_RESET BIT_0 2252 #define DMA_READ_MODE_ENABLE BIT_1 2253 #define DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2 2254 #define DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3 2255 #define DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4 2256 #define DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5 2257 #define DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6 2258 #define DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7 2259 #define DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8 2260 #define DMA_READ_MODE_LONG_READ_ATTN_ENABLE BIT_9 2261 #define DMA_READ_MODE_MULTI_SPLIT_ENABLE BIT_11 2262 #define DMA_READ_MODE_MULTI_SPLIT_RESET BIT_12 2263 #define DMA_READ_MODE_FIFO_SIZE_128 BIT_17 2264 #define DMA_READ_MODE_FIFO_LONG_BURST (BIT_16 | BIT_17) 2265 2266 T3_32BIT_REGISTER Status; 2267 #define DMA_READ_STATUS_TARGET_ABORT_ATTN BIT_2 2268 #define DMA_READ_STATUS_MASTER_ABORT_ATTN BIT_3 2269 #define DMA_READ_STATUS_PARITY_ERROR_ATTN BIT_4 2270 #define DMA_READ_STATUS_ADDR_OVERFLOW_ATTN BIT_5 2271 #define DMA_READ_STATUS_FIFO_OVERRUN_ATTN BIT_6 2272 #define DMA_READ_STATUS_FIFO_UNDERRUN_ATTN BIT_7 2273 #define DMA_READ_STATUS_FIFO_OVERREAD_ATTN BIT_8 2274 #define DMA_READ_STATUS_LONG_READ_ATTN BIT_9 2275 2276 /* Unused space. */ 2277 LM_UINT8 Unused[1016]; 2278} T3_DMA_READ, *PT3_DMA_READ; 2279 2280typedef union T3_CPU 2281{ 2282 struct 2283 { 2284 T3_32BIT_REGISTER mode; 2285 #define CPU_MODE_HALT BIT_10 2286 #define CPU_MODE_RESET BIT_0 2287 T3_32BIT_REGISTER state; 2288 T3_32BIT_REGISTER EventMask; 2289 T3_32BIT_REGISTER reserved1[4]; 2290 T3_32BIT_REGISTER PC; 2291 T3_32BIT_REGISTER Instruction; 2292 T3_32BIT_REGISTER SpadUnderflow; 2293 T3_32BIT_REGISTER WatchdogClear; 2294 T3_32BIT_REGISTER WatchdogVector; 2295 T3_32BIT_REGISTER WatchdogSavedPC; 2296 T3_32BIT_REGISTER HardwareBp; 2297 T3_32BIT_REGISTER reserved2[3]; 2298 T3_32BIT_REGISTER WatchdogSavedState; 2299 T3_32BIT_REGISTER LastBrchAddr; 2300 T3_32BIT_REGISTER SpadUnderflowSet; 2301 T3_32BIT_REGISTER reserved3[(0x200-0x50)/4]; 2302 T3_32BIT_REGISTER Regs[32]; 2303 T3_32BIT_REGISTER reserved4[(0x400-0x280)/4]; 2304 }reg; 2305}T3_CPU, *PT3_CPU; 2306 2307/******************************************************************************/ 2308/* Write DMA control registers. */ 2309/******************************************************************************/ 2310 2311typedef struct { 2312 T3_32BIT_REGISTER Mode; 2313 #define DMA_WRITE_MODE_RESET BIT_0 2314 #define DMA_WRITE_MODE_ENABLE BIT_1 2315 #define DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2 2316 #define DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3 2317 #define DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4 2318 #define DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5 2319 #define DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6 2320 #define DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7 2321 #define DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8 2322 #define DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE BIT_9 2323 #define DMA_WRITE_MODE_RECEIVE_ACCELERATE BIT_10 2324 2325 T3_32BIT_REGISTER Status; 2326 #define DMA_WRITE_STATUS_TARGET_ABORT_ATTN BIT_2 2327 #define DMA_WRITE_STATUS_MASTER_ABORT_ATTN BIT_3 2328 #define DMA_WRITE_STATUS_PARITY_ERROR_ATTN BIT_4 2329 #define DMA_WRITE_STATUS_ADDR_OVERFLOW_ATTN BIT_5 2330 #define DMA_WRITE_STATUS_FIFO_OVERRUN_ATTN BIT_6 2331 #define DMA_WRITE_STATUS_FIFO_UNDERRUN_ATTN BIT_7 2332 #define DMA_WRITE_STATUS_FIFO_OVERREAD_ATTN BIT_8 2333 #define DMA_WRITE_STATUS_LONG_READ_ATTN BIT_9 2334 2335 /* Unused space. */ 2336 LM_UINT8 Unused[1016]; 2337} T3_DMA_WRITE, *PT3_DMA_WRITE; 2338 2339 2340 2341/******************************************************************************/ 2342/* Mailbox registers. */ 2343/******************************************************************************/ 2344 2345typedef struct { 2346 /* Interrupt mailbox registers. */ 2347 T3_64BIT_REGISTER Interrupt[4]; 2348 2349 /* General mailbox registers. */ 2350 T3_64BIT_REGISTER General[8]; 2351 2352 /* Reload statistics mailbox. */ 2353 T3_64BIT_REGISTER ReloadStat; 2354 2355 /* Receive BD ring producer index registers. */ 2356 T3_64BIT_REGISTER RcvStdProdIdx; 2357 T3_64BIT_REGISTER RcvJumboProdIdx; 2358 T3_64BIT_REGISTER RcvMiniProdIdx; 2359 2360 /* Receive return ring consumer index registers. */ 2361 T3_64BIT_REGISTER RcvRetConIdx[16]; 2362 2363 /* Send BD ring host producer index registers. */ 2364 T3_64BIT_REGISTER SendHostProdIdx[16]; 2365 2366 /* Send BD ring nic producer index registers. */ 2367 T3_64BIT_REGISTER SendNicProdIdx[16]; 2368}T3_MAILBOX, *PT3_MAILBOX; 2369 2370typedef struct { 2371 T3_MAILBOX Mailbox; 2372 2373 /* Priority mailbox registers. */ 2374 T3_32BIT_REGISTER HighPriorityEventVector; 2375 T3_32BIT_REGISTER HighPriorityEventMask; 2376 T3_32BIT_REGISTER LowPriorityEventVector; 2377 T3_32BIT_REGISTER LowPriorityEventMask; 2378 2379 /* Unused space. */ 2380 LM_UINT8 Unused[496]; 2381} T3_GRC_MAILBOX, *PT3_GRC_MAILBOX; 2382 2383 2384/******************************************************************************/ 2385/* Flow through queues. */ 2386/******************************************************************************/ 2387 2388typedef struct { 2389 T3_32BIT_REGISTER Reset; 2390 2391 LM_UINT8 Unused[12]; 2392 2393 T3_32BIT_REGISTER DmaNormalReadFtqCtrl; 2394 T3_32BIT_REGISTER DmaNormalReadFtqFullCnt; 2395 T3_32BIT_REGISTER DmaNormalReadFtqFifoEnqueueDequeue; 2396 T3_32BIT_REGISTER DmaNormalReadFtqFifoWritePeek; 2397 2398 T3_32BIT_REGISTER DmaHighReadFtqCtrl; 2399 T3_32BIT_REGISTER DmaHighReadFtqFullCnt; 2400 T3_32BIT_REGISTER DmaHighReadFtqFifoEnqueueDequeue; 2401 T3_32BIT_REGISTER DmaHighReadFtqFifoWritePeek; 2402 2403 T3_32BIT_REGISTER DmaCompDiscardFtqCtrl; 2404 T3_32BIT_REGISTER DmaCompDiscardFtqFullCnt; 2405 T3_32BIT_REGISTER DmaCompDiscardFtqFifoEnqueueDequeue; 2406 T3_32BIT_REGISTER DmaCompDiscardFtqFifoWritePeek; 2407 2408 T3_32BIT_REGISTER SendBdCompFtqCtrl; 2409 T3_32BIT_REGISTER SendBdCompFtqFullCnt; 2410 T3_32BIT_REGISTER SendBdCompFtqFifoEnqueueDequeue; 2411 T3_32BIT_REGISTER SendBdCompFtqFifoWritePeek; 2412 2413 T3_32BIT_REGISTER SendDataInitiatorFtqCtrl; 2414 T3_32BIT_REGISTER SendDataInitiatorFtqFullCnt; 2415 T3_32BIT_REGISTER SendDataInitiatorFtqFifoEnqueueDequeue; 2416 T3_32BIT_REGISTER SendDataInitiatorFtqFifoWritePeek; 2417 2418 T3_32BIT_REGISTER DmaNormalWriteFtqCtrl; 2419 T3_32BIT_REGISTER DmaNormalWriteFtqFullCnt; 2420 T3_32BIT_REGISTER DmaNormalWriteFtqFifoEnqueueDequeue; 2421 T3_32BIT_REGISTER DmaNormalWriteFtqFifoWritePeek; 2422 2423 T3_32BIT_REGISTER DmaHighWriteFtqCtrl; 2424 T3_32BIT_REGISTER DmaHighWriteFtqFullCnt; 2425 T3_32BIT_REGISTER DmaHighWriteFtqFifoEnqueueDequeue; 2426 T3_32BIT_REGISTER DmaHighWriteFtqFifoWritePeek; 2427 2428 T3_32BIT_REGISTER SwType1FtqCtrl; 2429 T3_32BIT_REGISTER SwType1FtqFullCnt; 2430 T3_32BIT_REGISTER SwType1FtqFifoEnqueueDequeue; 2431 T3_32BIT_REGISTER SwType1FtqFifoWritePeek; 2432 2433 T3_32BIT_REGISTER SendDataCompFtqCtrl; 2434 T3_32BIT_REGISTER SendDataCompFtqFullCnt; 2435 T3_32BIT_REGISTER SendDataCompFtqFifoEnqueueDequeue; 2436 T3_32BIT_REGISTER SendDataCompFtqFifoWritePeek; 2437 2438 T3_32BIT_REGISTER HostCoalesceFtqCtrl; 2439 T3_32BIT_REGISTER HostCoalesceFtqFullCnt; 2440 T3_32BIT_REGISTER HostCoalesceFtqFifoEnqueueDequeue; 2441 T3_32BIT_REGISTER HostCoalesceFtqFifoWritePeek; 2442 2443 T3_32BIT_REGISTER MacTxFtqCtrl; 2444 T3_32BIT_REGISTER MacTxFtqFullCnt; 2445 T3_32BIT_REGISTER MacTxFtqFifoEnqueueDequeue; 2446 T3_32BIT_REGISTER MacTxFtqFifoWritePeek; 2447 2448 T3_32BIT_REGISTER MbufClustFreeFtqCtrl; 2449 T3_32BIT_REGISTER MbufClustFreeFtqFullCnt; 2450 T3_32BIT_REGISTER MbufClustFreeFtqFifoEnqueueDequeue; 2451 T3_32BIT_REGISTER MbufClustFreeFtqFifoWritePeek; 2452 2453 T3_32BIT_REGISTER RcvBdCompFtqCtrl; 2454 T3_32BIT_REGISTER RcvBdCompFtqFullCnt; 2455 T3_32BIT_REGISTER RcvBdCompFtqFifoEnqueueDequeue; 2456 T3_32BIT_REGISTER RcvBdCompFtqFifoWritePeek; 2457 2458 T3_32BIT_REGISTER RcvListPlmtFtqCtrl; 2459 T3_32BIT_REGISTER RcvListPlmtFtqFullCnt; 2460 T3_32BIT_REGISTER RcvListPlmtFtqFifoEnqueueDequeue; 2461 T3_32BIT_REGISTER RcvListPlmtFtqFifoWritePeek; 2462 2463 T3_32BIT_REGISTER RcvDataBdInitiatorFtqCtrl; 2464 T3_32BIT_REGISTER RcvDataBdInitiatorFtqFullCnt; 2465 T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoEnqueueDequeue; 2466 T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoWritePeek; 2467 2468 T3_32BIT_REGISTER RcvDataCompFtqCtrl; 2469 T3_32BIT_REGISTER RcvDataCompFtqFullCnt; 2470 T3_32BIT_REGISTER RcvDataCompFtqFifoEnqueueDequeue; 2471 T3_32BIT_REGISTER RcvDataCompFtqFifoWritePeek; 2472 2473 T3_32BIT_REGISTER SwType2FtqCtrl; 2474 T3_32BIT_REGISTER SwType2FtqFullCnt; 2475 T3_32BIT_REGISTER SwType2FtqFifoEnqueueDequeue; 2476 T3_32BIT_REGISTER SwType2FtqFifoWritePeek; 2477 2478 /* Unused space. */ 2479 LM_UINT8 Unused2[736]; 2480} T3_FTQ, *PT3_FTQ; 2481 2482 2483 2484/******************************************************************************/ 2485/* Message signaled interrupt registers. */ 2486/******************************************************************************/ 2487 2488typedef struct { 2489 T3_32BIT_REGISTER Mode; 2490#define MSI_MODE_RESET BIT_0 2491#define MSI_MODE_ENABLE BIT_1 2492 T3_32BIT_REGISTER Status; 2493 2494 T3_32BIT_REGISTER MsiFifoAccess; 2495 2496 /* Unused space. */ 2497 LM_UINT8 Unused[1012]; 2498} T3_MSG_SIGNALED_INT, *PT3_MSG_SIGNALED_INT; 2499 2500 2501 2502/******************************************************************************/ 2503/* DMA Completion registes. */ 2504/******************************************************************************/ 2505 2506typedef struct { 2507 T3_32BIT_REGISTER Mode; 2508 #define DMA_COMP_MODE_RESET BIT_0 2509 #define DMA_COMP_MODE_ENABLE BIT_1 2510 2511 /* Unused space. */ 2512 LM_UINT8 Unused[1020]; 2513} T3_DMA_COMPLETION, *PT3_DMA_COMPLETION; 2514 2515 2516 2517/******************************************************************************/ 2518/* GRC registers. */ 2519/******************************************************************************/ 2520 2521typedef struct { 2522 /* Mode control register. */ 2523 T3_32BIT_REGISTER Mode; 2524 #define GRC_MODE_UPDATE_ON_COALESCING BIT_0 2525 #define GRC_MODE_BYTE_SWAP_NON_FRAME_DATA BIT_1 2526 #define GRC_MODE_WORD_SWAP_NON_FRAME_DATA BIT_2 2527 #define GRC_MODE_BYTE_SWAP_DATA BIT_4 2528 #define GRC_MODE_WORD_SWAP_DATA BIT_5 2529 #define GRC_MODE_SPLIT_HEADER_MODE BIT_8 2530 #define GRC_MODE_NO_FRAME_CRACKING BIT_9 2531 #define GRC_MODE_INCLUDE_CRC BIT_10 2532 #define GRC_MODE_ALLOW_BAD_FRAMES BIT_11 2533 #define GRC_MODE_NO_INTERRUPT_ON_SENDS BIT_13 2534 #define GRC_MODE_NO_INTERRUPT_ON_RECEIVE BIT_14 2535 #define GRC_MODE_FORCE_32BIT_PCI_BUS_MODE BIT_15 2536 #define GRC_MODE_HOST_STACK_UP BIT_16 2537 #define GRC_MODE_HOST_SEND_BDS BIT_17 2538 #define GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM BIT_20 2539 #define GRC_MODE_NVRAM_WRITE_ENABLE BIT_21 2540 #define GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM BIT_23 2541 #define GRC_MODE_INT_ON_TX_CPU_ATTN BIT_24 2542 #define GRC_MODE_INT_ON_RX_CPU_ATTN BIT_25 2543 #define GRC_MODE_INT_ON_MAC_ATTN BIT_26 2544 #define GRC_MODE_INT_ON_DMA_ATTN BIT_27 2545 #define GRC_MODE_INT_ON_FLOW_ATTN BIT_28 2546 #define GRC_MODE_4X_NIC_BASED_SEND_RINGS BIT_29 2547 #define GRC_MODE_MULTICAST_FRAME_ENABLE BIT_30 2548 2549 /* Misc configuration register. */ 2550 T3_32BIT_REGISTER MiscCfg; 2551 #define GRC_MISC_CFG_CORE_CLOCK_RESET BIT_0 2552 #define GRC_MISC_PRESCALAR_TIMER_MASK 0xfe 2553 #define GRC_MISC_BD_ID_MASK 0x0001e000 2554 #define GRC_MISC_BD_ID_5700 0x0001e000 2555 #define GRC_MISC_BD_ID_5701 0x00000000 2556 #define GRC_MISC_BD_ID_5703 0x00000000 2557 #define GRC_MISC_BD_ID_5703S 0x00002000 2558 #define GRC_MISC_BD_ID_5702FE 0x00004000 2559 #define GRC_MISC_BD_ID_5704 0x00000000 2560 #define GRC_MISC_BD_ID_5704CIOBE 0x00004000 2561 #define GRC_MISC_BD_ID_5788 0x00010000 2562 #define GRC_MISC_BD_ID_5788M 0x00018000 2563 #define GRC_MISC_GPHY_KEEP_POWER_DURING_RESET BIT_26 2564 2565 /* Miscellaneous local control register. */ 2566 T3_32BIT_REGISTER LocalCtrl; 2567 #define GRC_MISC_LOCAL_CTRL_INT_ACTIVE BIT_0 2568 #define GRC_MISC_LOCAL_CTRL_CLEAR_INT BIT_1 2569 #define GRC_MISC_LOCAL_CTRL_SET_INT BIT_2 2570 #define GRC_MISC_LOCAL_CTRL_INT_ON_ATTN BIT_3 2571 #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT0 BIT_8 2572 #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT1 BIT_9 2573 #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT2 BIT_10 2574 #define GRC_MISC_LOCAL_CTRL_GPIO_OE0 BIT_11 2575 #define GRC_MISC_LOCAL_CTRL_GPIO_OE1 BIT_12 2576 #define GRC_MISC_LOCAL_CTRL_GPIO_OE2 BIT_13 2577 #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 BIT_14 2578 #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 BIT_15 2579 #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2 BIT_16 2580 #define GRC_MISC_LOCAL_CTRL_ENABLE_EXT_MEMORY BIT_17 2581 #define GRC_MISC_LOCAL_CTRL_BANK_SELECT BIT_21 2582 #define GRC_MISC_LOCAL_CTRL_SSRAM_TYPE BIT_22 2583 2584 #define GRC_MISC_MEMSIZE_256K 0 2585 #define GRC_MISC_MEMSIZE_512K (1 << 18) 2586 #define GRC_MISC_MEMSIZE_1024K (2 << 18) 2587 #define GRC_MISC_MEMSIZE_2048K (3 << 18) 2588 #define GRC_MISC_MEMSIZE_4096K (4 << 18) 2589 #define GRC_MISC_MEMSIZE_8192K (5 << 18) 2590 #define GRC_MISC_MEMSIZE_16M (6 << 18) 2591 #define GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM BIT_24 2592 2593 2594 T3_32BIT_REGISTER Timer; 2595 2596 T3_32BIT_REGISTER RxCpuEvent; 2597 T3_32BIT_REGISTER RxTimerRef; 2598 T3_32BIT_REGISTER RxCpuSemaphore; 2599 T3_32BIT_REGISTER RemoteRxCpuAttn; 2600 2601 T3_32BIT_REGISTER TxCpuEvent; 2602 T3_32BIT_REGISTER TxTimerRef; 2603 T3_32BIT_REGISTER TxCpuSemaphore; 2604 T3_32BIT_REGISTER RemoteTxCpuAttn; 2605 2606 T3_64BIT_REGISTER MemoryPowerUp; 2607 2608 T3_32BIT_REGISTER EepromAddr; 2609 #define SEEPROM_ADDR_WRITE 0 2610 #define SEEPROM_ADDR_READ (1 << 31) 2611 #define SEEPROM_ADDR_RW_MASK 0x80000000 2612 #define SEEPROM_ADDR_COMPLETE (1 << 30) 2613 #define SEEPROM_ADDR_FSM_RESET (1 << 29) 2614 #define SEEPROM_ADDR_DEV_ID(x) (x << 26) 2615 #define SEEPROM_ADDR_DEV_ID_MASK 0x1c000000 2616 #define SEEPROM_ADDR_START (1 << 25) 2617 #define SEEPROM_ADDR_CLK_PERD(x) (x << 16) 2618 #define SEEPROM_ADDR_ADDRESS(x) (x & 0xfffc) 2619 #define SEEPROM_ADDR_ADDRESS_MASK 0x0000ffff 2620 2621 #define SEEPROM_CLOCK_PERIOD 60 2622 #define SEEPROM_CHIP_SIZE (64 * 1024) 2623 2624 T3_32BIT_REGISTER EepromData; 2625 T3_32BIT_REGISTER EepromCtrl; 2626 2627 T3_32BIT_REGISTER MdiCtrl; 2628 T3_32BIT_REGISTER SepromDelay; 2629 2630 /* Unused space. */ 2631 LM_UINT8 Unused[948]; 2632} T3_GRC, *PT3_GRC; 2633 2634 2635/******************************************************************************/ 2636/* NVRAM control registers. */ 2637/******************************************************************************/ 2638 2639typedef struct 2640{ 2641 T3_32BIT_REGISTER Cmd; 2642 #define NVRAM_CMD_RESET BIT_0 2643 #define NVRAM_CMD_DONE BIT_3 2644 #define NVRAM_CMD_DO_IT BIT_4 2645 #define NVRAM_CMD_WR BIT_5 2646 #define NVRAM_CMD_RD BIT_NONE 2647 #define NVRAM_CMD_ERASE BIT_6 2648 #define NVRAM_CMD_FIRST BIT_7 2649 #define NVRAM_CMD_LAST BIT_8 2650 2651 T3_32BIT_REGISTER Status; 2652 T3_32BIT_REGISTER WriteData; 2653 2654 T3_32BIT_REGISTER Addr; 2655 #define NVRAM_ADDRESS_MASK 0xffffff 2656 2657 T3_32BIT_REGISTER ReadData; 2658 2659 /* Flash config 1 register. */ 2660 T3_32BIT_REGISTER Config1; 2661 #define FLASH_INTERFACE_ENABLE BIT_0 2662 #define FLASH_SSRAM_BUFFERED_MODE BIT_1 2663 #define FLASH_PASS_THRU_MODE BIT_2 2664 #define FLASH_BIT_BANG_MODE BIT_3 2665 #define FLASH_COMPAT_BYPASS BIT_31 2666 2667 #define BUFFERED_FLASH (FLASH_INTERFACE_ENABLE | FLASH_SSRAM_BUFFERED_MODE) 2668 2669 /* Buffered flash (Atmel: AT45DB011B) specific information */ 2670 #define BUFFERED_FLASH_PAGE_POS 9 2671 #define BUFFERED_FLASH_BYTE_ADDR_MASK ((1<<BUFFERED_FLASH_PAGE_POS) - 1) 2672 #define BUFFERED_FLASH_PAGE_SIZE 264 2673 #define BUFFERED_FLASH_PHY_PAGE_SIZE 512 2674 2675 T3_32BIT_REGISTER Config2; 2676 T3_32BIT_REGISTER Config3; 2677 T3_32BIT_REGISTER SwArb; 2678 #define SW_ARB_REQ_SET0 BIT_0 2679 #define SW_ARB_REQ_SET1 BIT_1 2680 #define SW_ARB_REQ_SET2 BIT_2 2681 #define SW_ARB_REQ_SET3 BIT_3 2682 #define SW_ARB_REQ_CLR0 BIT_4 2683 #define SW_ARB_REQ_CLR1 BIT_5 2684 #define SW_ARB_REQ_CLR2 BIT_6 2685 #define SW_ARB_REQ_CLR3 BIT_7 2686 #define SW_ARB_GNT0 BIT_8 2687 #define SW_ARB_GNT1 BIT_9 2688 #define SW_ARB_GNT2 BIT_10 2689 #define SW_ARB_GNT3 BIT_11 2690 #define SW_ARB_REQ0 BIT_12 2691 #define SW_ARB_REQ1 BIT_13 2692 #define SW_ARB_REQ2 BIT_14 2693 #define SW_ARB_REQ3 BIT_15 2694 2695 T3_32BIT_REGISTER NvmAccess; 2696 #define ACCESS_EN BIT_0 2697 #define ACCESS_WR_EN BIT_1 2698 2699 /* Unused space. */ 2700 LM_UINT8 Unused[984]; 2701} T3_NVRAM, *PT3_NVRAM; 2702 2703 2704/******************************************************************************/ 2705/* NIC's internal memory. */ 2706/******************************************************************************/ 2707 2708typedef struct { 2709 /* Page zero for the internal CPUs. */ 2710 LM_UINT8 PageZero[0x100]; /* 0x0000 */ 2711 2712 /* Send RCBs. */ 2713 T3_RCB SendRcb[16]; /* 0x0100 */ 2714 2715 /* Receive Return RCBs. */ 2716 T3_RCB RcvRetRcb[16]; /* 0x0200 */ 2717 2718 /* Statistics block. */ 2719 T3_STATS_BLOCK StatsBlk; /* 0x0300 */ 2720 2721 /* Status block. */ 2722 T3_STATUS_BLOCK StatusBlk; /* 0x0b00 */ 2723 2724 /* Reserved for software. */ 2725 LM_UINT8 Reserved[1200]; /* 0x0b50 */ 2726 2727 /* Unmapped region. */ 2728 LM_UINT8 Unmapped[4096]; /* 0x1000 */ 2729 2730 /* DMA descriptors. */ 2731 LM_UINT8 DmaDesc[8192]; /* 0x2000 */ 2732 2733 /* Buffer descriptors. */ 2734 LM_UINT8 BufferDesc[16384]; /* 0x4000 */ 2735} T3_FIRST_32K_SRAM, *PT3_FIRST_32K_SRAM; 2736 2737 2738 2739/******************************************************************************/ 2740/* Memory layout. */ 2741/******************************************************************************/ 2742 2743typedef struct { 2744 /* PCI configuration registers. */ 2745 T3_PCI_CONFIGURATION PciCfg; 2746 2747 /* Unused. */ 2748 LM_UINT8 Unused1[0x100]; /* 0x0100 */ 2749 2750 /* Mailbox . */ 2751 T3_MAILBOX Mailbox; /* 0x0200 */ 2752 2753 /* MAC control registers. */ 2754 T3_MAC_CONTROL MacCtrl; /* 0x0400 */ 2755 2756 /* Send data initiator control registers. */ 2757 T3_SEND_DATA_INITIATOR SndDataIn; /* 0x0c00 */ 2758 2759 /* Send data completion Control registers. */ 2760 T3_SEND_DATA_COMPLETION SndDataComp; /* 0x1000 */ 2761 2762 /* Send BD ring selector. */ 2763 T3_SEND_BD_SELECTOR SndBdSel; /* 0x1400 */ 2764 2765 /* Send BD initiator control registers. */ 2766 T3_SEND_BD_INITIATOR SndBdIn; /* 0x1800 */ 2767 2768 /* Send BD completion control registers. */ 2769 T3_SEND_BD_COMPLETION SndBdComp; /* 0x1c00 */ 2770 2771 /* Receive list placement control registers. */ 2772 T3_RCV_LIST_PLACEMENT RcvListPlmt; /* 0x2000 */ 2773 2774 /* Receive Data and Receive BD Initiator Control. */ 2775 T3_RCV_DATA_BD_INITIATOR RcvDataBdIn; /* 0x2400 */ 2776 2777 /* Receive Data Completion Control */ 2778 T3_RCV_DATA_COMPLETION RcvDataComp; /* 0x2800 */ 2779 2780 /* Receive BD Initiator Control Registers. */ 2781 T3_RCV_BD_INITIATOR RcvBdIn; /* 0x2c00 */ 2782 2783 /* Receive BD Completion Control Registers. */ 2784 T3_RCV_BD_COMPLETION RcvBdComp; /* 0x3000 */ 2785 2786 /* Receive list selector control registers. */ 2787 T3_RCV_LIST_SELECTOR RcvListSel; /* 0x3400 */ 2788 2789 /* Mbuf cluster free registers. */ 2790 T3_MBUF_CLUSTER_FREE MbufClusterFree; /* 0x3800 */ 2791 2792 /* Host coalescing control registers. */ 2793 T3_HOST_COALESCING HostCoalesce; /* 0x3c00 */ 2794 2795 /* Memory arbiter control registers. */ 2796 T3_MEM_ARBITER MemArbiter; /* 0x4000 */ 2797 2798 /* Buffer manger control registers. */ 2799 T3_BUFFER_MANAGER BufMgr; /* 0x4400 */ 2800 2801 /* Read DMA control registers. */ 2802 T3_DMA_READ DmaRead; /* 0x4800 */ 2803 2804 /* Write DMA control registers. */ 2805 T3_DMA_WRITE DmaWrite; /* 0x4c00 */ 2806 2807 T3_CPU rxCpu; /* 0x5000 */ 2808 T3_CPU txCpu; /* 0x5400 */ 2809 2810 /* Mailboxes. */ 2811 T3_GRC_MAILBOX GrcMailbox; /* 0x5800 */ 2812 2813 /* Flow Through queues. */ 2814 T3_FTQ Ftq; /* 0x5c00 */ 2815 2816 /* Message signaled interrupt registes. */ 2817 T3_MSG_SIGNALED_INT Msi; /* 0x6000 */ 2818 2819 /* DMA completion registers. */ 2820 T3_DMA_COMPLETION DmaComp; /* 0x6400 */ 2821 2822 /* GRC registers. */ 2823 T3_GRC Grc; /* 0x6800 */ 2824 2825 /* Unused space. */ 2826 LM_UINT8 Unused2[1024]; /* 0x6c00 */ 2827 2828 /* NVRAM registers. */ 2829 T3_NVRAM Nvram; /* 0x7000 */ 2830 2831 /* Unused space. */ 2832 LM_UINT8 Unused3[3072]; /* 0x7400 */ 2833 2834 /* The 32k memory window into the NIC's */ 2835 /* internal memory. The memory window is */ 2836 /* controlled by the Memory Window Base */ 2837 /* Address register. This register is located */ 2838 /* in the PCI configuration space. */ 2839 union { /* 0x8000 */ 2840 T3_FIRST_32K_SRAM First32k; 2841 2842 /* Use the memory window base address register to determine the */ 2843 /* MBUF segment. */ 2844 LM_UINT32 Mbuf[32768/4]; 2845 LM_UINT32 MemBlock32K[32768/4]; 2846 } uIntMem; 2847} T3_STD_MEM_MAP, *PT3_STD_MEM_MAP; 2848 2849 2850/******************************************************************************/ 2851/* Adapter info. */ 2852/******************************************************************************/ 2853 2854typedef struct 2855{ 2856 LM_UINT16 Svid; 2857 LM_UINT16 Ssid; 2858 LM_UINT32 PhyId; 2859 LM_UINT32 Serdes; /* 0 = copper PHY, 1 = Serdes */ 2860} LM_ADAPTER_INFO, *PLM_ADAPTER_INFO; 2861 2862 2863/******************************************************************************/ 2864/* Packet queues. */ 2865/******************************************************************************/ 2866 2867DECLARE_QUEUE_TYPE(LM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT); 2868DECLARE_QUEUE_TYPE(LM_TX_PACKET_Q, MAX_TX_PACKET_DESC_COUNT); 2869 2870 2871 2872/******************************************************************************/ 2873/* Tx counters. */ 2874/******************************************************************************/ 2875 2876typedef struct { 2877 LM_COUNTER TxPacketGoodCnt; 2878 LM_COUNTER TxBytesGoodCnt; 2879 LM_COUNTER TxPacketAbortedCnt; 2880 LM_COUNTER NoSendBdLeftCnt; 2881 LM_COUNTER NoMapRegisterLeftCnt; 2882 LM_COUNTER TooManyFragmentsCnt; 2883 LM_COUNTER NoTxPacketDescCnt; 2884} LM_TX_COUNTERS, *PLM_TX_COUNTERS; 2885 2886 2887 2888/******************************************************************************/ 2889/* Rx counters. */ 2890/******************************************************************************/ 2891 2892typedef struct { 2893 LM_COUNTER RxPacketGoodCnt; 2894 LM_COUNTER RxBytesGoodCnt; 2895 LM_COUNTER RxPacketErrCnt; 2896 LM_COUNTER RxErrCrcCnt; 2897 LM_COUNTER RxErrCollCnt; 2898 LM_COUNTER RxErrLinkLostCnt; 2899 LM_COUNTER RxErrPhyDecodeCnt; 2900 LM_COUNTER RxErrOddNibbleCnt; 2901 LM_COUNTER RxErrMacAbortCnt; 2902 LM_COUNTER RxErrShortPacketCnt; 2903 LM_COUNTER RxErrNoResourceCnt; 2904 LM_COUNTER RxErrLargePacketCnt; 2905} LM_RX_COUNTERS, *PLM_RX_COUNTERS; 2906 2907 2908 2909/******************************************************************************/ 2910/* Receive producer rings. */ 2911/******************************************************************************/ 2912 2913typedef enum { 2914 T3_UNKNOWN_RCV_PROD_RING = 0, 2915 T3_STD_RCV_PROD_RING = 1, 2916 T3_MINI_RCV_PROD_RING = 2, 2917 T3_JUMBO_RCV_PROD_RING = 3 2918} T3_RCV_PROD_RING, *PT3_RCV_PROD_RING; 2919 2920 2921 2922/******************************************************************************/ 2923/* Packet descriptor. */ 2924/******************************************************************************/ 2925 2926#define LM_PACKET_SIGNATURE_TX 0x6861766b 2927#define LM_PACKET_SIGNATURE_RX 0x6b766168 2928 2929typedef struct _LM_PACKET { 2930 /* Set in LM. */ 2931 LM_STATUS PacketStatus; 2932 2933 /* Set in LM for Rx, in UM for Tx. */ 2934 LM_UINT32 PacketSize; 2935 2936 LM_UINT16 Flags; 2937 2938 LM_UINT16 VlanTag; 2939 2940 union { 2941 /* Send info. */ 2942 struct { 2943 /* Set up by UM. */ 2944 LM_UINT32 FragCount; 2945 2946#if INCLUDE_TCP_SEG_SUPPORT 2947 LM_UINT32 MaxSegmentSize; 2948#endif 2949 } Tx; 2950 2951 /* Receive info. */ 2952 struct { 2953 /* This descriptor belongs to either Std, Mini, or Jumbo ring. */ 2954 LM_UINT16 RcvProdRing; 2955 LM_UINT16 RcvRingProdIdx; 2956 2957 /* Receive buffer size */ 2958 LM_UINT32 RxBufferSize; 2959 2960 /* Checksum information. */ 2961 LM_UINT16 IpChecksum; 2962 LM_UINT16 TcpUdpChecksum; 2963 2964 } Rx; 2965 } u; 2966} LM_PACKET; 2967 2968 2969 2970/******************************************************************************/ 2971/* Tigon3 device block. */ 2972/******************************************************************************/ 2973 2974typedef struct _LM_DEVICE_BLOCK { 2975 /* Memory view. */ 2976 PT3_STD_MEM_MAP pMemView; 2977 2978 /* Base address of the block of memory in which the LM_PACKET descriptors */ 2979 /* are allocated from. */ 2980 PLM_VOID pPacketDescBase; 2981 2982 LM_UINT32 MiscHostCtrl; 2983 LM_UINT32 GrcLocalCtrl; 2984 LM_UINT32 DmaReadWriteCtrl; 2985 LM_UINT32 PciState; 2986 LM_UINT32 ClockCtrl; 2987 LM_UINT32 DmaReadFifoSize; 2988 LM_UINT32 GrcMode; 2989 2990 LM_UINT32 PowerLevel; 2991 2992 LM_UINT32 Flags; 2993 2994 #define MINI_PCI_FLAG 0x1 2995 #define PCI_EXPRESS_FLAG 0x2 2996 #define BCM5788_FLAG 0x4 2997 #define FIBER_WOL_CAPABLE_FLAG 0x8 2998 #define WOL_LIMIT_10MBPS_FLAG 0x10 2999 #define ENABLE_MWI_FLAG 0x20 3000 #define USE_TAGGED_STATUS_FLAG 0x40 3001 3002 /* NIC will not compute the pseudo header checksum. The driver or OS */ 3003 /* must seed the checksum field with the pseudo checksum. */ 3004 #define NO_TX_PSEUDO_HDR_CSUM_FLAG 0x80 3005 3006 /* The receive checksum in the BD does not include the pseudo checksum. */ 3007 /* The OS or the driver must calculate the pseudo checksum and add it to */ 3008 /* the checksum in the BD. */ 3009 #define NO_RX_PSEUDO_HDR_CSUM_FLAG 0x100 3010 3011 #define ENABLE_PCIX_FIX_FLAG 0x200 3012 3013 #define TX_4G_WORKAROUND_FLAG 0x400 3014 #define UNDI_FIX_FLAG 0x800 3015 #define FLUSH_POSTED_WRITE_FLAG 0x1000 3016 #define REG_RD_BACK_FLAG 0x2000 3017 3018 /* Use NIC or Host based send BD. */ 3019 #define NIC_SEND_BD_FLAG 0x4000 3020 3021 /* Athlon fix. */ 3022 #define DELAY_PCI_GRANT_FLAG 0x8000 3023 3024 /* Enable OneDmaAtOnce */ 3025 #define ONE_DMA_AT_ONCE_FLAG 0x10000 3026 3027 /* Enable PCI-X multi split */ 3028 #define MULTI_SPLIT_ENABLE_FLAG 0x20000 3029 3030 #define RX_BD_LIMIT_64_FLAG 0x40000 3031 3032 #define DMA_WR_MODE_RX_ACCELERATE_FLAG 0x80000 3033 3034 /* write protect */ 3035 #define EEPROM_WP_FLAG 0x100000 3036 #define FLASH_DETECTED_FLAG 0x200000 3037 3038 #define DISABLE_D3HOT_FLAG 0x400000 3039 3040 /* Rx info */ 3041 LM_UINT32 RxStdDescCnt; 3042 LM_UINT32 RxStdQueuedCnt; 3043 LM_UINT32 RxStdProdIdx; 3044 3045 PT3_RCV_BD pRxStdBdVirt; 3046 LM_PHYSICAL_ADDRESS RxStdBdPhy; 3047 3048 LM_UINT32 RxPacketDescCnt; 3049 LM_RX_PACKET_Q RxPacketFreeQ; 3050 LM_RX_PACKET_Q RxPacketReceivedQ; 3051 3052 LM_PACKET *RxStdRing[T3_STD_RCV_RCB_ENTRY_COUNT]; 3053#if T3_JUMBO_RCV_RCB_ENTRY_COUNT 3054 LM_PACKET *RxJumboRing[T3_JUMBO_RCV_RCB_ENTRY_COUNT]; 3055#endif 3056 3057 /* Receive info. */ 3058 PT3_RCV_BD pRcvRetBdVirt; 3059 LM_PHYSICAL_ADDRESS RcvRetBdPhy; 3060 LM_UINT32 RcvRetConIdx; 3061 LM_UINT32 RcvRetRcbEntryCount; 3062 LM_UINT32 RcvRetRcbEntryCountMask; 3063 3064#if T3_JUMBO_RCV_RCB_ENTRY_COUNT 3065 LM_UINT32 RxJumboDescCnt; 3066 LM_UINT32 RxJumboBufferSize; 3067 LM_UINT32 RxJumboQueuedCnt; 3068 3069 LM_UINT32 RxJumboProdIdx; 3070 3071 PT3_RCV_BD pRxJumboBdVirt; 3072 LM_PHYSICAL_ADDRESS RxJumboBdPhy; 3073#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ 3074 3075 /* These values are used by the upper module to inform the protocol */ 3076 /* of the maximum transmit/receive packet size. */ 3077 LM_UINT32 TxMtu; /* Does not include CRC. */ 3078 LM_UINT32 RxMtu; /* Does not include CRC. */ 3079 3080#if INCLUDE_TCP_SEG_SUPPORT 3081 LM_UINT32 LargeSendMaxSize; 3082 LM_UINT32 LargeSendMinNumSeg; 3083#endif 3084 3085 /* We need to shadow the EMAC, Rx, Tx mode registers. With B0 silicon, */ 3086 /* we may have problems reading any MAC registers in 10mb mode. */ 3087 LM_UINT32 MacMode; 3088 LM_UINT32 RxMode; 3089 LM_UINT32 TxMode; 3090 3091 /* MiMode register. */ 3092 LM_UINT32 MiMode; 3093 3094 /* Host coalesce mode register. */ 3095 LM_UINT32 CoalesceMode; 3096 3097 /* Send info. */ 3098 LM_UINT32 TxPacketDescCnt; 3099 3100 /* Tx info. */ 3101 LM_TX_PACKET_Q TxPacketFreeQ; 3102 LM_TX_PACKET_Q TxPacketXmittedQ; 3103 3104 /* Pointers to SendBd. */ 3105 PT3_SND_BD pSendBdVirt; 3106 LM_PHYSICAL_ADDRESS SendBdPhy; /* Only valid for Host based Send BD. */ 3107 3108 /* Send producer and consumer indices. */ 3109 LM_UINT32 SendProdIdx; 3110 LM_UINT32 SendConIdx; 3111 3112 /* Number of BD left. */ 3113 MM_ATOMIC_T SendBdLeft; 3114 3115 T3_SND_BD ShadowSendBd[T3_SEND_RCB_ENTRY_COUNT]; 3116 LM_PACKET *SendRing[T3_SEND_RCB_ENTRY_COUNT]; 3117 3118 /* Counters. */ 3119 LM_RX_COUNTERS RxCounters; 3120 LM_TX_COUNTERS TxCounters; 3121 3122 /* Host coalescing parameters. */ 3123 LM_UINT32 RxCoalescingTicks; 3124 LM_UINT32 TxCoalescingTicks; 3125 LM_UINT32 RxMaxCoalescedFrames; 3126 LM_UINT32 TxMaxCoalescedFrames; 3127 LM_UINT32 StatsCoalescingTicks; 3128 LM_UINT32 RxCoalescingTicksDuringInt; 3129 LM_UINT32 TxCoalescingTicksDuringInt; 3130 LM_UINT32 RxMaxCoalescedFramesDuringInt; 3131 LM_UINT32 TxMaxCoalescedFramesDuringInt; 3132 3133 /* DMA water marks. */ 3134 LM_UINT32 DmaMbufLowMark; 3135 LM_UINT32 RxMacMbufLowMark; 3136 LM_UINT32 MbufHighMark; 3137 3138 /* Status block. */ 3139 PT3_STATUS_BLOCK pStatusBlkVirt; 3140 LM_PHYSICAL_ADDRESS StatusBlkPhy; 3141 3142 /* Statistics block. */ 3143 PT3_STATS_BLOCK pStatsBlkVirt; 3144 LM_PHYSICAL_ADDRESS StatsBlkPhy; 3145 3146 /* Current receive mask. */ 3147 LM_UINT32 ReceiveMask; 3148 3149 /* Task offload capabilities. */ 3150 LM_TASK_OFFLOAD TaskOffloadCap; 3151 3152 /* Task offload selected. */ 3153 LM_TASK_OFFLOAD TaskToOffload; 3154 3155 /* Wake up capability. */ 3156 LM_WAKE_UP_MODE WakeUpModeCap; 3157 3158 /* Wake up capability. */ 3159 LM_WAKE_UP_MODE WakeUpMode; 3160 3161 /* Flow control. */ 3162 LM_FLOW_CONTROL FlowControlCap; 3163 LM_FLOW_CONTROL FlowControl; 3164 3165 /* interrupt status tag */ 3166 LM_UINT32 LastTag; 3167 3168 /* Current node address. */ 3169 LM_UINT8 NodeAddress[8]; 3170 3171 /* The adapter's node address. */ 3172 LM_UINT8 PermanentNodeAddress[8]; 3173 3174 /* Adapter info. */ 3175 LM_UINT16 BusNum; // Init by the upper module. 3176 LM_UINT8 DevNum; // Init by the upper module. 3177 LM_UINT8 FunctNum; // Init by the upper module. 3178 LM_UINT16 PciVendorId; 3179 LM_UINT16 PciDeviceId; 3180 LM_UINT32 BondId; 3181 LM_UINT8 Irq; 3182 LM_UINT8 IntPin; 3183 LM_UINT8 CacheLineSize; 3184 LM_UINT8 PciRevId; 3185 LM_UINT32 PciCommandStatusWords; 3186 LM_UINT32 ChipRevId; 3187 LM_UINT16 SubsystemVendorId; 3188 LM_UINT16 SubsystemId; 3189 PLM_UINT8 pMappedMemBase; 3190 3191 /* Saved PCI configuration registers for restoring after a reset. */ 3192 LM_UINT32 SavedCacheLineReg; 3193 3194 /* Phy info. */ 3195 LM_UINT32 PhyAddr; 3196 LM_UINT32 PhyId; 3197 3198 /* Requested phy settings. */ 3199 LM_LINE_SPEED RequestedLineSpeed; 3200 LM_DUPLEX_MODE RequestedDuplexMode; 3201 3202 /* Disable auto-negotiation. */ 3203 LM_UINT32 DisableAutoNeg; 3204 3205 LM_UINT32 AutoNegJustInited; 3206 3207 /* Ways for the MAC to get link change interrupt. */ 3208 LM_UINT32 PhyIntMode; 3209 #define T3_PHY_INT_MODE_AUTO 0 3210 #define T3_PHY_INT_MODE_MI_INTERRUPT 1 3211 #define T3_PHY_INT_MODE_LINK_READY 2 3212 #define T3_PHY_INT_MODE_AUTO_POLLING 3 3213 3214 /* Ways to determine link change status. */ 3215 LM_UINT32 LinkChngMode; 3216 #define T3_LINK_CHNG_MODE_AUTO 0 3217 #define T3_LINK_CHNG_MODE_USE_STATUS_REG 1 3218 #define T3_LINK_CHNG_MODE_USE_STATUS_BLOCK 2 3219 3220 LM_UINT32 LedCtrl; 3221 3222 /* WOL Speed */ 3223 LM_UINT32 WolSpeed; 3224 #define WOL_SPEED_10MB 1 3225 #define WOL_SPEED_100MB 2 3226 3227 LM_UINT32 PhyFlags; 3228 #define PHY_RESET_ON_INIT 0x01 3229 #define PHY_RESET_ON_LINKDOWN 0x02 3230 #define PHY_ADC_FIX 0x04 3231 #define PHY_CHECK_TAPS_AFTER_RESET 0x08 3232 #define PHY_5704_A0_FIX 0x10 3233 #define PHY_ETHERNET_WIRESPEED 0x20 3234 #define PHY_5705_5750_FIX 0x40 3235 #define PHY_NO_GIGABIT 0x80 3236 #define PHY_CAPACITIVE_COUPLING 0x100 3237 3238 LM_UINT32 RestoreOnWakeUp; 3239 LM_LINE_SPEED WakeUpRequestedLineSpeed; 3240 LM_DUPLEX_MODE WakeUpRequestedDuplexMode; 3241 LM_UINT32 WakeUpDisableAutoNeg; 3242 3243 /* Current phy settings. */ 3244 LM_LINE_SPEED LineSpeed; 3245 LM_LINE_SPEED OldLineSpeed; 3246 LM_DUPLEX_MODE DuplexMode; 3247 LM_STATUS LinkStatus; 3248 LM_UINT32 advertising; 3249 LM_UINT32 advertising1000; 3250 3251 LM_UINT32 LoopBackMode; 3252 3253#define LM_MAC_LOOP_BACK_MODE 1 3254#define LM_PHY_LOOP_BACK_MODE 2 3255#define LM_EXT_LOOP_BACK_MODE 3 3256 3257 LM_LINE_SPEED SavedRequestedLineSpeed; 3258 LM_DUPLEX_MODE SavedRequestedDuplexMode; 3259 LM_UINT32 SavedDisableAutoNeg; 3260 3261 LM_UINT32 MulticastHash[4]; 3262 3263 LM_UINT32 AsfFlags; 3264 3265#define ASF_ENABLED 1 3266#define ASF_NEW_HANDSHAKE 2 /* if set, this bit implies ASF enabled as well */ 3267 3268 /* Split Mode flags */ 3269 LM_UINT32 SplitModeMaxReq; 3270 3271 #define SPLIT_MODE_5704_MAX_REQ 3 3272 3273 /* Init flag. */ 3274 LM_BOOL InitDone; 3275 3276 /* Shutdown flag. Set by the upper module. */ 3277 LM_BOOL ShuttingDown; 3278 3279 /* Flag to determine whether to call LM_QueueRxPackets or not in */ 3280 /* LM_ResetAdapter routine. */ 3281 LM_BOOL QueueRxPackets; 3282 LM_BOOL QueueAgain; 3283 3284 LM_UINT32 MbufBase; 3285 LM_UINT32 MbufSize; 3286 3287 LM_UINT32 NvramSize; 3288 3289#if INCLUDE_TBI_SUPPORT 3290 /* Autoneg state info. */ 3291 AN_STATE_INFO AnInfo; 3292 3293 LM_UINT32 TbiFlags; 3294 /* set if we have a SERDES PHY. */ 3295 #define ENABLE_TBI_FLAG 0x1 3296 #define TBI_POLLING_INTR_FLAG 0x2 3297 #define TBI_PURE_POLLING_FLAG 0x4 3298 #define TBI_POLLING_FLAGS (TBI_POLLING_INTR_FLAG | TBI_PURE_POLLING_FLAG) 3299 3300 LM_UINT32 IgnoreTbiLinkChange; 3301#endif 3302#ifdef BCM_NAPI_RXPOLL 3303 volatile LM_UINT32 RxPoll; 3304#endif 3305 char PartNo[24]; 3306 char BootCodeVer[16]; 3307 char BusSpeedStr[24]; 3308 3309} LM_DEVICE_BLOCK; 3310 3311 3312#define T3_REG_CPU_VIEW 0xc0000000 3313 3314#define T3_BLOCK_DMA_RD (1 << 0) 3315#define T3_BLOCK_DMA_COMP (1 << 1) 3316#define T3_BLOCK_RX_BD_INITIATOR (1 << 2) 3317#define T3_BLOCK_RX_BD_COMP (1 << 3) 3318#define T3_BLOCK_DMA_WR (1 << 4) 3319#define T3_BLOCK_MSI_HANDLER (1 << 5) 3320#define T3_BLOCK_RX_LIST_PLMT (1 << 6) 3321#define T3_BLOCK_RX_LIST_SELECTOR (1 << 7) 3322#define T3_BLOCK_RX_DATA_INITIATOR (1 << 8) 3323#define T3_BLOCK_RX_DATA_COMP (1 << 9) 3324#define T3_BLOCK_HOST_COALESING (1 << 10) 3325#define T3_BLOCK_MAC_RX_ENGINE (1 << 11) 3326#define T3_BLOCK_MBUF_CLUSTER_FREE (1 << 12) 3327#define T3_BLOCK_SEND_BD_INITIATOR (1 << 13) 3328#define T3_BLOCK_SEND_BD_COMP (1 << 14) 3329#define T3_BLOCK_SEND_BD_SELECTOR (1 << 15) 3330#define T3_BLOCK_SEND_DATA_INITIATOR (1 << 16) 3331#define T3_BLOCK_SEND_DATA_COMP (1 << 17) 3332#define T3_BLOCK_MAC_TX_ENGINE (1 << 18) 3333#define T3_BLOCK_MEM_ARBITOR (1 << 19) 3334#define T3_BLOCK_MBUF_MANAGER (1 << 20) 3335#define T3_BLOCK_MAC_GLOBAL (1 << 21) 3336 3337#define LM_ENABLE 1 3338#define LM_DISABLE 2 3339 3340#define RX_CPU_EVT_SW0 0 3341#define RX_CPU_EVT_SW1 1 3342#define RX_CPU_EVT_RLP 2 3343#define RX_CPU_EVT_SW3 3 3344#define RX_CPU_EVT_RLS 4 3345#define RX_CPU_EVT_SW4 5 3346#define RX_CPU_EVT_RX_BD_COMP 6 3347#define RX_CPU_EVT_SW5 7 3348#define RX_CPU_EVT_RDI 8 3349#define RX_CPU_EVT_DMA_WR 9 3350#define RX_CPU_EVT_DMA_RD 10 3351#define RX_CPU_EVT_SWQ 11 3352#define RX_CPU_EVT_SW6 12 3353#define RX_CPU_EVT_RDC 13 3354#define RX_CPU_EVT_SW7 14 3355#define RX_CPU_EVT_HOST_COALES 15 3356#define RX_CPU_EVT_SW8 16 3357#define RX_CPU_EVT_HIGH_DMA_WR 17 3358#define RX_CPU_EVT_HIGH_DMA_RD 18 3359#define RX_CPU_EVT_SW9 19 3360#define RX_CPU_EVT_DMA_ATTN 20 3361#define RX_CPU_EVT_LOW_P_MBOX 21 3362#define RX_CPU_EVT_HIGH_P_MBOX 22 3363#define RX_CPU_EVT_SW10 23 3364#define RX_CPU_EVT_TX_CPU_ATTN 24 3365#define RX_CPU_EVT_MAC_ATTN 25 3366#define RX_CPU_EVT_RX_CPU_ATTN 26 3367#define RX_CPU_EVT_FLOW_ATTN 27 3368#define RX_CPU_EVT_SW11 28 3369#define RX_CPU_EVT_TIMER 29 3370#define RX_CPU_EVT_SW12 30 3371#define RX_CPU_EVT_SW13 31 3372 3373/* RX-CPU event */ 3374#define RX_CPU_EVENT_SW_EVENT0 (1 << RX_CPU_EVT_SW0) 3375#define RX_CPU_EVENT_SW_EVENT1 (1 << RX_CPU_EVT_SW1) 3376#define RX_CPU_EVENT_RLP (1 << RX_CPU_EVT_RLP) 3377#define RX_CPU_EVENT_SW_EVENT3 (1 << RX_CPU_EVT_SW3) 3378#define RX_CPU_EVENT_RLS (1 << RX_CPU_EVT_RLS) 3379#define RX_CPU_EVENT_SW_EVENT4 (1 << RX_CPU_EVT_SW4) 3380#define RX_CPU_EVENT_RX_BD_COMP (1 << RX_CPU_EVT_RX_BD_COMP) 3381#define RX_CPU_EVENT_SW_EVENT5 (1 << RX_CPU_EVT_SW5) 3382#define RX_CPU_EVENT_RDI (1 << RX_CPU_EVT_RDI) 3383#define RX_CPU_EVENT_DMA_WR (1 << RX_CPU_EVT_DMA_WR) 3384#define RX_CPU_EVENT_DMA_RD (1 << RX_CPU_EVT_DMA_RD) 3385#define RX_CPU_EVENT_SWQ (1 << RX_CPU_EVT_SWQ) 3386#define RX_CPU_EVENT_SW_EVENT6 (1 << RX_CPU_EVT_SW6) 3387#define RX_CPU_EVENT_RDC (1 << RX_CPU_EVT_RDC) 3388#define RX_CPU_EVENT_SW_EVENT7 (1 << RX_CPU_EVT_SW7) 3389#define RX_CPU_EVENT_HOST_COALES (1 << RX_CPU_EVT_HOST_COALES) 3390#define RX_CPU_EVENT_SW_EVENT8 (1 << RX_CPU_EVT_SW8) 3391#define RX_CPU_EVENT_HIGH_DMA_WR (1 << RX_CPU_EVT_HIGH_DMA_WR) 3392#define RX_CPU_EVENT_HIGH_DMA_RD (1 << RX_CPU_EVT_HIGH_DMA_RD) 3393#define RX_CPU_EVENT_SW_EVENT9 (1 << RX_CPU_EVT_SW9) 3394#define RX_CPU_EVENT_DMA_ATTN (1 << RX_CPU_EVT_DMA_ATTN) 3395#define RX_CPU_EVENT_LOW_P_MBOX (1 << RX_CPU_EVT_LOW_P_MBOX) 3396#define RX_CPU_EVENT_HIGH_P_MBOX (1 << RX_CPU_EVT_HIGH_P_MBOX) 3397#define RX_CPU_EVENT_SW_EVENT10 (1 << RX_CPU_EVT_SW10) 3398#define RX_CPU_EVENT_TX_CPU_ATTN (1 << RX_CPU_EVT_TX_CPU_ATTN) 3399#define RX_CPU_EVENT_MAC_ATTN (1 << RX_CPU_EVT_MAC_ATTN) 3400#define RX_CPU_EVENT_RX_CPU_ATTN (1 << RX_CPU_EVT_RX_CPU_ATTN) 3401#define RX_CPU_EVENT_FLOW_ATTN (1 << RX_CPU_EVT_FLOW_ATTN) 3402#define RX_CPU_EVENT_SW_EVENT11 (1 << RX_CPU_EVT_SW11) 3403#define RX_CPU_EVENT_TIMER (1 << RX_CPU_EVT_TIMER) 3404#define RX_CPU_EVENT_SW_EVENT12 (1 << RX_CPU_EVT_SW12) 3405#define RX_CPU_EVENT_SW_EVENT13 (1 << RX_CPU_EVT_SW13) 3406 3407#define RX_CPU_MASK (RX_CPU_EVENT_SW_EVENT0 | \ 3408 RX_CPU_EVENT_RLP | \ 3409 RX_CPU_EVENT_RDI | \ 3410 RX_CPU_EVENT_RDC) 3411 3412#define TX_CPU_EVT_SW0 0 3413#define TX_CPU_EVT_SW1 1 3414#define TX_CPU_EVT_SW2 2 3415#define TX_CPU_EVT_SW3 3 3416#define TX_CPU_EVT_TX_MAC 4 3417#define TX_CPU_EVT_SW4 5 3418#define TX_CPU_EVT_SBDC 6 3419#define TX_CPU_EVT_SW5 7 3420#define TX_CPU_EVT_SDI 8 3421#define TX_CPU_EVT_DMA_WR 9 3422#define TX_CPU_EVT_DMA_RD 10 3423#define TX_CPU_EVT_SWQ 11 3424#define TX_CPU_EVT_SW6 12 3425#define TX_CPU_EVT_SDC 13 3426#define TX_CPU_EVT_SW7 14 3427#define TX_CPU_EVT_HOST_COALES 15 3428#define TX_CPU_EVT_SW8 16 3429#define TX_CPU_EVT_HIGH_DMA_WR 17 3430#define TX_CPU_EVT_HIGH_DMA_RD 18 3431#define TX_CPU_EVT_SW9 19 3432#define TX_CPU_EVT_DMA_ATTN 20 3433#define TX_CPU_EVT_LOW_P_MBOX 21 3434#define TX_CPU_EVT_HIGH_P_MBOX 22 3435#define TX_CPU_EVT_SW10 23 3436#define TX_CPU_EVT_RX_CPU_ATTN 24 3437#define TX_CPU_EVT_MAC_ATTN 25 3438#define TX_CPU_EVT_TX_CPU_ATTN 26 3439#define TX_CPU_EVT_FLOW_ATTN 27 3440#define TX_CPU_EVT_SW11 28 3441#define TX_CPU_EVT_TIMER 29 3442#define TX_CPU_EVT_SW12 30 3443#define TX_CPU_EVT_SW13 31 3444 3445 3446/* TX-CPU event */ 3447#define TX_CPU_EVENT_SW_EVENT0 (1 << TX_CPU_EVT_SW0) 3448#define TX_CPU_EVENT_SW_EVENT1 (1 << TX_CPU_EVT_SW1) 3449#define TX_CPU_EVENT_SW_EVENT2 (1 << TX_CPU_EVT_SW2) 3450#define TX_CPU_EVENT_SW_EVENT3 (1 << TX_CPU_EVT_SW3) 3451#define TX_CPU_EVENT_TX_MAC (1 << TX_CPU_EVT_TX_MAC) 3452#define TX_CPU_EVENT_SW_EVENT4 (1 << TX_CPU_EVT_SW4) 3453#define TX_CPU_EVENT_SBDC (1 << TX_CPU_EVT_SBDC) 3454#define TX_CPU_EVENT_SW_EVENT5 (1 << TX_CPU_EVT_SW5) 3455#define TX_CPU_EVENT_SDI (1 << TX_CPU_EVT_SDI) 3456#define TX_CPU_EVENT_DMA_WR (1 << TX_CPU_EVT_DMA_WR) 3457#define TX_CPU_EVENT_DMA_RD (1 << TX_CPU_EVT_DMA_RD) 3458#define TX_CPU_EVENT_SWQ (1 << TX_CPU_EVT_SWQ) 3459#define TX_CPU_EVENT_SW_EVENT6 (1 << TX_CPU_EVT_SW6) 3460#define TX_CPU_EVENT_SDC (1 << TX_CPU_EVT_SDC) 3461#define TX_CPU_EVENT_SW_EVENT7 (1 << TX_CPU_EVT_SW7) 3462#define TX_CPU_EVENT_HOST_COALES (1 << TX_CPU_EVT_HOST_COALES) 3463#define TX_CPU_EVENT_SW_EVENT8 (1 << TX_CPU_EVT_SW8) 3464#define TX_CPU_EVENT_HIGH_DMA_WR (1 << TX_CPU_EVT_HIGH_DMA_WR) 3465#define TX_CPU_EVENT_HIGH_DMA_RD (1 << TX_CPU_EVT_HIGH_DMA_RD) 3466#define TX_CPU_EVENT_SW_EVENT9 (1 << TX_CPU_EVT_SW9) 3467#define TX_CPU_EVENT_DMA_ATTN (1 << TX_CPU_EVT_DMA_ATTN) 3468#define TX_CPU_EVENT_LOW_P_MBOX (1 << TX_CPU_EVT_LOW_P_MBOX) 3469#define TX_CPU_EVENT_HIGH_P_MBOX (1 << TX_CPU_EVT_HIGH_P_MBOX) 3470#define TX_CPU_EVENT_SW_EVENT10 (1 << TX_CPU_EVT_SW10) 3471#define TX_CPU_EVENT_RX_CPU_ATTN (1 << TX_CPU_EVT_RX_CPU_ATTN) 3472#define TX_CPU_EVENT_MAC_ATTN (1 << TX_CPU_EVT_MAC_ATTN) 3473#define TX_CPU_EVENT_TX_CPU_ATTN (1 << TX_CPU_EVT_TX_CPU_ATTN) 3474#define TX_CPU_EVENT_FLOW_ATTN (1 << TX_CPU_EVT_FLOW_ATTN) 3475#define TX_CPU_EVENT_SW_EVENT11 (1 << TX_CPU_EVT_SW11) 3476#define TX_CPU_EVENT_TIMER (1 << TX_CPU_EVT_TIMER) 3477#define TX_CPU_EVENT_SW_EVENT12 (1 << TX_CPU_EVT_SW12) 3478#define TX_CPU_EVENT_SW_EVENT13 (1 << TX_CPU_EVT_SW13) 3479 3480 3481#define TX_CPU_MASK (TX_CPU_EVENT_SW_EVENT0 | \ 3482 TX_CPU_EVENT_SDI | \ 3483 TX_CPU_EVENT_SDC) 3484 3485 3486#define T3_FTQ_TYPE1_UNDERFLOW_BIT (1 << 29) 3487#define T3_FTQ_TYPE1_PASS_BIT (1 << 30) 3488#define T3_FTQ_TYPE1_SKIP_BIT (1 << 31) 3489 3490#define T3_FTQ_TYPE2_UNDERFLOW_BIT (1 << 13) 3491#define T3_FTQ_TYPE2_PASS_BIT (1 << 14) 3492#define T3_FTQ_TYPE2_SKIP_BIT (1 << 15) 3493 3494#define T3_QID_DMA_READ 1 3495#define T3_QID_DMA_HIGH_PRI_READ 2 3496#define T3_QID_DMA_COMP_DX 3 3497#define T3_QID_SEND_BD_COMP 4 3498#define T3_QID_SEND_DATA_INITIATOR 5 3499#define T3_QID_DMA_WRITE 6 3500#define T3_QID_DMA_HIGH_PRI_WRITE 7 3501#define T3_QID_SW_TYPE_1 8 3502#define T3_QID_SEND_DATA_COMP 9 3503#define T3_QID_HOST_COALESCING 10 3504#define T3_QID_MAC_TX 11 3505#define T3_QID_MBUF_CLUSTER_FREE 12 3506#define T3_QID_RX_BD_COMP 13 3507#define T3_QID_RX_LIST_PLM 14 3508#define T3_QID_RX_DATA_BD_INITIATOR 15 3509#define T3_QID_RX_DATA_COMP 16 3510#define T3_QID_SW_TYPE2 17 3511 3512LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice, 3513 PT3_FWIMG_INFO pFwImg, 3514 LM_UINT32 LoadCpu, 3515 LM_UINT32 StartCpu); 3516 3517/******************************************************************************/ 3518/* NIC register read/write macros. */ 3519/******************************************************************************/ 3520 3521/* MAC register access. */ 3522LM_UINT32 LM_RegRd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register); 3523 3524LM_VOID LM_RegRdBack(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register); 3525 3526LM_VOID LM_RegWr(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, 3527 LM_UINT32 Value32, LM_UINT32 ReadBack); 3528 3529LM_UINT32 LM_RegRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register); 3530LM_VOID LM_RegWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, 3531 LM_UINT32 Value32); 3532 3533/* MAC memory access. */ 3534LM_UINT32 LM_MemRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr); 3535 3536LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, 3537 LM_UINT32 Value32); 3538 3539#define MB_REG_WR(pDevice, OffsetName, Value32) \ 3540 ((pDevice)->Flags & UNDI_FIX_FLAG) ? \ 3541 LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600, \ 3542 Value32) : \ 3543 (void) MM_MEMWRITEL(&((pDevice)->pMemView->OffsetName), Value32) 3544 3545#define MB_REG_RD(pDevice, OffsetName) \ 3546 (((pDevice)->Flags & UNDI_FIX_FLAG) ? \ 3547 LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600) : \ 3548 MM_MEMREADL(&((pDevice)->pMemView->OffsetName))) 3549 3550#define REG_RD(pDevice, OffsetName) \ 3551 LM_RegRd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)) 3552 3553#define REG_RD_BACK(pDevice, OffsetName) \ 3554 LM_RegRdBack(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)) 3555 3556#define REG_WR(pDevice, OffsetName, Value32) \ 3557 LM_RegWr(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName), Value32, TRUE) 3558 3559#define RAW_REG_WR(pDevice, OffsetName, Value32) \ 3560 LM_RegWr(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName), Value32, FALSE) 3561 3562#define REG_RD_OFFSET(pDevice, Offset) \ 3563 MM_MEMREADL(((LM_UINT8 *) (pDevice)->pMemView + Offset)) 3564 3565#define REG_WR_OFFSET(pDevice, Offset, Value32) \ 3566 MM_MEMWRITEL(((LM_UINT8 *) (pDevice)->pMemView + Offset), Value32) 3567 3568#define MEM_RD(pDevice, AddrName) \ 3569 LM_MemRdInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName)) 3570#define MEM_WR(pDevice, AddrName, Value32) \ 3571 LM_MemWrInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName), Value32) 3572 3573#define MEM_RD_OFFSET(pDevice, Offset) \ 3574 LM_MemRdInd(pDevice, Offset) 3575#define MEM_WR_OFFSET(pDevice, Offset, Value32) \ 3576 LM_MemWrInd(pDevice, Offset, Value32) 3577 3578 3579#endif /* TIGON3_H */ 3580 3581