1#ifndef B57MM_H 2#define B57MM_H 3 4#include <PCI.h> 5#include <Drivers.h> 6#include <OS.h> 7#include <ByteOrder.h> 8#include <KernelExport.h> 9 10typedef vint32 MM_ATOMIC_T; 11 12//#define MM_SWAP_LE16(x) B_SWAP_INT16(x) 13#define MM_SWAP_LE16(x) x 14#define MM_SWAP_LE32(x) x 15#define MM_SWAP_BE32(x) B_SWAP_INT32(x) 16 17/*#define MM_ATOMIC_SET(ptr, val) atomic_and(ptr, 0); atomic_add(ptr,val) 18#define MM_ATOMIC_READ(ptr) atomic_add(ptr,0) 19#define MM_ATOMIC_INC(ptr) atomic_add(ptr,1) 20#define MM_ATOMIC_ADD(ptr, val) atomic_add(ptr,val) 21#define MM_ATOMIC_DEC(ptr) atomic_add(ptr,-1) 22#define MM_ATOMIC_SUB(ptr, val) atomic_add(ptr,0-val)*/ 23 24#define MM_ATOMIC_SET(ptr, val) *(ptr)=val 25#define MM_ATOMIC_READ(ptr) *(ptr) 26#define MM_ATOMIC_INC(ptr) (*(ptr))++ 27#define MM_ATOMIC_ADD(ptr, val) *(ptr)+=val 28#define MM_ATOMIC_DEC(ptr) (*(ptr))-- 29#define MM_ATOMIC_SUB(ptr, val) *(ptr)-=val 30 31/* All critical sections are protected by locking mechanisms already */ 32 33#define __io_virt(x) ((void *)(x)) 34#define readl(addr) (*(volatile unsigned int *) __io_virt(addr)) 35#define writel(b,addr) (*(volatile unsigned int *) __io_virt(addr) = (b)) 36#define __raw_readl readl 37#define __raw_writel writel 38 39#define udelay spin 40 41#define MM_MEMWRITEL(ptr, val) __raw_writel(val, ptr) 42#define MM_MEMREADL(ptr) __raw_readl(ptr) 43 44#ifdef __INTEL__ 45#define mb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory") 46#else 47#ifdef __HAIKU__ 48#define mb() memory_write_barrier() 49#else 50#warning no memory barrier function defined. 51#define mb() 52#endif 53#endif 54#define wmb() mb() 55#define rmb() mb() 56 57#define readl(addr) (*(volatile unsigned int *) __io_virt(addr)) 58 59#define MM_MB() mb() 60#define MM_WMB() wmb() 61#define MM_RMB() rmb() 62 63#define STATIC static 64 65extern int b57_Packet_Desc_Size; 66 67#define MM_PACKET_DESC_SIZE b57_Packet_Desc_Size 68 69#include "lm.h" 70#include "queue.h" 71#include "tigon3.h" 72 73struct be_b57_dev { 74 struct _LM_DEVICE_BLOCK lm_dev; 75 76 struct pci_info pci_data; 77 78 sem_id packet_release_sem; 79 //sem_id interrupt_sem; 80 //thread_id interrupt_handler; 81 82 LM_RX_PACKET_Q RxPacketReadQ; 83 84 void *mem_list[16]; 85 int mem_list_num; 86 87 area_id lockmem_list[16]; 88 int lockmem_list_num; 89 90 area_id mem_base; 91 92 vint32 opened; 93 int block; 94 spinlock lock; 95 cpu_status cpu; 96 97#ifdef HAIKU_TARGET_PLATFORM_HAIKU 98 sem_id linkChangeSem; 99#endif 100}; 101 102struct B_UM_PACKET { 103 struct _LM_PACKET pkt; 104 105 void *data; 106 size_t size; 107}; 108 109static inline void MM_MapRxDma(PLM_DEVICE_BLOCK pDevice, 110 struct _LM_PACKET *pPacket, 111 T3_64BIT_HOST_ADDR *paddr) 112{ 113 physical_entry entry; 114 struct B_UM_PACKET *bpkt = (struct B_UM_PACKET *)(pPacket); 115 116 get_memory_map(bpkt->data,pPacket->u.Rx.RxBufferSize,&entry,1); 117 paddr->Low = (LM_UINT32)entry.address; 118 paddr->High = (LM_UINT32)(entry.address >> 32); 119} 120 121static inline void MM_MapTxDma(PLM_DEVICE_BLOCK pDevice, 122 struct _LM_PACKET *pPacket, 123 T3_64BIT_HOST_ADDR *paddr, LM_UINT32 *len, int frag) 124{ 125 struct B_UM_PACKET *pkt = (struct B_UM_PACKET *)pPacket; 126 physical_entry entry; 127 128 get_memory_map(pkt->data,pkt->size,&entry,1); 129 paddr->Low = (LM_UINT32)entry.address; 130 paddr->High = (LM_UINT32)(entry.address >> 32); 131 *len = pPacket->PacketSize; 132} 133 134#if (BITS_PER_LONG == 64) 135#define MM_GETSTATS(_Ctr) \ 136 (unsigned long) (_Ctr).Low + ((unsigned long) (_Ctr).High << 32) 137#else 138#define MM_GETSTATS(_Ctr) \ 139 (unsigned long) (_Ctr).Low 140#endif 141 142#define MM_ACQUIRE_UNDI_LOCK(_pDevice)/* \ 143 ((struct be_b57_dev *)(_pDevice))->cpu = disable_interrupts(); \ 144 acquire_spinlock(&(((struct be_b57_dev *)(_pDevice))->lock));*/ 145 146#define MM_RELEASE_UNDI_LOCK(_pDevice)/* \ 147 release_spinlock(&(((struct be_b57_dev *)(_pDevice))->lock)); \ 148 enable_interrupts(((struct be_b57_dev *)(_pDevice))->cpu);*/ 149 150#define MM_ACQUIRE_PHY_LOCK_IN_IRQ(_pDevice)/* \ 151 ((struct be_b57_dev *)(_pDevice))->cpu = disable_interrupts(); \ 152 acquire_spinlock(&(((struct be_b57_dev *)(_pDevice))->lock));*/ 153 154#define MM_RELEASE_PHY_LOCK_IN_IRQ(_pDevice) /*\ 155 release_spinlock(&(((struct be_b57_dev *)(_pDevice))->lock)); \ 156 enable_interrupts(((struct be_b57_dev *)(_pDevice))->cpu);*/ 157 158#define MM_PTR(_ptr) ((unsigned long) (_ptr)) 159#define MM_UINT_PTR(_ptr) ((unsigned long) (_ptr)) 160#define printf(fmt, args...) dprintf(fmt, ##args) 161#define DbgPrint(fmt, arg...) dprintf(fmt, ##arg) 162#define DbgBreakPoint() 163#define MM_Wait(time) udelay(time) 164#define ASSERT(expr) \ 165 if (!(expr)) { \ 166 dprintf("ASSERT failed: %s\n", #expr); \ 167 } 168 169#endif 170