1/*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD$"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/kernel.h> 38#include <sys/malloc.h> 39#include <sys/mbuf.h> 40#include <sys/rman.h> 41#include <sys/module.h> 42#include <sys/queue.h> 43#include <sys/socket.h> 44#include <sys/sockio.h> 45#include <sys/sysctl.h> 46#include <sys/taskqueue.h> 47 48#include <net/bpf.h> 49#include <net/if.h> 50#include <net/if_arp.h> 51#include <net/ethernet.h> 52#include <net/if_dl.h> 53#include <net/if_media.h> 54#include <net/if_types.h> 55#include <net/if_vlan_var.h> 56 57#include <netinet/in.h> 58#include <netinet/in_systm.h> 59#include <netinet/ip.h> 60#include <netinet/tcp.h> 61 62#include <dev/mii/mii.h> 63#include <dev/mii/miivar.h> 64 65#include <dev/pci/pcireg.h> 66#include <dev/pci/pcivar.h> 67 68#include <machine/bus.h> 69#include <machine/in_cksum.h> 70 71#include <dev/age/if_agereg.h> 72#include <dev/age/if_agevar.h> 73 74/* "device miibus" required. See GENERIC if you get errors here. */ 75#include "miibus_if.h" 76 77#define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 78 79MODULE_DEPEND(age, pci, 1, 1, 1); 80MODULE_DEPEND(age, ether, 1, 1, 1); 81MODULE_DEPEND(age, miibus, 1, 1, 1); 82 83/* Tunables. */ 84static int msi_disable = 0; 85static int msix_disable = 0; 86TUNABLE_INT("hw.age.msi_disable", &msi_disable); 87TUNABLE_INT("hw.age.msix_disable", &msix_disable); 88 89/* 90 * Devices supported by this driver. 91 */ 92static struct age_dev { 93 uint16_t age_vendorid; 94 uint16_t age_deviceid; 95 const char *age_name; 96} age_devs[] = { 97 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1, 98 "Attansic Technology Corp, L1 Gigabit Ethernet" }, 99}; 100 101static int age_miibus_readreg(device_t, int, int); 102static int age_miibus_writereg(device_t, int, int, int); 103static void age_miibus_statchg(device_t); 104static void age_mediastatus(struct ifnet *, struct ifmediareq *); 105static int age_mediachange(struct ifnet *); 106static int age_probe(device_t); 107static void age_get_macaddr(struct age_softc *); 108static void age_phy_reset(struct age_softc *); 109static int age_attach(device_t); 110static int age_detach(device_t); 111static void age_sysctl_node(struct age_softc *); 112static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int); 113static int age_check_boundary(struct age_softc *); 114static int age_dma_alloc(struct age_softc *); 115static void age_dma_free(struct age_softc *); 116static int age_shutdown(device_t); 117static void age_setwol(struct age_softc *); 118static int age_suspend(device_t); 119static int age_resume(device_t); 120static int age_encap(struct age_softc *, struct mbuf **); 121static void age_start(struct ifnet *); 122static void age_start_locked(struct ifnet *); 123static void age_watchdog(struct age_softc *); 124static int age_ioctl(struct ifnet *, u_long, caddr_t); 125static void age_mac_config(struct age_softc *); 126static void age_link_task(void *, int); 127static void age_stats_update(struct age_softc *); 128static int age_intr(void *); 129static void age_int_task(void *, int); 130static void age_txintr(struct age_softc *, int); 131static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 132static int age_rxintr(struct age_softc *, int, int); 133static void age_tick(void *); 134static void age_reset(struct age_softc *); 135static void age_init(void *); 136static void age_init_locked(struct age_softc *); 137static void age_stop(struct age_softc *); 138static void age_stop_txmac(struct age_softc *); 139static void age_stop_rxmac(struct age_softc *); 140static void age_init_tx_ring(struct age_softc *); 141static int age_init_rx_ring(struct age_softc *); 142static void age_init_rr_ring(struct age_softc *); 143static void age_init_cmb_block(struct age_softc *); 144static void age_init_smb_block(struct age_softc *); 145static int age_newbuf(struct age_softc *, struct age_rxdesc *); 146static void age_rxvlan(struct age_softc *); 147static void age_rxfilter(struct age_softc *); 148static int sysctl_age_stats(SYSCTL_HANDLER_ARGS); 149static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 150static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS); 151static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS); 152 153 154static device_method_t age_methods[] = { 155 /* Device interface. */ 156 DEVMETHOD(device_probe, age_probe), 157 DEVMETHOD(device_attach, age_attach), 158 DEVMETHOD(device_detach, age_detach), 159 DEVMETHOD(device_shutdown, age_shutdown), 160 DEVMETHOD(device_suspend, age_suspend), 161 DEVMETHOD(device_resume, age_resume), 162 163 /* MII interface. */ 164 DEVMETHOD(miibus_readreg, age_miibus_readreg), 165 DEVMETHOD(miibus_writereg, age_miibus_writereg), 166 DEVMETHOD(miibus_statchg, age_miibus_statchg), 167 168 { NULL, NULL } 169}; 170 171static driver_t age_driver = { 172 "age", 173 age_methods, 174 sizeof(struct age_softc) 175}; 176 177static devclass_t age_devclass; 178 179DRIVER_MODULE(age, pci, age_driver, age_devclass, 0, 0); 180DRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, 0, 0); 181 182static struct resource_spec age_res_spec_mem[] = { 183 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 184 { -1, 0, 0 } 185}; 186 187static struct resource_spec age_irq_spec_legacy[] = { 188 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 189 { -1, 0, 0 } 190}; 191 192static struct resource_spec age_irq_spec_msi[] = { 193 { SYS_RES_IRQ, 1, RF_ACTIVE }, 194 { -1, 0, 0 } 195}; 196 197static struct resource_spec age_irq_spec_msix[] = { 198 { SYS_RES_IRQ, 1, RF_ACTIVE }, 199 { -1, 0, 0 } 200}; 201 202/* 203 * Read a PHY register on the MII of the L1. 204 */ 205static int 206age_miibus_readreg(device_t dev, int phy, int reg) 207{ 208 struct age_softc *sc; 209 uint32_t v; 210 int i; 211 212 sc = device_get_softc(dev); 213 214 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 215 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 216 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 217 DELAY(1); 218 v = CSR_READ_4(sc, AGE_MDIO); 219 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 220 break; 221 } 222 223 if (i == 0) { 224 device_printf(sc->age_dev, "phy read timeout : %d\n", reg); 225 return (0); 226 } 227 228 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 229} 230 231/* 232 * Write a PHY register on the MII of the L1. 233 */ 234static int 235age_miibus_writereg(device_t dev, int phy, int reg, int val) 236{ 237 struct age_softc *sc; 238 uint32_t v; 239 int i; 240 241 sc = device_get_softc(dev); 242 243 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 244 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 245 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 246 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 247 DELAY(1); 248 v = CSR_READ_4(sc, AGE_MDIO); 249 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 250 break; 251 } 252 253 if (i == 0) 254 device_printf(sc->age_dev, "phy write timeout : %d\n", reg); 255 256 return (0); 257} 258 259/* 260 * Callback from MII layer when media changes. 261 */ 262static void 263age_miibus_statchg(device_t dev) 264{ 265 struct age_softc *sc; 266 267 sc = device_get_softc(dev); 268 taskqueue_enqueue(taskqueue_swi, &sc->age_link_task); 269} 270 271/* 272 * Get the current interface media status. 273 */ 274static void 275age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 276{ 277 struct age_softc *sc; 278 struct mii_data *mii; 279 280 sc = ifp->if_softc; 281 AGE_LOCK(sc); 282 mii = device_get_softc(sc->age_miibus); 283 284 mii_pollstat(mii); 285 ifmr->ifm_status = mii->mii_media_status; 286 ifmr->ifm_active = mii->mii_media_active; 287 AGE_UNLOCK(sc); 288} 289 290/* 291 * Set hardware to newly-selected media. 292 */ 293static int 294age_mediachange(struct ifnet *ifp) 295{ 296 struct age_softc *sc; 297 struct mii_data *mii; 298 struct mii_softc *miisc; 299 int error; 300 301 sc = ifp->if_softc; 302 AGE_LOCK(sc); 303 mii = device_get_softc(sc->age_miibus); 304 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 305 PHY_RESET(miisc); 306 error = mii_mediachg(mii); 307 AGE_UNLOCK(sc); 308 309 return (error); 310} 311 312static int 313age_probe(device_t dev) 314{ 315 struct age_dev *sp; 316 int i; 317 uint16_t vendor, devid; 318 319 vendor = pci_get_vendor(dev); 320 devid = pci_get_device(dev); 321 sp = age_devs; 322 for (i = 0; i < sizeof(age_devs) / sizeof(age_devs[0]); 323 i++, sp++) { 324 if (vendor == sp->age_vendorid && 325 devid == sp->age_deviceid) { 326 device_set_desc(dev, sp->age_name); 327 return (BUS_PROBE_DEFAULT); 328 } 329 } 330 331 return (ENXIO); 332} 333 334static void 335age_get_macaddr(struct age_softc *sc) 336{ 337 uint32_t ea[2], reg; 338 int i, vpdc; 339 340 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 341 if ((reg & SPI_VPD_ENB) != 0) { 342 /* Get VPD stored in TWSI EEPROM. */ 343 reg &= ~SPI_VPD_ENB; 344 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 345 } 346 347 if (pci_find_cap(sc->age_dev, PCIY_VPD, &vpdc) == 0) { 348 /* 349 * PCI VPD capability found, let TWSI reload EEPROM. 350 * This will set ethernet address of controller. 351 */ 352 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 353 TWSI_CTRL_SW_LD_START); 354 for (i = 100; i > 0; i--) { 355 DELAY(1000); 356 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 357 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 358 break; 359 } 360 if (i == 0) 361 device_printf(sc->age_dev, 362 "reloading EEPROM timeout!\n"); 363 } else { 364 if (bootverbose) 365 device_printf(sc->age_dev, 366 "PCI VPD capability not found!\n"); 367 } 368 369 ea[0] = CSR_READ_4(sc, AGE_PAR0); 370 ea[1] = CSR_READ_4(sc, AGE_PAR1); 371 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 372 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 373 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 374 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 375 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 376 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 377} 378 379static void 380age_phy_reset(struct age_softc *sc) 381{ 382 uint16_t reg, pn; 383 int i, linkup; 384 385 /* Reset PHY. */ 386 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 387 DELAY(2000); 388 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 389 DELAY(2000); 390 391#define ATPHY_DBG_ADDR 0x1D 392#define ATPHY_DBG_DATA 0x1E 393#define ATPHY_CDTC 0x16 394#define PHY_CDTC_ENB 0x0001 395#define PHY_CDTC_POFF 8 396#define ATPHY_CDTS 0x1C 397#define PHY_CDTS_STAT_OK 0x0000 398#define PHY_CDTS_STAT_SHORT 0x0100 399#define PHY_CDTS_STAT_OPEN 0x0200 400#define PHY_CDTS_STAT_INVAL 0x0300 401#define PHY_CDTS_STAT_MASK 0x0300 402 403 /* Check power saving mode. Magic from Linux. */ 404 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 405 for (linkup = 0, pn = 0; pn < 4; pn++) { 406 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC, 407 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 408 for (i = 200; i > 0; i--) { 409 DELAY(1000); 410 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 411 ATPHY_CDTC); 412 if ((reg & PHY_CDTC_ENB) == 0) 413 break; 414 } 415 DELAY(1000); 416 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 417 ATPHY_CDTS); 418 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 419 linkup++; 420 break; 421 } 422 } 423 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, 424 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 425 if (linkup == 0) { 426 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 427 ATPHY_DBG_ADDR, 0); 428 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 429 ATPHY_DBG_DATA, 0x124E); 430 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 431 ATPHY_DBG_ADDR, 1); 432 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 433 ATPHY_DBG_DATA); 434 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 435 ATPHY_DBG_DATA, reg | 0x03); 436 /* XXX */ 437 DELAY(1500 * 1000); 438 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 439 ATPHY_DBG_ADDR, 0); 440 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 441 ATPHY_DBG_DATA, 0x024E); 442 } 443 444#undef ATPHY_DBG_ADDR 445#undef ATPHY_DBG_DATA 446#undef ATPHY_CDTC 447#undef PHY_CDTC_ENB 448#undef PHY_CDTC_POFF 449#undef ATPHY_CDTS 450#undef PHY_CDTS_STAT_OK 451#undef PHY_CDTS_STAT_SHORT 452#undef PHY_CDTS_STAT_OPEN 453#undef PHY_CDTS_STAT_INVAL 454#undef PHY_CDTS_STAT_MASK 455} 456 457static int 458age_attach(device_t dev) 459{ 460 struct age_softc *sc; 461 struct ifnet *ifp; 462 uint16_t burst; 463 int error, i, msic, msixc, pmc; 464 465 error = 0; 466 sc = device_get_softc(dev); 467 sc->age_dev = dev; 468 469 mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 470 MTX_DEF); 471 callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0); 472 TASK_INIT(&sc->age_int_task, 0, age_int_task, sc); 473 TASK_INIT(&sc->age_link_task, 0, age_link_task, sc); 474 475 /* Map the device. */ 476 pci_enable_busmaster(dev); 477 sc->age_res_spec = age_res_spec_mem; 478 sc->age_irq_spec = age_irq_spec_legacy; 479 error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res); 480 if (error != 0) { 481 device_printf(dev, "cannot allocate memory resources.\n"); 482 goto fail; 483 } 484 485 /* Set PHY address. */ 486 sc->age_phyaddr = AGE_PHY_ADDR; 487 488 /* Reset PHY. */ 489 age_phy_reset(sc); 490 491 /* Reset the ethernet controller. */ 492 age_reset(sc); 493 494 /* Get PCI and chip id/revision. */ 495 sc->age_rev = pci_get_revid(dev); 496 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 497 MASTER_CHIP_REV_SHIFT; 498 if (bootverbose) { 499 device_printf(dev, "PCI device revision : 0x%04x\n", 500 sc->age_rev); 501 device_printf(dev, "Chip id/revision : 0x%04x\n", 502 sc->age_chip_rev); 503 } 504 505 /* 506 * XXX 507 * Unintialized hardware returns an invalid chip id/revision 508 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that 509 * unplugged cable results in putting hardware into automatic 510 * power down mode which in turn returns invalld chip revision. 511 */ 512 if (sc->age_chip_rev == 0xFFFF) { 513 device_printf(dev,"invalid chip revision : 0x%04x -- " 514 "not initialized?\n", sc->age_chip_rev); 515 error = ENXIO; 516 goto fail; 517 } 518 519 device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n", 520 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 521 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 522 523 /* Allocate IRQ resources. */ 524 msixc = pci_msix_count(dev); 525 msic = pci_msi_count(dev); 526 if (bootverbose) { 527 device_printf(dev, "MSIX count : %d\n", msixc); 528 device_printf(dev, "MSI count : %d\n", msic); 529 } 530 531 /* Prefer MSIX over MSI. */ 532 if (msix_disable == 0 || msi_disable == 0) { 533 if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES && 534 pci_alloc_msix(dev, &msixc) == 0) { 535 if (msic == AGE_MSIX_MESSAGES) { 536 device_printf(dev, "Using %d MSIX messages.\n", 537 msixc); 538 sc->age_flags |= AGE_FLAG_MSIX; 539 sc->age_irq_spec = age_irq_spec_msix; 540 } else 541 pci_release_msi(dev); 542 } 543 if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 && 544 msic == AGE_MSI_MESSAGES && 545 pci_alloc_msi(dev, &msic) == 0) { 546 if (msic == AGE_MSI_MESSAGES) { 547 device_printf(dev, "Using %d MSI messages.\n", 548 msic); 549 sc->age_flags |= AGE_FLAG_MSI; 550 sc->age_irq_spec = age_irq_spec_msi; 551 } else 552 pci_release_msi(dev); 553 } 554 } 555 556 error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq); 557 if (error != 0) { 558 device_printf(dev, "cannot allocate IRQ resources.\n"); 559 goto fail; 560 } 561 562 563 /* Get DMA parameters from PCIe device control register. */ 564 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 565 sc->age_flags |= AGE_FLAG_PCIE; 566 burst = pci_read_config(dev, i + 0x08, 2); 567 /* Max read request size. */ 568 sc->age_dma_rd_burst = ((burst >> 12) & 0x07) << 569 DMA_CFG_RD_BURST_SHIFT; 570 /* Max payload size. */ 571 sc->age_dma_wr_burst = ((burst >> 5) & 0x07) << 572 DMA_CFG_WR_BURST_SHIFT; 573 if (bootverbose) { 574 device_printf(dev, "Read request size : %d bytes.\n", 575 128 << ((burst >> 12) & 0x07)); 576 device_printf(dev, "TLP payload size : %d bytes.\n", 577 128 << ((burst >> 5) & 0x07)); 578 } 579 } else { 580 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 581 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 582 } 583 584 /* Create device sysctl node. */ 585 age_sysctl_node(sc); 586 587 if ((error = age_dma_alloc(sc) != 0)) 588 goto fail; 589 590 /* Load station address. */ 591 age_get_macaddr(sc); 592 593 ifp = sc->age_ifp = if_alloc(IFT_ETHER); 594 if (ifp == NULL) { 595 device_printf(dev, "cannot allocate ifnet structure.\n"); 596 error = ENXIO; 597 goto fail; 598 } 599 600 ifp->if_softc = sc; 601 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 602 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 603 ifp->if_ioctl = age_ioctl; 604 ifp->if_start = age_start; 605 ifp->if_init = age_init; 606 ifp->if_snd.ifq_drv_maxlen = AGE_TX_RING_CNT - 1; 607 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 608 IFQ_SET_READY(&ifp->if_snd); 609 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 610 ifp->if_hwassist = AGE_CSUM_FEATURES | CSUM_TSO; 611 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 612 sc->age_flags |= AGE_FLAG_PMCAP; 613 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 614 } 615 ifp->if_capenable = ifp->if_capabilities; 616 617 /* Set up MII bus. */ 618 error = mii_attach(dev, &sc->age_miibus, ifp, age_mediachange, 619 age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY, 620 0); 621 if (error != 0) { 622 device_printf(dev, "attaching PHYs failed\n"); 623 goto fail; 624 } 625 626 ether_ifattach(ifp, sc->age_eaddr); 627 628 /* VLAN capability setup. */ 629 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 630 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 631 ifp->if_capenable = ifp->if_capabilities; 632 633 /* Tell the upper layer(s) we support long frames. */ 634 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 635 636 /* Create local taskq. */ 637 sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK, 638 taskqueue_thread_enqueue, &sc->age_tq); 639 if (sc->age_tq == NULL) { 640 device_printf(dev, "could not create taskqueue.\n"); 641 ether_ifdetach(ifp); 642 error = ENXIO; 643 goto fail; 644 } 645 taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq", 646 device_get_nameunit(sc->age_dev)); 647 648 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 649 msic = AGE_MSIX_MESSAGES; 650 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 651 msic = AGE_MSI_MESSAGES; 652 else 653 msic = 1; 654 for (i = 0; i < msic; i++) { 655 error = bus_setup_intr(dev, sc->age_irq[i], 656 INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc, 657 &sc->age_intrhand[i]); 658 if (error != 0) 659 break; 660 } 661 if (error != 0) { 662 device_printf(dev, "could not set up interrupt handler.\n"); 663 taskqueue_free(sc->age_tq); 664 sc->age_tq = NULL; 665 ether_ifdetach(ifp); 666 goto fail; 667 } 668 669fail: 670 if (error != 0) 671 age_detach(dev); 672 673 return (error); 674} 675 676static int 677age_detach(device_t dev) 678{ 679 struct age_softc *sc; 680 struct ifnet *ifp; 681 int i, msic; 682 683 sc = device_get_softc(dev); 684 685 ifp = sc->age_ifp; 686 if (device_is_attached(dev)) { 687 AGE_LOCK(sc); 688 sc->age_flags |= AGE_FLAG_DETACH; 689 age_stop(sc); 690 AGE_UNLOCK(sc); 691 callout_drain(&sc->age_tick_ch); 692 taskqueue_drain(sc->age_tq, &sc->age_int_task); 693 taskqueue_drain(taskqueue_swi, &sc->age_link_task); 694 ether_ifdetach(ifp); 695 } 696 697 if (sc->age_tq != NULL) { 698 taskqueue_drain(sc->age_tq, &sc->age_int_task); 699 taskqueue_free(sc->age_tq); 700 sc->age_tq = NULL; 701 } 702 703 if (sc->age_miibus != NULL) { 704 device_delete_child(dev, sc->age_miibus); 705 sc->age_miibus = NULL; 706 } 707 bus_generic_detach(dev); 708 age_dma_free(sc); 709 710 if (ifp != NULL) { 711 if_free(ifp); 712 sc->age_ifp = NULL; 713 } 714 715 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 716 msic = AGE_MSIX_MESSAGES; 717 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 718 msic = AGE_MSI_MESSAGES; 719 else 720 msic = 1; 721 for (i = 0; i < msic; i++) { 722 if (sc->age_intrhand[i] != NULL) { 723 bus_teardown_intr(dev, sc->age_irq[i], 724 sc->age_intrhand[i]); 725 sc->age_intrhand[i] = NULL; 726 } 727 } 728 729 bus_release_resources(dev, sc->age_irq_spec, sc->age_irq); 730 if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0) 731 pci_release_msi(dev); 732 bus_release_resources(dev, sc->age_res_spec, sc->age_res); 733 mtx_destroy(&sc->age_mtx); 734 735 return (0); 736} 737 738static void 739age_sysctl_node(struct age_softc *sc) 740{ 741 int error; 742 743 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 744 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 745 "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_age_stats, 746 "I", "Statistics"); 747 748 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 749 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 750 "int_mod", CTLTYPE_INT | CTLFLAG_RW, &sc->age_int_mod, 0, 751 sysctl_hw_age_int_mod, "I", "age interrupt moderation"); 752 753 /* Pull in device tunables. */ 754 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 755 error = resource_int_value(device_get_name(sc->age_dev), 756 device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod); 757 if (error == 0) { 758 if (sc->age_int_mod < AGE_IM_TIMER_MIN || 759 sc->age_int_mod > AGE_IM_TIMER_MAX) { 760 device_printf(sc->age_dev, 761 "int_mod value out of range; using default: %d\n", 762 AGE_IM_TIMER_DEFAULT); 763 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 764 } 765 } 766 767 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 768 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 769 "process_limit", CTLTYPE_INT | CTLFLAG_RW, &sc->age_process_limit, 770 0, sysctl_hw_age_proc_limit, "I", 771 "max number of Rx events to process"); 772 773 /* Pull in device tunables. */ 774 sc->age_process_limit = AGE_PROC_DEFAULT; 775 error = resource_int_value(device_get_name(sc->age_dev), 776 device_get_unit(sc->age_dev), "process_limit", 777 &sc->age_process_limit); 778 if (error == 0) { 779 if (sc->age_process_limit < AGE_PROC_MIN || 780 sc->age_process_limit > AGE_PROC_MAX) { 781 device_printf(sc->age_dev, 782 "process_limit value out of range; " 783 "using default: %d\n", AGE_PROC_DEFAULT); 784 sc->age_process_limit = AGE_PROC_DEFAULT; 785 } 786 } 787} 788 789struct age_dmamap_arg { 790 bus_addr_t age_busaddr; 791}; 792 793static void 794age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 795{ 796 struct age_dmamap_arg *ctx; 797 798 if (error != 0) 799 return; 800 801 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 802 803 ctx = (struct age_dmamap_arg *)arg; 804 ctx->age_busaddr = segs[0].ds_addr; 805} 806 807/* 808 * Attansic L1 controller have single register to specify high 809 * address part of DMA blocks. So all descriptor structures and 810 * DMA memory blocks should have the same high address of given 811 * 4GB address space(i.e. crossing 4GB boundary is not allowed). 812 */ 813static int 814age_check_boundary(struct age_softc *sc) 815{ 816 bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end; 817 bus_addr_t cmb_block_end, smb_block_end; 818 819 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 820 tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ; 821 rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ; 822 rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ; 823 cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ; 824 smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ; 825 826 if ((AGE_ADDR_HI(tx_ring_end) != 827 AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) || 828 (AGE_ADDR_HI(rx_ring_end) != 829 AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) || 830 (AGE_ADDR_HI(rr_ring_end) != 831 AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) || 832 (AGE_ADDR_HI(cmb_block_end) != 833 AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) || 834 (AGE_ADDR_HI(smb_block_end) != 835 AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr))) 836 return (EFBIG); 837 838 if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) || 839 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) || 840 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) || 841 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end))) 842 return (EFBIG); 843 844 return (0); 845} 846 847static int 848age_dma_alloc(struct age_softc *sc) 849{ 850 struct age_txdesc *txd; 851 struct age_rxdesc *rxd; 852 bus_addr_t lowaddr; 853 struct age_dmamap_arg ctx; 854 int error, i; 855 856 lowaddr = BUS_SPACE_MAXADDR; 857 858again: 859 /* Create parent ring/DMA block tag. */ 860 error = bus_dma_tag_create( 861 bus_get_dma_tag(sc->age_dev), /* parent */ 862 1, 0, /* alignment, boundary */ 863 lowaddr, /* lowaddr */ 864 BUS_SPACE_MAXADDR, /* highaddr */ 865 NULL, NULL, /* filter, filterarg */ 866 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 867 0, /* nsegments */ 868 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 869 0, /* flags */ 870 NULL, NULL, /* lockfunc, lockarg */ 871 &sc->age_cdata.age_parent_tag); 872 if (error != 0) { 873 device_printf(sc->age_dev, 874 "could not create parent DMA tag.\n"); 875 goto fail; 876 } 877 878 /* Create tag for Tx ring. */ 879 error = bus_dma_tag_create( 880 sc->age_cdata.age_parent_tag, /* parent */ 881 AGE_TX_RING_ALIGN, 0, /* alignment, boundary */ 882 BUS_SPACE_MAXADDR, /* lowaddr */ 883 BUS_SPACE_MAXADDR, /* highaddr */ 884 NULL, NULL, /* filter, filterarg */ 885 AGE_TX_RING_SZ, /* maxsize */ 886 1, /* nsegments */ 887 AGE_TX_RING_SZ, /* maxsegsize */ 888 0, /* flags */ 889 NULL, NULL, /* lockfunc, lockarg */ 890 &sc->age_cdata.age_tx_ring_tag); 891 if (error != 0) { 892 device_printf(sc->age_dev, 893 "could not create Tx ring DMA tag.\n"); 894 goto fail; 895 } 896 897 /* Create tag for Rx ring. */ 898 error = bus_dma_tag_create( 899 sc->age_cdata.age_parent_tag, /* parent */ 900 AGE_RX_RING_ALIGN, 0, /* alignment, boundary */ 901 BUS_SPACE_MAXADDR, /* lowaddr */ 902 BUS_SPACE_MAXADDR, /* highaddr */ 903 NULL, NULL, /* filter, filterarg */ 904 AGE_RX_RING_SZ, /* maxsize */ 905 1, /* nsegments */ 906 AGE_RX_RING_SZ, /* maxsegsize */ 907 0, /* flags */ 908 NULL, NULL, /* lockfunc, lockarg */ 909 &sc->age_cdata.age_rx_ring_tag); 910 if (error != 0) { 911 device_printf(sc->age_dev, 912 "could not create Rx ring DMA tag.\n"); 913 goto fail; 914 } 915 916 /* Create tag for Rx return ring. */ 917 error = bus_dma_tag_create( 918 sc->age_cdata.age_parent_tag, /* parent */ 919 AGE_RR_RING_ALIGN, 0, /* alignment, boundary */ 920 BUS_SPACE_MAXADDR, /* lowaddr */ 921 BUS_SPACE_MAXADDR, /* highaddr */ 922 NULL, NULL, /* filter, filterarg */ 923 AGE_RR_RING_SZ, /* maxsize */ 924 1, /* nsegments */ 925 AGE_RR_RING_SZ, /* maxsegsize */ 926 0, /* flags */ 927 NULL, NULL, /* lockfunc, lockarg */ 928 &sc->age_cdata.age_rr_ring_tag); 929 if (error != 0) { 930 device_printf(sc->age_dev, 931 "could not create Rx return ring DMA tag.\n"); 932 goto fail; 933 } 934 935 /* Create tag for coalesing message block. */ 936 error = bus_dma_tag_create( 937 sc->age_cdata.age_parent_tag, /* parent */ 938 AGE_CMB_ALIGN, 0, /* alignment, boundary */ 939 BUS_SPACE_MAXADDR, /* lowaddr */ 940 BUS_SPACE_MAXADDR, /* highaddr */ 941 NULL, NULL, /* filter, filterarg */ 942 AGE_CMB_BLOCK_SZ, /* maxsize */ 943 1, /* nsegments */ 944 AGE_CMB_BLOCK_SZ, /* maxsegsize */ 945 0, /* flags */ 946 NULL, NULL, /* lockfunc, lockarg */ 947 &sc->age_cdata.age_cmb_block_tag); 948 if (error != 0) { 949 device_printf(sc->age_dev, 950 "could not create CMB DMA tag.\n"); 951 goto fail; 952 } 953 954 /* Create tag for statistics message block. */ 955 error = bus_dma_tag_create( 956 sc->age_cdata.age_parent_tag, /* parent */ 957 AGE_SMB_ALIGN, 0, /* alignment, boundary */ 958 BUS_SPACE_MAXADDR, /* lowaddr */ 959 BUS_SPACE_MAXADDR, /* highaddr */ 960 NULL, NULL, /* filter, filterarg */ 961 AGE_SMB_BLOCK_SZ, /* maxsize */ 962 1, /* nsegments */ 963 AGE_SMB_BLOCK_SZ, /* maxsegsize */ 964 0, /* flags */ 965 NULL, NULL, /* lockfunc, lockarg */ 966 &sc->age_cdata.age_smb_block_tag); 967 if (error != 0) { 968 device_printf(sc->age_dev, 969 "could not create SMB DMA tag.\n"); 970 goto fail; 971 } 972 973 /* Allocate DMA'able memory and load the DMA map. */ 974 error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag, 975 (void **)&sc->age_rdata.age_tx_ring, 976 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 977 &sc->age_cdata.age_tx_ring_map); 978 if (error != 0) { 979 device_printf(sc->age_dev, 980 "could not allocate DMA'able memory for Tx ring.\n"); 981 goto fail; 982 } 983 ctx.age_busaddr = 0; 984 error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag, 985 sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring, 986 AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0); 987 if (error != 0 || ctx.age_busaddr == 0) { 988 device_printf(sc->age_dev, 989 "could not load DMA'able memory for Tx ring.\n"); 990 goto fail; 991 } 992 sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr; 993 /* Rx ring */ 994 error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag, 995 (void **)&sc->age_rdata.age_rx_ring, 996 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 997 &sc->age_cdata.age_rx_ring_map); 998 if (error != 0) { 999 device_printf(sc->age_dev, 1000 "could not allocate DMA'able memory for Rx ring.\n"); 1001 goto fail; 1002 } 1003 ctx.age_busaddr = 0; 1004 error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag, 1005 sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring, 1006 AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0); 1007 if (error != 0 || ctx.age_busaddr == 0) { 1008 device_printf(sc->age_dev, 1009 "could not load DMA'able memory for Rx ring.\n"); 1010 goto fail; 1011 } 1012 sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr; 1013 /* Rx return ring */ 1014 error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag, 1015 (void **)&sc->age_rdata.age_rr_ring, 1016 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1017 &sc->age_cdata.age_rr_ring_map); 1018 if (error != 0) { 1019 device_printf(sc->age_dev, 1020 "could not allocate DMA'able memory for Rx return ring.\n"); 1021 goto fail; 1022 } 1023 ctx.age_busaddr = 0; 1024 error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag, 1025 sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring, 1026 AGE_RR_RING_SZ, age_dmamap_cb, 1027 &ctx, 0); 1028 if (error != 0 || ctx.age_busaddr == 0) { 1029 device_printf(sc->age_dev, 1030 "could not load DMA'able memory for Rx return ring.\n"); 1031 goto fail; 1032 } 1033 sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr; 1034 /* CMB block */ 1035 error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag, 1036 (void **)&sc->age_rdata.age_cmb_block, 1037 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1038 &sc->age_cdata.age_cmb_block_map); 1039 if (error != 0) { 1040 device_printf(sc->age_dev, 1041 "could not allocate DMA'able memory for CMB block.\n"); 1042 goto fail; 1043 } 1044 ctx.age_busaddr = 0; 1045 error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag, 1046 sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block, 1047 AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1048 if (error != 0 || ctx.age_busaddr == 0) { 1049 device_printf(sc->age_dev, 1050 "could not load DMA'able memory for CMB block.\n"); 1051 goto fail; 1052 } 1053 sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr; 1054 /* SMB block */ 1055 error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag, 1056 (void **)&sc->age_rdata.age_smb_block, 1057 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1058 &sc->age_cdata.age_smb_block_map); 1059 if (error != 0) { 1060 device_printf(sc->age_dev, 1061 "could not allocate DMA'able memory for SMB block.\n"); 1062 goto fail; 1063 } 1064 ctx.age_busaddr = 0; 1065 error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag, 1066 sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block, 1067 AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1068 if (error != 0 || ctx.age_busaddr == 0) { 1069 device_printf(sc->age_dev, 1070 "could not load DMA'able memory for SMB block.\n"); 1071 goto fail; 1072 } 1073 sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr; 1074 1075 /* 1076 * All ring buffer and DMA blocks should have the same 1077 * high address part of 64bit DMA address space. 1078 */ 1079 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1080 (error = age_check_boundary(sc)) != 0) { 1081 device_printf(sc->age_dev, "4GB boundary crossed, " 1082 "switching to 32bit DMA addressing mode.\n"); 1083 age_dma_free(sc); 1084 /* Limit DMA address space to 32bit and try again. */ 1085 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1086 goto again; 1087 } 1088 1089 /* 1090 * Create Tx/Rx buffer parent tag. 1091 * L1 supports full 64bit DMA addressing in Tx/Rx buffers 1092 * so it needs separate parent DMA tag. 1093 * XXX 1094 * It seems enabling 64bit DMA causes data corruption. Limit 1095 * DMA address space to 32bit. 1096 */ 1097 error = bus_dma_tag_create( 1098 bus_get_dma_tag(sc->age_dev), /* parent */ 1099 1, 0, /* alignment, boundary */ 1100 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1101 BUS_SPACE_MAXADDR, /* highaddr */ 1102 NULL, NULL, /* filter, filterarg */ 1103 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1104 0, /* nsegments */ 1105 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1106 0, /* flags */ 1107 NULL, NULL, /* lockfunc, lockarg */ 1108 &sc->age_cdata.age_buffer_tag); 1109 if (error != 0) { 1110 device_printf(sc->age_dev, 1111 "could not create parent buffer DMA tag.\n"); 1112 goto fail; 1113 } 1114 1115 /* Create tag for Tx buffers. */ 1116 error = bus_dma_tag_create( 1117 sc->age_cdata.age_buffer_tag, /* parent */ 1118 1, 0, /* alignment, boundary */ 1119 BUS_SPACE_MAXADDR, /* lowaddr */ 1120 BUS_SPACE_MAXADDR, /* highaddr */ 1121 NULL, NULL, /* filter, filterarg */ 1122 AGE_TSO_MAXSIZE, /* maxsize */ 1123 AGE_MAXTXSEGS, /* nsegments */ 1124 AGE_TSO_MAXSEGSIZE, /* maxsegsize */ 1125 0, /* flags */ 1126 NULL, NULL, /* lockfunc, lockarg */ 1127 &sc->age_cdata.age_tx_tag); 1128 if (error != 0) { 1129 device_printf(sc->age_dev, "could not create Tx DMA tag.\n"); 1130 goto fail; 1131 } 1132 1133 /* Create tag for Rx buffers. */ 1134 error = bus_dma_tag_create( 1135 sc->age_cdata.age_buffer_tag, /* parent */ 1136 1, 0, /* alignment, boundary */ 1137 BUS_SPACE_MAXADDR, /* lowaddr */ 1138 BUS_SPACE_MAXADDR, /* highaddr */ 1139 NULL, NULL, /* filter, filterarg */ 1140 MCLBYTES, /* maxsize */ 1141 1, /* nsegments */ 1142 MCLBYTES, /* maxsegsize */ 1143 0, /* flags */ 1144 NULL, NULL, /* lockfunc, lockarg */ 1145 &sc->age_cdata.age_rx_tag); 1146 if (error != 0) { 1147 device_printf(sc->age_dev, "could not create Rx DMA tag.\n"); 1148 goto fail; 1149 } 1150 1151 /* Create DMA maps for Tx buffers. */ 1152 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1153 txd = &sc->age_cdata.age_txdesc[i]; 1154 txd->tx_m = NULL; 1155 txd->tx_dmamap = NULL; 1156 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0, 1157 &txd->tx_dmamap); 1158 if (error != 0) { 1159 device_printf(sc->age_dev, 1160 "could not create Tx dmamap.\n"); 1161 goto fail; 1162 } 1163 } 1164 /* Create DMA maps for Rx buffers. */ 1165 if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1166 &sc->age_cdata.age_rx_sparemap)) != 0) { 1167 device_printf(sc->age_dev, 1168 "could not create spare Rx dmamap.\n"); 1169 goto fail; 1170 } 1171 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1172 rxd = &sc->age_cdata.age_rxdesc[i]; 1173 rxd->rx_m = NULL; 1174 rxd->rx_dmamap = NULL; 1175 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1176 &rxd->rx_dmamap); 1177 if (error != 0) { 1178 device_printf(sc->age_dev, 1179 "could not create Rx dmamap.\n"); 1180 goto fail; 1181 } 1182 } 1183 1184fail: 1185 return (error); 1186} 1187 1188static void 1189age_dma_free(struct age_softc *sc) 1190{ 1191 struct age_txdesc *txd; 1192 struct age_rxdesc *rxd; 1193 int i; 1194 1195 /* Tx buffers */ 1196 if (sc->age_cdata.age_tx_tag != NULL) { 1197 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1198 txd = &sc->age_cdata.age_txdesc[i]; 1199 if (txd->tx_dmamap != NULL) { 1200 bus_dmamap_destroy(sc->age_cdata.age_tx_tag, 1201 txd->tx_dmamap); 1202 txd->tx_dmamap = NULL; 1203 } 1204 } 1205 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag); 1206 sc->age_cdata.age_tx_tag = NULL; 1207 } 1208 /* Rx buffers */ 1209 if (sc->age_cdata.age_rx_tag != NULL) { 1210 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1211 rxd = &sc->age_cdata.age_rxdesc[i]; 1212 if (rxd->rx_dmamap != NULL) { 1213 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1214 rxd->rx_dmamap); 1215 rxd->rx_dmamap = NULL; 1216 } 1217 } 1218 if (sc->age_cdata.age_rx_sparemap != NULL) { 1219 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1220 sc->age_cdata.age_rx_sparemap); 1221 sc->age_cdata.age_rx_sparemap = NULL; 1222 } 1223 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag); 1224 sc->age_cdata.age_rx_tag = NULL; 1225 } 1226 /* Tx ring. */ 1227 if (sc->age_cdata.age_tx_ring_tag != NULL) { 1228 if (sc->age_cdata.age_tx_ring_map != NULL) 1229 bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag, 1230 sc->age_cdata.age_tx_ring_map); 1231 if (sc->age_cdata.age_tx_ring_map != NULL && 1232 sc->age_rdata.age_tx_ring != NULL) 1233 bus_dmamem_free(sc->age_cdata.age_tx_ring_tag, 1234 sc->age_rdata.age_tx_ring, 1235 sc->age_cdata.age_tx_ring_map); 1236 sc->age_rdata.age_tx_ring = NULL; 1237 sc->age_cdata.age_tx_ring_map = NULL; 1238 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag); 1239 sc->age_cdata.age_tx_ring_tag = NULL; 1240 } 1241 /* Rx ring. */ 1242 if (sc->age_cdata.age_rx_ring_tag != NULL) { 1243 if (sc->age_cdata.age_rx_ring_map != NULL) 1244 bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag, 1245 sc->age_cdata.age_rx_ring_map); 1246 if (sc->age_cdata.age_rx_ring_map != NULL && 1247 sc->age_rdata.age_rx_ring != NULL) 1248 bus_dmamem_free(sc->age_cdata.age_rx_ring_tag, 1249 sc->age_rdata.age_rx_ring, 1250 sc->age_cdata.age_rx_ring_map); 1251 sc->age_rdata.age_rx_ring = NULL; 1252 sc->age_cdata.age_rx_ring_map = NULL; 1253 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag); 1254 sc->age_cdata.age_rx_ring_tag = NULL; 1255 } 1256 /* Rx return ring. */ 1257 if (sc->age_cdata.age_rr_ring_tag != NULL) { 1258 if (sc->age_cdata.age_rr_ring_map != NULL) 1259 bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag, 1260 sc->age_cdata.age_rr_ring_map); 1261 if (sc->age_cdata.age_rr_ring_map != NULL && 1262 sc->age_rdata.age_rr_ring != NULL) 1263 bus_dmamem_free(sc->age_cdata.age_rr_ring_tag, 1264 sc->age_rdata.age_rr_ring, 1265 sc->age_cdata.age_rr_ring_map); 1266 sc->age_rdata.age_rr_ring = NULL; 1267 sc->age_cdata.age_rr_ring_map = NULL; 1268 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag); 1269 sc->age_cdata.age_rr_ring_tag = NULL; 1270 } 1271 /* CMB block */ 1272 if (sc->age_cdata.age_cmb_block_tag != NULL) { 1273 if (sc->age_cdata.age_cmb_block_map != NULL) 1274 bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag, 1275 sc->age_cdata.age_cmb_block_map); 1276 if (sc->age_cdata.age_cmb_block_map != NULL && 1277 sc->age_rdata.age_cmb_block != NULL) 1278 bus_dmamem_free(sc->age_cdata.age_cmb_block_tag, 1279 sc->age_rdata.age_cmb_block, 1280 sc->age_cdata.age_cmb_block_map); 1281 sc->age_rdata.age_cmb_block = NULL; 1282 sc->age_cdata.age_cmb_block_map = NULL; 1283 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag); 1284 sc->age_cdata.age_cmb_block_tag = NULL; 1285 } 1286 /* SMB block */ 1287 if (sc->age_cdata.age_smb_block_tag != NULL) { 1288 if (sc->age_cdata.age_smb_block_map != NULL) 1289 bus_dmamap_unload(sc->age_cdata.age_smb_block_tag, 1290 sc->age_cdata.age_smb_block_map); 1291 if (sc->age_cdata.age_smb_block_map != NULL && 1292 sc->age_rdata.age_smb_block != NULL) 1293 bus_dmamem_free(sc->age_cdata.age_smb_block_tag, 1294 sc->age_rdata.age_smb_block, 1295 sc->age_cdata.age_smb_block_map); 1296 sc->age_rdata.age_smb_block = NULL; 1297 sc->age_cdata.age_smb_block_map = NULL; 1298 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag); 1299 sc->age_cdata.age_smb_block_tag = NULL; 1300 } 1301 1302 if (sc->age_cdata.age_buffer_tag != NULL) { 1303 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag); 1304 sc->age_cdata.age_buffer_tag = NULL; 1305 } 1306 if (sc->age_cdata.age_parent_tag != NULL) { 1307 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag); 1308 sc->age_cdata.age_parent_tag = NULL; 1309 } 1310} 1311 1312/* 1313 * Make sure the interface is stopped at reboot time. 1314 */ 1315static int 1316age_shutdown(device_t dev) 1317{ 1318 1319 return (age_suspend(dev)); 1320} 1321 1322static void 1323age_setwol(struct age_softc *sc) 1324{ 1325 struct ifnet *ifp; 1326 struct mii_data *mii; 1327 uint32_t reg, pmcs; 1328 uint16_t pmstat; 1329 int aneg, i, pmc; 1330 1331 AGE_LOCK_ASSERT(sc); 1332 1333 if (pci_find_cap(sc->age_dev, PCIY_PMG, &pmc) != 0) { 1334 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1335 /* 1336 * No PME capability, PHY power down. 1337 * XXX 1338 * Due to an unknown reason powering down PHY resulted 1339 * in unexpected results such as inaccessbility of 1340 * hardware of freshly rebooted system. Disable 1341 * powering down PHY until I got more information for 1342 * Attansic/Atheros PHY hardwares. 1343 */ 1344#ifdef notyet 1345 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1346 MII_BMCR, BMCR_PDOWN); 1347#endif 1348 return; 1349 } 1350 1351 ifp = sc->age_ifp; 1352 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1353 /* 1354 * Note, this driver resets the link speed to 10/100Mbps with 1355 * auto-negotiation but we don't know whether that operation 1356 * would succeed or not as it have no control after powering 1357 * off. If the renegotiation fail WOL may not work. Running 1358 * at 1Gbps will draw more power than 375mA at 3.3V which is 1359 * specified in PCI specification and that would result in 1360 * complete shutdowning power to ethernet controller. 1361 * 1362 * TODO 1363 * Save current negotiated media speed/duplex/flow-control 1364 * to softc and restore the same link again after resuming. 1365 * PHY handling such as power down/resetting to 100Mbps 1366 * may be better handled in suspend method in phy driver. 1367 */ 1368 mii = device_get_softc(sc->age_miibus); 1369 mii_pollstat(mii); 1370 aneg = 0; 1371 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1372 switch IFM_SUBTYPE(mii->mii_media_active) { 1373 case IFM_10_T: 1374 case IFM_100_TX: 1375 goto got_link; 1376 case IFM_1000_T: 1377 aneg++; 1378 default: 1379 break; 1380 } 1381 } 1382 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1383 MII_100T2CR, 0); 1384 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1385 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | 1386 ANAR_10 | ANAR_CSMA); 1387 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1388 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1389 DELAY(1000); 1390 if (aneg != 0) { 1391 /* Poll link state until age(4) get a 10/100 link. */ 1392 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1393 mii_pollstat(mii); 1394 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1395 switch (IFM_SUBTYPE( 1396 mii->mii_media_active)) { 1397 case IFM_10_T: 1398 case IFM_100_TX: 1399 age_mac_config(sc); 1400 goto got_link; 1401 default: 1402 break; 1403 } 1404 } 1405 AGE_UNLOCK(sc); 1406#ifdef __HAIKU__ 1407 DELAY(1); 1408#else 1409 pause("agelnk", hz); 1410#endif 1411 AGE_LOCK(sc); 1412 } 1413 if (i == MII_ANEGTICKS_GIGE) 1414 device_printf(sc->age_dev, 1415 "establishing link failed, " 1416 "WOL may not work!"); 1417 } 1418 /* 1419 * No link, force MAC to have 100Mbps, full-duplex link. 1420 * This is the last resort and may/may not work. 1421 */ 1422 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1423 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1424 age_mac_config(sc); 1425 } 1426 1427got_link: 1428 pmcs = 0; 1429 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1430 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1431 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); 1432 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1433 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC); 1434 reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST); 1435 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1436 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1437 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1438 reg |= MAC_CFG_RX_ENB; 1439 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1440 } 1441 1442 /* Request PME. */ 1443 pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2); 1444 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1445 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1446 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1447 pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1448#ifdef notyet 1449 /* See above for powering down PHY issues. */ 1450 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1451 /* No WOL, PHY power down. */ 1452 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1453 MII_BMCR, BMCR_PDOWN); 1454 } 1455#endif 1456} 1457 1458static int 1459age_suspend(device_t dev) 1460{ 1461 struct age_softc *sc; 1462 1463 sc = device_get_softc(dev); 1464 1465 AGE_LOCK(sc); 1466 age_stop(sc); 1467 age_setwol(sc); 1468 AGE_UNLOCK(sc); 1469 1470 return (0); 1471} 1472 1473static int 1474age_resume(device_t dev) 1475{ 1476 struct age_softc *sc; 1477 struct ifnet *ifp; 1478 1479 sc = device_get_softc(dev); 1480 1481 AGE_LOCK(sc); 1482 age_phy_reset(sc); 1483 ifp = sc->age_ifp; 1484 if ((ifp->if_flags & IFF_UP) != 0) 1485 age_init_locked(sc); 1486 1487 AGE_UNLOCK(sc); 1488 1489 return (0); 1490} 1491 1492static int 1493age_encap(struct age_softc *sc, struct mbuf **m_head) 1494{ 1495 struct age_txdesc *txd, *txd_last; 1496 struct tx_desc *desc; 1497 struct mbuf *m; 1498 struct ip *ip; 1499 struct tcphdr *tcp; 1500 bus_dma_segment_t txsegs[AGE_MAXTXSEGS]; 1501 bus_dmamap_t map; 1502 uint32_t cflags, ip_off, poff, vtag; 1503 int error, i, nsegs, prod, si; 1504 1505 AGE_LOCK_ASSERT(sc); 1506 1507 M_ASSERTPKTHDR((*m_head)); 1508 1509 m = *m_head; 1510 ip = NULL; 1511 tcp = NULL; 1512 cflags = vtag = 0; 1513 ip_off = poff = 0; 1514 if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1515 /* 1516 * L1 requires offset of TCP/UDP payload in its Tx 1517 * descriptor to perform hardware Tx checksum offload. 1518 * Additionally, TSO requires IP/TCP header size and 1519 * modification of IP/TCP header in order to make TSO 1520 * engine work. This kind of operation takes many CPU 1521 * cycles on FreeBSD so fast host CPU is needed to get 1522 * smooth TSO performance. 1523 */ 1524 struct ether_header *eh; 1525 1526 if (M_WRITABLE(m) == 0) { 1527 /* Get a writable copy. */ 1528 m = m_dup(*m_head, M_DONTWAIT); 1529 /* Release original mbufs. */ 1530 m_freem(*m_head); 1531 if (m == NULL) { 1532 *m_head = NULL; 1533 return (ENOBUFS); 1534 } 1535 *m_head = m; 1536 } 1537 ip_off = sizeof(struct ether_header); 1538 m = m_pullup(m, ip_off); 1539 if (m == NULL) { 1540 *m_head = NULL; 1541 return (ENOBUFS); 1542 } 1543 eh = mtod(m, struct ether_header *); 1544 /* 1545 * Check if hardware VLAN insertion is off. 1546 * Additional check for LLC/SNAP frame? 1547 */ 1548 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1549 ip_off = sizeof(struct ether_vlan_header); 1550 m = m_pullup(m, ip_off); 1551 if (m == NULL) { 1552 *m_head = NULL; 1553 return (ENOBUFS); 1554 } 1555 } 1556 m = m_pullup(m, ip_off + sizeof(struct ip)); 1557 if (m == NULL) { 1558 *m_head = NULL; 1559 return (ENOBUFS); 1560 } 1561 ip = (struct ip *)(mtod(m, char *) + ip_off); 1562 poff = ip_off + (ip->ip_hl << 2); 1563 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1564 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1565 if (m == NULL) { 1566 *m_head = NULL; 1567 return (ENOBUFS); 1568 } 1569 ip = (struct ip *)(mtod(m, char *) + ip_off); 1570 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1571 /* 1572 * L1 requires IP/TCP header size and offset as 1573 * well as TCP pseudo checksum which complicates 1574 * TSO configuration. I guess this comes from the 1575 * adherence to Microsoft NDIS Large Send 1576 * specification which requires insertion of 1577 * pseudo checksum by upper stack. The pseudo 1578 * checksum that NDIS refers to doesn't include 1579 * TCP payload length so age(4) should recompute 1580 * the pseudo checksum here. Hopefully this wouldn't 1581 * be much burden on modern CPUs. 1582 * Reset IP checksum and recompute TCP pseudo 1583 * checksum as NDIS specification said. 1584 */ 1585 ip->ip_sum = 0; 1586 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) 1587 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1588 ip->ip_dst.s_addr, 1589 htons((tcp->th_off << 2) + IPPROTO_TCP)); 1590 else 1591 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1592 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1593 } 1594 *m_head = m; 1595 } 1596 1597 si = prod = sc->age_cdata.age_tx_prod; 1598 txd = &sc->age_cdata.age_txdesc[prod]; 1599 txd_last = txd; 1600 map = txd->tx_dmamap; 1601 1602 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1603 *m_head, txsegs, &nsegs, 0); 1604 if (error == EFBIG) { 1605 m = m_collapse(*m_head, M_DONTWAIT, AGE_MAXTXSEGS); 1606 if (m == NULL) { 1607 m_freem(*m_head); 1608 *m_head = NULL; 1609 return (ENOMEM); 1610 } 1611 *m_head = m; 1612 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1613 *m_head, txsegs, &nsegs, 0); 1614 if (error != 0) { 1615 m_freem(*m_head); 1616 *m_head = NULL; 1617 return (error); 1618 } 1619 } else if (error != 0) 1620 return (error); 1621 if (nsegs == 0) { 1622 m_freem(*m_head); 1623 *m_head = NULL; 1624 return (EIO); 1625 } 1626 1627 /* Check descriptor overrun. */ 1628 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1629 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map); 1630 return (ENOBUFS); 1631 } 1632 1633 m = *m_head; 1634 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1635 /* Configure TSO. */ 1636 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) { 1637 /* Not TSO but IP/TCP checksum offload. */ 1638 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1639 /* Clear TSO in order not to set AGE_TD_TSO_HDR. */ 1640 m->m_pkthdr.csum_flags &= ~CSUM_TSO; 1641 } else { 1642 /* Request TSO and set MSS. */ 1643 cflags |= AGE_TD_TSO_IPV4; 1644 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1645 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << 1646 AGE_TD_TSO_MSS_SHIFT); 1647 } 1648 /* Set IP/TCP header size. */ 1649 cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT; 1650 cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT; 1651 } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1652 /* Configure Tx IP/TCP/UDP checksum offload. */ 1653 cflags |= AGE_TD_CSUM; 1654 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1655 cflags |= AGE_TD_TCPCSUM; 1656 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1657 cflags |= AGE_TD_UDPCSUM; 1658 /* Set checksum start offset. */ 1659 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1660 /* Set checksum insertion position of TCP/UDP. */ 1661 cflags |= ((poff + m->m_pkthdr.csum_data) << 1662 AGE_TD_CSUM_XSUMOFFSET_SHIFT); 1663 } 1664 1665 /* Configure VLAN hardware tag insertion. */ 1666 if ((m->m_flags & M_VLANTAG) != 0) { 1667 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1668 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1669 cflags |= AGE_TD_INSERT_VLAN_TAG; 1670 } 1671 1672 desc = NULL; 1673 for (i = 0; i < nsegs; i++) { 1674 desc = &sc->age_rdata.age_tx_ring[prod]; 1675 desc->addr = htole64(txsegs[i].ds_addr); 1676 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag); 1677 desc->flags = htole32(cflags); 1678 sc->age_cdata.age_tx_cnt++; 1679 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1680 } 1681 /* Update producer index. */ 1682 sc->age_cdata.age_tx_prod = prod; 1683 1684 /* Set EOP on the last descriptor. */ 1685 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1686 desc = &sc->age_rdata.age_tx_ring[prod]; 1687 desc->flags |= htole32(AGE_TD_EOP); 1688 1689 /* Lastly set TSO header and modify IP/TCP header for TSO operation. */ 1690 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1691 desc = &sc->age_rdata.age_tx_ring[si]; 1692 desc->flags |= htole32(AGE_TD_TSO_HDR); 1693 } 1694 1695 /* Swap dmamap of the first and the last. */ 1696 txd = &sc->age_cdata.age_txdesc[prod]; 1697 map = txd_last->tx_dmamap; 1698 txd_last->tx_dmamap = txd->tx_dmamap; 1699 txd->tx_dmamap = map; 1700 txd->tx_m = m; 1701 1702 /* Sync descriptors. */ 1703 bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE); 1704 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 1705 sc->age_cdata.age_tx_ring_map, 1706 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1707 1708 return (0); 1709} 1710 1711static void 1712age_start(struct ifnet *ifp) 1713{ 1714 struct age_softc *sc; 1715 1716 sc = ifp->if_softc; 1717 AGE_LOCK(sc); 1718 age_start_locked(ifp); 1719 AGE_UNLOCK(sc); 1720} 1721 1722static void 1723age_start_locked(struct ifnet *ifp) 1724{ 1725 struct age_softc *sc; 1726 struct mbuf *m_head; 1727 int enq; 1728 1729 sc = ifp->if_softc; 1730 1731 AGE_LOCK_ASSERT(sc); 1732 1733 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1734 IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0) 1735 return; 1736 1737 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1738 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1739 if (m_head == NULL) 1740 break; 1741 /* 1742 * Pack the data into the transmit ring. If we 1743 * don't have room, set the OACTIVE flag and wait 1744 * for the NIC to drain the ring. 1745 */ 1746 if (age_encap(sc, &m_head)) { 1747 if (m_head == NULL) 1748 break; 1749 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1750 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1751 break; 1752 } 1753 1754 enq++; 1755 /* 1756 * If there's a BPF listener, bounce a copy of this frame 1757 * to him. 1758 */ 1759 ETHER_BPF_MTAP(ifp, m_head); 1760 } 1761 1762 if (enq > 0) { 1763 /* Update mbox. */ 1764 AGE_COMMIT_MBOX(sc); 1765 /* Set a timeout in case the chip goes out to lunch. */ 1766 sc->age_watchdog_timer = AGE_TX_TIMEOUT; 1767 } 1768} 1769 1770static void 1771age_watchdog(struct age_softc *sc) 1772{ 1773 struct ifnet *ifp; 1774 1775 AGE_LOCK_ASSERT(sc); 1776 1777 if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer) 1778 return; 1779 1780 ifp = sc->age_ifp; 1781 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1782 if_printf(sc->age_ifp, "watchdog timeout (missed link)\n"); 1783 ifp->if_oerrors++; 1784 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1785 age_init_locked(sc); 1786 return; 1787 } 1788 if (sc->age_cdata.age_tx_cnt == 0) { 1789 if_printf(sc->age_ifp, 1790 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1791 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1792 age_start_locked(ifp); 1793 return; 1794 } 1795 if_printf(sc->age_ifp, "watchdog timeout\n"); 1796 ifp->if_oerrors++; 1797 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1798 age_init_locked(sc); 1799 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1800 age_start_locked(ifp); 1801} 1802 1803static int 1804age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1805{ 1806 struct age_softc *sc; 1807 struct ifreq *ifr; 1808 struct mii_data *mii; 1809 uint32_t reg; 1810 int error, mask; 1811 1812 sc = ifp->if_softc; 1813 ifr = (struct ifreq *)data; 1814 error = 0; 1815 switch (cmd) { 1816 case SIOCSIFMTU: 1817 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU) 1818 error = EINVAL; 1819 else if (ifp->if_mtu != ifr->ifr_mtu) { 1820 AGE_LOCK(sc); 1821 ifp->if_mtu = ifr->ifr_mtu; 1822 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1823 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1824 age_init_locked(sc); 1825 } 1826 AGE_UNLOCK(sc); 1827 } 1828 break; 1829 case SIOCSIFFLAGS: 1830 AGE_LOCK(sc); 1831 if ((ifp->if_flags & IFF_UP) != 0) { 1832 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1833 if (((ifp->if_flags ^ sc->age_if_flags) 1834 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1835 age_rxfilter(sc); 1836 } else { 1837 if ((sc->age_flags & AGE_FLAG_DETACH) == 0) 1838 age_init_locked(sc); 1839 } 1840 } else { 1841 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1842 age_stop(sc); 1843 } 1844 sc->age_if_flags = ifp->if_flags; 1845 AGE_UNLOCK(sc); 1846 break; 1847 case SIOCADDMULTI: 1848 case SIOCDELMULTI: 1849 AGE_LOCK(sc); 1850 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1851 age_rxfilter(sc); 1852 AGE_UNLOCK(sc); 1853 break; 1854 case SIOCSIFMEDIA: 1855 case SIOCGIFMEDIA: 1856 mii = device_get_softc(sc->age_miibus); 1857 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1858 break; 1859 case SIOCSIFCAP: 1860 AGE_LOCK(sc); 1861 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1862 if ((mask & IFCAP_TXCSUM) != 0 && 1863 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1864 ifp->if_capenable ^= IFCAP_TXCSUM; 1865 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1866 ifp->if_hwassist |= AGE_CSUM_FEATURES; 1867 else 1868 ifp->if_hwassist &= ~AGE_CSUM_FEATURES; 1869 } 1870 if ((mask & IFCAP_RXCSUM) != 0 && 1871 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1872 ifp->if_capenable ^= IFCAP_RXCSUM; 1873 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1874 reg &= ~MAC_CFG_RXCSUM_ENB; 1875 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1876 reg |= MAC_CFG_RXCSUM_ENB; 1877 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1878 } 1879 if ((mask & IFCAP_TSO4) != 0 && 1880 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 1881 ifp->if_capenable ^= IFCAP_TSO4; 1882 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 1883 ifp->if_hwassist |= CSUM_TSO; 1884 else 1885 ifp->if_hwassist &= ~CSUM_TSO; 1886 } 1887 1888 if ((mask & IFCAP_WOL_MCAST) != 0 && 1889 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 1890 ifp->if_capenable ^= IFCAP_WOL_MCAST; 1891 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1892 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 1893 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1894 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1895 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 1896 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1897 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1898 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 1899 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1900 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1901 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1902 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1903 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 1904 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 1905 age_rxvlan(sc); 1906 } 1907 AGE_UNLOCK(sc); 1908 VLAN_CAPABILITIES(ifp); 1909 break; 1910 default: 1911 error = ether_ioctl(ifp, cmd, data); 1912 break; 1913 } 1914 1915 return (error); 1916} 1917 1918static void 1919age_mac_config(struct age_softc *sc) 1920{ 1921 struct mii_data *mii; 1922 uint32_t reg; 1923 1924 AGE_LOCK_ASSERT(sc); 1925 1926 mii = device_get_softc(sc->age_miibus); 1927 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1928 reg &= ~MAC_CFG_FULL_DUPLEX; 1929 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1930 reg &= ~MAC_CFG_SPEED_MASK; 1931 /* Reprogram MAC with resolved speed/duplex. */ 1932 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1933 case IFM_10_T: 1934 case IFM_100_TX: 1935 reg |= MAC_CFG_SPEED_10_100; 1936 break; 1937 case IFM_1000_T: 1938 reg |= MAC_CFG_SPEED_1000; 1939 break; 1940 } 1941 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1942 reg |= MAC_CFG_FULL_DUPLEX; 1943#ifdef notyet 1944 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1945 reg |= MAC_CFG_TX_FC; 1946 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1947 reg |= MAC_CFG_RX_FC; 1948#endif 1949 } 1950 1951 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1952} 1953 1954static void 1955age_link_task(void *arg, int pending) 1956{ 1957 struct age_softc *sc; 1958 struct mii_data *mii; 1959 struct ifnet *ifp; 1960 uint32_t reg; 1961 1962 sc = (struct age_softc *)arg; 1963 1964 AGE_LOCK(sc); 1965 mii = device_get_softc(sc->age_miibus); 1966 ifp = sc->age_ifp; 1967 if (mii == NULL || ifp == NULL || 1968 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1969 AGE_UNLOCK(sc); 1970 return; 1971 } 1972 1973 sc->age_flags &= ~AGE_FLAG_LINK; 1974 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1975 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1976 case IFM_10_T: 1977 case IFM_100_TX: 1978 case IFM_1000_T: 1979 sc->age_flags |= AGE_FLAG_LINK; 1980 break; 1981 default: 1982 break; 1983 } 1984 } 1985 1986 /* Stop Rx/Tx MACs. */ 1987 age_stop_rxmac(sc); 1988 age_stop_txmac(sc); 1989 1990 /* Program MACs with resolved speed/duplex/flow-control. */ 1991 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 1992 age_mac_config(sc); 1993 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1994 /* Restart DMA engine and Tx/Rx MAC. */ 1995 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 1996 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 1997 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 1998 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1999 } 2000 2001 AGE_UNLOCK(sc); 2002} 2003 2004static void 2005age_stats_update(struct age_softc *sc) 2006{ 2007 struct age_stats *stat; 2008 struct smb *smb; 2009 struct ifnet *ifp; 2010 2011 AGE_LOCK_ASSERT(sc); 2012 2013 stat = &sc->age_stat; 2014 2015 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2016 sc->age_cdata.age_smb_block_map, 2017 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2018 2019 smb = sc->age_rdata.age_smb_block; 2020 if (smb->updated == 0) 2021 return; 2022 2023 ifp = sc->age_ifp; 2024 /* Rx stats. */ 2025 stat->rx_frames += smb->rx_frames; 2026 stat->rx_bcast_frames += smb->rx_bcast_frames; 2027 stat->rx_mcast_frames += smb->rx_mcast_frames; 2028 stat->rx_pause_frames += smb->rx_pause_frames; 2029 stat->rx_control_frames += smb->rx_control_frames; 2030 stat->rx_crcerrs += smb->rx_crcerrs; 2031 stat->rx_lenerrs += smb->rx_lenerrs; 2032 stat->rx_bytes += smb->rx_bytes; 2033 stat->rx_runts += smb->rx_runts; 2034 stat->rx_fragments += smb->rx_fragments; 2035 stat->rx_pkts_64 += smb->rx_pkts_64; 2036 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2037 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2038 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2039 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2040 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2041 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2042 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2043 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2044 stat->rx_desc_oflows += smb->rx_desc_oflows; 2045 stat->rx_alignerrs += smb->rx_alignerrs; 2046 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2047 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2048 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2049 2050 /* Tx stats. */ 2051 stat->tx_frames += smb->tx_frames; 2052 stat->tx_bcast_frames += smb->tx_bcast_frames; 2053 stat->tx_mcast_frames += smb->tx_mcast_frames; 2054 stat->tx_pause_frames += smb->tx_pause_frames; 2055 stat->tx_excess_defer += smb->tx_excess_defer; 2056 stat->tx_control_frames += smb->tx_control_frames; 2057 stat->tx_deferred += smb->tx_deferred; 2058 stat->tx_bytes += smb->tx_bytes; 2059 stat->tx_pkts_64 += smb->tx_pkts_64; 2060 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2061 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2062 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2063 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2064 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2065 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2066 stat->tx_single_colls += smb->tx_single_colls; 2067 stat->tx_multi_colls += smb->tx_multi_colls; 2068 stat->tx_late_colls += smb->tx_late_colls; 2069 stat->tx_excess_colls += smb->tx_excess_colls; 2070 stat->tx_underrun += smb->tx_underrun; 2071 stat->tx_desc_underrun += smb->tx_desc_underrun; 2072 stat->tx_lenerrs += smb->tx_lenerrs; 2073 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2074 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2075 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2076 2077 /* Update counters in ifnet. */ 2078 ifp->if_opackets += smb->tx_frames; 2079 2080 ifp->if_collisions += smb->tx_single_colls + 2081 smb->tx_multi_colls + smb->tx_late_colls + 2082 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2083 2084 ifp->if_oerrors += smb->tx_excess_colls + 2085 smb->tx_late_colls + smb->tx_underrun + 2086 smb->tx_pkts_truncated; 2087 2088 ifp->if_ipackets += smb->rx_frames; 2089 2090 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2091 smb->rx_runts + smb->rx_pkts_truncated + 2092 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2093 smb->rx_alignerrs; 2094 2095 /* Update done, clear. */ 2096 smb->updated = 0; 2097 2098 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2099 sc->age_cdata.age_smb_block_map, 2100 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2101} 2102 2103static int 2104age_intr(void *arg) 2105{ 2106 struct age_softc *sc; 2107 uint32_t status; 2108 2109 sc = (struct age_softc *)arg; 2110 2111 status = CSR_READ_4(sc, AGE_INTR_STATUS); 2112 if (status == 0 || (status & AGE_INTRS) == 0) 2113 return (FILTER_STRAY); 2114 /* Disable interrupts. */ 2115 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2116 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2117 2118 return (FILTER_HANDLED); 2119} 2120 2121static void 2122age_int_task(void *arg, int pending) 2123{ 2124 struct age_softc *sc; 2125 struct ifnet *ifp; 2126 struct cmb *cmb; 2127 uint32_t status; 2128 2129 sc = (struct age_softc *)arg; 2130 2131 AGE_LOCK(sc); 2132 2133 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2134 sc->age_cdata.age_cmb_block_map, 2135 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2136 cmb = sc->age_rdata.age_cmb_block; 2137 status = le32toh(cmb->intr_status); 2138 if (sc->age_morework != 0) 2139 status |= INTR_CMB_RX; 2140 if ((status & AGE_INTRS) == 0) 2141 goto done; 2142 2143 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 2144 TPD_CONS_SHIFT; 2145 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 2146 RRD_PROD_SHIFT; 2147 /* Let hardware know CMB was served. */ 2148 cmb->intr_status = 0; 2149 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2150 sc->age_cdata.age_cmb_block_map, 2151 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2152 2153#if 0 2154 printf("INTR: 0x%08x\n", status); 2155 status &= ~INTR_DIS_DMA; 2156 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2157#endif 2158 ifp = sc->age_ifp; 2159 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2160 if ((status & INTR_CMB_RX) != 0) 2161 sc->age_morework = age_rxintr(sc, sc->age_rr_prod, 2162 sc->age_process_limit); 2163 if ((status & INTR_CMB_TX) != 0) 2164 age_txintr(sc, sc->age_tpd_cons); 2165 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2166 if ((status & INTR_DMA_RD_TO_RST) != 0) 2167 device_printf(sc->age_dev, 2168 "DMA read error! -- resetting\n"); 2169 if ((status & INTR_DMA_WR_TO_RST) != 0) 2170 device_printf(sc->age_dev, 2171 "DMA write error! -- resetting\n"); 2172 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2173 age_init_locked(sc); 2174 } 2175 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2176 age_start_locked(ifp); 2177 if ((status & INTR_SMB) != 0) 2178 age_stats_update(sc); 2179 } 2180 2181 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 2182 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2183 sc->age_cdata.age_cmb_block_map, 2184 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2185 status = le32toh(cmb->intr_status); 2186 if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) { 2187 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2188 AGE_UNLOCK(sc); 2189 return; 2190 } 2191 2192done: 2193 /* Re-enable interrupts. */ 2194 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2195 AGE_UNLOCK(sc); 2196} 2197 2198static void 2199age_txintr(struct age_softc *sc, int tpd_cons) 2200{ 2201 struct ifnet *ifp; 2202 struct age_txdesc *txd; 2203 int cons, prog; 2204 2205 AGE_LOCK_ASSERT(sc); 2206 2207 ifp = sc->age_ifp; 2208 2209 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2210 sc->age_cdata.age_tx_ring_map, 2211 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2212 2213 /* 2214 * Go through our Tx list and free mbufs for those 2215 * frames which have been transmitted. 2216 */ 2217 cons = sc->age_cdata.age_tx_cons; 2218 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 2219 if (sc->age_cdata.age_tx_cnt <= 0) 2220 break; 2221 prog++; 2222 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2223 sc->age_cdata.age_tx_cnt--; 2224 txd = &sc->age_cdata.age_txdesc[cons]; 2225 /* 2226 * Clear Tx descriptors, it's not required but would 2227 * help debugging in case of Tx issues. 2228 */ 2229 txd->tx_desc->addr = 0; 2230 txd->tx_desc->len = 0; 2231 txd->tx_desc->flags = 0; 2232 2233 if (txd->tx_m == NULL) 2234 continue; 2235 /* Reclaim transmitted mbufs. */ 2236 bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap, 2237 BUS_DMASYNC_POSTWRITE); 2238 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap); 2239 m_freem(txd->tx_m); 2240 txd->tx_m = NULL; 2241 } 2242 2243 if (prog > 0) { 2244 sc->age_cdata.age_tx_cons = cons; 2245 2246 /* 2247 * Unarm watchdog timer only when there are no pending 2248 * Tx descriptors in queue. 2249 */ 2250 if (sc->age_cdata.age_tx_cnt == 0) 2251 sc->age_watchdog_timer = 0; 2252 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2253 sc->age_cdata.age_tx_ring_map, 2254 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2255 } 2256} 2257 2258/* Receive a frame. */ 2259static void 2260age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 2261{ 2262 struct age_rxdesc *rxd; 2263 struct rx_desc *desc; 2264 struct ifnet *ifp; 2265 struct mbuf *mp, *m; 2266 uint32_t status, index, vtag; 2267 int count, nsegs, pktlen; 2268 int rx_cons; 2269 2270 AGE_LOCK_ASSERT(sc); 2271 2272 ifp = sc->age_ifp; 2273 status = le32toh(rxrd->flags); 2274 index = le32toh(rxrd->index); 2275 rx_cons = AGE_RX_CONS(index); 2276 nsegs = AGE_RX_NSEGS(index); 2277 2278 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2279 if ((status & AGE_RRD_ERROR) != 0 && 2280 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 2281 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 2282 /* 2283 * We want to pass the following frames to upper 2284 * layer regardless of error status of Rx return 2285 * ring. 2286 * 2287 * o IP/TCP/UDP checksum is bad. 2288 * o frame length and protocol specific length 2289 * does not match. 2290 */ 2291 sc->age_cdata.age_rx_cons += nsegs; 2292 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2293 return; 2294 } 2295 2296 pktlen = 0; 2297 for (count = 0; count < nsegs; count++, 2298 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 2299 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 2300 mp = rxd->rx_m; 2301 desc = rxd->rx_desc; 2302 /* Add a new receive buffer to the ring. */ 2303 if (age_newbuf(sc, rxd) != 0) { 2304 ifp->if_iqdrops++; 2305 /* Reuse Rx buffers. */ 2306 if (sc->age_cdata.age_rxhead != NULL) { 2307 m_freem(sc->age_cdata.age_rxhead); 2308 AGE_RXCHAIN_RESET(sc); 2309 } 2310 break; 2311 } 2312 2313 /* The length of the first mbuf is computed last. */ 2314 if (count != 0) { 2315 mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 2316 pktlen += mp->m_len; 2317 } 2318 2319 /* Chain received mbufs. */ 2320 if (sc->age_cdata.age_rxhead == NULL) { 2321 sc->age_cdata.age_rxhead = mp; 2322 sc->age_cdata.age_rxtail = mp; 2323 } else { 2324 mp->m_flags &= ~M_PKTHDR; 2325 sc->age_cdata.age_rxprev_tail = 2326 sc->age_cdata.age_rxtail; 2327 sc->age_cdata.age_rxtail->m_next = mp; 2328 sc->age_cdata.age_rxtail = mp; 2329 } 2330 2331 if (count == nsegs - 1) { 2332 /* 2333 * It seems that L1 controller has no way 2334 * to tell hardware to strip CRC bytes. 2335 */ 2336 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 2337 if (nsegs > 1) { 2338 /* Remove the CRC bytes in chained mbufs. */ 2339 pktlen -= ETHER_CRC_LEN; 2340 if (mp->m_len <= ETHER_CRC_LEN) { 2341 sc->age_cdata.age_rxtail = 2342 sc->age_cdata.age_rxprev_tail; 2343 sc->age_cdata.age_rxtail->m_len -= 2344 (ETHER_CRC_LEN - mp->m_len); 2345 sc->age_cdata.age_rxtail->m_next = NULL; 2346 m_freem(mp); 2347 } else { 2348 mp->m_len -= ETHER_CRC_LEN; 2349 } 2350 } 2351 2352 m = sc->age_cdata.age_rxhead; 2353 m->m_flags |= M_PKTHDR; 2354 m->m_pkthdr.rcvif = ifp; 2355 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 2356 /* Set the first mbuf length. */ 2357 m->m_len = sc->age_cdata.age_rxlen - pktlen; 2358 2359 /* 2360 * Set checksum information. 2361 * It seems that L1 controller can compute partial 2362 * checksum. The partial checksum value can be used 2363 * to accelerate checksum computation for fragmented 2364 * TCP/UDP packets. Upper network stack already 2365 * takes advantage of the partial checksum value in 2366 * IP reassembly stage. But I'm not sure the 2367 * correctness of the partial hardware checksum 2368 * assistance due to lack of data sheet. If it is 2369 * proven to work on L1 I'll enable it. 2370 */ 2371 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2372 (status & AGE_RRD_IPV4) != 0) { 2373 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2374 if ((status & AGE_RRD_IPCSUM_NOK) == 0) 2375 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2376 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 2377 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 2378 m->m_pkthdr.csum_flags |= 2379 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2380 m->m_pkthdr.csum_data = 0xffff; 2381 } 2382 /* 2383 * Don't mark bad checksum for TCP/UDP frames 2384 * as fragmented frames may always have set 2385 * bad checksummed bit of descriptor status. 2386 */ 2387 } 2388 2389 /* Check for VLAN tagged frames. */ 2390 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2391 (status & AGE_RRD_VLAN) != 0) { 2392 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 2393 m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag); 2394 m->m_flags |= M_VLANTAG; 2395 } 2396 2397 /* Pass it on. */ 2398 AGE_UNLOCK(sc); 2399 (*ifp->if_input)(ifp, m); 2400 AGE_LOCK(sc); 2401 2402 /* Reset mbuf chains. */ 2403 AGE_RXCHAIN_RESET(sc); 2404 } 2405 } 2406 2407 if (count != nsegs) { 2408 sc->age_cdata.age_rx_cons += nsegs; 2409 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2410 } else 2411 sc->age_cdata.age_rx_cons = rx_cons; 2412} 2413 2414static int 2415age_rxintr(struct age_softc *sc, int rr_prod, int count) 2416{ 2417 struct rx_rdesc *rxrd; 2418 int rr_cons, nsegs, pktlen, prog; 2419 2420 AGE_LOCK_ASSERT(sc); 2421 2422 rr_cons = sc->age_cdata.age_rr_cons; 2423 if (rr_cons == rr_prod) 2424 return (0); 2425 2426 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2427 sc->age_cdata.age_rr_ring_map, 2428 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2429 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2430 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2431 2432 for (prog = 0; rr_cons != rr_prod; prog++) { 2433 if (count <= 0) 2434 break; 2435 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 2436 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 2437 if (nsegs == 0) 2438 break; 2439 /* 2440 * Check number of segments against received bytes. 2441 * Non-matching value would indicate that hardware 2442 * is still trying to update Rx return descriptors. 2443 * I'm not sure whether this check is really needed. 2444 */ 2445 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2446 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 2447 (MCLBYTES - ETHER_ALIGN))) 2448 break; 2449 2450 prog++; 2451 /* Received a frame. */ 2452 age_rxeof(sc, rxrd); 2453 /* Clear return ring. */ 2454 rxrd->index = 0; 2455 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 2456 } 2457 2458 if (prog > 0) { 2459 /* Update the consumer index. */ 2460 sc->age_cdata.age_rr_cons = rr_cons; 2461 2462 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2463 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 2464 /* Sync descriptors. */ 2465 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2466 sc->age_cdata.age_rr_ring_map, 2467 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2468 2469 /* Notify hardware availability of new Rx buffers. */ 2470 AGE_COMMIT_MBOX(sc); 2471 } 2472 2473 return (count > 0 ? 0 : EAGAIN); 2474} 2475 2476static void 2477age_tick(void *arg) 2478{ 2479 struct age_softc *sc; 2480 struct mii_data *mii; 2481 2482 sc = (struct age_softc *)arg; 2483 2484 AGE_LOCK_ASSERT(sc); 2485 2486 mii = device_get_softc(sc->age_miibus); 2487 mii_tick(mii); 2488 age_watchdog(sc); 2489 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2490} 2491 2492static void 2493age_reset(struct age_softc *sc) 2494{ 2495 uint32_t reg; 2496 int i; 2497 2498 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 2499 CSR_READ_4(sc, AGE_MASTER_CFG); 2500 DELAY(1000); 2501 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2502 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2503 break; 2504 DELAY(10); 2505 } 2506 2507 if (i == 0) 2508 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg); 2509 /* Initialize PCIe module. From Linux. */ 2510 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2511 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2512} 2513 2514static void 2515age_init(void *xsc) 2516{ 2517 struct age_softc *sc; 2518 2519 sc = (struct age_softc *)xsc; 2520 AGE_LOCK(sc); 2521 age_init_locked(sc); 2522 AGE_UNLOCK(sc); 2523} 2524 2525static void 2526age_init_locked(struct age_softc *sc) 2527{ 2528 struct ifnet *ifp; 2529 struct mii_data *mii; 2530 uint8_t eaddr[ETHER_ADDR_LEN]; 2531 bus_addr_t paddr; 2532 uint32_t reg, fsize; 2533 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 2534 int error; 2535 2536 AGE_LOCK_ASSERT(sc); 2537 2538 ifp = sc->age_ifp; 2539 mii = device_get_softc(sc->age_miibus); 2540 2541 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2542 return; 2543 2544 /* 2545 * Cancel any pending I/O. 2546 */ 2547 age_stop(sc); 2548 2549 /* 2550 * Reset the chip to a known state. 2551 */ 2552 age_reset(sc); 2553 2554 /* Initialize descriptors. */ 2555 error = age_init_rx_ring(sc); 2556 if (error != 0) { 2557 device_printf(sc->age_dev, "no memory for Rx buffers.\n"); 2558 age_stop(sc); 2559 return; 2560 } 2561 age_init_rr_ring(sc); 2562 age_init_tx_ring(sc); 2563 age_init_cmb_block(sc); 2564 age_init_smb_block(sc); 2565 2566 /* Reprogram the station address. */ 2567 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2568 CSR_WRITE_4(sc, AGE_PAR0, 2569 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2570 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 2571 2572 /* Set descriptor base addresses. */ 2573 paddr = sc->age_rdata.age_tx_ring_paddr; 2574 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 2575 paddr = sc->age_rdata.age_rx_ring_paddr; 2576 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 2577 paddr = sc->age_rdata.age_rr_ring_paddr; 2578 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 2579 paddr = sc->age_rdata.age_tx_ring_paddr; 2580 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 2581 paddr = sc->age_rdata.age_cmb_block_paddr; 2582 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2583 paddr = sc->age_rdata.age_smb_block_paddr; 2584 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2585 /* Set Rx/Rx return descriptor counter. */ 2586 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 2587 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 2588 DESC_RRD_CNT_MASK) | 2589 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 2590 /* Set Tx descriptor counter. */ 2591 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 2592 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 2593 2594 /* Tell hardware that we're ready to load descriptors. */ 2595 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 2596 2597 /* 2598 * Initialize mailbox register. 2599 * Updated producer/consumer index information is exchanged 2600 * through this mailbox register. However Tx producer and 2601 * Rx return consumer/Rx producer are all shared such that 2602 * it's hard to separate code path between Tx and Rx without 2603 * locking. If L1 hardware have a separate mail box register 2604 * for Tx and Rx consumer/producer management we could have 2605 * indepent Tx/Rx handler which in turn Rx handler could have 2606 * been run without any locking. 2607 */ 2608 AGE_COMMIT_MBOX(sc); 2609 2610 /* Configure IPG/IFG parameters. */ 2611 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 2612 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 2613 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2614 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2615 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 2616 2617 /* Set parameters for half-duplex media. */ 2618 CSR_WRITE_4(sc, AGE_HDPX_CFG, 2619 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2620 HDPX_CFG_LCOL_MASK) | 2621 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2622 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2623 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2624 HDPX_CFG_ABEBT_MASK) | 2625 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2626 HDPX_CFG_JAMIPG_MASK)); 2627 2628 /* Configure interrupt moderation timer. */ 2629 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 2630 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 2631 reg &= ~MASTER_MTIMER_ENB; 2632 if (AGE_USECS(sc->age_int_mod) == 0) 2633 reg &= ~MASTER_ITIMER_ENB; 2634 else 2635 reg |= MASTER_ITIMER_ENB; 2636 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 2637 if (bootverbose) 2638 device_printf(sc->age_dev, "interrupt moderation is %d us.\n", 2639 sc->age_int_mod); 2640 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 2641 2642 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 2643 if (ifp->if_mtu < ETHERMTU) 2644 sc->age_max_frame_size = ETHERMTU; 2645 else 2646 sc->age_max_frame_size = ifp->if_mtu; 2647 sc->age_max_frame_size += ETHER_HDR_LEN + 2648 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 2649 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 2650 /* Configure jumbo frame. */ 2651 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 2652 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 2653 (((fsize / sizeof(uint64_t)) << 2654 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 2655 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 2656 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 2657 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 2658 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 2659 2660 /* Configure flow-control parameters. From Linux. */ 2661 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 2662 /* 2663 * Magic workaround for old-L1. 2664 * Don't know which hw revision requires this magic. 2665 */ 2666 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2667 /* 2668 * Another magic workaround for flow-control mode 2669 * change. From Linux. 2670 */ 2671 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2672 } 2673 /* 2674 * TODO 2675 * Should understand pause parameter relationships between FIFO 2676 * size and number of Rx descriptors and Rx return descriptors. 2677 * 2678 * Magic parameters came from Linux. 2679 */ 2680 switch (sc->age_chip_rev) { 2681 case 0x8001: 2682 case 0x9001: 2683 case 0x9002: 2684 case 0x9003: 2685 rxf_hi = AGE_RX_RING_CNT / 16; 2686 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 2687 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 2688 rrd_lo = AGE_RR_RING_CNT / 16; 2689 break; 2690 default: 2691 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 2692 rxf_lo = reg / 16; 2693 if (rxf_lo < 192) 2694 rxf_lo = 192; 2695 rxf_hi = (reg * 7) / 8; 2696 if (rxf_hi < rxf_lo) 2697 rxf_hi = rxf_lo + 16; 2698 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 2699 rrd_lo = reg / 8; 2700 rrd_hi = (reg * 7) / 8; 2701 if (rrd_lo < 2) 2702 rrd_lo = 2; 2703 if (rrd_hi < rrd_lo) 2704 rrd_hi = rrd_lo + 3; 2705 break; 2706 } 2707 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 2708 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 2709 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 2710 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 2711 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 2712 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 2713 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 2714 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 2715 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 2716 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 2717 2718 /* Configure RxQ. */ 2719 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2720 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2721 RXQ_CFG_RD_BURST_MASK) | 2722 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 2723 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 2724 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 2725 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 2726 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2727 2728 /* Configure TxQ. */ 2729 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2730 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2731 TXQ_CFG_TPD_BURST_MASK) | 2732 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 2733 TXQ_CFG_TX_FIFO_BURST_MASK) | 2734 ((TXQ_CFG_TPD_FETCH_DEFAULT << 2735 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 2736 TXQ_CFG_ENB); 2737 2738 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG, 2739 (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) & 2740 TX_JUMBO_TPD_TH_MASK) | 2741 ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) & 2742 TX_JUMBO_TPD_IPG_MASK)); 2743 /* Configure DMA parameters. */ 2744 CSR_WRITE_4(sc, AGE_DMA_CFG, 2745 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 2746 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 2747 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 2748 2749 /* Configure CMB DMA write threshold. */ 2750 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 2751 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 2752 CMB_WR_THRESH_RRD_MASK) | 2753 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 2754 CMB_WR_THRESH_TPD_MASK)); 2755 2756 /* Set CMB/SMB timer and enable them. */ 2757 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 2758 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 2759 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 2760 /* Request SMB updates for every seconds. */ 2761 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 2762 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 2763 2764 /* 2765 * Disable all WOL bits as WOL can interfere normal Rx 2766 * operation. 2767 */ 2768 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 2769 2770 /* 2771 * Configure Tx/Rx MACs. 2772 * - Auto-padding for short frames. 2773 * - Enable CRC generation. 2774 * Start with full-duplex/1000Mbps media. Actual reconfiguration 2775 * of MAC is followed after link establishment. 2776 */ 2777 CSR_WRITE_4(sc, AGE_MAC_CFG, 2778 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 2779 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 2780 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2781 MAC_CFG_PREAMBLE_MASK)); 2782 /* Set up the receive filter. */ 2783 age_rxfilter(sc); 2784 age_rxvlan(sc); 2785 2786 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2787 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2788 reg |= MAC_CFG_RXCSUM_ENB; 2789 2790 /* Ack all pending interrupts and clear it. */ 2791 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2792 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 2793 2794 /* Finally enable Tx/Rx MAC. */ 2795 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2796 2797 sc->age_flags &= ~AGE_FLAG_LINK; 2798 /* Switch to the current media. */ 2799 mii_mediachg(mii); 2800 2801 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2802 2803 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2804 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2805} 2806 2807static void 2808age_stop(struct age_softc *sc) 2809{ 2810 struct ifnet *ifp; 2811 struct age_txdesc *txd; 2812 struct age_rxdesc *rxd; 2813 uint32_t reg; 2814 int i; 2815 2816 AGE_LOCK_ASSERT(sc); 2817 /* 2818 * Mark the interface down and cancel the watchdog timer. 2819 */ 2820 ifp = sc->age_ifp; 2821 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2822 sc->age_flags &= ~AGE_FLAG_LINK; 2823 callout_stop(&sc->age_tick_ch); 2824 sc->age_watchdog_timer = 0; 2825 2826 /* 2827 * Disable interrupts. 2828 */ 2829 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 2830 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 2831 /* Stop CMB/SMB updates. */ 2832 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 2833 /* Stop Rx/Tx MAC. */ 2834 age_stop_rxmac(sc); 2835 age_stop_txmac(sc); 2836 /* Stop DMA. */ 2837 CSR_WRITE_4(sc, AGE_DMA_CFG, 2838 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 2839 /* Stop TxQ/RxQ. */ 2840 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2841 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 2842 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2843 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 2844 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2845 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2846 break; 2847 DELAY(10); 2848 } 2849 if (i == 0) 2850 device_printf(sc->age_dev, 2851 "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg); 2852 2853 /* Reclaim Rx buffers that have been processed. */ 2854 if (sc->age_cdata.age_rxhead != NULL) 2855 m_freem(sc->age_cdata.age_rxhead); 2856 AGE_RXCHAIN_RESET(sc); 2857 /* 2858 * Free RX and TX mbufs still in the queues. 2859 */ 2860 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2861 rxd = &sc->age_cdata.age_rxdesc[i]; 2862 if (rxd->rx_m != NULL) { 2863 bus_dmamap_sync(sc->age_cdata.age_rx_tag, 2864 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2865 bus_dmamap_unload(sc->age_cdata.age_rx_tag, 2866 rxd->rx_dmamap); 2867 m_freem(rxd->rx_m); 2868 rxd->rx_m = NULL; 2869 } 2870 } 2871 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2872 txd = &sc->age_cdata.age_txdesc[i]; 2873 if (txd->tx_m != NULL) { 2874 bus_dmamap_sync(sc->age_cdata.age_tx_tag, 2875 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2876 bus_dmamap_unload(sc->age_cdata.age_tx_tag, 2877 txd->tx_dmamap); 2878 m_freem(txd->tx_m); 2879 txd->tx_m = NULL; 2880 } 2881 } 2882} 2883 2884static void 2885age_stop_txmac(struct age_softc *sc) 2886{ 2887 uint32_t reg; 2888 int i; 2889 2890 AGE_LOCK_ASSERT(sc); 2891 2892 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2893 if ((reg & MAC_CFG_TX_ENB) != 0) { 2894 reg &= ~MAC_CFG_TX_ENB; 2895 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2896 } 2897 /* Stop Tx DMA engine. */ 2898 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2899 if ((reg & DMA_CFG_RD_ENB) != 0) { 2900 reg &= ~DMA_CFG_RD_ENB; 2901 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2902 } 2903 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2904 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2905 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2906 break; 2907 DELAY(10); 2908 } 2909 if (i == 0) 2910 device_printf(sc->age_dev, "stopping TxMAC timeout!\n"); 2911} 2912 2913static void 2914age_stop_rxmac(struct age_softc *sc) 2915{ 2916 uint32_t reg; 2917 int i; 2918 2919 AGE_LOCK_ASSERT(sc); 2920 2921 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2922 if ((reg & MAC_CFG_RX_ENB) != 0) { 2923 reg &= ~MAC_CFG_RX_ENB; 2924 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2925 } 2926 /* Stop Rx DMA engine. */ 2927 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2928 if ((reg & DMA_CFG_WR_ENB) != 0) { 2929 reg &= ~DMA_CFG_WR_ENB; 2930 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2931 } 2932 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2933 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2934 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2935 break; 2936 DELAY(10); 2937 } 2938 if (i == 0) 2939 device_printf(sc->age_dev, "stopping RxMAC timeout!\n"); 2940} 2941 2942static void 2943age_init_tx_ring(struct age_softc *sc) 2944{ 2945 struct age_ring_data *rd; 2946 struct age_txdesc *txd; 2947 int i; 2948 2949 AGE_LOCK_ASSERT(sc); 2950 2951 sc->age_cdata.age_tx_prod = 0; 2952 sc->age_cdata.age_tx_cons = 0; 2953 sc->age_cdata.age_tx_cnt = 0; 2954 2955 rd = &sc->age_rdata; 2956 bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 2957 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2958 txd = &sc->age_cdata.age_txdesc[i]; 2959 txd->tx_desc = &rd->age_tx_ring[i]; 2960 txd->tx_m = NULL; 2961 } 2962 2963 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2964 sc->age_cdata.age_tx_ring_map, 2965 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2966} 2967 2968static int 2969age_init_rx_ring(struct age_softc *sc) 2970{ 2971 struct age_ring_data *rd; 2972 struct age_rxdesc *rxd; 2973 int i; 2974 2975 AGE_LOCK_ASSERT(sc); 2976 2977 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2978 sc->age_morework = 0; 2979 rd = &sc->age_rdata; 2980 bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 2981 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2982 rxd = &sc->age_cdata.age_rxdesc[i]; 2983 rxd->rx_m = NULL; 2984 rxd->rx_desc = &rd->age_rx_ring[i]; 2985 if (age_newbuf(sc, rxd) != 0) 2986 return (ENOBUFS); 2987 } 2988 2989 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2990 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 2991 2992 return (0); 2993} 2994 2995static void 2996age_init_rr_ring(struct age_softc *sc) 2997{ 2998 struct age_ring_data *rd; 2999 3000 AGE_LOCK_ASSERT(sc); 3001 3002 sc->age_cdata.age_rr_cons = 0; 3003 AGE_RXCHAIN_RESET(sc); 3004 3005 rd = &sc->age_rdata; 3006 bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 3007 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 3008 sc->age_cdata.age_rr_ring_map, 3009 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3010} 3011 3012static void 3013age_init_cmb_block(struct age_softc *sc) 3014{ 3015 struct age_ring_data *rd; 3016 3017 AGE_LOCK_ASSERT(sc); 3018 3019 rd = &sc->age_rdata; 3020 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 3021 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 3022 sc->age_cdata.age_cmb_block_map, 3023 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3024} 3025 3026static void 3027age_init_smb_block(struct age_softc *sc) 3028{ 3029 struct age_ring_data *rd; 3030 3031 AGE_LOCK_ASSERT(sc); 3032 3033 rd = &sc->age_rdata; 3034 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 3035 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 3036 sc->age_cdata.age_smb_block_map, 3037 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3038} 3039 3040static int 3041age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) 3042{ 3043 struct rx_desc *desc; 3044 struct mbuf *m; 3045 bus_dma_segment_t segs[1]; 3046 bus_dmamap_t map; 3047 int nsegs; 3048 3049 AGE_LOCK_ASSERT(sc); 3050 3051 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3052 if (m == NULL) 3053 return (ENOBUFS); 3054 m->m_len = m->m_pkthdr.len = MCLBYTES; 3055 m_adj(m, ETHER_ALIGN); 3056 3057 if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag, 3058 sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3059 m_freem(m); 3060 return (ENOBUFS); 3061 } 3062 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3063 3064 if (rxd->rx_m != NULL) { 3065 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3066 BUS_DMASYNC_POSTREAD); 3067 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap); 3068 } 3069 map = rxd->rx_dmamap; 3070 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 3071 sc->age_cdata.age_rx_sparemap = map; 3072 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3073 BUS_DMASYNC_PREREAD); 3074 rxd->rx_m = m; 3075 3076 desc = rxd->rx_desc; 3077 desc->addr = htole64(segs[0].ds_addr); 3078 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) << 3079 AGE_RD_LEN_SHIFT); 3080 return (0); 3081} 3082 3083static void 3084age_rxvlan(struct age_softc *sc) 3085{ 3086 struct ifnet *ifp; 3087 uint32_t reg; 3088 3089 AGE_LOCK_ASSERT(sc); 3090 3091 ifp = sc->age_ifp; 3092 reg = CSR_READ_4(sc, AGE_MAC_CFG); 3093 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3094 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3095 reg |= MAC_CFG_VLAN_TAG_STRIP; 3096 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 3097} 3098 3099static void 3100age_rxfilter(struct age_softc *sc) 3101{ 3102 struct ifnet *ifp; 3103 struct ifmultiaddr *ifma; 3104 uint32_t crc; 3105 uint32_t mchash[2]; 3106 uint32_t rxcfg; 3107 3108 AGE_LOCK_ASSERT(sc); 3109 3110 ifp = sc->age_ifp; 3111 3112 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 3113 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3114 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3115 rxcfg |= MAC_CFG_BCAST; 3116 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3117 if ((ifp->if_flags & IFF_PROMISC) != 0) 3118 rxcfg |= MAC_CFG_PROMISC; 3119 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3120 rxcfg |= MAC_CFG_ALLMULTI; 3121 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 3122 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 3123 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3124 return; 3125 } 3126 3127 /* Program new filter. */ 3128 bzero(mchash, sizeof(mchash)); 3129 3130 if_maddr_rlock(ifp); 3131 TAILQ_FOREACH(ifma, &sc->age_ifp->if_multiaddrs, ifma_link) { 3132 if (ifma->ifma_addr->sa_family != AF_LINK) 3133 continue; 3134 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3135 ifma->ifma_addr), ETHER_ADDR_LEN); 3136 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3137 } 3138 if_maddr_runlock(ifp); 3139 3140 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 3141 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 3142 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3143} 3144 3145static int 3146sysctl_age_stats(SYSCTL_HANDLER_ARGS) 3147{ 3148 struct age_softc *sc; 3149 struct age_stats *stats; 3150 int error, result; 3151 3152 result = -1; 3153 error = sysctl_handle_int(oidp, &result, 0, req); 3154 3155 if (error != 0 || req->newptr == NULL) 3156 return (error); 3157 3158 if (result != 1) 3159 return (error); 3160 3161 sc = (struct age_softc *)arg1; 3162 stats = &sc->age_stat; 3163 printf("%s statistics:\n", device_get_nameunit(sc->age_dev)); 3164 printf("Transmit good frames : %ju\n", 3165 (uintmax_t)stats->tx_frames); 3166 printf("Transmit good broadcast frames : %ju\n", 3167 (uintmax_t)stats->tx_bcast_frames); 3168 printf("Transmit good multicast frames : %ju\n", 3169 (uintmax_t)stats->tx_mcast_frames); 3170 printf("Transmit pause control frames : %u\n", 3171 stats->tx_pause_frames); 3172 printf("Transmit control frames : %u\n", 3173 stats->tx_control_frames); 3174 printf("Transmit frames with excessive deferrals : %u\n", 3175 stats->tx_excess_defer); 3176 printf("Transmit deferrals : %u\n", 3177 stats->tx_deferred); 3178 printf("Transmit good octets : %ju\n", 3179 (uintmax_t)stats->tx_bytes); 3180 printf("Transmit good broadcast octets : %ju\n", 3181 (uintmax_t)stats->tx_bcast_bytes); 3182 printf("Transmit good multicast octets : %ju\n", 3183 (uintmax_t)stats->tx_mcast_bytes); 3184 printf("Transmit frames 64 bytes : %ju\n", 3185 (uintmax_t)stats->tx_pkts_64); 3186 printf("Transmit frames 65 to 127 bytes : %ju\n", 3187 (uintmax_t)stats->tx_pkts_65_127); 3188 printf("Transmit frames 128 to 255 bytes : %ju\n", 3189 (uintmax_t)stats->tx_pkts_128_255); 3190 printf("Transmit frames 256 to 511 bytes : %ju\n", 3191 (uintmax_t)stats->tx_pkts_256_511); 3192 printf("Transmit frames 512 to 1024 bytes : %ju\n", 3193 (uintmax_t)stats->tx_pkts_512_1023); 3194 printf("Transmit frames 1024 to 1518 bytes : %ju\n", 3195 (uintmax_t)stats->tx_pkts_1024_1518); 3196 printf("Transmit frames 1519 to MTU bytes : %ju\n", 3197 (uintmax_t)stats->tx_pkts_1519_max); 3198 printf("Transmit single collisions : %u\n", 3199 stats->tx_single_colls); 3200 printf("Transmit multiple collisions : %u\n", 3201 stats->tx_multi_colls); 3202 printf("Transmit late collisions : %u\n", 3203 stats->tx_late_colls); 3204 printf("Transmit abort due to excessive collisions : %u\n", 3205 stats->tx_excess_colls); 3206 printf("Transmit underruns due to FIFO underruns : %u\n", 3207 stats->tx_underrun); 3208 printf("Transmit descriptor write-back errors : %u\n", 3209 stats->tx_desc_underrun); 3210 printf("Transmit frames with length mismatched frame size : %u\n", 3211 stats->tx_lenerrs); 3212 printf("Transmit frames with truncated due to MTU size : %u\n", 3213 stats->tx_lenerrs); 3214 3215 printf("Receive good frames : %ju\n", 3216 (uintmax_t)stats->rx_frames); 3217 printf("Receive good broadcast frames : %ju\n", 3218 (uintmax_t)stats->rx_bcast_frames); 3219 printf("Receive good multicast frames : %ju\n", 3220 (uintmax_t)stats->rx_mcast_frames); 3221 printf("Receive pause control frames : %u\n", 3222 stats->rx_pause_frames); 3223 printf("Receive control frames : %u\n", 3224 stats->rx_control_frames); 3225 printf("Receive CRC errors : %u\n", 3226 stats->rx_crcerrs); 3227 printf("Receive frames with length errors : %u\n", 3228 stats->rx_lenerrs); 3229 printf("Receive good octets : %ju\n", 3230 (uintmax_t)stats->rx_bytes); 3231 printf("Receive good broadcast octets : %ju\n", 3232 (uintmax_t)stats->rx_bcast_bytes); 3233 printf("Receive good multicast octets : %ju\n", 3234 (uintmax_t)stats->rx_mcast_bytes); 3235 printf("Receive frames too short : %u\n", 3236 stats->rx_runts); 3237 printf("Receive fragmented frames : %ju\n", 3238 (uintmax_t)stats->rx_fragments); 3239 printf("Receive frames 64 bytes : %ju\n", 3240 (uintmax_t)stats->rx_pkts_64); 3241 printf("Receive frames 65 to 127 bytes : %ju\n", 3242 (uintmax_t)stats->rx_pkts_65_127); 3243 printf("Receive frames 128 to 255 bytes : %ju\n", 3244 (uintmax_t)stats->rx_pkts_128_255); 3245 printf("Receive frames 256 to 511 bytes : %ju\n", 3246 (uintmax_t)stats->rx_pkts_256_511); 3247 printf("Receive frames 512 to 1024 bytes : %ju\n", 3248 (uintmax_t)stats->rx_pkts_512_1023); 3249 printf("Receive frames 1024 to 1518 bytes : %ju\n", 3250 (uintmax_t)stats->rx_pkts_1024_1518); 3251 printf("Receive frames 1519 to MTU bytes : %ju\n", 3252 (uintmax_t)stats->rx_pkts_1519_max); 3253 printf("Receive frames too long : %ju\n", 3254 (uint64_t)stats->rx_pkts_truncated); 3255 printf("Receive frames with FIFO overflow : %u\n", 3256 stats->rx_fifo_oflows); 3257 printf("Receive frames with return descriptor overflow : %u\n", 3258 stats->rx_desc_oflows); 3259 printf("Receive frames with alignment errors : %u\n", 3260 stats->rx_alignerrs); 3261 printf("Receive frames dropped due to address filtering : %ju\n", 3262 (uint64_t)stats->rx_pkts_filtered); 3263 3264 return (error); 3265} 3266 3267static int 3268sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3269{ 3270 int error, value; 3271 3272 if (arg1 == NULL) 3273 return (EINVAL); 3274 value = *(int *)arg1; 3275 error = sysctl_handle_int(oidp, &value, 0, req); 3276 if (error || req->newptr == NULL) 3277 return (error); 3278 if (value < low || value > high) 3279 return (EINVAL); 3280 *(int *)arg1 = value; 3281 3282 return (0); 3283} 3284 3285static int 3286sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS) 3287{ 3288 return (sysctl_int_range(oidp, arg1, arg2, req, 3289 AGE_PROC_MIN, AGE_PROC_MAX)); 3290} 3291 3292static int 3293sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS) 3294{ 3295 3296 return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN, 3297 AGE_IM_TIMER_MAX)); 3298} 3299