1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD$"); 35 36/* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77/* 78 * The 3c90x series chips use a bus-master DMA interface for transfering 79 * packets to and from the controller chip. Some of the "vortex" cards 80 * (3c59x) also supported a bus master mode, however for those chips 81 * you could only DMA packets to/from a contiguous memory buffer. For 82 * transmission this would mean copying the contents of the queued mbuf 83 * chain into an mbuf cluster and then DMAing the cluster. This extra 84 * copy would sort of defeat the purpose of the bus master support for 85 * any packet that doesn't fit into a single mbuf. 86 * 87 * By contrast, the 3c90x cards support a fragment-based bus master 88 * mode where mbuf chains can be encapsulated using TX descriptors. 89 * This is similar to other PCI chips such as the Texas Instruments 90 * ThunderLAN and the Intel 82557/82558. 91 * 92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 93 * bus master chips because they maintain the old PIO interface for 94 * backwards compatibility, but starting with the 3c905B and the 95 * "cyclone" chips, the compatibility interface has been dropped. 96 * Since using bus master DMA is a big win, we use this driver to 97 * support the PCI "boomerang" chips even though they work with the 98 * "vortex" driver in order to obtain better performance. 99 */ 100 101#ifdef HAVE_KERNEL_OPTION_HEADERS 102#include "opt_device_polling.h" 103#endif 104 105#include <sys/param.h> 106#include <sys/systm.h> 107#include <sys/sockio.h> 108#include <sys/endian.h> 109#include <sys/mbuf.h> 110#include <sys/kernel.h> 111#include <sys/module.h> 112#include <sys/socket.h> 113#include <sys/taskqueue.h> 114 115#include <net/if.h> 116#include <net/if_arp.h> 117#include <net/ethernet.h> 118#include <net/if_dl.h> 119#include <net/if_media.h> 120#include <net/if_types.h> 121 122#include <net/bpf.h> 123 124#include <machine/bus.h> 125#include <machine/resource.h> 126#include <sys/bus.h> 127#include <sys/rman.h> 128 129#include <dev/mii/mii.h> 130#include <dev/mii/mii_bitbang.h> 131#include <dev/mii/miivar.h> 132 133#include <dev/pci/pcireg.h> 134#include <dev/pci/pcivar.h> 135 136MODULE_DEPEND(xl, pci, 1, 1, 1); 137MODULE_DEPEND(xl, ether, 1, 1, 1); 138MODULE_DEPEND(xl, miibus, 1, 1, 1); 139 140/* "device miibus" required. See GENERIC if you get errors here. */ 141#include "miibus_if.h" 142 143#include <dev/xl/if_xlreg.h> 144 145/* 146 * TX Checksumming is disabled by default for two reasons: 147 * - TX Checksumming will occasionally produce corrupt packets 148 * - TX Checksumming seems to reduce performance 149 * 150 * Only 905B/C cards were reported to have this problem, it is possible 151 * that later chips _may_ be immune. 152 */ 153#define XL905B_TXCSUM_BROKEN 1 154 155#ifdef XL905B_TXCSUM_BROKEN 156#define XL905B_CSUM_FEATURES 0 157#else 158#define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 159#endif 160 161/* 162 * Various supported device vendors/types and their names. 163 */ 164static const struct xl_type const xl_devs[] = { 165 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 166 "3Com 3c900-TPO Etherlink XL" }, 167 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 168 "3Com 3c900-COMBO Etherlink XL" }, 169 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 170 "3Com 3c905-TX Fast Etherlink XL" }, 171 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 172 "3Com 3c905-T4 Fast Etherlink XL" }, 173 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 174 "3Com 3c900B-TPO Etherlink XL" }, 175 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 176 "3Com 3c900B-COMBO Etherlink XL" }, 177 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 178 "3Com 3c900B-TPC Etherlink XL" }, 179 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 180 "3Com 3c900B-FL Etherlink XL" }, 181 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 182 "3Com 3c905B-TX Fast Etherlink XL" }, 183 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 184 "3Com 3c905B-T4 Fast Etherlink XL" }, 185 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 186 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 187 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 188 "3Com 3c905B-COMBO Fast Etherlink XL" }, 189 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 190 "3Com 3c905C-TX Fast Etherlink XL" }, 191 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 192 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 193 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM, 194 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" }, 195 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 196 "3Com 3c980 Fast Etherlink XL" }, 197 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 198 "3Com 3c980C Fast Etherlink XL" }, 199 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 200 "3Com 3cSOHO100-TX OfficeConnect" }, 201 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 202 "3Com 3c450-TX HomeConnect" }, 203 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 204 "3Com 3c555 Fast Etherlink XL" }, 205 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 206 "3Com 3c556 Fast Etherlink XL" }, 207 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 208 "3Com 3c556B Fast Etherlink XL" }, 209 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 210 "3Com 3c575TX Fast Etherlink XL" }, 211 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 212 "3Com 3c575B Fast Etherlink XL" }, 213 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 214 "3Com 3c575C Fast Etherlink XL" }, 215 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 216 "3Com 3c656 Fast Etherlink XL" }, 217 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 218 "3Com 3c656B Fast Etherlink XL" }, 219 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 220 "3Com 3c656C Fast Etherlink XL" }, 221 { 0, 0, NULL } 222}; 223 224static int xl_probe(device_t); 225static int xl_attach(device_t); 226static int xl_detach(device_t); 227 228static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *); 229static void xl_tick(void *); 230static void xl_stats_update(struct xl_softc *); 231static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **); 232static int xl_rxeof(struct xl_softc *); 233static void xl_rxeof_task(void *, int); 234static int xl_rx_resync(struct xl_softc *); 235static void xl_txeof(struct xl_softc *); 236static void xl_txeof_90xB(struct xl_softc *); 237static void xl_txeoc(struct xl_softc *); 238static void xl_intr(void *); 239static void xl_start(struct ifnet *); 240static void xl_start_locked(struct ifnet *); 241static void xl_start_90xB_locked(struct ifnet *); 242static int xl_ioctl(struct ifnet *, u_long, caddr_t); 243static void xl_init(void *); 244static void xl_init_locked(struct xl_softc *); 245static void xl_stop(struct xl_softc *); 246static int xl_watchdog(struct xl_softc *); 247static int xl_shutdown(device_t); 248static int xl_suspend(device_t); 249static int xl_resume(device_t); 250static void xl_setwol(struct xl_softc *); 251 252#ifdef DEVICE_POLLING 253static int xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 254static int xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); 255#endif 256 257static int xl_ifmedia_upd(struct ifnet *); 258static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 259 260static int xl_eeprom_wait(struct xl_softc *); 261static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int); 262 263static void xl_rxfilter(struct xl_softc *); 264static void xl_rxfilter_90x(struct xl_softc *); 265static void xl_rxfilter_90xB(struct xl_softc *); 266static void xl_setcfg(struct xl_softc *); 267static void xl_setmode(struct xl_softc *, int); 268static void xl_reset(struct xl_softc *); 269static int xl_list_rx_init(struct xl_softc *); 270static int xl_list_tx_init(struct xl_softc *); 271static int xl_list_tx_init_90xB(struct xl_softc *); 272static void xl_wait(struct xl_softc *); 273static void xl_mediacheck(struct xl_softc *); 274static void xl_choose_media(struct xl_softc *sc, int *media); 275static void xl_choose_xcvr(struct xl_softc *, int); 276static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int); 277#ifdef notdef 278static void xl_testpacket(struct xl_softc *); 279#endif 280 281static int xl_miibus_readreg(device_t, int, int); 282static int xl_miibus_writereg(device_t, int, int, int); 283static void xl_miibus_statchg(device_t); 284static void xl_miibus_mediainit(device_t); 285 286/* 287 * MII bit-bang glue 288 */ 289static uint32_t xl_mii_bitbang_read(device_t); 290static void xl_mii_bitbang_write(device_t, uint32_t); 291 292static const struct mii_bitbang_ops xl_mii_bitbang_ops = { 293 xl_mii_bitbang_read, 294 xl_mii_bitbang_write, 295 { 296 XL_MII_DATA, /* MII_BIT_MDO */ 297 XL_MII_DATA, /* MII_BIT_MDI */ 298 XL_MII_CLK, /* MII_BIT_MDC */ 299 XL_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 300 0, /* MII_BIT_DIR_PHY_HOST */ 301 } 302}; 303 304static device_method_t xl_methods[] = { 305 /* Device interface */ 306 DEVMETHOD(device_probe, xl_probe), 307 DEVMETHOD(device_attach, xl_attach), 308 DEVMETHOD(device_detach, xl_detach), 309 DEVMETHOD(device_shutdown, xl_shutdown), 310 DEVMETHOD(device_suspend, xl_suspend), 311 DEVMETHOD(device_resume, xl_resume), 312 313 /* MII interface */ 314 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 315 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 316 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 317 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 318 319 DEVMETHOD_END 320}; 321 322static driver_t xl_driver = { 323 "xl", 324 xl_methods, 325 sizeof(struct xl_softc) 326}; 327 328static devclass_t xl_devclass; 329 330DRIVER_MODULE_ORDERED(xl, pci, xl_driver, xl_devclass, NULL, NULL, 331 SI_ORDER_ANY); 332DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, NULL, NULL); 333 334static void 335xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 336{ 337 u_int32_t *paddr; 338 339 paddr = arg; 340 *paddr = segs->ds_addr; 341} 342 343/* 344 * Murphy's law says that it's possible the chip can wedge and 345 * the 'command in progress' bit may never clear. Hence, we wait 346 * only a finite amount of time to avoid getting caught in an 347 * infinite loop. Normally this delay routine would be a macro, 348 * but it isn't called during normal operation so we can afford 349 * to make it a function. Suppress warning when card gone. 350 */ 351static void 352xl_wait(struct xl_softc *sc) 353{ 354 register int i; 355 356 for (i = 0; i < XL_TIMEOUT; i++) { 357 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0) 358 break; 359 } 360 361 if (i == XL_TIMEOUT && bus_child_present(sc->xl_dev)) 362 device_printf(sc->xl_dev, "command never completed!\n"); 363} 364 365/* 366 * MII access routines are provided for adapters with external 367 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 368 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 369 * Note: if you don't perform the MDIO operations just right, 370 * it's possible to end up with code that works correctly with 371 * some chips/CPUs/processor speeds/bus speeds/etc but not 372 * with others. 373 */ 374 375/* 376 * Read the MII serial port for the MII bit-bang module. 377 */ 378static uint32_t 379xl_mii_bitbang_read(device_t dev) 380{ 381 struct xl_softc *sc; 382 uint32_t val; 383 384 sc = device_get_softc(dev); 385 386 /* We're already in window 4. */ 387 val = CSR_READ_2(sc, XL_W4_PHY_MGMT); 388 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2, 389 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 390 391 return (val); 392} 393 394/* 395 * Write the MII serial port for the MII bit-bang module. 396 */ 397static void 398xl_mii_bitbang_write(device_t dev, uint32_t val) 399{ 400 struct xl_softc *sc; 401 402 sc = device_get_softc(dev); 403 404 /* We're already in window 4. */ 405 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val); 406 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2, 407 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 408} 409 410static int 411xl_miibus_readreg(device_t dev, int phy, int reg) 412{ 413 struct xl_softc *sc; 414 415 sc = device_get_softc(dev); 416 417 /* Select the window 4. */ 418 XL_SEL_WIN(4); 419 420 return (mii_bitbang_readreg(dev, &xl_mii_bitbang_ops, phy, reg)); 421} 422 423static int 424xl_miibus_writereg(device_t dev, int phy, int reg, int data) 425{ 426 struct xl_softc *sc; 427 428 sc = device_get_softc(dev); 429 430 /* Select the window 4. */ 431 XL_SEL_WIN(4); 432 433 mii_bitbang_writereg(dev, &xl_mii_bitbang_ops, phy, reg, data); 434 435 return (0); 436} 437 438static void 439xl_miibus_statchg(device_t dev) 440{ 441 struct xl_softc *sc; 442 struct mii_data *mii; 443 uint8_t macctl; 444 445 sc = device_get_softc(dev); 446 mii = device_get_softc(sc->xl_miibus); 447 448 xl_setcfg(sc); 449 450 /* Set ASIC's duplex mode to match the PHY. */ 451 XL_SEL_WIN(3); 452 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 453 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 454 macctl |= XL_MACCTRL_DUPLEX; 455 if (sc->xl_type == XL_TYPE_905B) { 456 if ((IFM_OPTIONS(mii->mii_media_active) & 457 IFM_ETH_RXPAUSE) != 0) 458 macctl |= XL_MACCTRL_FLOW_CONTROL_ENB; 459 else 460 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB; 461 } 462 } else { 463 macctl &= ~XL_MACCTRL_DUPLEX; 464 if (sc->xl_type == XL_TYPE_905B) 465 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB; 466 } 467 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 468} 469 470/* 471 * Special support for the 3c905B-COMBO. This card has 10/100 support 472 * plus BNC and AUI ports. This means we will have both an miibus attached 473 * plus some non-MII media settings. In order to allow this, we have to 474 * add the extra media to the miibus's ifmedia struct, but we can't do 475 * that during xl_attach() because the miibus hasn't been attached yet. 476 * So instead, we wait until the miibus probe/attach is done, at which 477 * point we will get a callback telling is that it's safe to add our 478 * extra media. 479 */ 480static void 481xl_miibus_mediainit(device_t dev) 482{ 483 struct xl_softc *sc; 484 struct mii_data *mii; 485 struct ifmedia *ifm; 486 487 sc = device_get_softc(dev); 488 mii = device_get_softc(sc->xl_miibus); 489 ifm = &mii->mii_media; 490 491 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) { 492 /* 493 * Check for a 10baseFL board in disguise. 494 */ 495 if (sc->xl_type == XL_TYPE_905B && 496 sc->xl_media == XL_MEDIAOPT_10FL) { 497 if (bootverbose) 498 device_printf(sc->xl_dev, "found 10baseFL\n"); 499 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL); 500 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0, 501 NULL); 502 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 503 ifmedia_add(ifm, 504 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL); 505 } else { 506 if (bootverbose) 507 device_printf(sc->xl_dev, "found AUI\n"); 508 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL); 509 } 510 } 511 512 if (sc->xl_media & XL_MEDIAOPT_BNC) { 513 if (bootverbose) 514 device_printf(sc->xl_dev, "found BNC\n"); 515 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL); 516 } 517} 518 519/* 520 * The EEPROM is slow: give it time to come ready after issuing 521 * it a command. 522 */ 523static int 524xl_eeprom_wait(struct xl_softc *sc) 525{ 526 int i; 527 528 for (i = 0; i < 100; i++) { 529 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 530 DELAY(162); 531 else 532 break; 533 } 534 535 if (i == 100) { 536 device_printf(sc->xl_dev, "eeprom failed to come ready\n"); 537 return (1); 538 } 539 540 return (0); 541} 542 543/* 544 * Read a sequence of words from the EEPROM. Note that ethernet address 545 * data is stored in the EEPROM in network byte order. 546 */ 547static int 548xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 549{ 550 int err = 0, i; 551 u_int16_t word = 0, *ptr; 552 553#define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 554#define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 555 /* 556 * XXX: WARNING! DANGER! 557 * It's easy to accidentally overwrite the rom content! 558 * Note: the 3c575 uses 8bit EEPROM offsets. 559 */ 560 XL_SEL_WIN(0); 561 562 if (xl_eeprom_wait(sc)) 563 return (1); 564 565 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 566 off += 0x30; 567 568 for (i = 0; i < cnt; i++) { 569 if (sc->xl_flags & XL_FLAG_8BITROM) 570 CSR_WRITE_2(sc, XL_W0_EE_CMD, 571 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 572 else 573 CSR_WRITE_2(sc, XL_W0_EE_CMD, 574 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 575 err = xl_eeprom_wait(sc); 576 if (err) 577 break; 578 word = CSR_READ_2(sc, XL_W0_EE_DATA); 579 ptr = (u_int16_t *)(dest + (i * 2)); 580 if (swap) 581 *ptr = ntohs(word); 582 else 583 *ptr = word; 584 } 585 586 return (err ? 1 : 0); 587} 588 589static void 590xl_rxfilter(struct xl_softc *sc) 591{ 592 593 if (sc->xl_type == XL_TYPE_905B) 594 xl_rxfilter_90xB(sc); 595 else 596 xl_rxfilter_90x(sc); 597} 598 599/* 600 * NICs older than the 3c905B have only one multicast option, which 601 * is to enable reception of all multicast frames. 602 */ 603static void 604xl_rxfilter_90x(struct xl_softc *sc) 605{ 606 struct ifnet *ifp; 607 struct ifmultiaddr *ifma; 608 u_int8_t rxfilt; 609 610 XL_LOCK_ASSERT(sc); 611 612 ifp = sc->xl_ifp; 613 614 XL_SEL_WIN(5); 615 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 616 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI | 617 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL); 618 619 /* Set the individual bit to receive frames for this host only. */ 620 rxfilt |= XL_RXFILTER_INDIVIDUAL; 621 /* Set capture broadcast bit to capture broadcast frames. */ 622 if (ifp->if_flags & IFF_BROADCAST) 623 rxfilt |= XL_RXFILTER_BROADCAST; 624 625 /* If we want promiscuous mode, set the allframes bit. */ 626 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 627 if (ifp->if_flags & IFF_PROMISC) 628 rxfilt |= XL_RXFILTER_ALLFRAMES; 629 if (ifp->if_flags & IFF_ALLMULTI) 630 rxfilt |= XL_RXFILTER_ALLMULTI; 631 } else { 632 if_maddr_rlock(ifp); 633 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 634 if (ifma->ifma_addr->sa_family != AF_LINK) 635 continue; 636 rxfilt |= XL_RXFILTER_ALLMULTI; 637 break; 638 } 639 if_maddr_runlock(ifp); 640 } 641 642 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 643 XL_SEL_WIN(7); 644} 645 646/* 647 * 3c905B adapters have a hash filter that we can program. 648 */ 649static void 650xl_rxfilter_90xB(struct xl_softc *sc) 651{ 652 struct ifnet *ifp; 653 struct ifmultiaddr *ifma; 654 int i, mcnt; 655 u_int16_t h; 656 u_int8_t rxfilt; 657 658 XL_LOCK_ASSERT(sc); 659 660 ifp = sc->xl_ifp; 661 662 XL_SEL_WIN(5); 663 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 664 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI | 665 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL | 666 XL_RXFILTER_MULTIHASH); 667 668 /* Set the individual bit to receive frames for this host only. */ 669 rxfilt |= XL_RXFILTER_INDIVIDUAL; 670 /* Set capture broadcast bit to capture broadcast frames. */ 671 if (ifp->if_flags & IFF_BROADCAST) 672 rxfilt |= XL_RXFILTER_BROADCAST; 673 674 /* If we want promiscuous mode, set the allframes bit. */ 675 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 676 if (ifp->if_flags & IFF_PROMISC) 677 rxfilt |= XL_RXFILTER_ALLFRAMES; 678 if (ifp->if_flags & IFF_ALLMULTI) 679 rxfilt |= XL_RXFILTER_ALLMULTI; 680 } else { 681 /* First, zot all the existing hash bits. */ 682 for (i = 0; i < XL_HASHFILT_SIZE; i++) 683 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i); 684 685 /* Now program new ones. */ 686 mcnt = 0; 687 if_maddr_rlock(ifp); 688 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 689 if (ifma->ifma_addr->sa_family != AF_LINK) 690 continue; 691 /* 692 * Note: the 3c905B currently only supports a 64-bit 693 * hash table, which means we really only need 6 bits, 694 * but the manual indicates that future chip revisions 695 * will have a 256-bit hash table, hence the routine 696 * is set up to calculate 8 bits of position info in 697 * case we need it some day. 698 * Note II, The Sequel: _CURRENT_ versions of the 699 * 3c905B have a 256 bit hash table. This means we have 700 * to use all 8 bits regardless. On older cards, the 701 * upper 2 bits will be ignored. Grrrr.... 702 */ 703 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 704 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 705 CSR_WRITE_2(sc, XL_COMMAND, 706 h | XL_CMD_RX_SET_HASH | XL_HASH_SET); 707 mcnt++; 708 } 709 if_maddr_runlock(ifp); 710 if (mcnt > 0) 711 rxfilt |= XL_RXFILTER_MULTIHASH; 712 } 713 714 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 715 XL_SEL_WIN(7); 716} 717 718static void 719xl_setcfg(struct xl_softc *sc) 720{ 721 u_int32_t icfg; 722 723 /*XL_LOCK_ASSERT(sc);*/ 724 725 XL_SEL_WIN(3); 726 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 727 icfg &= ~XL_ICFG_CONNECTOR_MASK; 728 if (sc->xl_media & XL_MEDIAOPT_MII || 729 sc->xl_media & XL_MEDIAOPT_BT4) 730 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 731 if (sc->xl_media & XL_MEDIAOPT_BTX) 732 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 733 734 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 735 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 736} 737 738static void 739xl_setmode(struct xl_softc *sc, int media) 740{ 741 u_int32_t icfg; 742 u_int16_t mediastat; 743 char *pmsg = "", *dmsg = ""; 744 745 XL_LOCK_ASSERT(sc); 746 747 XL_SEL_WIN(4); 748 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 749 XL_SEL_WIN(3); 750 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 751 752 if (sc->xl_media & XL_MEDIAOPT_BT) { 753 if (IFM_SUBTYPE(media) == IFM_10_T) { 754 pmsg = "10baseT transceiver"; 755 sc->xl_xcvr = XL_XCVR_10BT; 756 icfg &= ~XL_ICFG_CONNECTOR_MASK; 757 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 758 mediastat |= XL_MEDIASTAT_LINKBEAT | 759 XL_MEDIASTAT_JABGUARD; 760 mediastat &= ~XL_MEDIASTAT_SQEENB; 761 } 762 } 763 764 if (sc->xl_media & XL_MEDIAOPT_BFX) { 765 if (IFM_SUBTYPE(media) == IFM_100_FX) { 766 pmsg = "100baseFX port"; 767 sc->xl_xcvr = XL_XCVR_100BFX; 768 icfg &= ~XL_ICFG_CONNECTOR_MASK; 769 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 770 mediastat |= XL_MEDIASTAT_LINKBEAT; 771 mediastat &= ~XL_MEDIASTAT_SQEENB; 772 } 773 } 774 775 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 776 if (IFM_SUBTYPE(media) == IFM_10_5) { 777 pmsg = "AUI port"; 778 sc->xl_xcvr = XL_XCVR_AUI; 779 icfg &= ~XL_ICFG_CONNECTOR_MASK; 780 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 781 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 782 XL_MEDIASTAT_JABGUARD); 783 mediastat |= ~XL_MEDIASTAT_SQEENB; 784 } 785 if (IFM_SUBTYPE(media) == IFM_10_FL) { 786 pmsg = "10baseFL transceiver"; 787 sc->xl_xcvr = XL_XCVR_AUI; 788 icfg &= ~XL_ICFG_CONNECTOR_MASK; 789 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 790 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 791 XL_MEDIASTAT_JABGUARD); 792 mediastat |= ~XL_MEDIASTAT_SQEENB; 793 } 794 } 795 796 if (sc->xl_media & XL_MEDIAOPT_BNC) { 797 if (IFM_SUBTYPE(media) == IFM_10_2) { 798 pmsg = "AUI port"; 799 sc->xl_xcvr = XL_XCVR_COAX; 800 icfg &= ~XL_ICFG_CONNECTOR_MASK; 801 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 802 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 803 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB); 804 } 805 } 806 807 if ((media & IFM_GMASK) == IFM_FDX || 808 IFM_SUBTYPE(media) == IFM_100_FX) { 809 dmsg = "full"; 810 XL_SEL_WIN(3); 811 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 812 } else { 813 dmsg = "half"; 814 XL_SEL_WIN(3); 815 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 816 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 817 } 818 819 if (IFM_SUBTYPE(media) == IFM_10_2) 820 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 821 else 822 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 823 824 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 825 XL_SEL_WIN(4); 826 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 827 828 DELAY(800); 829 XL_SEL_WIN(7); 830 831 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg); 832} 833 834static void 835xl_reset(struct xl_softc *sc) 836{ 837 register int i; 838 839 XL_LOCK_ASSERT(sc); 840 841 XL_SEL_WIN(0); 842 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 843 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 844 XL_RESETOPT_DISADVFD:0)); 845 846 /* 847 * If we're using memory mapped register mode, pause briefly 848 * after issuing the reset command before trying to access any 849 * other registers. With my 3c575C CardBus card, failing to do 850 * this results in the system locking up while trying to poll 851 * the command busy bit in the status register. 852 */ 853 if (sc->xl_flags & XL_FLAG_USE_MMIO) 854 DELAY(100000); 855 856 for (i = 0; i < XL_TIMEOUT; i++) { 857 DELAY(10); 858 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 859 break; 860 } 861 862 if (i == XL_TIMEOUT) 863 device_printf(sc->xl_dev, "reset didn't complete\n"); 864 865 /* Reset TX and RX. */ 866 /* Note: the RX reset takes an absurd amount of time 867 * on newer versions of the Tornado chips such as those 868 * on the 3c905CX and newer 3c908C cards. We wait an 869 * extra amount of time so that xl_wait() doesn't complain 870 * and annoy the users. 871 */ 872 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 873 DELAY(100000); 874 xl_wait(sc); 875 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 876 xl_wait(sc); 877 878 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 879 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 880 XL_SEL_WIN(2); 881 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, 882 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) | 883 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ? 884 XL_RESETOPT_INVERT_LED : 0) | 885 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ? 886 XL_RESETOPT_INVERT_MII : 0)); 887 } 888 889 /* Wait a little while for the chip to get its brains in order. */ 890 DELAY(100000); 891} 892 893/* 894 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 895 * IDs against our list and return a device name if we find a match. 896 */ 897static int 898xl_probe(device_t dev) 899{ 900 const struct xl_type *t; 901 902 t = xl_devs; 903 904 while (t->xl_name != NULL) { 905 if ((pci_get_vendor(dev) == t->xl_vid) && 906 (pci_get_device(dev) == t->xl_did)) { 907 device_set_desc(dev, t->xl_name); 908 return (BUS_PROBE_DEFAULT); 909 } 910 t++; 911 } 912 913 return (ENXIO); 914} 915 916/* 917 * This routine is a kludge to work around possible hardware faults 918 * or manufacturing defects that can cause the media options register 919 * (or reset options register, as it's called for the first generation 920 * 3c90x adapters) to return an incorrect result. I have encountered 921 * one Dell Latitude laptop docking station with an integrated 3c905-TX 922 * which doesn't have any of the 'mediaopt' bits set. This screws up 923 * the attach routine pretty badly because it doesn't know what media 924 * to look for. If we find ourselves in this predicament, this routine 925 * will try to guess the media options values and warn the user of a 926 * possible manufacturing defect with his adapter/system/whatever. 927 */ 928static void 929xl_mediacheck(struct xl_softc *sc) 930{ 931 932 /* 933 * If some of the media options bits are set, assume they are 934 * correct. If not, try to figure it out down below. 935 * XXX I should check for 10baseFL, but I don't have an adapter 936 * to test with. 937 */ 938 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 939 /* 940 * Check the XCVR value. If it's not in the normal range 941 * of values, we need to fake it up here. 942 */ 943 if (sc->xl_xcvr <= XL_XCVR_AUTO) 944 return; 945 else { 946 device_printf(sc->xl_dev, 947 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr); 948 device_printf(sc->xl_dev, 949 "choosing new default based on card type\n"); 950 } 951 } else { 952 if (sc->xl_type == XL_TYPE_905B && 953 sc->xl_media & XL_MEDIAOPT_10FL) 954 return; 955 device_printf(sc->xl_dev, 956"WARNING: no media options bits set in the media options register!!\n"); 957 device_printf(sc->xl_dev, 958"this could be a manufacturing defect in your adapter or system\n"); 959 device_printf(sc->xl_dev, 960"attempting to guess media type; you should probably consult your vendor\n"); 961 } 962 963 xl_choose_xcvr(sc, 1); 964} 965 966static void 967xl_choose_xcvr(struct xl_softc *sc, int verbose) 968{ 969 u_int16_t devid; 970 971 /* 972 * Read the device ID from the EEPROM. 973 * This is what's loaded into the PCI device ID register, so it has 974 * to be correct otherwise we wouldn't have gotten this far. 975 */ 976 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 977 978 switch (devid) { 979 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 980 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 981 sc->xl_media = XL_MEDIAOPT_BT; 982 sc->xl_xcvr = XL_XCVR_10BT; 983 if (verbose) 984 device_printf(sc->xl_dev, 985 "guessing 10BaseT transceiver\n"); 986 break; 987 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 988 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 989 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 990 sc->xl_xcvr = XL_XCVR_10BT; 991 if (verbose) 992 device_printf(sc->xl_dev, 993 "guessing COMBO (AUI/BNC/TP)\n"); 994 break; 995 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 996 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 997 sc->xl_xcvr = XL_XCVR_10BT; 998 if (verbose) 999 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n"); 1000 break; 1001 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1002 sc->xl_media = XL_MEDIAOPT_10FL; 1003 sc->xl_xcvr = XL_XCVR_AUI; 1004 if (verbose) 1005 device_printf(sc->xl_dev, "guessing 10baseFL\n"); 1006 break; 1007 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1008 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1009 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1010 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1011 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1012 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1013 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1014 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1015 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1016 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1017 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1018 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */ 1019 sc->xl_media = XL_MEDIAOPT_MII; 1020 sc->xl_xcvr = XL_XCVR_MII; 1021 if (verbose) 1022 device_printf(sc->xl_dev, "guessing MII\n"); 1023 break; 1024 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1025 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1026 sc->xl_media = XL_MEDIAOPT_BT4; 1027 sc->xl_xcvr = XL_XCVR_MII; 1028 if (verbose) 1029 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n"); 1030 break; 1031 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1032 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1033 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1034 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1035 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1036 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1037 sc->xl_media = XL_MEDIAOPT_BTX; 1038 sc->xl_xcvr = XL_XCVR_AUTO; 1039 if (verbose) 1040 device_printf(sc->xl_dev, "guessing 10/100 internal\n"); 1041 break; 1042 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1043 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1044 sc->xl_xcvr = XL_XCVR_AUTO; 1045 if (verbose) 1046 device_printf(sc->xl_dev, 1047 "guessing 10/100 plus BNC/AUI\n"); 1048 break; 1049 default: 1050 device_printf(sc->xl_dev, 1051 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1052 sc->xl_media = XL_MEDIAOPT_BT; 1053 break; 1054 } 1055} 1056 1057/* 1058 * Attach the interface. Allocate softc structures, do ifmedia 1059 * setup and ethernet/BPF attach. 1060 */ 1061static int 1062xl_attach(device_t dev) 1063{ 1064 u_char eaddr[ETHER_ADDR_LEN]; 1065 u_int16_t sinfo2, xcvr[2]; 1066 struct xl_softc *sc; 1067 struct ifnet *ifp; 1068 int media, pmcap; 1069 int error = 0, phy, rid, res, unit; 1070 uint16_t did; 1071 1072 sc = device_get_softc(dev); 1073 sc->xl_dev = dev; 1074 1075 unit = device_get_unit(dev); 1076 1077 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1078 MTX_DEF); 1079 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1080 1081 did = pci_get_device(dev); 1082 1083 sc->xl_flags = 0; 1084 if (did == TC_DEVICEID_HURRICANE_555) 1085 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1086 if (did == TC_DEVICEID_HURRICANE_556 || 1087 did == TC_DEVICEID_HURRICANE_556B) 1088 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1089 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1090 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1091 if (did == TC_DEVICEID_HURRICANE_555 || 1092 did == TC_DEVICEID_HURRICANE_556) 1093 sc->xl_flags |= XL_FLAG_8BITROM; 1094 if (did == TC_DEVICEID_HURRICANE_556B) 1095 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1096 1097 if (did == TC_DEVICEID_HURRICANE_575B || 1098 did == TC_DEVICEID_HURRICANE_575C || 1099 did == TC_DEVICEID_HURRICANE_656B || 1100 did == TC_DEVICEID_TORNADO_656C) 1101 sc->xl_flags |= XL_FLAG_FUNCREG; 1102 if (did == TC_DEVICEID_HURRICANE_575A || 1103 did == TC_DEVICEID_HURRICANE_575B || 1104 did == TC_DEVICEID_HURRICANE_575C || 1105 did == TC_DEVICEID_HURRICANE_656B || 1106 did == TC_DEVICEID_TORNADO_656C) 1107 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1108 XL_FLAG_8BITROM; 1109 if (did == TC_DEVICEID_HURRICANE_656) 1110 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1111 if (did == TC_DEVICEID_HURRICANE_575B) 1112 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1113 if (did == TC_DEVICEID_HURRICANE_575C) 1114 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1115 if (did == TC_DEVICEID_TORNADO_656C) 1116 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1117 if (did == TC_DEVICEID_HURRICANE_656 || 1118 did == TC_DEVICEID_HURRICANE_656B) 1119 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1120 XL_FLAG_INVERT_LED_PWR; 1121 if (did == TC_DEVICEID_TORNADO_10_100BT_920B || 1122 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM) 1123 sc->xl_flags |= XL_FLAG_PHYOK; 1124 1125 switch (did) { 1126#ifdef __HAIKU__ 1127 case TC_DEVICEID_BOOMERANG_10BT_COMBO: 1128#endif 1129 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1130 case TC_DEVICEID_HURRICANE_575A: 1131 case TC_DEVICEID_HURRICANE_575B: 1132 case TC_DEVICEID_HURRICANE_575C: 1133 sc->xl_flags |= XL_FLAG_NO_MMIO; 1134 break; 1135 default: 1136 break; 1137 } 1138 1139 /* 1140 * Map control/status registers. 1141 */ 1142 pci_enable_busmaster(dev); 1143 1144 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) { 1145 rid = XL_PCI_LOMEM; 1146 res = SYS_RES_MEMORY; 1147 1148 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1149 } 1150 1151 if (sc->xl_res != NULL) { 1152 sc->xl_flags |= XL_FLAG_USE_MMIO; 1153 if (bootverbose) 1154 device_printf(dev, "using memory mapped I/O\n"); 1155 } else { 1156 rid = XL_PCI_LOIO; 1157 res = SYS_RES_IOPORT; 1158 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1159 if (sc->xl_res == NULL) { 1160 device_printf(dev, "couldn't map ports/memory\n"); 1161 error = ENXIO; 1162 goto fail; 1163 } 1164 if (bootverbose) 1165 device_printf(dev, "using port I/O\n"); 1166 } 1167 1168 sc->xl_btag = rman_get_bustag(sc->xl_res); 1169 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1170 1171 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1172 rid = XL_PCI_FUNCMEM; 1173 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1174 RF_ACTIVE); 1175 1176 if (sc->xl_fres == NULL) { 1177 device_printf(dev, "couldn't map funcreg memory\n"); 1178 error = ENXIO; 1179 goto fail; 1180 } 1181 1182 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1183 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1184 } 1185 1186 /* Allocate interrupt */ 1187 rid = 0; 1188 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1189 RF_SHAREABLE | RF_ACTIVE); 1190 if (sc->xl_irq == NULL) { 1191 device_printf(dev, "couldn't map interrupt\n"); 1192 error = ENXIO; 1193 goto fail; 1194 } 1195 1196 /* Initialize interface name. */ 1197 ifp = sc->xl_ifp = if_alloc(IFT_ETHER); 1198 if (ifp == NULL) { 1199 device_printf(dev, "can not if_alloc()\n"); 1200 error = ENOSPC; 1201 goto fail; 1202 } 1203 ifp->if_softc = sc; 1204 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1205 1206 /* Reset the adapter. */ 1207 XL_LOCK(sc); 1208 xl_reset(sc); 1209 XL_UNLOCK(sc); 1210 1211 /* 1212 * Get station address from the EEPROM. 1213 */ 1214 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1215 device_printf(dev, "failed to read station address\n"); 1216 error = ENXIO; 1217 goto fail; 1218 } 1219 1220 callout_init_mtx(&sc->xl_tick_callout, &sc->xl_mtx, 0); 1221 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc); 1222 1223 /* 1224 * Now allocate a tag for the DMA descriptor lists and a chunk 1225 * of DMA-able memory based on the tag. Also obtain the DMA 1226 * addresses of the RX and TX ring, which we'll need later. 1227 * All of our lists are allocated as a contiguous block 1228 * of memory. 1229 */ 1230 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1231 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1232 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL, 1233 &sc->xl_ldata.xl_rx_tag); 1234 if (error) { 1235 device_printf(dev, "failed to allocate rx dma tag\n"); 1236 goto fail; 1237 } 1238 1239 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1240 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | 1241 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_rx_dmamap); 1242 if (error) { 1243 device_printf(dev, "no memory for rx list buffers!\n"); 1244 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1245 sc->xl_ldata.xl_rx_tag = NULL; 1246 goto fail; 1247 } 1248 1249 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1250 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1251 XL_RX_LIST_SZ, xl_dma_map_addr, 1252 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1253 if (error) { 1254 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1255 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1256 sc->xl_ldata.xl_rx_dmamap); 1257 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1258 sc->xl_ldata.xl_rx_tag = NULL; 1259 goto fail; 1260 } 1261 1262 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1263 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1264 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL, 1265 &sc->xl_ldata.xl_tx_tag); 1266 if (error) { 1267 device_printf(dev, "failed to allocate tx dma tag\n"); 1268 goto fail; 1269 } 1270 1271 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1272 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | 1273 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_tx_dmamap); 1274 if (error) { 1275 device_printf(dev, "no memory for list buffers!\n"); 1276 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1277 sc->xl_ldata.xl_tx_tag = NULL; 1278 goto fail; 1279 } 1280 1281 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1282 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1283 XL_TX_LIST_SZ, xl_dma_map_addr, 1284 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1285 if (error) { 1286 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1287 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1288 sc->xl_ldata.xl_tx_dmamap); 1289 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1290 sc->xl_ldata.xl_tx_tag = NULL; 1291 goto fail; 1292 } 1293 1294 /* 1295 * Allocate a DMA tag for the mapping of mbufs. 1296 */ 1297 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1298 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1299 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL, 1300 NULL, &sc->xl_mtag); 1301 if (error) { 1302 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1303 goto fail; 1304 } 1305 1306 /* We need a spare DMA map for the RX ring. */ 1307 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1308 if (error) 1309 goto fail; 1310 1311 /* 1312 * Figure out the card type. 3c905B adapters have the 1313 * 'supportsNoTxLength' bit set in the capabilities 1314 * word in the EEPROM. 1315 * Note: my 3c575C CardBus card lies. It returns a value 1316 * of 0x1578 for its capabilities word, which is somewhat 1317 * nonsensical. Another way to distinguish a 3c90x chip 1318 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1319 * bit. This will only be set for 3c90x boomerage chips. 1320 */ 1321 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1322 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1323 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1324 sc->xl_type = XL_TYPE_905B; 1325 else 1326 sc->xl_type = XL_TYPE_90X; 1327 1328 /* Check availability of WOL. */ 1329 if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 && 1330 pci_find_cap(dev, PCIY_PMG, &pmcap) == 0) { 1331 sc->xl_pmcap = pmcap; 1332 sc->xl_flags |= XL_FLAG_WOL; 1333 sinfo2 = 0; 1334 xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0); 1335 if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose) 1336 device_printf(dev, 1337 "No auxiliary remote wakeup connector!\n"); 1338 } 1339 1340 /* Set the TX start threshold for best performance. */ 1341 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 1342 1343 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1344 ifp->if_ioctl = xl_ioctl; 1345 ifp->if_capabilities = IFCAP_VLAN_MTU; 1346 if (sc->xl_type == XL_TYPE_905B) { 1347 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1348#ifdef XL905B_TXCSUM_BROKEN 1349 ifp->if_capabilities |= IFCAP_RXCSUM; 1350#else 1351 ifp->if_capabilities |= IFCAP_HWCSUM; 1352#endif 1353 } 1354 if ((sc->xl_flags & XL_FLAG_WOL) != 0) 1355 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 1356 ifp->if_capenable = ifp->if_capabilities; 1357#ifdef DEVICE_POLLING 1358 ifp->if_capabilities |= IFCAP_POLLING; 1359#endif 1360 ifp->if_start = xl_start; 1361 ifp->if_init = xl_init; 1362 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1363 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1; 1364 IFQ_SET_READY(&ifp->if_snd); 1365 1366 /* 1367 * Now we have to see what sort of media we have. 1368 * This includes probing for an MII interace and a 1369 * possible PHY. 1370 */ 1371 XL_SEL_WIN(3); 1372 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1373 if (bootverbose) 1374 device_printf(dev, "media options word: %x\n", sc->xl_media); 1375 1376 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1377 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1378 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1379 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1380 1381#ifdef __HAIKU__ 1382 if (did == TC_DEVICEID_BOOMERANG_10BT_COMBO) 1383 sc->xl_xcvr = XL_XCVR_10BT; 1384#endif 1385 1386 xl_mediacheck(sc); 1387 1388 if (sc->xl_media & XL_MEDIAOPT_MII || 1389 sc->xl_media & XL_MEDIAOPT_BTX || 1390 sc->xl_media & XL_MEDIAOPT_BT4) { 1391 if (bootverbose) 1392 device_printf(dev, "found MII/AUTO\n"); 1393 xl_setcfg(sc); 1394 /* 1395 * Attach PHYs only at MII address 24 if !XL_FLAG_PHYOK. 1396 * This is to guard against problems with certain 3Com ASIC 1397 * revisions that incorrectly map the internal transceiver 1398 * control registers at all MII addresses. 1399 */ 1400 phy = MII_PHY_ANY; 1401 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0) 1402 phy = 24; 1403 error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd, 1404 xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 1405 sc->xl_type == XL_TYPE_905B ? MIIF_DOPAUSE : 0); 1406 if (error != 0) { 1407 device_printf(dev, "attaching PHYs failed\n"); 1408 goto fail; 1409 } 1410 goto done; 1411 } 1412 1413 /* 1414 * Sanity check. If the user has selected "auto" and this isn't 1415 * a 10/100 card of some kind, we need to force the transceiver 1416 * type to something sane. 1417 */ 1418 if (sc->xl_xcvr == XL_XCVR_AUTO) 1419 xl_choose_xcvr(sc, bootverbose); 1420 1421 /* 1422 * Do ifmedia setup. 1423 */ 1424 if (sc->xl_media & XL_MEDIAOPT_BT) { 1425 if (bootverbose) 1426 device_printf(dev, "found 10baseT\n"); 1427 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1428 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1429 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1430 ifmedia_add(&sc->ifmedia, 1431 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1432 } 1433 1434 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1435 /* 1436 * Check for a 10baseFL board in disguise. 1437 */ 1438 if (sc->xl_type == XL_TYPE_905B && 1439 sc->xl_media == XL_MEDIAOPT_10FL) { 1440 if (bootverbose) 1441 device_printf(dev, "found 10baseFL\n"); 1442 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1443 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1444 0, NULL); 1445 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1446 ifmedia_add(&sc->ifmedia, 1447 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1448 } else { 1449 if (bootverbose) 1450 device_printf(dev, "found AUI\n"); 1451 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1452 } 1453 } 1454 1455 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1456 if (bootverbose) 1457 device_printf(dev, "found BNC\n"); 1458 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1459 } 1460 1461 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1462 if (bootverbose) 1463 device_printf(dev, "found 100baseFX\n"); 1464 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1465 } 1466 1467 media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1468 xl_choose_media(sc, &media); 1469 1470 if (sc->xl_miibus == NULL) 1471 ifmedia_set(&sc->ifmedia, media); 1472 1473done: 1474 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1475 XL_SEL_WIN(0); 1476 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1477 } 1478 1479 /* 1480 * Call MI attach routine. 1481 */ 1482 ether_ifattach(ifp, eaddr); 1483 1484 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1485 NULL, xl_intr, sc, &sc->xl_intrhand); 1486 if (error) { 1487 device_printf(dev, "couldn't set up irq\n"); 1488 ether_ifdetach(ifp); 1489 goto fail; 1490 } 1491 1492fail: 1493 if (error) 1494 xl_detach(dev); 1495 1496 return (error); 1497} 1498 1499/* 1500 * Choose a default media. 1501 * XXX This is a leaf function only called by xl_attach() and 1502 * acquires/releases the non-recursible driver mutex to 1503 * satisfy lock assertions. 1504 */ 1505static void 1506xl_choose_media(struct xl_softc *sc, int *media) 1507{ 1508 1509 XL_LOCK(sc); 1510 1511 switch (sc->xl_xcvr) { 1512 case XL_XCVR_10BT: 1513 *media = IFM_ETHER|IFM_10_T; 1514 xl_setmode(sc, *media); 1515 break; 1516 case XL_XCVR_AUI: 1517 if (sc->xl_type == XL_TYPE_905B && 1518 sc->xl_media == XL_MEDIAOPT_10FL) { 1519 *media = IFM_ETHER|IFM_10_FL; 1520 xl_setmode(sc, *media); 1521 } else { 1522 *media = IFM_ETHER|IFM_10_5; 1523 xl_setmode(sc, *media); 1524 } 1525 break; 1526 case XL_XCVR_COAX: 1527 *media = IFM_ETHER|IFM_10_2; 1528 xl_setmode(sc, *media); 1529 break; 1530 case XL_XCVR_AUTO: 1531 case XL_XCVR_100BTX: 1532 case XL_XCVR_MII: 1533 /* Chosen by miibus */ 1534 break; 1535 case XL_XCVR_100BFX: 1536 *media = IFM_ETHER|IFM_100_FX; 1537 break; 1538 default: 1539 device_printf(sc->xl_dev, "unknown XCVR type: %d\n", 1540 sc->xl_xcvr); 1541 /* 1542 * This will probably be wrong, but it prevents 1543 * the ifmedia code from panicking. 1544 */ 1545 *media = IFM_ETHER|IFM_10_T; 1546 break; 1547 } 1548 1549 XL_UNLOCK(sc); 1550} 1551 1552/* 1553 * Shutdown hardware and free up resources. This can be called any 1554 * time after the mutex has been initialized. It is called in both 1555 * the error case in attach and the normal detach case so it needs 1556 * to be careful about only freeing resources that have actually been 1557 * allocated. 1558 */ 1559static int 1560xl_detach(device_t dev) 1561{ 1562 struct xl_softc *sc; 1563 struct ifnet *ifp; 1564 int rid, res; 1565 1566 sc = device_get_softc(dev); 1567 ifp = sc->xl_ifp; 1568 1569 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized")); 1570 1571#ifdef DEVICE_POLLING 1572 if (ifp && ifp->if_capenable & IFCAP_POLLING) 1573 ether_poll_deregister(ifp); 1574#endif 1575 1576 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1577 rid = XL_PCI_LOMEM; 1578 res = SYS_RES_MEMORY; 1579 } else { 1580 rid = XL_PCI_LOIO; 1581 res = SYS_RES_IOPORT; 1582 } 1583 1584 /* These should only be active if attach succeeded */ 1585 if (device_is_attached(dev)) { 1586 XL_LOCK(sc); 1587 xl_stop(sc); 1588 XL_UNLOCK(sc); 1589 taskqueue_drain(taskqueue_swi, &sc->xl_task); 1590 callout_drain(&sc->xl_tick_callout); 1591 ether_ifdetach(ifp); 1592 } 1593 if (sc->xl_miibus) 1594 device_delete_child(dev, sc->xl_miibus); 1595 bus_generic_detach(dev); 1596 ifmedia_removeall(&sc->ifmedia); 1597 1598 if (sc->xl_intrhand) 1599 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1600 if (sc->xl_irq) 1601 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1602 if (sc->xl_fres != NULL) 1603 bus_release_resource(dev, SYS_RES_MEMORY, 1604 XL_PCI_FUNCMEM, sc->xl_fres); 1605 if (sc->xl_res) 1606 bus_release_resource(dev, res, rid, sc->xl_res); 1607 1608 if (ifp) 1609 if_free(ifp); 1610 1611 if (sc->xl_mtag) { 1612 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1613 bus_dma_tag_destroy(sc->xl_mtag); 1614 } 1615 if (sc->xl_ldata.xl_rx_tag) { 1616 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1617 sc->xl_ldata.xl_rx_dmamap); 1618 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1619 sc->xl_ldata.xl_rx_dmamap); 1620 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1621 } 1622 if (sc->xl_ldata.xl_tx_tag) { 1623 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1624 sc->xl_ldata.xl_tx_dmamap); 1625 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1626 sc->xl_ldata.xl_tx_dmamap); 1627 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1628 } 1629 1630 mtx_destroy(&sc->xl_mtx); 1631 1632 return (0); 1633} 1634 1635/* 1636 * Initialize the transmit descriptors. 1637 */ 1638static int 1639xl_list_tx_init(struct xl_softc *sc) 1640{ 1641 struct xl_chain_data *cd; 1642 struct xl_list_data *ld; 1643 int error, i; 1644 1645 XL_LOCK_ASSERT(sc); 1646 1647 cd = &sc->xl_cdata; 1648 ld = &sc->xl_ldata; 1649 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1650 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1651 error = bus_dmamap_create(sc->xl_mtag, 0, 1652 &cd->xl_tx_chain[i].xl_map); 1653 if (error) 1654 return (error); 1655 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1656 i * sizeof(struct xl_list); 1657 if (i == (XL_TX_LIST_CNT - 1)) 1658 cd->xl_tx_chain[i].xl_next = NULL; 1659 else 1660 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1661 } 1662 1663 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1664 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1665 1666 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1667 return (0); 1668} 1669 1670/* 1671 * Initialize the transmit descriptors. 1672 */ 1673static int 1674xl_list_tx_init_90xB(struct xl_softc *sc) 1675{ 1676 struct xl_chain_data *cd; 1677 struct xl_list_data *ld; 1678 int error, i; 1679 1680 XL_LOCK_ASSERT(sc); 1681 1682 cd = &sc->xl_cdata; 1683 ld = &sc->xl_ldata; 1684 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1685 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1686 error = bus_dmamap_create(sc->xl_mtag, 0, 1687 &cd->xl_tx_chain[i].xl_map); 1688 if (error) 1689 return (error); 1690 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1691 i * sizeof(struct xl_list); 1692 if (i == (XL_TX_LIST_CNT - 1)) 1693 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1694 else 1695 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1696 if (i == 0) 1697 cd->xl_tx_chain[i].xl_prev = 1698 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1699 else 1700 cd->xl_tx_chain[i].xl_prev = 1701 &cd->xl_tx_chain[i - 1]; 1702 } 1703 1704 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1705 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1706 1707 cd->xl_tx_prod = 1; 1708 cd->xl_tx_cons = 1; 1709 cd->xl_tx_cnt = 0; 1710 1711 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1712 return (0); 1713} 1714 1715/* 1716 * Initialize the RX descriptors and allocate mbufs for them. Note that 1717 * we arrange the descriptors in a closed ring, so that the last descriptor 1718 * points back to the first. 1719 */ 1720static int 1721xl_list_rx_init(struct xl_softc *sc) 1722{ 1723 struct xl_chain_data *cd; 1724 struct xl_list_data *ld; 1725 int error, i, next; 1726 u_int32_t nextptr; 1727 1728 XL_LOCK_ASSERT(sc); 1729 1730 cd = &sc->xl_cdata; 1731 ld = &sc->xl_ldata; 1732 1733 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1734 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1735 error = bus_dmamap_create(sc->xl_mtag, 0, 1736 &cd->xl_rx_chain[i].xl_map); 1737 if (error) 1738 return (error); 1739 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1740 if (error) 1741 return (error); 1742 if (i == (XL_RX_LIST_CNT - 1)) 1743 next = 0; 1744 else 1745 next = i + 1; 1746 nextptr = ld->xl_rx_dmaaddr + 1747 next * sizeof(struct xl_list_onefrag); 1748 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1749 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1750 } 1751 1752 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1753 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1754 1755 return (0); 1756} 1757 1758/* 1759 * Initialize an RX descriptor and attach an MBUF cluster. 1760 * If we fail to do so, we need to leave the old mbuf and 1761 * the old DMA map untouched so that it can be reused. 1762 */ 1763static int 1764xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) 1765{ 1766 struct mbuf *m_new = NULL; 1767 bus_dmamap_t map; 1768 bus_dma_segment_t segs[1]; 1769 int error, nseg; 1770 1771 XL_LOCK_ASSERT(sc); 1772 1773 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1774 if (m_new == NULL) 1775 return (ENOBUFS); 1776 1777 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1778 1779 /* Force longword alignment for packet payload. */ 1780 m_adj(m_new, ETHER_ALIGN); 1781 1782 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new, 1783 segs, &nseg, BUS_DMA_NOWAIT); 1784 if (error) { 1785 m_freem(m_new); 1786 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n", 1787 error); 1788 return (error); 1789 } 1790 KASSERT(nseg == 1, 1791 ("%s: too many DMA segments (%d)", __func__, nseg)); 1792 1793 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1794 map = c->xl_map; 1795 c->xl_map = sc->xl_tmpmap; 1796 sc->xl_tmpmap = map; 1797 c->xl_mbuf = m_new; 1798 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1799 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr); 1800 c->xl_ptr->xl_status = 0; 1801 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1802 return (0); 1803} 1804 1805static int 1806xl_rx_resync(struct xl_softc *sc) 1807{ 1808 struct xl_chain_onefrag *pos; 1809 int i; 1810 1811 XL_LOCK_ASSERT(sc); 1812 1813 pos = sc->xl_cdata.xl_rx_head; 1814 1815 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1816 if (pos->xl_ptr->xl_status) 1817 break; 1818 pos = pos->xl_next; 1819 } 1820 1821 if (i == XL_RX_LIST_CNT) 1822 return (0); 1823 1824 sc->xl_cdata.xl_rx_head = pos; 1825 1826 return (EAGAIN); 1827} 1828 1829/* 1830 * A frame has been uploaded: pass the resulting mbuf chain up to 1831 * the higher level protocols. 1832 */ 1833static int 1834xl_rxeof(struct xl_softc *sc) 1835{ 1836 struct mbuf *m; 1837 struct ifnet *ifp = sc->xl_ifp; 1838 struct xl_chain_onefrag *cur_rx; 1839 int total_len; 1840 int rx_npkts = 0; 1841 u_int32_t rxstat; 1842 1843 XL_LOCK_ASSERT(sc); 1844again: 1845 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 1846 BUS_DMASYNC_POSTREAD); 1847 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 1848#ifdef DEVICE_POLLING 1849 if (ifp->if_capenable & IFCAP_POLLING) { 1850 if (sc->rxcycles <= 0) 1851 break; 1852 sc->rxcycles--; 1853 } 1854#endif 1855 cur_rx = sc->xl_cdata.xl_rx_head; 1856 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1857 total_len = rxstat & XL_RXSTAT_LENMASK; 1858 rx_npkts++; 1859 1860 /* 1861 * Since we have told the chip to allow large frames, 1862 * we need to trap giant frame errors in software. We allow 1863 * a little more than the normal frame size to account for 1864 * frames with VLAN tags. 1865 */ 1866 if (total_len > XL_MAX_FRAMELEN) 1867 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 1868 1869 /* 1870 * If an error occurs, update stats, clear the 1871 * status word and leave the mbuf cluster in place: 1872 * it should simply get re-used next time this descriptor 1873 * comes up in the ring. 1874 */ 1875 if (rxstat & XL_RXSTAT_UP_ERROR) { 1876 ifp->if_ierrors++; 1877 cur_rx->xl_ptr->xl_status = 0; 1878 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1879 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1880 continue; 1881 } 1882 1883 /* 1884 * If the error bit was not set, the upload complete 1885 * bit should be set which means we have a valid packet. 1886 * If not, something truly strange has happened. 1887 */ 1888 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 1889 device_printf(sc->xl_dev, 1890 "bad receive status -- packet dropped\n"); 1891 ifp->if_ierrors++; 1892 cur_rx->xl_ptr->xl_status = 0; 1893 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1894 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1895 continue; 1896 } 1897 1898 /* No errors; receive the packet. */ 1899 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 1900 BUS_DMASYNC_POSTREAD); 1901 m = cur_rx->xl_mbuf; 1902 1903 /* 1904 * Try to conjure up a new mbuf cluster. If that 1905 * fails, it means we have an out of memory condition and 1906 * should leave the buffer in place and continue. This will 1907 * result in a lost packet, but there's little else we 1908 * can do in this situation. 1909 */ 1910 if (xl_newbuf(sc, cur_rx)) { 1911 ifp->if_ierrors++; 1912 cur_rx->xl_ptr->xl_status = 0; 1913 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1914 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1915 continue; 1916 } 1917 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1918 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1919 1920 ifp->if_ipackets++; 1921 m->m_pkthdr.rcvif = ifp; 1922 m->m_pkthdr.len = m->m_len = total_len; 1923 1924 if (ifp->if_capenable & IFCAP_RXCSUM) { 1925 /* Do IP checksum checking. */ 1926 if (rxstat & XL_RXSTAT_IPCKOK) 1927 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1928 if (!(rxstat & XL_RXSTAT_IPCKERR)) 1929 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1930 if ((rxstat & XL_RXSTAT_TCPCOK && 1931 !(rxstat & XL_RXSTAT_TCPCKERR)) || 1932 (rxstat & XL_RXSTAT_UDPCKOK && 1933 !(rxstat & XL_RXSTAT_UDPCKERR))) { 1934 m->m_pkthdr.csum_flags |= 1935 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1936 m->m_pkthdr.csum_data = 0xffff; 1937 } 1938 } 1939 1940 XL_UNLOCK(sc); 1941 (*ifp->if_input)(ifp, m); 1942 XL_LOCK(sc); 1943 1944 /* 1945 * If we are running from the taskqueue, the interface 1946 * might have been stopped while we were passing the last 1947 * packet up the network stack. 1948 */ 1949 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1950 return (rx_npkts); 1951 } 1952 1953 /* 1954 * Handle the 'end of channel' condition. When the upload 1955 * engine hits the end of the RX ring, it will stall. This 1956 * is our cue to flush the RX ring, reload the uplist pointer 1957 * register and unstall the engine. 1958 * XXX This is actually a little goofy. With the ThunderLAN 1959 * chip, you get an interrupt when the receiver hits the end 1960 * of the receive ring, which tells you exactly when you 1961 * you need to reload the ring pointer. Here we have to 1962 * fake it. I'm mad at myself for not being clever enough 1963 * to avoid the use of a goto here. 1964 */ 1965 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 1966 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 1967 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 1968 xl_wait(sc); 1969 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 1970 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 1971 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 1972 goto again; 1973 } 1974 return (rx_npkts); 1975} 1976 1977/* 1978 * Taskqueue wrapper for xl_rxeof(). 1979 */ 1980static void 1981xl_rxeof_task(void *arg, int pending) 1982{ 1983 struct xl_softc *sc = (struct xl_softc *)arg; 1984 1985 XL_LOCK(sc); 1986 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING) 1987 xl_rxeof(sc); 1988 XL_UNLOCK(sc); 1989} 1990 1991/* 1992 * A frame was downloaded to the chip. It's safe for us to clean up 1993 * the list buffers. 1994 */ 1995static void 1996xl_txeof(struct xl_softc *sc) 1997{ 1998 struct xl_chain *cur_tx; 1999 struct ifnet *ifp = sc->xl_ifp; 2000 2001 XL_LOCK_ASSERT(sc); 2002 2003 /* 2004 * Go through our tx list and free mbufs for those 2005 * frames that have been uploaded. Note: the 3c905B 2006 * sets a special bit in the status word to let us 2007 * know that a frame has been downloaded, but the 2008 * original 3c900/3c905 adapters don't do that. 2009 * Consequently, we have to use a different test if 2010 * xl_type != XL_TYPE_905B. 2011 */ 2012 while (sc->xl_cdata.xl_tx_head != NULL) { 2013 cur_tx = sc->xl_cdata.xl_tx_head; 2014 2015 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2016 break; 2017 2018 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2019 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2020 BUS_DMASYNC_POSTWRITE); 2021 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2022 m_freem(cur_tx->xl_mbuf); 2023 cur_tx->xl_mbuf = NULL; 2024 ifp->if_opackets++; 2025 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2026 2027 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2028 sc->xl_cdata.xl_tx_free = cur_tx; 2029 } 2030 2031 if (sc->xl_cdata.xl_tx_head == NULL) { 2032 sc->xl_wdog_timer = 0; 2033 sc->xl_cdata.xl_tx_tail = NULL; 2034 } else { 2035 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2036 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2037 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2038 sc->xl_cdata.xl_tx_head->xl_phys); 2039 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2040 } 2041 } 2042} 2043 2044static void 2045xl_txeof_90xB(struct xl_softc *sc) 2046{ 2047 struct xl_chain *cur_tx = NULL; 2048 struct ifnet *ifp = sc->xl_ifp; 2049 int idx; 2050 2051 XL_LOCK_ASSERT(sc); 2052 2053 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2054 BUS_DMASYNC_POSTREAD); 2055 idx = sc->xl_cdata.xl_tx_cons; 2056 while (idx != sc->xl_cdata.xl_tx_prod) { 2057 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2058 2059 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2060 XL_TXSTAT_DL_COMPLETE)) 2061 break; 2062 2063 if (cur_tx->xl_mbuf != NULL) { 2064 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2065 BUS_DMASYNC_POSTWRITE); 2066 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2067 m_freem(cur_tx->xl_mbuf); 2068 cur_tx->xl_mbuf = NULL; 2069 } 2070 2071 ifp->if_opackets++; 2072 2073 sc->xl_cdata.xl_tx_cnt--; 2074 XL_INC(idx, XL_TX_LIST_CNT); 2075 } 2076 2077 if (sc->xl_cdata.xl_tx_cnt == 0) 2078 sc->xl_wdog_timer = 0; 2079 sc->xl_cdata.xl_tx_cons = idx; 2080 2081 if (cur_tx != NULL) 2082 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2083} 2084 2085/* 2086 * TX 'end of channel' interrupt handler. Actually, we should 2087 * only get a 'TX complete' interrupt if there's a transmit error, 2088 * so this is really TX error handler. 2089 */ 2090static void 2091xl_txeoc(struct xl_softc *sc) 2092{ 2093 u_int8_t txstat; 2094 2095 XL_LOCK_ASSERT(sc); 2096 2097 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2098 if (txstat & XL_TXSTATUS_UNDERRUN || 2099 txstat & XL_TXSTATUS_JABBER || 2100 txstat & XL_TXSTATUS_RECLAIM) { 2101 device_printf(sc->xl_dev, 2102 "transmission error: 0x%02x\n", txstat); 2103 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2104 xl_wait(sc); 2105 if (sc->xl_type == XL_TYPE_905B) { 2106 if (sc->xl_cdata.xl_tx_cnt) { 2107 int i; 2108 struct xl_chain *c; 2109 2110 i = sc->xl_cdata.xl_tx_cons; 2111 c = &sc->xl_cdata.xl_tx_chain[i]; 2112 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2113 c->xl_phys); 2114 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2115 sc->xl_wdog_timer = 5; 2116 } 2117 } else { 2118 if (sc->xl_cdata.xl_tx_head != NULL) { 2119 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2120 sc->xl_cdata.xl_tx_head->xl_phys); 2121 sc->xl_wdog_timer = 5; 2122 } 2123 } 2124 /* 2125 * Remember to set this for the 2126 * first generation 3c90X chips. 2127 */ 2128 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2129 if (txstat & XL_TXSTATUS_UNDERRUN && 2130 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2131 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2132 device_printf(sc->xl_dev, 2133"tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh); 2134 } 2135 CSR_WRITE_2(sc, XL_COMMAND, 2136 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2137 if (sc->xl_type == XL_TYPE_905B) { 2138 CSR_WRITE_2(sc, XL_COMMAND, 2139 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2140 } 2141 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2142 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2143 } else { 2144 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2145 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2146 } 2147 /* 2148 * Write an arbitrary byte to the TX_STATUS register 2149 * to clear this interrupt/error and advance to the next. 2150 */ 2151 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2152 } 2153} 2154 2155static void 2156xl_intr(void *arg) 2157{ 2158 struct xl_softc *sc = arg; 2159 struct ifnet *ifp = sc->xl_ifp; 2160 u_int16_t status; 2161 2162 XL_LOCK(sc); 2163 2164#ifdef DEVICE_POLLING 2165 if (ifp->if_capenable & IFCAP_POLLING) { 2166 XL_UNLOCK(sc); 2167 return; 2168 } 2169#endif 2170 2171 2172#ifndef __HAIKU__ 2173 for (;;) { 2174 status = CSR_READ_2(sc, XL_STATUS); 2175 if ((status & XL_INTRS) == 0 || status == 0xFFFF) 2176 break; 2177 CSR_WRITE_2(sc, XL_COMMAND, 2178 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2179#else 2180 status = atomic_get((int32 *)&sc->xl_intr_status); 2181 for (;;) { 2182#endif 2183 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2184 break; 2185 2186 if (status & XL_STAT_UP_COMPLETE) { 2187 if (xl_rxeof(sc) == 0) { 2188 while (xl_rx_resync(sc)) 2189 xl_rxeof(sc); 2190 } 2191 } 2192 2193 if (status & XL_STAT_DOWN_COMPLETE) { 2194 if (sc->xl_type == XL_TYPE_905B) 2195 xl_txeof_90xB(sc); 2196 else 2197 xl_txeof(sc); 2198 } 2199 2200 if (status & XL_STAT_TX_COMPLETE) { 2201 ifp->if_oerrors++; 2202 xl_txeoc(sc); 2203 } 2204 2205 if (status & XL_STAT_ADFAIL) { 2206 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2207 xl_init_locked(sc); 2208 break; 2209 } 2210 2211 if (status & XL_STAT_STATSOFLOW) 2212 xl_stats_update(sc); 2213#ifdef __HAIKU__ 2214 status = CSR_READ_2(sc, XL_STATUS); 2215 if ((status & XL_INTRS) == 0 || status == 0xFFFF) 2216 break; 2217 CSR_WRITE_2(sc, XL_COMMAND, 2218 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2219#endif 2220 } 2221 2222 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2223 ifp->if_drv_flags & IFF_DRV_RUNNING) { 2224 if (sc->xl_type == XL_TYPE_905B) 2225 xl_start_90xB_locked(ifp); 2226 else 2227 xl_start_locked(ifp); 2228 } 2229 2230 XL_UNLOCK(sc); 2231} 2232 2233#ifdef DEVICE_POLLING 2234static int 2235xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2236{ 2237 struct xl_softc *sc = ifp->if_softc; 2238 int rx_npkts = 0; 2239 2240 XL_LOCK(sc); 2241 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2242 rx_npkts = xl_poll_locked(ifp, cmd, count); 2243 XL_UNLOCK(sc); 2244 return (rx_npkts); 2245} 2246 2247static int 2248xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2249{ 2250 struct xl_softc *sc = ifp->if_softc; 2251 int rx_npkts; 2252 2253 XL_LOCK_ASSERT(sc); 2254 2255 sc->rxcycles = count; 2256 rx_npkts = xl_rxeof(sc); 2257 if (sc->xl_type == XL_TYPE_905B) 2258 xl_txeof_90xB(sc); 2259 else 2260 xl_txeof(sc); 2261 2262 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2263 if (sc->xl_type == XL_TYPE_905B) 2264 xl_start_90xB_locked(ifp); 2265 else 2266 xl_start_locked(ifp); 2267 } 2268 2269 if (cmd == POLL_AND_CHECK_STATUS) { 2270 u_int16_t status; 2271 2272 status = CSR_READ_2(sc, XL_STATUS); 2273 if (status & XL_INTRS && status != 0xFFFF) { 2274 CSR_WRITE_2(sc, XL_COMMAND, 2275 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2276 2277 if (status & XL_STAT_TX_COMPLETE) { 2278 ifp->if_oerrors++; 2279 xl_txeoc(sc); 2280 } 2281 2282 if (status & XL_STAT_ADFAIL) { 2283 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2284 xl_init_locked(sc); 2285 } 2286 2287 if (status & XL_STAT_STATSOFLOW) 2288 xl_stats_update(sc); 2289 } 2290 } 2291 return (rx_npkts); 2292} 2293#endif /* DEVICE_POLLING */ 2294 2295static void 2296xl_tick(void *xsc) 2297{ 2298 struct xl_softc *sc = xsc; 2299 struct mii_data *mii; 2300 2301 XL_LOCK_ASSERT(sc); 2302 2303 if (sc->xl_miibus != NULL) { 2304 mii = device_get_softc(sc->xl_miibus); 2305 mii_tick(mii); 2306 } 2307 2308 xl_stats_update(sc); 2309 if (xl_watchdog(sc) == EJUSTRETURN) 2310 return; 2311 2312 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc); 2313} 2314 2315static void 2316xl_stats_update(struct xl_softc *sc) 2317{ 2318 struct ifnet *ifp = sc->xl_ifp; 2319 struct xl_stats xl_stats; 2320 u_int8_t *p; 2321 int i; 2322 2323 XL_LOCK_ASSERT(sc); 2324 2325 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2326 2327 p = (u_int8_t *)&xl_stats; 2328 2329 /* Read all the stats registers. */ 2330 XL_SEL_WIN(6); 2331 2332 for (i = 0; i < 16; i++) 2333 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2334 2335 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2336 2337 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2338 xl_stats.xl_tx_single_collision + xl_stats.xl_tx_late_collision; 2339 2340 /* 2341 * Boomerang and cyclone chips have an extra stats counter 2342 * in window 4 (BadSSD). We have to read this too in order 2343 * to clear out all the stats registers and avoid a statsoflow 2344 * interrupt. 2345 */ 2346 XL_SEL_WIN(4); 2347 CSR_READ_1(sc, XL_W4_BADSSD); 2348 XL_SEL_WIN(7); 2349} 2350 2351/* 2352 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2353 * pointers to the fragment pointers. 2354 */ 2355static int 2356xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head) 2357{ 2358 struct mbuf *m_new; 2359 struct ifnet *ifp = sc->xl_ifp; 2360 int error, i, nseg, total_len; 2361 u_int32_t status; 2362 2363 XL_LOCK_ASSERT(sc); 2364 2365 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head, 2366 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2367 2368 if (error && error != EFBIG) { 2369 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2370 return (error); 2371 } 2372 2373 /* 2374 * Handle special case: we used up all 63 fragments, 2375 * but we have more mbufs left in the chain. Copy the 2376 * data into an mbuf cluster. Note that we don't 2377 * bother clearing the values in the other fragment 2378 * pointers/counters; it wouldn't gain us anything, 2379 * and would waste cycles. 2380 */ 2381 if (error) { 2382 m_new = m_collapse(*m_head, M_DONTWAIT, XL_MAXFRAGS); 2383 if (m_new == NULL) { 2384 m_freem(*m_head); 2385 *m_head = NULL; 2386 return (ENOBUFS); 2387 } 2388 *m_head = m_new; 2389 2390 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, 2391 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2392 if (error) { 2393 m_freem(*m_head); 2394 *m_head = NULL; 2395 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2396 return (error); 2397 } 2398 } 2399 2400 KASSERT(nseg <= XL_MAXFRAGS, 2401 ("%s: too many DMA segments (%d)", __func__, nseg)); 2402 if (nseg == 0) { 2403 m_freem(*m_head); 2404 *m_head = NULL; 2405 return (EIO); 2406 } 2407 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2408 2409 total_len = 0; 2410 for (i = 0; i < nseg; i++) { 2411 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES, 2412 ("segment size too large")); 2413 c->xl_ptr->xl_frag[i].xl_addr = 2414 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr); 2415 c->xl_ptr->xl_frag[i].xl_len = 2416 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len); 2417 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len; 2418 } 2419 c->xl_ptr->xl_frag[nseg - 1].xl_len |= htole32(XL_LAST_FRAG); 2420 2421 if (sc->xl_type == XL_TYPE_905B) { 2422 status = XL_TXSTAT_RND_DEFEAT; 2423 2424#ifndef XL905B_TXCSUM_BROKEN 2425 if ((*m_head)->m_pkthdr.csum_flags) { 2426 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2427 status |= XL_TXSTAT_IPCKSUM; 2428 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2429 status |= XL_TXSTAT_TCPCKSUM; 2430 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2431 status |= XL_TXSTAT_UDPCKSUM; 2432 } 2433#endif 2434 } else 2435 status = total_len; 2436 c->xl_ptr->xl_status = htole32(status); 2437 c->xl_ptr->xl_next = 0; 2438 2439 c->xl_mbuf = *m_head; 2440 return (0); 2441} 2442 2443/* 2444 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2445 * to the mbuf data regions directly in the transmit lists. We also save a 2446 * copy of the pointers since the transmit list fragment pointers are 2447 * physical addresses. 2448 */ 2449 2450static void 2451xl_start(struct ifnet *ifp) 2452{ 2453 struct xl_softc *sc = ifp->if_softc; 2454 2455 XL_LOCK(sc); 2456 2457 if (sc->xl_type == XL_TYPE_905B) 2458 xl_start_90xB_locked(ifp); 2459 else 2460 xl_start_locked(ifp); 2461 2462 XL_UNLOCK(sc); 2463} 2464 2465static void 2466xl_start_locked(struct ifnet *ifp) 2467{ 2468 struct xl_softc *sc = ifp->if_softc; 2469 struct mbuf *m_head; 2470 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2471 struct xl_chain *prev_tx; 2472 int error; 2473 2474 XL_LOCK_ASSERT(sc); 2475 2476 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2477 IFF_DRV_RUNNING) 2478 return; 2479 /* 2480 * Check for an available queue slot. If there are none, 2481 * punt. 2482 */ 2483 if (sc->xl_cdata.xl_tx_free == NULL) { 2484 xl_txeoc(sc); 2485 xl_txeof(sc); 2486 if (sc->xl_cdata.xl_tx_free == NULL) { 2487 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2488 return; 2489 } 2490 } 2491 2492 start_tx = sc->xl_cdata.xl_tx_free; 2493 2494 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2495 sc->xl_cdata.xl_tx_free != NULL;) { 2496 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2497 if (m_head == NULL) 2498 break; 2499 2500 /* Pick a descriptor off the free list. */ 2501 prev_tx = cur_tx; 2502 cur_tx = sc->xl_cdata.xl_tx_free; 2503 2504 /* Pack the data into the descriptor. */ 2505 error = xl_encap(sc, cur_tx, &m_head); 2506 if (error) { 2507 cur_tx = prev_tx; 2508 if (m_head == NULL) 2509 break; 2510 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2511 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2512 break; 2513 } 2514 2515 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2516 cur_tx->xl_next = NULL; 2517 2518 /* Chain it together. */ 2519 if (prev != NULL) { 2520 prev->xl_next = cur_tx; 2521 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2522 } 2523 prev = cur_tx; 2524 2525 /* 2526 * If there's a BPF listener, bounce a copy of this frame 2527 * to him. 2528 */ 2529 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2530 } 2531 2532 /* 2533 * If there are no packets queued, bail. 2534 */ 2535 if (cur_tx == NULL) 2536 return; 2537 2538 /* 2539 * Place the request for the upload interrupt 2540 * in the last descriptor in the chain. This way, if 2541 * we're chaining several packets at once, we'll only 2542 * get an interrupt once for the whole chain rather than 2543 * once for each packet. 2544 */ 2545 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR); 2546 2547 /* 2548 * Queue the packets. If the TX channel is clear, update 2549 * the downlist pointer register. 2550 */ 2551 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2552 xl_wait(sc); 2553 2554 if (sc->xl_cdata.xl_tx_head != NULL) { 2555 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2556 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2557 htole32(start_tx->xl_phys); 2558 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &= 2559 htole32(~XL_TXSTAT_DL_INTR); 2560 sc->xl_cdata.xl_tx_tail = cur_tx; 2561 } else { 2562 sc->xl_cdata.xl_tx_head = start_tx; 2563 sc->xl_cdata.xl_tx_tail = cur_tx; 2564 } 2565 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2566 BUS_DMASYNC_PREWRITE); 2567 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2568 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2569 2570 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2571 2572 XL_SEL_WIN(7); 2573 2574 /* 2575 * Set a timeout in case the chip goes out to lunch. 2576 */ 2577 sc->xl_wdog_timer = 5; 2578 2579 /* 2580 * XXX Under certain conditions, usually on slower machines 2581 * where interrupts may be dropped, it's possible for the 2582 * adapter to chew up all the buffers in the receive ring 2583 * and stall, without us being able to do anything about it. 2584 * To guard against this, we need to make a pass over the 2585 * RX queue to make sure there aren't any packets pending. 2586 * Doing it here means we can flush the receive ring at the 2587 * same time the chip is DMAing the transmit descriptors we 2588 * just gave it. 2589 * 2590 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2591 * nature of their chips in all their marketing literature; 2592 * we may as well take advantage of it. :) 2593 */ 2594 taskqueue_enqueue(taskqueue_swi, &sc->xl_task); 2595} 2596 2597static void 2598xl_start_90xB_locked(struct ifnet *ifp) 2599{ 2600 struct xl_softc *sc = ifp->if_softc; 2601 struct mbuf *m_head; 2602 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2603 struct xl_chain *prev_tx; 2604 int error, idx; 2605 2606 XL_LOCK_ASSERT(sc); 2607 2608 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2609 IFF_DRV_RUNNING) 2610 return; 2611 2612 idx = sc->xl_cdata.xl_tx_prod; 2613 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2614 2615 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2616 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) { 2617 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2618 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2619 break; 2620 } 2621 2622 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2623 if (m_head == NULL) 2624 break; 2625 2626 prev_tx = cur_tx; 2627 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2628 2629 /* Pack the data into the descriptor. */ 2630 error = xl_encap(sc, cur_tx, &m_head); 2631 if (error) { 2632 cur_tx = prev_tx; 2633 if (m_head == NULL) 2634 break; 2635 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2636 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2637 break; 2638 } 2639 2640 /* Chain it together. */ 2641 if (prev != NULL) 2642 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2643 prev = cur_tx; 2644 2645 /* 2646 * If there's a BPF listener, bounce a copy of this frame 2647 * to him. 2648 */ 2649 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2650 2651 XL_INC(idx, XL_TX_LIST_CNT); 2652 sc->xl_cdata.xl_tx_cnt++; 2653 } 2654 2655 /* 2656 * If there are no packets queued, bail. 2657 */ 2658 if (cur_tx == NULL) 2659 return; 2660 2661 /* 2662 * Place the request for the upload interrupt 2663 * in the last descriptor in the chain. This way, if 2664 * we're chaining several packets at once, we'll only 2665 * get an interrupt once for the whole chain rather than 2666 * once for each packet. 2667 */ 2668 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR); 2669 2670 /* Start transmission */ 2671 sc->xl_cdata.xl_tx_prod = idx; 2672 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2673 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2674 BUS_DMASYNC_PREWRITE); 2675 2676 /* 2677 * Set a timeout in case the chip goes out to lunch. 2678 */ 2679 sc->xl_wdog_timer = 5; 2680} 2681 2682static void 2683xl_init(void *xsc) 2684{ 2685 struct xl_softc *sc = xsc; 2686 2687 XL_LOCK(sc); 2688 xl_init_locked(sc); 2689 XL_UNLOCK(sc); 2690} 2691 2692static void 2693xl_init_locked(struct xl_softc *sc) 2694{ 2695 struct ifnet *ifp = sc->xl_ifp; 2696 int error, i; 2697 struct mii_data *mii = NULL; 2698 2699 XL_LOCK_ASSERT(sc); 2700 2701 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2702 return; 2703 /* 2704 * Cancel pending I/O and free all RX/TX buffers. 2705 */ 2706 xl_stop(sc); 2707 2708 /* Reset the chip to a known state. */ 2709 xl_reset(sc); 2710 2711 if (sc->xl_miibus == NULL) { 2712 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2713 xl_wait(sc); 2714 } 2715 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2716 xl_wait(sc); 2717 DELAY(10000); 2718 2719 if (sc->xl_miibus != NULL) 2720 mii = device_get_softc(sc->xl_miibus); 2721 2722 /* 2723 * Clear WOL status and disable all WOL feature as WOL 2724 * would interfere Rx operation under normal environments. 2725 */ 2726 if ((sc->xl_flags & XL_FLAG_WOL) != 0) { 2727 XL_SEL_WIN(7); 2728 CSR_READ_2(sc, XL_W7_BM_PME); 2729 CSR_WRITE_2(sc, XL_W7_BM_PME, 0); 2730 } 2731 /* Init our MAC address */ 2732 XL_SEL_WIN(2); 2733 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2734 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2735 IF_LLADDR(sc->xl_ifp)[i]); 2736 } 2737 2738 /* Clear the station mask. */ 2739 for (i = 0; i < 3; i++) 2740 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2741#ifdef notdef 2742 /* Reset TX and RX. */ 2743 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2744 xl_wait(sc); 2745 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2746 xl_wait(sc); 2747#endif 2748 /* Init circular RX list. */ 2749 error = xl_list_rx_init(sc); 2750 if (error) { 2751 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n", 2752 error); 2753 xl_stop(sc); 2754 return; 2755 } 2756 2757 /* Init TX descriptors. */ 2758 if (sc->xl_type == XL_TYPE_905B) 2759 error = xl_list_tx_init_90xB(sc); 2760 else 2761 error = xl_list_tx_init(sc); 2762 if (error) { 2763 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n", 2764 error); 2765 xl_stop(sc); 2766 return; 2767 } 2768 2769 /* 2770 * Set the TX freethresh value. 2771 * Note that this has no effect on 3c905B "cyclone" 2772 * cards but is required for 3c900/3c905 "boomerang" 2773 * cards in order to enable the download engine. 2774 */ 2775 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2776 2777 /* Set the TX start threshold for best performance. */ 2778 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2779 2780 /* 2781 * If this is a 3c905B, also set the tx reclaim threshold. 2782 * This helps cut down on the number of tx reclaim errors 2783 * that could happen on a busy network. The chip multiplies 2784 * the register value by 16 to obtain the actual threshold 2785 * in bytes, so we divide by 16 when setting the value here. 2786 * The existing threshold value can be examined by reading 2787 * the register at offset 9 in window 5. 2788 */ 2789 if (sc->xl_type == XL_TYPE_905B) { 2790 CSR_WRITE_2(sc, XL_COMMAND, 2791 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2792 } 2793 2794 /* Set RX filter bits. */ 2795 xl_rxfilter(sc); 2796 2797 /* 2798 * Load the address of the RX list. We have to 2799 * stall the upload engine before we can manipulate 2800 * the uplist pointer register, then unstall it when 2801 * we're finished. We also have to wait for the 2802 * stall command to complete before proceeding. 2803 * Note that we have to do this after any RX resets 2804 * have completed since the uplist register is cleared 2805 * by a reset. 2806 */ 2807 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2808 xl_wait(sc); 2809 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2810 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2811 xl_wait(sc); 2812 2813 if (sc->xl_type == XL_TYPE_905B) { 2814 /* Set polling interval */ 2815 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2816 /* Load the address of the TX list */ 2817 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2818 xl_wait(sc); 2819 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2820 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2821 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2822 xl_wait(sc); 2823 } 2824 2825 /* 2826 * If the coax transceiver is on, make sure to enable 2827 * the DC-DC converter. 2828 */ 2829 XL_SEL_WIN(3); 2830 if (sc->xl_xcvr == XL_XCVR_COAX) 2831 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2832 else 2833 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2834 2835 /* 2836 * increase packet size to allow reception of 802.1q or ISL packets. 2837 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2838 * control register. For 3c90xB/C chips, use the RX packet size 2839 * register. 2840 */ 2841 2842 if (sc->xl_type == XL_TYPE_905B) 2843 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2844 else { 2845 u_int8_t macctl; 2846 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2847 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2848 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2849 } 2850 2851 /* Clear out the stats counters. */ 2852 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2853 xl_stats_update(sc); 2854 XL_SEL_WIN(4); 2855 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2856 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2857 2858 /* 2859 * Enable interrupts. 2860 */ 2861 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2862 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2863#ifdef DEVICE_POLLING 2864 /* Disable interrupts if we are polling. */ 2865 if (ifp->if_capenable & IFCAP_POLLING) 2866 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 2867 else 2868#endif 2869 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2870 if (sc->xl_flags & XL_FLAG_FUNCREG) 2871 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2872 2873 /* Set the RX early threshold */ 2874 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2875 CSR_WRITE_4(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2876 2877 /* Enable receiver and transmitter. */ 2878 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2879 xl_wait(sc); 2880 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2881 xl_wait(sc); 2882 2883 /* XXX Downcall to miibus. */ 2884 if (mii != NULL) 2885 mii_mediachg(mii); 2886 2887 /* Select window 7 for normal operations. */ 2888 XL_SEL_WIN(7); 2889 2890 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2891 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2892 2893 sc->xl_wdog_timer = 0; 2894 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc); 2895} 2896 2897/* 2898 * Set media options. 2899 */ 2900static int 2901xl_ifmedia_upd(struct ifnet *ifp) 2902{ 2903 struct xl_softc *sc = ifp->if_softc; 2904 struct ifmedia *ifm = NULL; 2905 struct mii_data *mii = NULL; 2906 2907 XL_LOCK(sc); 2908 2909 if (sc->xl_miibus != NULL) 2910 mii = device_get_softc(sc->xl_miibus); 2911 if (mii == NULL) 2912 ifm = &sc->ifmedia; 2913 else 2914 ifm = &mii->mii_media; 2915 2916 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2917 case IFM_100_FX: 2918 case IFM_10_FL: 2919 case IFM_10_2: 2920 case IFM_10_5: 2921 xl_setmode(sc, ifm->ifm_media); 2922 XL_UNLOCK(sc); 2923 return (0); 2924 } 2925 2926 if (sc->xl_media & XL_MEDIAOPT_MII || 2927 sc->xl_media & XL_MEDIAOPT_BTX || 2928 sc->xl_media & XL_MEDIAOPT_BT4) { 2929 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2930 xl_init_locked(sc); 2931 } else { 2932 xl_setmode(sc, ifm->ifm_media); 2933 } 2934 2935 XL_UNLOCK(sc); 2936 2937 return (0); 2938} 2939 2940/* 2941 * Report current media status. 2942 */ 2943static void 2944xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2945{ 2946 struct xl_softc *sc = ifp->if_softc; 2947 u_int32_t icfg; 2948 u_int16_t status = 0; 2949 struct mii_data *mii = NULL; 2950 2951 XL_LOCK(sc); 2952 2953 if (sc->xl_miibus != NULL) 2954 mii = device_get_softc(sc->xl_miibus); 2955 2956 XL_SEL_WIN(4); 2957 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 2958 2959 XL_SEL_WIN(3); 2960 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 2961 icfg >>= XL_ICFG_CONNECTOR_BITS; 2962 2963 ifmr->ifm_active = IFM_ETHER; 2964 ifmr->ifm_status = IFM_AVALID; 2965 2966 if ((status & XL_MEDIASTAT_CARRIER) == 0) 2967 ifmr->ifm_status |= IFM_ACTIVE; 2968 2969 switch (icfg) { 2970 case XL_XCVR_10BT: 2971 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2972 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2973 ifmr->ifm_active |= IFM_FDX; 2974 else 2975 ifmr->ifm_active |= IFM_HDX; 2976 break; 2977 case XL_XCVR_AUI: 2978 if (sc->xl_type == XL_TYPE_905B && 2979 sc->xl_media == XL_MEDIAOPT_10FL) { 2980 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 2981 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2982 ifmr->ifm_active |= IFM_FDX; 2983 else 2984 ifmr->ifm_active |= IFM_HDX; 2985 } else 2986 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2987 break; 2988 case XL_XCVR_COAX: 2989 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 2990 break; 2991 /* 2992 * XXX MII and BTX/AUTO should be separate cases. 2993 */ 2994 2995 case XL_XCVR_100BTX: 2996 case XL_XCVR_AUTO: 2997 case XL_XCVR_MII: 2998 if (mii != NULL) { 2999 mii_pollstat(mii); 3000 ifmr->ifm_active = mii->mii_media_active; 3001 ifmr->ifm_status = mii->mii_media_status; 3002 } 3003 break; 3004 case XL_XCVR_100BFX: 3005 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3006 break; 3007 default: 3008 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3009 break; 3010 } 3011 3012 XL_UNLOCK(sc); 3013} 3014 3015static int 3016xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3017{ 3018 struct xl_softc *sc = ifp->if_softc; 3019 struct ifreq *ifr = (struct ifreq *) data; 3020 int error = 0, mask; 3021 struct mii_data *mii = NULL; 3022 3023 switch (command) { 3024 case SIOCSIFFLAGS: 3025 XL_LOCK(sc); 3026 if (ifp->if_flags & IFF_UP) { 3027 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3028 (ifp->if_flags ^ sc->xl_if_flags) & 3029 (IFF_PROMISC | IFF_ALLMULTI)) 3030 xl_rxfilter(sc); 3031 else 3032 xl_init_locked(sc); 3033 } else { 3034 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3035 xl_stop(sc); 3036 } 3037 sc->xl_if_flags = ifp->if_flags; 3038 XL_UNLOCK(sc); 3039 break; 3040 case SIOCADDMULTI: 3041 case SIOCDELMULTI: 3042 /* XXX Downcall from if_addmulti() possibly with locks held. */ 3043 XL_LOCK(sc); 3044 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3045 xl_rxfilter(sc); 3046 XL_UNLOCK(sc); 3047 break; 3048 case SIOCGIFMEDIA: 3049 case SIOCSIFMEDIA: 3050 if (sc->xl_miibus != NULL) 3051 mii = device_get_softc(sc->xl_miibus); 3052 if (mii == NULL) 3053 error = ifmedia_ioctl(ifp, ifr, 3054 &sc->ifmedia, command); 3055 else 3056 error = ifmedia_ioctl(ifp, ifr, 3057 &mii->mii_media, command); 3058 break; 3059 case SIOCSIFCAP: 3060 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3061#ifdef DEVICE_POLLING 3062 if ((mask & IFCAP_POLLING) != 0 && 3063 (ifp->if_capabilities & IFCAP_POLLING) != 0) { 3064 ifp->if_capenable ^= IFCAP_POLLING; 3065 if ((ifp->if_capenable & IFCAP_POLLING) != 0) { 3066 error = ether_poll_register(xl_poll, ifp); 3067 if (error) 3068 break; 3069 XL_LOCK(sc); 3070 /* Disable interrupts */ 3071 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3072 ifp->if_capenable |= IFCAP_POLLING; 3073 XL_UNLOCK(sc); 3074 } else { 3075 error = ether_poll_deregister(ifp); 3076 /* Enable interrupts. */ 3077 XL_LOCK(sc); 3078 CSR_WRITE_2(sc, XL_COMMAND, 3079 XL_CMD_INTR_ACK | 0xFF); 3080 CSR_WRITE_2(sc, XL_COMMAND, 3081 XL_CMD_INTR_ENB | XL_INTRS); 3082 if (sc->xl_flags & XL_FLAG_FUNCREG) 3083 bus_space_write_4(sc->xl_ftag, 3084 sc->xl_fhandle, 4, 0x8000); 3085 XL_UNLOCK(sc); 3086 } 3087 } 3088#endif /* DEVICE_POLLING */ 3089 XL_LOCK(sc); 3090 if ((mask & IFCAP_TXCSUM) != 0 && 3091 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3092 ifp->if_capenable ^= IFCAP_TXCSUM; 3093 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3094 ifp->if_hwassist |= XL905B_CSUM_FEATURES; 3095 else 3096 ifp->if_hwassist &= ~XL905B_CSUM_FEATURES; 3097 } 3098 if ((mask & IFCAP_RXCSUM) != 0 && 3099 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 3100 ifp->if_capenable ^= IFCAP_RXCSUM; 3101 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3102 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 3103 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3104 XL_UNLOCK(sc); 3105 break; 3106 default: 3107 error = ether_ioctl(ifp, command, data); 3108 break; 3109 } 3110 3111 return (error); 3112} 3113 3114static int 3115xl_watchdog(struct xl_softc *sc) 3116{ 3117 struct ifnet *ifp = sc->xl_ifp; 3118 u_int16_t status = 0; 3119 int misintr; 3120 3121 XL_LOCK_ASSERT(sc); 3122 3123 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0) 3124 return (0); 3125 3126 xl_rxeof(sc); 3127 xl_txeoc(sc); 3128 misintr = 0; 3129 if (sc->xl_type == XL_TYPE_905B) { 3130 xl_txeof_90xB(sc); 3131 if (sc->xl_cdata.xl_tx_cnt == 0) 3132 misintr++; 3133 } else { 3134 xl_txeof(sc); 3135 if (sc->xl_cdata.xl_tx_head == NULL) 3136 misintr++; 3137 } 3138 if (misintr != 0) { 3139 device_printf(sc->xl_dev, 3140 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 3141 return (0); 3142 } 3143 3144 ifp->if_oerrors++; 3145 XL_SEL_WIN(4); 3146 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3147 device_printf(sc->xl_dev, "watchdog timeout\n"); 3148 3149 if (status & XL_MEDIASTAT_CARRIER) 3150 device_printf(sc->xl_dev, 3151 "no carrier - transceiver cable problem?\n"); 3152 3153 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3154 xl_init_locked(sc); 3155 3156 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 3157 if (sc->xl_type == XL_TYPE_905B) 3158 xl_start_90xB_locked(ifp); 3159 else 3160 xl_start_locked(ifp); 3161 } 3162 3163 return (EJUSTRETURN); 3164} 3165 3166/* 3167 * Stop the adapter and free any mbufs allocated to the 3168 * RX and TX lists. 3169 */ 3170static void 3171xl_stop(struct xl_softc *sc) 3172{ 3173 register int i; 3174 struct ifnet *ifp = sc->xl_ifp; 3175 3176 XL_LOCK_ASSERT(sc); 3177 3178 sc->xl_wdog_timer = 0; 3179 3180 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3181 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3182 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3183 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3184 xl_wait(sc); 3185 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3186 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3187 DELAY(800); 3188 3189#ifdef foo 3190 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3191 xl_wait(sc); 3192 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3193 xl_wait(sc); 3194#endif 3195 3196 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3197 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3198 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3199 if (sc->xl_flags & XL_FLAG_FUNCREG) 3200 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3201 3202 /* Stop the stats updater. */ 3203 callout_stop(&sc->xl_tick_callout); 3204 3205 /* 3206 * Free data in the RX lists. 3207 */ 3208 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3209 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3210 bus_dmamap_unload(sc->xl_mtag, 3211 sc->xl_cdata.xl_rx_chain[i].xl_map); 3212 bus_dmamap_destroy(sc->xl_mtag, 3213 sc->xl_cdata.xl_rx_chain[i].xl_map); 3214 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3215 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3216 } 3217 } 3218 if (sc->xl_ldata.xl_rx_list != NULL) 3219 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3220 /* 3221 * Free the TX list buffers. 3222 */ 3223 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3224 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3225 bus_dmamap_unload(sc->xl_mtag, 3226 sc->xl_cdata.xl_tx_chain[i].xl_map); 3227 bus_dmamap_destroy(sc->xl_mtag, 3228 sc->xl_cdata.xl_tx_chain[i].xl_map); 3229 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3230 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3231 } 3232 } 3233 if (sc->xl_ldata.xl_tx_list != NULL) 3234 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3235 3236 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3237} 3238 3239/* 3240 * Stop all chip I/O so that the kernel's probe routines don't 3241 * get confused by errant DMAs when rebooting. 3242 */ 3243static int 3244xl_shutdown(device_t dev) 3245{ 3246 3247 return (xl_suspend(dev)); 3248} 3249 3250static int 3251xl_suspend(device_t dev) 3252{ 3253 struct xl_softc *sc; 3254 3255 sc = device_get_softc(dev); 3256 3257 XL_LOCK(sc); 3258 xl_stop(sc); 3259 xl_setwol(sc); 3260 XL_UNLOCK(sc); 3261 3262 return (0); 3263} 3264 3265static int 3266xl_resume(device_t dev) 3267{ 3268 struct xl_softc *sc; 3269 struct ifnet *ifp; 3270 3271 sc = device_get_softc(dev); 3272 ifp = sc->xl_ifp; 3273 3274 XL_LOCK(sc); 3275 3276 if (ifp->if_flags & IFF_UP) { 3277 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3278 xl_init_locked(sc); 3279 } 3280 3281 XL_UNLOCK(sc); 3282 3283 return (0); 3284} 3285 3286static void 3287xl_setwol(struct xl_softc *sc) 3288{ 3289 struct ifnet *ifp; 3290 u_int16_t cfg, pmstat; 3291 3292 if ((sc->xl_flags & XL_FLAG_WOL) == 0) 3293 return; 3294 3295 ifp = sc->xl_ifp; 3296 XL_SEL_WIN(7); 3297 /* Clear any pending PME events. */ 3298 CSR_READ_2(sc, XL_W7_BM_PME); 3299 cfg = 0; 3300 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3301 cfg |= XL_BM_PME_MAGIC; 3302 CSR_WRITE_2(sc, XL_W7_BM_PME, cfg); 3303 /* Enable RX. */ 3304 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3305 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 3306 /* Request PME. */ 3307 pmstat = pci_read_config(sc->xl_dev, 3308 sc->xl_pmcap + PCIR_POWER_STATUS, 2); 3309 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3310 pmstat |= PCIM_PSTAT_PMEENABLE; 3311 else 3312 pmstat &= ~PCIM_PSTAT_PMEENABLE; 3313 pci_write_config(sc->xl_dev, 3314 sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2); 3315} 3316