1/* 2 * Copyright 2006-2009, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel D��rfler, axeld@pinc-software.de 7 */ 8#ifndef INTEL_EXTREME_H 9#define INTEL_EXTREME_H 10 11 12#include "lock.h" 13 14#include <Accelerant.h> 15#include <Drivers.h> 16#include <PCI.h> 17 18 19#define VENDOR_ID_INTEL 0x8086 20 21#define INTEL_TYPE_FAMILY_MASK 0x000f0000 22#define INTEL_TYPE_GROUP_MASK 0x000ffff0 23#define INTEL_TYPE_MODEL_MASK 0x000fffff 24// families 25#define INTEL_TYPE_7xx 0x00010000 26#define INTEL_TYPE_8xx 0x00020000 27#define INTEL_TYPE_9xx 0x00040000 28// groups 29#define INTEL_TYPE_83x (INTEL_TYPE_8xx | 0x0010) 30#define INTEL_TYPE_85x (INTEL_TYPE_8xx | 0x0020) 31#define INTEL_TYPE_91x (INTEL_TYPE_9xx | 0x0040) 32#define INTEL_TYPE_94x (INTEL_TYPE_9xx | 0x0080) 33#define INTEL_TYPE_96x (INTEL_TYPE_9xx | 0x0100) 34#define INTEL_TYPE_Gxx (INTEL_TYPE_9xx | 0x0200) 35#define INTEL_TYPE_G4x (INTEL_TYPE_9xx | 0x0400) 36#define INTEL_TYPE_IGD (INTEL_TYPE_9xx | 0x0800) 37#define INTEL_TYPE_ILK (INTEL_TYPE_9xx | 0x1000) 38#define INTEL_TYPE_SNB (INTEL_TYPE_9xx | 0x2000) 39#define INTEL_TYPE_IVB (INTEL_TYPE_9xx | 0x4000) 40// models 41#define INTEL_TYPE_SERVER 0x0004 42#define INTEL_TYPE_MOBILE 0x0008 43#define INTEL_TYPE_915 (INTEL_TYPE_91x) 44#define INTEL_TYPE_915M (INTEL_TYPE_91x | INTEL_TYPE_MOBILE) 45#define INTEL_TYPE_945 (INTEL_TYPE_94x) 46#define INTEL_TYPE_945M (INTEL_TYPE_94x | INTEL_TYPE_MOBILE) 47#define INTEL_TYPE_965 (INTEL_TYPE_96x) 48#define INTEL_TYPE_965M (INTEL_TYPE_96x | INTEL_TYPE_MOBILE) 49#define INTEL_TYPE_G33 (INTEL_TYPE_Gxx) 50#define INTEL_TYPE_G45 (INTEL_TYPE_G4x) 51#define INTEL_TYPE_GM45 (INTEL_TYPE_G4x | INTEL_TYPE_MOBILE) 52#define INTEL_TYPE_IGDG (INTEL_TYPE_IGD) 53#define INTEL_TYPE_IGDGM (INTEL_TYPE_IGD | INTEL_TYPE_MOBILE) 54#define INTEL_TYPE_ILKG (INTEL_TYPE_ILK) 55#define INTEL_TYPE_ILKGM (INTEL_TYPE_ILK | INTEL_TYPE_MOBILE) 56#define INTEL_TYPE_SNBG (INTEL_TYPE_SNB) 57#define INTEL_TYPE_SNBGM (INTEL_TYPE_SNB | INTEL_TYPE_MOBILE) 58#define INTEL_TYPE_SNBGS (INTEL_TYPE_SNB | INTEL_TYPE_SERVER) 59#define INTEL_TYPE_IVBG (INTEL_TYPE_IVB) 60#define INTEL_TYPE_IVBGM (INTEL_TYPE_IVB | INTEL_TYPE_MOBILE) 61#define INTEL_TYPE_IVBGS (INTEL_TYPE_IVB | INTEL_TYPE_SERVER) 62 63#define DEVICE_NAME "intel_extreme" 64#define INTEL_ACCELERANT_NAME "intel_extreme.accelerant" 65 66// We encode the register block into the value and extract/translate it when 67// actually accessing. 68#define REGISTER_BLOCK_COUNT 6 69#define REGISTER_BLOCK_SHIFT 24 70#define REGISTER_BLOCK_MASK 0xff000000 71#define REGISTER_REGISTER_MASK 0x00ffffff 72#define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT) 73#define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK) 74 75#define REGS_FLAT (0 << REGISTER_BLOCK_SHIFT) 76#define REGS_NORTH_SHARED (1 << REGISTER_BLOCK_SHIFT) 77#define REGS_NORTH_PIPE_AND_PORT (2 << REGISTER_BLOCK_SHIFT) 78#define REGS_NORTH_PLANE_CONTROL (3 << REGISTER_BLOCK_SHIFT) 79#define REGS_SOUTH_SHARED (4 << REGISTER_BLOCK_SHIFT) 80#define REGS_SOUTH_TRANSCODER_PORT (5 << REGISTER_BLOCK_SHIFT) 81 82// register blocks for (G)MCH/ICH based platforms 83#define MCH_SHARED_REGISTER_BASE 0x00000 84#define MCH_PIPE_AND_PORT_REGISTER_BASE 0x60000 85#define MCH_PLANE_CONTROL_REGISTER_BASE 0x70000 86#define ICH_SHARED_REGISTER_BASE 0x00000 87#define ICH_PORT_REGISTER_BASE 0x60000 88 89// PCH - Platform Control Hub - Newer hardware moves from a MCH/ICH based setup 90// to a PCH based one, that means anything that used to communicate via (G)MCH 91// registers needs to use different ones on PCH based platforms (Ironlake and 92// up, SandyBridge, etc.). 93#define PCH_NORTH_SHARED_REGISTER_BASE 0x40000 94#define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE 0x60000 95#define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE 0x70000 96#define PCH_SOUTH_SHARED_REGISTER_BASE 0xc0000 97#define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE 0xe0000 98 99 100struct DeviceType { 101 uint32 type; 102 103 DeviceType(int t) 104 { 105 type = t; 106 } 107 108 DeviceType& operator=(int t) 109 { 110 type = t; 111 return *this; 112 } 113 114 bool InFamily(uint32 family) const 115 { 116 return (type & INTEL_TYPE_FAMILY_MASK) == family; 117 } 118 119 bool InGroup(uint32 group) const 120 { 121 return (type & INTEL_TYPE_GROUP_MASK) == group; 122 } 123 124 bool IsModel(uint32 model) const 125 { 126 return (type & INTEL_TYPE_MODEL_MASK) == model; 127 } 128 129 bool HasPlatformControlHub() const 130 { 131 return InGroup(INTEL_TYPE_ILK) || InGroup(INTEL_TYPE_SNB) 132 || InGroup(INTEL_TYPE_IVB); 133 } 134}; 135 136// info about PLL on graphics card 137struct pll_info { 138 uint32 reference_frequency; 139 uint32 max_frequency; 140 uint32 min_frequency; 141 uint32 divisor_register; 142}; 143 144struct ring_buffer { 145 struct lock lock; 146 uint32 register_base; 147 uint32 offset; 148 uint32 size; 149 uint32 position; 150 uint32 space_left; 151 uint8* base; 152}; 153 154struct overlay_registers; 155 156struct intel_shared_info { 157 area_id mode_list_area; // area containing display mode list 158 uint32 mode_count; 159 160 display_mode current_mode; 161 uint32 bytes_per_row; 162 uint32 bits_per_pixel; 163 uint32 dpms_mode; 164 165 area_id registers_area; // area of memory mapped registers 166 uint32 register_blocks[REGISTER_BLOCK_COUNT]; 167 uint8* status_page; 168 phys_addr_t physical_status_page; 169 uint8* graphics_memory; 170 phys_addr_t physical_graphics_memory; 171 uint32 graphics_memory_size; 172 173 addr_t frame_buffer; 174 uint32 frame_buffer_offset; 175 176 struct lock accelerant_lock; 177 struct lock engine_lock; 178 179 ring_buffer primary_ring_buffer; 180 181 int32 overlay_channel_used; 182 bool overlay_active; 183 uint32 overlay_token; 184 phys_addr_t physical_overlay_registers; 185 uint32 overlay_offset; 186 187 bool hardware_cursor_enabled; 188 sem_id vblank_sem; 189 190 uint8* cursor_memory; 191 phys_addr_t physical_cursor_memory; 192 uint32 cursor_buffer_offset; 193 uint32 cursor_format; 194 bool cursor_visible; 195 uint16 cursor_hot_x; 196 uint16 cursor_hot_y; 197 198 DeviceType device_type; 199 char device_identifier[32]; 200 struct pll_info pll_info; 201}; 202 203//----------------- ioctl() interface ---------------- 204 205// magic code for ioctls 206#define INTEL_PRIVATE_DATA_MAGIC 'itic' 207 208// list ioctls 209enum { 210 INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 211 212 INTEL_GET_DEVICE_NAME, 213 INTEL_ALLOCATE_GRAPHICS_MEMORY, 214 INTEL_FREE_GRAPHICS_MEMORY 215}; 216 217// retrieve the area_id of the kernel/accelerant shared info 218struct intel_get_private_data { 219 uint32 magic; // magic number 220 area_id shared_info_area; 221}; 222 223// allocate graphics memory 224struct intel_allocate_graphics_memory { 225 uint32 magic; 226 uint32 size; 227 uint32 alignment; 228 uint32 flags; 229 uint32 buffer_base; 230}; 231 232// free graphics memory 233struct intel_free_graphics_memory { 234 uint32 magic; 235 uint32 buffer_base; 236}; 237 238//---------------------------------------------------------- 239// Register definitions, taken from X driver 240 241// PCI bridge memory management 242#define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 243 // GGC - (G)MCH Graphics Control Register 244#define MEMORY_CONTROL_ENABLED 0x0004 245#define MEMORY_MASK 0x0001 246#define STOLEN_MEMORY_MASK 0x00f0 247#define i965_GTT_MASK 0x000e 248#define G33_GTT_MASK 0x0300 249#define G4X_GTT_MASK 0x0f00 // GGMS (GSM Memory Size) mask 250 251// models i830 and up 252#define i830_LOCAL_MEMORY_ONLY 0x10 253#define i830_STOLEN_512K 0x20 254#define i830_STOLEN_1M 0x30 255#define i830_STOLEN_8M 0x40 256#define i830_FRAME_BUFFER_64M 0x01 257#define i830_FRAME_BUFFER_128M 0x00 258 259// models i855 and up 260#define i855_STOLEN_MEMORY_1M 0x10 261#define i855_STOLEN_MEMORY_4M 0x20 262#define i855_STOLEN_MEMORY_8M 0x30 263#define i855_STOLEN_MEMORY_16M 0x40 264#define i855_STOLEN_MEMORY_32M 0x50 265#define i855_STOLEN_MEMORY_48M 0x60 266#define i855_STOLEN_MEMORY_64M 0x70 267#define i855_STOLEN_MEMORY_128M 0x80 268#define i855_STOLEN_MEMORY_256M 0x90 269 270#define G4X_STOLEN_MEMORY_96MB 0xa0 // GMS - Graphics Mode Select 271#define G4X_STOLEN_MEMORY_160MB 0xb0 272#define G4X_STOLEN_MEMORY_224MB 0xc0 273#define G4X_STOLEN_MEMORY_352MB 0xd0 274 275// SandyBridge (SNB) 276#define SNB_GRAPHICS_MEMORY_CONTROL 0x50 277 278#define SNB_STOLEN_MEMORY_MASK 0xf8 279#define SNB_STOLEN_MEMORY_32MB (1 << 3) 280#define SNB_STOLEN_MEMORY_64MB (2 << 3) 281#define SNB_STOLEN_MEMORY_96MB (3 << 3) 282#define SNB_STOLEN_MEMORY_128MB (4 << 3) 283#define SNB_STOLEN_MEMORY_160MB (5 << 3) 284#define SNB_STOLEN_MEMORY_192MB (6 << 3) 285#define SNB_STOLEN_MEMORY_224MB (7 << 3) 286#define SNB_STOLEN_MEMORY_256MB (8 << 3) 287#define SNB_STOLEN_MEMORY_288MB (9 << 3) 288#define SNB_STOLEN_MEMORY_320MB (10 << 3) 289#define SNB_STOLEN_MEMORY_352MB (11 << 3) 290#define SNB_STOLEN_MEMORY_384MB (12 << 3) 291#define SNB_STOLEN_MEMORY_416MB (13 << 3) 292#define SNB_STOLEN_MEMORY_448MB (14 << 3) 293#define SNB_STOLEN_MEMORY_480MB (15 << 3) 294#define SNB_STOLEN_MEMORY_512MB (16 << 3) 295 296#define SNB_GTT_SIZE_MASK (3 << 8) 297#define SNB_GTT_SIZE_NONE (0 << 8) 298#define SNB_GTT_SIZE_1MB (1 << 8) 299#define SNB_GTT_SIZE_2MB (2 << 8) 300 301// graphics page translation table 302#define INTEL_PAGE_TABLE_CONTROL 0x02020 303#define PAGE_TABLE_ENABLED 0x00000001 304#define INTEL_PAGE_TABLE_ERROR 0x02024 305#define INTEL_HARDWARE_STATUS_PAGE 0x02080 306#define i915_GTT_BASE 0x1c 307#define i830_GTT_BASE 0x10000 // (- 0x2ffff) 308#define i830_GTT_SIZE 0x20000 309#define i965_GTT_BASE 0x80000 // (- 0xfffff) 310#define i965_GTT_SIZE 0x80000 311#define i965_GTT_128K (2 << 1) 312#define i965_GTT_256K (1 << 1) 313#define i965_GTT_512K (0 << 1) 314#define G33_GTT_1M (1 << 8) 315#define G33_GTT_2M (2 << 8) 316#define G4X_GTT_NONE 0x000 // GGMS - GSM Memory Size 317#define G4X_GTT_1M_NO_IVT 0x100 // no Intel Virtualization Tech. 318#define G4X_GTT_2M_NO_IVT 0x300 319#define G4X_GTT_2M_IVT 0x900 // with Intel Virt. Tech. 320#define G4X_GTT_3M_IVT 0xa00 321#define G4X_GTT_4M_IVT 0xb00 322 323 324#define GTT_ENTRY_VALID 0x01 325#define GTT_ENTRY_LOCAL_MEMORY 0x02 326#define GTT_PAGE_SHIFT 12 327 328 329// ring buffer 330#define INTEL_PRIMARY_RING_BUFFER 0x02030 331#define INTEL_SECONDARY_RING_BUFFER_0 0x02100 332#define INTEL_SECONDARY_RING_BUFFER_1 0x02110 333// offsets for the ring buffer base registers above 334#define RING_BUFFER_TAIL 0x0 335#define RING_BUFFER_HEAD 0x4 336#define RING_BUFFER_START 0x8 337#define RING_BUFFER_CONTROL 0xc 338#define INTEL_RING_BUFFER_SIZE_MASK 0x001ff000 339#define INTEL_RING_BUFFER_HEAD_MASK 0x001ffffc 340#define INTEL_RING_BUFFER_ENABLED 1 341 342// interrupts 343#define INTEL_INTERRUPT_ENABLED 0x020a0 344#define INTEL_INTERRUPT_IDENTITY 0x020a4 345#define INTEL_INTERRUPT_MASK 0x020a8 346#define INTEL_INTERRUPT_STATUS 0x020ac 347#define INTERRUPT_VBLANK_PIPEA (1 << 7) 348#define INTERRUPT_VBLANK_PIPEB (1 << 5) 349 350// PCH interrupts 351#define PCH_INTERRUPT_STATUS 0x44000 352#define PCH_INTERRUPT_MASK 0x44004 353#define PCH_INTERRUPT_IDENTITY 0x44008 354#define PCH_INTERRUPT_ENABLED 0x4400c 355#define PCH_INTERRUPT_VBLANK_PIPEA (1 << 7) 356#define PCH_INTERRUPT_VBLANK_PIPEB (1 << 15) 357 358// display ports 359#define INTEL_DISPLAY_A_ANALOG_PORT (0x1100 | REGS_SOUTH_TRANSCODER_PORT) 360#define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31) 361#define DISPLAY_MONITOR_PIPE_B (1UL << 30) 362#define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15) 363#define DISPLAY_MONITOR_MODE_MASK (3UL << 10) 364#define DISPLAY_MONITOR_ON 0 365#define DISPLAY_MONITOR_SUSPEND (1UL << 10) 366#define DISPLAY_MONITOR_STAND_BY (2UL << 10) 367#define DISPLAY_MONITOR_OFF (3UL << 10) 368#define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3) 369#define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3) 370#define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3) 371#define INTEL_DISPLAY_A_DIGITAL_PORT (0x1120 | REGS_SOUTH_TRANSCODER_PORT) 372#define INTEL_DISPLAY_C_DIGITAL (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 373#define INTEL_DISPLAY_LVDS_PORT (0x1180 | REGS_SOUTH_TRANSCODER_PORT) 374#define LVDS_POST2_RATE_SLOW 14 // PLL Divisors 375#define LVDS_POST2_RATE_FAST 7 376#define LVDS_CLKB_POWER_MASK (3 << 4) 377#define LVDS_CLKB_POWER_UP (3 << 4) 378#define LVDS_PORT_EN (1 << 31) 379#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 380#define LVDS_PIPEB_SELECT (1 << 30) 381#define LVDS_B0B3PAIRS_POWER_UP (3 << 2) 382#define LVDS_PLL_MODE_LVDS (2 << 26) 383#define LVDS_18BIT_DITHER (1 << 25) 384 385// PLL flags 386#define DISPLAY_PLL_ENABLED (1UL << 31) 387#define DISPLAY_PLL_2X_CLOCK (1UL << 30) 388#define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29) 389#define DISPLAY_PLL_NO_VGA_CONTROL (1UL << 28) 390#define DISPLAY_PLL_MODE_ANALOG (1UL << 26) 391#define DISPLAY_PLL_DIVIDE_HIGH (1UL << 24) 392#define DISPLAY_PLL_DIVIDE_4X (1UL << 23) 393#define DISPLAY_PLL_POST1_DIVIDE_2 (1UL << 21) 394#define DISPLAY_PLL_POST1_DIVISOR_MASK 0x001f0000 395#define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK 0x00ff0000 396#define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK 0x00ff8000 397#define DISPLAY_PLL_POST1_DIVISOR_SHIFT 16 398#define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT 15 399#define DISPLAY_PLL_DIVISOR_1 (1UL << 8) 400#define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000 401#define DISPLAY_PLL_IGD_N_DIVISOR_MASK 0x00ff0000 402#define DISPLAY_PLL_M1_DIVISOR_MASK 0x00001f00 403#define DISPLAY_PLL_M2_DIVISOR_MASK 0x0000001f 404#define DISPLAY_PLL_IGD_M2_DIVISOR_MASK 0x000000ff 405#define DISPLAY_PLL_N_DIVISOR_SHIFT 16 406#define DISPLAY_PLL_M1_DIVISOR_SHIFT 8 407#define DISPLAY_PLL_M2_DIVISOR_SHIFT 0 408#define DISPLAY_PLL_PULSE_PHASE_SHIFT 9 409 410// display 411#define INTEL_DISPLAY_A_HTOTAL (0x0000 | REGS_SOUTH_TRANSCODER_PORT) 412#define INTEL_DISPLAY_A_HBLANK (0x0004 | REGS_SOUTH_TRANSCODER_PORT) 413#define INTEL_DISPLAY_A_HSYNC (0x0008 | REGS_SOUTH_TRANSCODER_PORT) 414#define INTEL_DISPLAY_A_VTOTAL (0x000c | REGS_SOUTH_TRANSCODER_PORT) 415#define INTEL_DISPLAY_A_VBLANK (0x0010 | REGS_SOUTH_TRANSCODER_PORT) 416#define INTEL_DISPLAY_A_VSYNC (0x0014 | REGS_SOUTH_TRANSCODER_PORT) 417#define INTEL_DISPLAY_B_HTOTAL (0x1000 | REGS_SOUTH_TRANSCODER_PORT) 418#define INTEL_DISPLAY_B_HBLANK (0x1004 | REGS_SOUTH_TRANSCODER_PORT) 419#define INTEL_DISPLAY_B_HSYNC (0x1008 | REGS_SOUTH_TRANSCODER_PORT) 420#define INTEL_DISPLAY_B_VTOTAL (0x100c | REGS_SOUTH_TRANSCODER_PORT) 421#define INTEL_DISPLAY_B_VBLANK (0x1010 | REGS_SOUTH_TRANSCODER_PORT) 422#define INTEL_DISPLAY_B_VSYNC (0x1014 | REGS_SOUTH_TRANSCODER_PORT) 423 424#define INTEL_DISPLAY_A_IMAGE_SIZE (0x001c | REGS_NORTH_PIPE_AND_PORT) 425#define INTEL_DISPLAY_B_IMAGE_SIZE (0x101c | REGS_NORTH_PIPE_AND_PORT) 426 427#define INTEL_DISPLAY_B_DIGITAL_PORT (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 428 429// planes 430#define INTEL_DISPLAY_A_PIPE_CONTROL (0x0008 | REGS_NORTH_PLANE_CONTROL) 431#define INTEL_DISPLAY_B_PIPE_CONTROL (0x1008 | REGS_NORTH_PLANE_CONTROL) 432#define DISPLAY_PIPE_ENABLED (1UL << 31) 433 434#define INTEL_DISPLAY_A_PIPE_STATUS (0x0024 | REGS_NORTH_PLANE_CONTROL) 435#define INTEL_DISPLAY_B_PIPE_STATUS (0x1024 | REGS_NORTH_PLANE_CONTROL) 436#define DISPLAY_PIPE_VBLANK_ENABLED (1UL << 17) 437#define DISPLAY_PIPE_VBLANK_STATUS (1UL << 1) 438 439#define INTEL_DISPLAY_A_CONTROL (0x0180 | REGS_NORTH_PLANE_CONTROL) 440#define INTEL_DISPLAY_A_BASE (0x0184 | REGS_NORTH_PLANE_CONTROL) 441#define INTEL_DISPLAY_A_BYTES_PER_ROW (0x0188 | REGS_NORTH_PLANE_CONTROL) 442#define INTEL_DISPLAY_A_POS (0x018c | REGS_NORTH_PLANE_CONTROL) 443 // reserved on A 444#define INTEL_DISPLAY_A_PIPE_SIZE (0x0190 | REGS_NORTH_PLANE_CONTROL) 445#define INTEL_DISPLAY_A_SURFACE (0x019c | REGS_NORTH_PLANE_CONTROL) 446 // i965 and up only 447 448#define INTEL_DISPLAY_B_CONTROL (0x1180 | REGS_NORTH_PLANE_CONTROL) 449#define INTEL_DISPLAY_B_BASE (0x1184 | REGS_NORTH_PLANE_CONTROL) 450#define INTEL_DISPLAY_B_BYTES_PER_ROW (0x1188 | REGS_NORTH_PLANE_CONTROL) 451#define INTEL_DISPLAY_B_POS (0x118c | REGS_NORTH_PLANE_CONTROL) 452#define INTEL_DISPLAY_B_PIPE_SIZE (0x1190 | REGS_NORTH_PLANE_CONTROL) 453#define INTEL_DISPLAY_B_SURFACE (0x119c | REGS_NORTH_PLANE_CONTROL) 454 // i965 and up only 455 456#define DISPLAY_CONTROL_ENABLED (1UL << 31) 457#define DISPLAY_CONTROL_GAMMA (1UL << 30) 458#define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26) 459#define DISPLAY_CONTROL_CMAP8 (2UL << 26) 460#define DISPLAY_CONTROL_RGB15 (4UL << 26) 461#define DISPLAY_CONTROL_RGB16 (5UL << 26) 462#define DISPLAY_CONTROL_RGB32 (6UL << 26) 463 464// cursors 465#define INTEL_CURSOR_CONTROL (0x0080 | REGS_NORTH_PLANE_CONTROL) 466#define INTEL_CURSOR_BASE (0x0084 | REGS_NORTH_PLANE_CONTROL) 467#define INTEL_CURSOR_POSITION (0x0088 | REGS_NORTH_PLANE_CONTROL) 468#define INTEL_CURSOR_PALETTE (0x0090 | REGS_NORTH_PLANE_CONTROL) 469 // (- 0x009f) 470#define INTEL_CURSOR_SIZE (0x00a0 | REGS_NORTH_PLANE_CONTROL) 471#define CURSOR_ENABLED (1UL << 31) 472#define CURSOR_FORMAT_2_COLORS (0UL << 24) 473#define CURSOR_FORMAT_3_COLORS (1UL << 24) 474#define CURSOR_FORMAT_4_COLORS (2UL << 24) 475#define CURSOR_FORMAT_ARGB (4UL << 24) 476#define CURSOR_FORMAT_XRGB (5UL << 24) 477#define CURSOR_POSITION_NEGATIVE 0x8000 478#define CURSOR_POSITION_MASK 0x3fff 479 480// palette registers 481#define INTEL_DISPLAY_A_PALETTE (0xa000 | REGS_NORTH_SHARED) 482#define INTEL_DISPLAY_B_PALETTE (0xa800 | REGS_NORTH_SHARED) 483 484// PLL registers 485#define INTEL_DISPLAY_A_PLL (0x6014 | REGS_SOUTH_SHARED) 486#define INTEL_DISPLAY_B_PLL (0x6018 | REGS_SOUTH_SHARED) 487#define INTEL_DISPLAY_A_PLL_MULTIPLIER_DIVISOR \ 488 (0x601c | REGS_SOUTH_SHARED) 489#define INTEL_DISPLAY_B_PLL_MULTIPLIER_DIVISOR \ 490 (0x6020 | REGS_SOUTH_SHARED) 491#define INTEL_DISPLAY_A_PLL_DIVISOR_0 (0x6040 | REGS_SOUTH_SHARED) 492#define INTEL_DISPLAY_A_PLL_DIVISOR_1 (0x6044 | REGS_SOUTH_SHARED) 493#define INTEL_DISPLAY_B_PLL_DIVISOR_0 (0x6048 | REGS_SOUTH_SHARED) 494#define INTEL_DISPLAY_B_PLL_DIVISOR_1 (0x604c | REGS_SOUTH_SHARED) 495 496// i2c 497#define INTEL_I2C_IO_A (0x5010 | REGS_SOUTH_SHARED) 498#define INTEL_I2C_IO_B (0x5014 | REGS_SOUTH_SHARED) 499#define INTEL_I2C_IO_C (0x5018 | REGS_SOUTH_SHARED) 500#define INTEL_I2C_IO_D (0x501c | REGS_SOUTH_SHARED) 501#define INTEL_I2C_IO_E (0x5020 | REGS_SOUTH_SHARED) 502#define INTEL_I2C_IO_F (0x5024 | REGS_SOUTH_SHARED) 503#define INTEL_I2C_IO_G (0x5028 | REGS_SOUTH_SHARED) 504#define INTEL_I2C_IO_H (0x502c | REGS_SOUTH_SHARED) 505 506#define I2C_CLOCK_DIRECTION_MASK (1 << 0) 507#define I2C_CLOCK_DIRECTION_OUT (1 << 1) 508#define I2C_CLOCK_VALUE_MASK (1 << 2) 509#define I2C_CLOCK_VALUE_OUT (1 << 3) 510#define I2C_CLOCK_VALUE_IN (1 << 4) 511#define I2C_DATA_DIRECTION_MASK (1 << 8) 512#define I2C_DATA_DIRECTION_OUT (1 << 9) 513#define I2C_DATA_VALUE_MASK (1 << 10) 514#define I2C_DATA_VALUE_OUT (1 << 11) 515#define I2C_DATA_VALUE_IN (1 << 12) 516#define I2C_RESERVED ((1 << 13) | (1 << 5)) 517 518// TODO: on IronLake this is in the north shared block at 0x41000 519#define INTEL_VGA_DISPLAY_CONTROL 0x71400 520#define VGA_DISPLAY_DISABLED (1UL << 31) 521 522// LVDS panel 523#define INTEL_PANEL_STATUS 0x61200 524#define PANEL_STATUS_POWER_ON (1UL << 31) 525#define INTEL_PANEL_CONTROL 0x61204 526#define PANEL_CONTROL_POWER_TARGET_ON (1UL << 0) 527#define INTEL_PANEL_FIT_CONTROL 0x61230 528#define INTEL_PANEL_FIT_RATIOS 0x61234 529 530// LVDS on IronLake and up 531#define PCH_PANEL_CONTROL 0xc7200 532#define PCH_PANEL_STATUS 0xc7204 533#define PANEL_REGISTER_UNLOCK (0xabcd << 16) 534#define PCH_LVDS_DETECTED (1 << 1) 535 536 537// ring buffer commands 538 539#define COMMAND_NOOP 0x00 540#define COMMAND_WAIT_FOR_EVENT (0x03 << 23) 541#define COMMAND_WAIT_FOR_OVERLAY_FLIP (1 << 16) 542 543#define COMMAND_FLUSH (0x04 << 23) 544 545// overlay flip 546#define COMMAND_OVERLAY_FLIP (0x11 << 23) 547#define COMMAND_OVERLAY_CONTINUE (0 << 21) 548#define COMMAND_OVERLAY_ON (1 << 21) 549#define COMMAND_OVERLAY_OFF (2 << 21) 550#define OVERLAY_UPDATE_COEFFICIENTS 0x1 551 552// 2D acceleration 553#define XY_COMMAND_SOURCE_BLIT 0x54c00006 554#define XY_COMMAND_COLOR_BLIT 0x54000004 555#define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007 556#define XY_COMMAND_SCANLINE_BLIT 0x49400001 557#define COMMAND_COLOR_BLIT 0x50000003 558#define COMMAND_BLIT_RGBA 0x00300000 559 560#define COMMAND_MODE_SOLID_PATTERN 0x80 561#define COMMAND_MODE_CMAP8 0x00 562#define COMMAND_MODE_RGB15 0x02 563#define COMMAND_MODE_RGB16 0x01 564#define COMMAND_MODE_RGB32 0x03 565 566// overlay 567#define INTEL_OVERLAY_UPDATE 0x30000 568#define INTEL_OVERLAY_TEST 0x30004 569#define INTEL_OVERLAY_STATUS 0x30008 570#define INTEL_OVERLAY_EXTENDED_STATUS 0x3000c 571#define INTEL_OVERLAY_GAMMA_5 0x30010 572#define INTEL_OVERLAY_GAMMA_4 0x30014 573#define INTEL_OVERLAY_GAMMA_3 0x30018 574#define INTEL_OVERLAY_GAMMA_2 0x3001c 575#define INTEL_OVERLAY_GAMMA_1 0x30020 576#define INTEL_OVERLAY_GAMMA_0 0x30024 577 578struct overlay_scale { 579 uint32 _reserved0 : 3; 580 uint32 horizontal_scale_fraction : 12; 581 uint32 _reserved1 : 1; 582 uint32 horizontal_downscale_factor : 3; 583 uint32 _reserved2 : 1; 584 uint32 vertical_scale_fraction : 12; 585}; 586 587#define OVERLAY_FORMAT_RGB15 0x2 588#define OVERLAY_FORMAT_RGB16 0x3 589#define OVERLAY_FORMAT_RGB32 0x1 590#define OVERLAY_FORMAT_YCbCr422 0x8 591#define OVERLAY_FORMAT_YCbCr411 0x9 592#define OVERLAY_FORMAT_YCbCr420 0xc 593 594#define OVERLAY_MIRROR_NORMAL 0x0 595#define OVERLAY_MIRROR_HORIZONTAL 0x1 596#define OVERLAY_MIRROR_VERTICAL 0x2 597 598// The real overlay registers are written to using an update buffer 599 600struct overlay_registers { 601 uint32 buffer_rgb0; 602 uint32 buffer_rgb1; 603 uint32 buffer_u0; 604 uint32 buffer_v0; 605 uint32 buffer_u1; 606 uint32 buffer_v1; 607 // (0x18) OSTRIDE - overlay stride 608 uint16 stride_rgb; 609 uint16 stride_uv; 610 // (0x1c) YRGB_VPH - Y/RGB vertical phase 611 uint16 vertical_phase0_rgb; 612 uint16 vertical_phase1_rgb; 613 // (0x20) UV_VPH - UV vertical phase 614 uint16 vertical_phase0_uv; 615 uint16 vertical_phase1_uv; 616 // (0x24) HORZ_PH - horizontal phase 617 uint16 horizontal_phase_rgb; 618 uint16 horizontal_phase_uv; 619 // (0x28) INIT_PHS - initial phase shift 620 uint32 initial_vertical_phase0_shift_rgb0 : 4; 621 uint32 initial_vertical_phase1_shift_rgb0 : 4; 622 uint32 initial_horizontal_phase_shift_rgb0 : 4; 623 uint32 initial_vertical_phase0_shift_uv : 4; 624 uint32 initial_vertical_phase1_shift_uv : 4; 625 uint32 initial_horizontal_phase_shift_uv : 4; 626 uint32 _reserved0 : 8; 627 // (0x2c) DWINPOS - destination window position 628 uint16 window_left; 629 uint16 window_top; 630 // (0x30) DWINSZ - destination window size 631 uint16 window_width; 632 uint16 window_height; 633 // (0x34) SWIDTH - source width 634 uint16 source_width_rgb; 635 uint16 source_width_uv; 636 // (0x38) SWITDHSW - source width in 8 byte steps 637 uint16 source_bytes_per_row_rgb; 638 uint16 source_bytes_per_row_uv; 639 uint16 source_height_rgb; 640 uint16 source_height_uv; 641 overlay_scale scale_rgb; 642 overlay_scale scale_uv; 643 // (0x48) OCLRC0 - overlay color correction 0 644 uint32 brightness_correction : 8; // signed, -128 to 127 645 uint32 _reserved1 : 10; 646 uint32 contrast_correction : 9; // fixed point: 3.6 bits 647 uint32 _reserved2 : 5; 648 // (0x4c) OCLRC1 - overlay color correction 1 649 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 650 uint32 _reserved3 : 6; 651 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 652 uint32 _reserved4 : 5; 653 // (0x50) DCLRKV - destination color key value 654 uint32 color_key_blue : 8; 655 uint32 color_key_green : 8; 656 uint32 color_key_red : 8; 657 uint32 _reserved5 : 8; 658 // (0x54) DCLRKM - destination color key mask 659 uint32 color_key_mask_blue : 8; 660 uint32 color_key_mask_green : 8; 661 uint32 color_key_mask_red : 8; 662 uint32 _reserved6 : 7; 663 uint32 color_key_enabled : 1; 664 // (0x58) SCHRKVH - source chroma key high value 665 uint32 source_chroma_key_high_red : 8; 666 uint32 source_chroma_key_high_blue : 8; 667 uint32 source_chroma_key_high_green : 8; 668 uint32 _reserved7 : 8; 669 // (0x5c) SCHRKVL - source chroma key low value 670 uint32 source_chroma_key_low_red : 8; 671 uint32 source_chroma_key_low_blue : 8; 672 uint32 source_chroma_key_low_green : 8; 673 uint32 _reserved8 : 8; 674 // (0x60) SCHRKEN - source chroma key enable 675 uint32 _reserved9 : 24; 676 uint32 source_chroma_key_red_enabled : 1; 677 uint32 source_chroma_key_blue_enabled : 1; 678 uint32 source_chroma_key_green_enabled : 1; 679 uint32 _reserved10 : 5; 680 // (0x64) OCONFIG - overlay configuration 681 uint32 _reserved11 : 3; 682 uint32 color_control_output_mode : 1; 683 uint32 yuv_to_rgb_bypass : 1; 684 uint32 _reserved12 : 11; 685 uint32 gamma2_enabled : 1; 686 uint32 _reserved13 : 1; 687 uint32 select_pipe : 1; 688 uint32 slot_time : 8; 689 uint32 _reserved14 : 5; 690 // (0x68) OCOMD - overlay command 691 uint32 overlay_enabled : 1; 692 uint32 active_field : 1; 693 uint32 active_buffer : 2; 694 uint32 test_mode : 1; 695 uint32 buffer_field_mode : 1; 696 uint32 _reserved15 : 1; 697 uint32 tv_flip_field_enabled : 1; 698 uint32 _reserved16 : 1; 699 uint32 tv_flip_field_parity : 1; 700 uint32 source_format : 4; 701 uint32 ycbcr422_order : 2; 702 uint32 _reserved18 : 1; 703 uint32 mirroring_mode : 2; 704 uint32 _reserved19 : 13; 705 706 uint32 _reserved20; 707 708 uint32 start_0y; 709 uint32 start_1y; 710 uint32 start_0u; 711 uint32 start_0v; 712 uint32 start_1u; 713 uint32 start_1v; 714 uint32 _reserved21[6]; 715#if 0 716 // (0x70) AWINPOS - alpha blend window position 717 uint32 awinpos; 718 // (0x74) AWINSZ - alpha blend window size 719 uint32 awinsz; 720 721 uint32 _reserved21[10]; 722#endif 723 724 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 725 // the next two registers switch the usual Y/RGB vs. UV order) 726 uint16 horizontal_scale_uv; 727 uint16 horizontal_scale_rgb; 728 // (0xa4) UVSCALEV - vertical downscale 729 uint16 vertical_scale_uv; 730 uint16 vertical_scale_rgb; 731 732 uint32 _reserved22[86]; 733 734 // (0x200) polyphase filter coefficients 735 uint16 vertical_coefficients_rgb[128]; 736 uint16 horizontal_coefficients_rgb[128]; 737 738 uint32 _reserved23[64]; 739 740 // (0x500) 741 uint16 vertical_coefficients_uv[128]; 742 uint16 horizontal_coefficients_uv[128]; 743}; 744 745// i965 overlay support is currently realized using its 3D hardware 746#define INTEL_i965_OVERLAY_STATE_SIZE 36864 747#define INTEL_i965_3D_CONTEXT_SIZE 32768 748 749inline bool 750intel_uses_physical_overlay(intel_shared_info &info) 751{ 752 return !info.device_type.InGroup(INTEL_TYPE_Gxx); 753} 754 755 756struct hardware_status { 757 uint32 interrupt_status_register; 758 uint32 _reserved0[3]; 759 void* primary_ring_head_storage; 760 uint32 _reserved1[3]; 761 void* secondary_ring_0_head_storage; 762 void* secondary_ring_1_head_storage; 763 uint32 _reserved2[2]; 764 void* binning_head_storage; 765 uint32 _reserved3[3]; 766 uint32 store[1008]; 767}; 768 769#endif /* INTEL_EXTREME_H */ 770