1/* Definitions of target machine for GNU compiler for Hitachi Super-H. 2 Copyright (C) 1993-1998 Free Software Foundation, Inc. 3 Contributed by Steve Chamberlain (sac@cygnus.com). 4 Improved by Jim Wilson (wilson@cygnus.com). 5 6This file is part of GNU CC. 7 8GNU CC is free software; you can redistribute it and/or modify 9it under the terms of the GNU General Public License as published by 10the Free Software Foundation; either version 2, or (at your option) 11any later version. 12 13GNU CC is distributed in the hope that it will be useful, 14but WITHOUT ANY WARRANTY; without even the implied warranty of 15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16GNU General Public License for more details. 17 18You should have received a copy of the GNU General Public License 19along with GNU CC; see the file COPYING. If not, write to 20the Free Software Foundation, 59 Temple Place - Suite 330, 21Boston, MA 02111-1307, USA. */ 22 23 24#define TARGET_VERSION \ 25 fputs (" (Hitachi SH)", stderr); 26 27/* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't 28 include it here, because hconfig.h is also included by gencodes.c . */ 29extern int code_for_indirect_jump_scratch; 30 31/* Generate SDB debugging information. */ 32 33#define SDB_DEBUGGING_INFO 34 35/* Output DBX (stabs) debugging information if doing -gstabs. */ 36 37#include "dbxcoff.h" 38 39#define SDB_DELIM ";" 40 41#define CPP_SPEC "%{ml:-D__LITTLE_ENDIAN__} \ 42%{m1:-D__sh1__} \ 43%{m2:-D__sh2__} \ 44%{m3:-D__sh3__} \ 45%{m3e:-D__SH3E__} \ 46%{m4-single-only:-D__SH4_SINGLE_ONLY__} \ 47%{m4-single:-D__SH4_SINGLE__} \ 48%{m4:-D__SH4__} \ 49%{!m1:%{!m2:%{!m3:%{!m3e:%{!m4:%{!m4-single:%{!m4-single-only:-D__sh1__}}}}}}} \ 50%{mhitachi:-D__HITACHI__}" 51 52#define CPP_PREDEFINES "-D__sh__ -Acpu(sh) -Amachine(sh)" 53 54#define ASM_SPEC "%{ml:-little} %{mrelax:-relax}" 55 56#define LINK_SPEC "%{ml:-m shl} %{mrelax:-relax}" 57 58/* We can not debug without a frame pointer. */ 59/* #define CAN_DEBUG_WITHOUT_FP */ 60 61#define CONDITIONAL_REGISTER_USAGE \ 62 if (! TARGET_SH4 || ! TARGET_FMOVD) \ 63 { \ 64 int regno; \ 65 for (regno = FIRST_XD_REG; regno <= LAST_XD_REG; regno++) \ 66 fixed_regs[regno] = call_used_regs[regno] = 1; \ 67 if (! TARGET_SH4) \ 68 { \ 69 if (! TARGET_SH3E) \ 70 { \ 71 int regno; \ 72 for (regno = FIRST_FP_REG; regno <= LAST_FP_REG; regno++) \ 73 fixed_regs[regno] = call_used_regs[regno] = 1; \ 74 fixed_regs[FPUL_REG] = call_used_regs[FPUL_REG] = 1; \ 75 } \ 76 } \ 77 } \ 78 /* Hitachi saves and restores mac registers on call. */ \ 79 if (TARGET_HITACHI) \ 80 { \ 81 call_used_regs[MACH_REG] = 0; \ 82 call_used_regs[MACL_REG] = 0; \ 83 } 84 85/* ??? Need to write documentation for all SH options and add it to the 86 invoke.texi file. */ 87 88/* Run-time compilation parameters selecting different hardware subsets. */ 89 90extern int target_flags; 91#define ISIZE_BIT (1<<1) 92#define DALIGN_BIT (1<<6) 93#define SH1_BIT (1<<8) 94#define SH2_BIT (1<<9) 95#define SH3_BIT (1<<10) 96#define SH3E_BIT (1<<11) 97#define HARD_SH4_BIT (1<<5) 98#define FPU_SINGLE_BIT (1<<7) 99#define SH4_BIT (1<<12) 100#define FMOVD_BIT (1<<4) 101#define SPACE_BIT (1<<13) 102#define BIGTABLE_BIT (1<<14) 103#define RELAX_BIT (1<<15) 104#define HITACHI_BIT (1<<22) 105#define PADSTRUCT_BIT (1<<28) 106#define LITTLE_ENDIAN_BIT (1<<29) 107#define IEEE_BIT (1<<30) 108 109/* Nonzero if we should dump out instruction size info. */ 110#define TARGET_DUMPISIZE (target_flags & ISIZE_BIT) 111 112/* Nonzero to align doubles on 64 bit boundaries. */ 113#define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT) 114 115/* Nonzero if we should generate code using type 1 insns. */ 116#define TARGET_SH1 (target_flags & SH1_BIT) 117 118/* Nonzero if we should generate code using type 2 insns. */ 119#define TARGET_SH2 (target_flags & SH2_BIT) 120 121/* Nonzero if we should generate code using type 3 insns. */ 122#define TARGET_SH3 (target_flags & SH3_BIT) 123 124/* Nonzero if we should generate code using type 3E insns. */ 125#define TARGET_SH3E (target_flags & SH3E_BIT) 126 127/* Nonzero if the cache line size is 32. */ 128#define TARGET_CACHE32 (target_flags & HARD_SH4_BIT) 129 130/* Nonzero if we schedule for a superscalar implementation. */ 131#define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT) 132 133/* Nonzero if the target has separate instruction and data caches. */ 134#define TARGET_HARWARD (target_flags & HARD_SH4_BIT) 135 136/* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */ 137#define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT) 138 139/* Nonzero if the default precision of th FPU is single */ 140#define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT) 141 142/* Nonzero if we should generate code using type 4 insns. */ 143#define TARGET_SH4 (target_flags & SH4_BIT) 144 145/* Nonzero if we should generate fmovd. */ 146#define TARGET_FMOVD (target_flags & FMOVD_BIT) 147 148/* Nonzero if we respect NANs. */ 149#define TARGET_IEEE (target_flags & IEEE_BIT) 150 151/* Nonzero if we should generate smaller code rather than faster code. */ 152#define TARGET_SMALLCODE (target_flags & SPACE_BIT) 153 154/* Nonzero to use long jump tables. */ 155#define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT) 156 157/* Nonzero to generate pseudo-ops needed by the assembler and linker 158 to do function call relaxing. */ 159#define TARGET_RELAX (target_flags & RELAX_BIT) 160 161/* Nonzero if using Hitachi's calling convention. */ 162#define TARGET_HITACHI (target_flags & HITACHI_BIT) 163 164/* Nonzero if padding structures to a multiple of 4 bytes. This is 165 incompatible with Hitachi's compiler, and gives unusual structure layouts 166 which confuse programmers. 167 ??? This option is not useful, but is retained in case there are people 168 who are still relying on it. It may be deleted in the future. */ 169#define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT) 170 171/* Nonzero if generating code for a little endian SH. */ 172#define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT) 173 174#define TARGET_SWITCHES \ 175{ {"1", SH1_BIT}, \ 176 {"2", SH2_BIT}, \ 177 {"3", SH3_BIT|SH2_BIT}, \ 178 {"3e", SH3E_BIT|SH3_BIT|SH2_BIT|FPU_SINGLE_BIT}, \ 179 {"4-single-only", SH3E_BIT|SH3_BIT|SH2_BIT|SH3E_BIT|HARD_SH4_BIT|FPU_SINGLE_BIT}, \ 180 {"4-single", SH4_BIT|SH3E_BIT|SH3_BIT|SH2_BIT|HARD_SH4_BIT|FPU_SINGLE_BIT},\ 181 {"4", SH4_BIT|SH3E_BIT|SH3_BIT|SH2_BIT|HARD_SH4_BIT}, \ 182 {"b", -LITTLE_ENDIAN_BIT}, \ 183 {"bigtable", BIGTABLE_BIT}, \ 184 {"dalign", DALIGN_BIT}, \ 185 {"fmovd", FMOVD_BIT}, \ 186 {"hitachi", HITACHI_BIT}, \ 187 {"ieee", IEEE_BIT}, \ 188 {"isize", ISIZE_BIT}, \ 189 {"l", LITTLE_ENDIAN_BIT}, \ 190 {"no-ieee", -IEEE_BIT}, \ 191 {"padstruct", PADSTRUCT_BIT}, \ 192 {"relax", RELAX_BIT}, \ 193 {"space", SPACE_BIT}, \ 194 SUBTARGET_SWITCHES \ 195 {"", TARGET_DEFAULT} \ 196} 197 198/* This are meant to be redefined in the host dependent files */ 199#define SUBTARGET_SWITCHES 200 201#define TARGET_DEFAULT (0) 202 203#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \ 204do { \ 205 if (LEVEL) \ 206 flag_omit_frame_pointer = -1; \ 207 if (LEVEL) \ 208 sh_flag_remove_dead_before_cse = 1; \ 209 if (SIZE) \ 210 target_flags |= SPACE_BIT; \ 211} while (0) 212 213#define ASSEMBLER_DIALECT assembler_dialect 214 215extern int assembler_dialect; 216 217#define OVERRIDE_OPTIONS \ 218do { \ 219 sh_cpu = CPU_SH1; \ 220 assembler_dialect = 0; \ 221 if (TARGET_SH2) \ 222 sh_cpu = CPU_SH2; \ 223 if (TARGET_SH3) \ 224 sh_cpu = CPU_SH3; \ 225 if (TARGET_SH3E) \ 226 sh_cpu = CPU_SH3E; \ 227 if (TARGET_SH4) \ 228 { \ 229 assembler_dialect = 1; \ 230 sh_cpu = CPU_SH4; \ 231 } \ 232 if (! TARGET_SH4 || ! TARGET_FMOVD) \ 233 { \ 234 /* Prevent usage of explicit register names for variables \ 235 for registers not present / not addressable in the \ 236 target architecture. */ \ 237 int regno; \ 238 for (regno = (TARGET_SH3E) ? 17 : 0; \ 239 regno <= 24; regno++) \ 240 fp_reg_names[regno][0] = 0; \ 241 } \ 242 if (flag_omit_frame_pointer < 0) \ 243 /* The debugging information is sufficient, \ 244 but gdb doesn't implement this yet */ \ 245 if (0) \ 246 flag_omit_frame_pointer \ 247 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \ 248 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \ 249 else \ 250 flag_omit_frame_pointer = 0; \ 251 \ 252 /* Never run scheduling before reload, since that can \ 253 break global alloc, and generates slower code anyway due \ 254 to the pressure on R0. */ \ 255 flag_schedule_insns = 0; \ 256 sh_addr_diff_vec_mode = TARGET_BIGTABLE ? SImode : HImode; \ 257} while (0) 258 259/* Target machine storage layout. */ 260 261/* Define to use software floating point emulator for REAL_ARITHMETIC and 262 decimal <-> binary conversion. */ 263#define REAL_ARITHMETIC 264 265/* Define this if most significant bit is lowest numbered 266 in instructions that operate on numbered bit-fields. */ 267 268#define BITS_BIG_ENDIAN 0 269 270/* Define this if most significant byte of a word is the lowest numbered. */ 271#define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) 272 273/* Define this if most significant word of a multiword number is the lowest 274 numbered. */ 275#define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) 276 277/* Define this to set the endianness to use in libgcc2.c, which can 278 not depend on target_flags. */ 279#if defined(__LITTLE_ENDIAN__) 280#define LIBGCC2_WORDS_BIG_ENDIAN 0 281#else 282#define LIBGCC2_WORDS_BIG_ENDIAN 1 283#endif 284 285/* Number of bits in an addressable storage unit. */ 286#define BITS_PER_UNIT 8 287 288/* Width in bits of a "word", which is the contents of a machine register. 289 Note that this is not necessarily the width of data type `int'; 290 if using 16-bit ints on a 68000, this would still be 32. 291 But on a machine with 16-bit registers, this would be 16. */ 292#define BITS_PER_WORD 32 293#define MAX_BITS_PER_WORD 32 294 295/* Width of a word, in units (bytes). */ 296#define UNITS_PER_WORD 4 297 298/* Width in bits of a pointer. 299 See also the macro `Pmode' defined below. */ 300#define POINTER_SIZE 32 301 302/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 303#define PARM_BOUNDARY 32 304 305/* Boundary (in *bits*) on which stack pointer should be aligned. */ 306#define STACK_BOUNDARY BIGGEST_ALIGNMENT 307 308/* The log (base 2) of the cache line size, in bytes. Processors prior to 309 SH2 have no actual cache, but they fetch code in chunks of 4 bytes. 310 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */ 311#define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2) 312 313/* Allocation boundary (in *bits*) for the code of a function. 314 32 bit alignment is faster, because instructions are always fetched as a 315 pair from a longword boundary. */ 316#define FUNCTION_BOUNDARY (TARGET_SMALLCODE ? 16 : (1 << CACHE_LOG) * 8) 317 318/* Alignment of field after `int : 0' in a structure. */ 319#define EMPTY_FIELD_BOUNDARY 32 320 321/* No data type wants to be aligned rounder than this. */ 322#define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32) 323 324/* The best alignment to use in cases where we have a choice. */ 325#define FASTEST_ALIGNMENT 32 326 327/* Make strings word-aligned so strcpy from constants will be faster. */ 328#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 329 ((TREE_CODE (EXP) == STRING_CST \ 330 && (ALIGN) < FASTEST_ALIGNMENT) \ 331 ? FASTEST_ALIGNMENT : (ALIGN)) 332 333#ifndef MAX_OFILE_ALIGNMENT 334#define MAX_OFILE_ALIGNMENT 128 335#endif 336 337/* Make arrays of chars word-aligned for the same reasons. */ 338#define DATA_ALIGNMENT(TYPE, ALIGN) \ 339 (TREE_CODE (TYPE) == ARRAY_TYPE \ 340 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 341 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 342 343/* Number of bits which any structure or union's size must be a 344 multiple of. Each structure or union's size is rounded up to a 345 multiple of this. */ 346#define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8) 347 348/* Set this nonzero if move instructions will actually fail to work 349 when given unaligned data. */ 350#define STRICT_ALIGNMENT 1 351 352/* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */ 353#define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \ 354 barrier_align (LABEL_AFTER_BARRIER) 355 356#define LOOP_ALIGN(A_LABEL) \ 357 ((! optimize || TARGET_HARWARD || TARGET_SMALLCODE) ? 0 : 2) 358 359#define LABEL_ALIGN(A_LABEL) \ 360( \ 361 (PREV_INSN (A_LABEL) \ 362 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \ 363 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \ 364 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == 1) \ 365 /* explicit alignment insn in constant tables. */ \ 366 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \ 367 : 0) 368 369/* Jump tables must be 32 bit aligned, no matter the size of the element. */ 370#define ADDR_VEC_ALIGN(ADDR_VEC) 2 371 372/* The base two logarithm of the known minimum alignment of an insn length. */ 373#define INSN_LENGTH_ALIGNMENT(A_INSN) \ 374 (GET_CODE (A_INSN) == INSN \ 375 ? 1 \ 376 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \ 377 ? 1 \ 378 : CACHE_LOG) 379 380/* Standard register usage. */ 381 382/* Register allocation for the Hitachi calling convention: 383 384 r0 arg return 385 r1..r3 scratch 386 r4..r7 args in 387 r8..r13 call saved 388 r14 frame pointer/call saved 389 r15 stack pointer 390 ap arg pointer (doesn't really exist, always eliminated) 391 pr subroutine return address 392 t t bit 393 mach multiply/accumulate result, high part 394 macl multiply/accumulate result, low part. 395 fpul fp/int communication register 396 rap return address pointer register 397 fr0 fp arg return 398 fr1..fr3 scratch floating point registers 399 fr4..fr11 fp args in 400 fr12..fr15 call saved floating point registers */ 401 402/* Number of actual hardware registers. 403 The hardware registers are assigned numbers for the compiler 404 from 0 to just below FIRST_PSEUDO_REGISTER. 405 All registers that the compiler knows about must be given numbers, 406 even those that are not normally considered general registers. */ 407 408#define AP_REG 16 409#define PR_REG 17 410#define T_REG 18 411#define GBR_REG 19 412#define MACH_REG 20 413#define MACL_REG 21 414#define SPECIAL_REG(REGNO) ((REGNO) >= 18 && (REGNO) <= 21) 415#define FPUL_REG 22 416#define RAP_REG 23 417#define FIRST_FP_REG 24 418#define LAST_FP_REG 39 419#define FIRST_XD_REG 40 420#define LAST_XD_REG 47 421#define FPSCR_REG 48 422 423#define FIRST_PSEUDO_REGISTER 49 424 425/* 1 for registers that have pervasive standard uses 426 and are not available for the register allocator. 427 428 Mach register is fixed 'cause it's only 10 bits wide for SH1. 429 It is 32 bits wide for SH2. */ 430 431#define FIXED_REGISTERS \ 432 { 0, 0, 0, 0, \ 433 0, 0, 0, 0, \ 434 0, 0, 0, 0, \ 435 0, 0, 0, 1, \ 436 1, 1, 1, 1, \ 437 1, 1, 0, 1, \ 438 0, 0, 0, 0, \ 439 0, 0, 0, 0, \ 440 0, 0, 0, 0, \ 441 0, 0, 0, 0, \ 442 0, 0, 0, 0, \ 443 0, 0, 0, 0, \ 444 1, \ 445} 446 447/* 1 for registers not available across function calls. 448 These must include the FIXED_REGISTERS and also any 449 registers that can be used without being saved. 450 The latter must include the registers where values are returned 451 and the register where structure-value addresses are passed. 452 Aside from that, you can include as many other registers as you like. */ 453 454#define CALL_USED_REGISTERS \ 455 { 1, 1, 1, 1, \ 456 1, 1, 1, 1, \ 457 0, 0, 0, 0, \ 458 0, 0, 0, 1, \ 459 1, 0, 1, 1, \ 460 1, 1, 1, 1, \ 461 1, 1, 1, 1, \ 462 1, 1, 1, 1, \ 463 1, 1, 1, 1, \ 464 0, 0, 0, 0, \ 465 1, 1, 1, 1, \ 466 1, 1, 0, 0, \ 467 1, \ 468} 469 470/* Return number of consecutive hard regs needed starting at reg REGNO 471 to hold something of mode MODE. 472 This is ordinarily the length in words of a value of mode MODE 473 but can be less for certain modes in special long registers. 474 475 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */ 476 477#define HARD_REGNO_NREGS(REGNO, MODE) \ 478 ((REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG \ 479 ? (GET_MODE_SIZE (MODE) / (2 * UNITS_PER_WORD)) \ 480 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \ 481 482/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 483 We can allow any mode in any general register. The special registers 484 only allow SImode. Don't allow any mode in the PR. */ 485 486/* We cannot hold DCmode values in the XD registers because alter_reg 487 handles subregs of them incorrectly. We could work around this by 488 spacing the XD registers like the DR registers, but this would require 489 additional memory in every compilation to hold larger register vectors. 490 We could hold SFmode / SCmode values in XD registers, but that 491 would require a tertiary reload when reloading from / to memory, 492 and a secondary reload to reload from / to general regs; that 493 seems to be a loosing proposition. */ 494#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 495 (SPECIAL_REG (REGNO) ? (MODE) == SImode \ 496 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \ 497 : (REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG && (MODE) == SFmode \ 498 ? 1 \ 499 : (REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG \ 500 ? ((MODE) == SFmode \ 501 || (TARGET_SH3E && (MODE) == SCmode) \ 502 || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode) \ 503 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \ 504 : (REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG \ 505 ? (MODE) == DFmode \ 506 : (REGNO) == PR_REG ? 0 \ 507 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \ 508 : 1) 509 510/* Value is 1 if it is a good idea to tie two pseudo registers 511 when one has mode MODE1 and one has mode MODE2. 512 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 513 for any hard reg, then this must be 0 for correct output. */ 514 515#define MODES_TIEABLE_P(MODE1, MODE2) \ 516 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) 517 518/* Specify the registers used for certain standard purposes. 519 The values of these macros are register numbers. */ 520 521/* Define this if the program counter is overloaded on a register. */ 522/* #define PC_REGNUM 15*/ 523 524/* Register to use for pushing function arguments. */ 525#define STACK_POINTER_REGNUM 15 526 527/* Base register for access to local variables of the function. */ 528#define FRAME_POINTER_REGNUM 14 529 530/* Fake register that holds the address on the stack of the 531 current function's return address. */ 532#define RETURN_ADDRESS_POINTER_REGNUM 23 533 534/* Value should be nonzero if functions must have frame pointers. 535 Zero means the frame pointer need not be set up (and parms may be accessed 536 via the stack pointer) in functions that seem suitable. */ 537 538#define FRAME_POINTER_REQUIRED 0 539 540/* Definitions for register eliminations. 541 542 We have three registers that can be eliminated on the SH. First, the 543 frame pointer register can often be eliminated in favor of the stack 544 pointer register. Secondly, the argument pointer register can always be 545 eliminated; it is replaced with either the stack or frame pointer. 546 Third, there is the return address pointer, which can also be replaced 547 with either the stack or the frame pointer. */ 548 549/* This is an array of structures. Each structure initializes one pair 550 of eliminable registers. The "from" register number is given first, 551 followed by "to". Eliminations of the same "from" register are listed 552 in order of preference. */ 553 554/* If you add any registers here that are not actually hard registers, 555 and that have any alternative of elimination that doesn't always 556 apply, you need to amend calc_live_regs to exclude it, because 557 reload spills all eliminable registers where it sees an 558 can_eliminate == 0 entry, thus making them 'live' . 559 If you add any hard registers that can be eliminated in different 560 ways, you have to patch reload to spill them only when all alternatives 561 of elimination fail. */ 562 563#define ELIMINABLE_REGS \ 564{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 565 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 566 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ 567 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 568 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},} 569 570/* Given FROM and TO register numbers, say whether this elimination 571 is allowed. */ 572#define CAN_ELIMINATE(FROM, TO) \ 573 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)) 574 575/* Define the offset between two registers, one to be eliminated, and the other 576 its replacement, at the start of a routine. */ 577 578#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 579 OFFSET = initial_elimination_offset ((FROM), (TO)) 580 581/* Base register for access to arguments of the function. */ 582#define ARG_POINTER_REGNUM 16 583 584/* Register in which the static-chain is passed to a function. */ 585#define STATIC_CHAIN_REGNUM 13 586 587/* The register in which a struct value address is passed. */ 588 589#define STRUCT_VALUE_REGNUM 2 590 591/* If the structure value address is not passed in a register, define 592 `STRUCT_VALUE' as an expression returning an RTX for the place 593 where the address is passed. If it returns 0, the address is 594 passed as an "invisible" first argument. */ 595 596/*#define STRUCT_VALUE ((rtx)0)*/ 597 598/* Don't default to pcc-struct-return, because we have already specified 599 exactly how to return structures in the RETURN_IN_MEMORY macro. */ 600 601#define DEFAULT_PCC_STRUCT_RETURN 0 602 603/* Define the classes of registers for register constraints in the 604 machine description. Also define ranges of constants. 605 606 One of the classes must always be named ALL_REGS and include all hard regs. 607 If there is more than one class, another class must be named NO_REGS 608 and contain no registers. 609 610 The name GENERAL_REGS must be the name of a class (or an alias for 611 another name such as ALL_REGS). This is the class of registers 612 that is allowed by "g" or "r" in a register constraint. 613 Also, registers outside this class are allocated only when 614 instructions express preferences for them. 615 616 The classes must be numbered in nondecreasing order; that is, 617 a larger-numbered class must never be contained completely 618 in a smaller-numbered class. 619 620 For any two classes, it is very desirable that there be another 621 class that represents their union. */ 622 623/* The SH has two sorts of general registers, R0 and the rest. R0 can 624 be used as the destination of some of the arithmetic ops. There are 625 also some special purpose registers; the T bit register, the 626 Procedure Return Register and the Multiply Accumulate Registers. */ 627/* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by 628 reg_class_subunion. We don't want to have an actual union class 629 of these, because it would only be used when both classes are calculated 630 to give the same cost, but there is only one FPUL register. 631 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS 632 applying to the actual instruction alternative considered. E.g., the 633 y/r alternative of movsi_ie is considered to have no more cost that 634 the r/r alternative, which is patently untrue. */ 635 636enum reg_class 637{ 638 NO_REGS, 639 R0_REGS, 640 PR_REGS, 641 T_REGS, 642 MAC_REGS, 643 FPUL_REGS, 644 GENERAL_REGS, 645 FP0_REGS, 646 FP_REGS, 647 DF_REGS, 648 FPSCR_REGS, 649 GENERAL_FP_REGS, 650 ALL_REGS, 651 LIM_REG_CLASSES 652}; 653 654#define N_REG_CLASSES (int) LIM_REG_CLASSES 655 656/* Give names of register classes as strings for dump file. */ 657#define REG_CLASS_NAMES \ 658{ \ 659 "NO_REGS", \ 660 "R0_REGS", \ 661 "PR_REGS", \ 662 "T_REGS", \ 663 "MAC_REGS", \ 664 "FPUL_REGS", \ 665 "GENERAL_REGS", \ 666 "FP0_REGS", \ 667 "FP_REGS", \ 668 "DF_REGS", \ 669 "FPSCR_REGS", \ 670 "GENERAL_FP_REGS", \ 671 "ALL_REGS", \ 672} 673 674/* Define which registers fit in which classes. 675 This is an initializer for a vector of HARD_REG_SET 676 of length N_REG_CLASSES. */ 677 678#define REG_CLASS_CONTENTS \ 679{ \ 680 { 0x00000000, 0x00000000 }, /* NO_REGS */ \ 681 { 0x00000001, 0x00000000 }, /* R0_REGS */ \ 682 { 0x00020000, 0x00000000 }, /* PR_REGS */ \ 683 { 0x00040000, 0x00000000 }, /* T_REGS */ \ 684 { 0x00300000, 0x00000000 }, /* MAC_REGS */ \ 685 { 0x00400000, 0x00000000 }, /* FPUL_REGS */ \ 686 { 0x0081FFFF, 0x00000000 }, /* GENERAL_REGS */ \ 687 { 0x01000000, 0x00000000 }, /* FP0_REGS */ \ 688 { 0xFF000000, 0x000000FF }, /* FP_REGS */ \ 689 { 0xFF000000, 0x0000FFFF }, /* DF_REGS */ \ 690 { 0x00000000, 0x00010000 }, /* FPSCR_REGS */ \ 691 { 0xFF81FFFF, 0x0000FFFF }, /* GENERAL_FP_REGS */ \ 692 { 0xFFFFFFFF, 0x0001FFFF }, /* ALL_REGS */ \ 693} 694 695/* The same information, inverted: 696 Return the class number of the smallest class containing 697 reg number REGNO. This could be a conditional expression 698 or could index an array. */ 699 700extern int regno_reg_class[]; 701#define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)] 702 703/* When defined, the compiler allows registers explicitly used in the 704 rtl to be used as spill registers but prevents the compiler from 705 extending the lifetime of these registers. */ 706 707#define SMALL_REGISTER_CLASSES 1 708 709/* The order in which register should be allocated. */ 710/* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo, 711 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be 712 spilled or used otherwise, we better have the FP_REGS allocated first. */ 713#define REG_ALLOC_ORDER \ 714 { 25,26,27,28,29,30,31,24,32,33,34,35,36,37,38,39, \ 715 40,41,42,43,44,45,46,47,48, \ 716 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14, \ 717 22,15,16,17,18,19,20,21,23 } 718 719/* The class value for index registers, and the one for base regs. */ 720#define INDEX_REG_CLASS R0_REGS 721#define BASE_REG_CLASS GENERAL_REGS 722 723/* Get reg_class from a letter such as appears in the machine 724 description. */ 725extern enum reg_class reg_class_from_letter[]; 726 727#define REG_CLASS_FROM_LETTER(C) \ 728 ( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C)-'a'] : NO_REGS ) 729 730/* The letters I, J, K, L and M in a register constraint string 731 can be used to stand for particular ranges of immediate operands. 732 This macro defines what the ranges are. 733 C is the letter, and VALUE is a constant value. 734 Return 1 if VALUE is in the range specified by C. 735 I: arithmetic operand -127..128, as used in add, sub, etc 736 K: shift operand 1,2,8 or 16 737 L: logical operand 0..255, as used in and, or, etc. 738 M: constant 1 739 N: constant 0 */ 740 741#define CONST_OK_FOR_I(VALUE) (((int)(VALUE))>= -128 && ((int)(VALUE)) <= 127) 742#define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16) 743#define CONST_OK_FOR_L(VALUE) (((int)(VALUE))>= 0 && ((int)(VALUE)) <= 255) 744#define CONST_OK_FOR_M(VALUE) ((VALUE)==1) 745#define CONST_OK_FOR_N(VALUE) ((VALUE)==0) 746#define CONST_OK_FOR_LETTER_P(VALUE, C) \ 747 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \ 748 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \ 749 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \ 750 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \ 751 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \ 752 : 0) 753 754/* Similar, but for floating constants, and defining letters G and H. 755 Here VALUE is the CONST_DOUBLE rtx itself. */ 756 757#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 758((C) == 'G' ? fp_zero_operand (VALUE) \ 759 : (C) == 'H' ? fp_one_operand (VALUE) \ 760 : (C) == 'F') 761 762/* Given an rtx X being reloaded into a reg required to be 763 in class CLASS, return the class of reg to actually use. 764 In general this is just CLASS; but on some machines 765 in some cases it is preferable to use a more restrictive class. */ 766 767#define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS) 768 769#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \ 770 ((((((CLASS) == FP_REGS || (CLASS) == FP0_REGS \ 771 || (CLASS) == DF_REGS) \ 772 && (GET_CODE (X) == REG && REGNO (X) <= AP_REG)) \ 773 || (((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS) \ 774 && GET_CODE (X) == REG \ 775 && REGNO (X) >= FIRST_FP_REG && REGNO (X) <= LAST_FP_REG)) \ 776 && MODE == SFmode) \ 777 ? FPUL_REGS \ 778 : ((CLASS) == FPUL_REGS \ 779 && (GET_CODE (X) == MEM \ 780 || (GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER)))\ 781 ? GENERAL_REGS \ 782 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \ 783 && GET_CODE (X) == REG && REGNO (X) > 15 \ 784 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \ 785 ? GENERAL_REGS : NO_REGS) 786 787#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \ 788 ((((CLASS) == FP_REGS || (CLASS) == FP0_REGS || (CLASS) == DF_REGS) \ 789 && immediate_operand ((X), (MODE)) \ 790 && ! ((fp_zero_operand (X) || fp_one_operand (X)) && (MODE) == SFmode))\ 791 ? R0_REGS \ 792 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \ 793 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I (INTVAL (X)) \ 794 ? GENERAL_REGS \ 795 : R0_REGS) \ 796 : (CLASS == FPSCR_REGS \ 797 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ 798 || GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)) \ 799 ? GENERAL_REGS \ 800 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X))) 801 802/* Return the maximum number of consecutive registers 803 needed to represent mode MODE in a register of class CLASS. 804 805 On SH this is the size of MODE in words. */ 806#define CLASS_MAX_NREGS(CLASS, MODE) \ 807 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 808 809/* If defined, gives a class of registers that cannot be used as the 810 operand of a SUBREG that changes the size of the object. */ 811 812#define CLASS_CANNOT_CHANGE_SIZE DF_REGS 813 814/* Stack layout; function entry, exit and calling. */ 815 816/* Define the number of registers that can hold parameters. 817 These macros are used only in other macro definitions below. */ 818 819#define NPARM_REGS(MODE) \ 820 (TARGET_SH3E && (MODE) == SFmode \ 821 ? 8 \ 822 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 823 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ 824 ? 8 \ 825 : 4) 826 827#define FIRST_PARM_REG 4 828#define FIRST_RET_REG 0 829 830#define FIRST_FP_PARM_REG (FIRST_FP_REG + 4) 831#define FIRST_FP_RET_REG FIRST_FP_REG 832 833/* Define this if pushing a word on the stack 834 makes the stack pointer a smaller address. */ 835#define STACK_GROWS_DOWNWARD 836 837/* Define this macro if the addresses of local variable slots are at 838 negative offsets from the frame pointer. 839 840 The SH only has positive indexes, so grow the frame up. */ 841/* #define FRAME_GROWS_DOWNWARD */ 842 843/* Offset from the frame pointer to the first local variable slot to 844 be allocated. */ 845#define STARTING_FRAME_OFFSET 0 846 847/* If we generate an insn to push BYTES bytes, 848 this says how many the stack pointer really advances by. */ 849/* Don't define PUSH_ROUNDING, since the hardware doesn't do this. 850 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to 851 do correct alignment. */ 852#if 0 853#define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) 854#endif 855 856/* Offset of first parameter from the argument pointer register value. */ 857#define FIRST_PARM_OFFSET(FNDECL) 0 858 859/* Value is the number of byte of arguments automatically 860 popped when returning from a subroutine call. 861 FUNDECL is the declaration node of the function (as a tree), 862 FUNTYPE is the data type of the function (as a tree), 863 or for a library call it is an identifier node for the subroutine name. 864 SIZE is the number of bytes of arguments passed on the stack. 865 866 On the SH, the caller does not pop any of its arguments that were passed 867 on the stack. */ 868#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 869 870/* Nonzero if we do not know how to pass TYPE solely in registers. 871 Values that come in registers with inconvenient padding are stored 872 to memory at the function start. */ 873 874#define MUST_PASS_IN_STACK(MODE,TYPE) \ 875 ((TYPE) != 0 \ 876 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ 877 || TREE_ADDRESSABLE (TYPE))) 878/* Some subroutine macros specific to this machine. */ 879 880#define BASE_RETURN_VALUE_REG(MODE) \ 881 ((TARGET_SH3E && ((MODE) == SFmode)) \ 882 ? FIRST_FP_RET_REG \ 883 : TARGET_SH3E && (MODE) == SCmode \ 884 ? FIRST_FP_RET_REG \ 885 : (TARGET_SH4 \ 886 && ((MODE) == DFmode || (MODE) == SFmode \ 887 || (MODE) == DCmode || (MODE) == SCmode )) \ 888 ? FIRST_FP_RET_REG \ 889 : FIRST_RET_REG) 890 891#define BASE_ARG_REG(MODE) \ 892 ((TARGET_SH3E && ((MODE) == SFmode)) \ 893 ? FIRST_FP_PARM_REG \ 894 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 895 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\ 896 ? FIRST_FP_PARM_REG \ 897 : FIRST_PARM_REG) 898 899/* Define how to find the value returned by a function. 900 VALTYPE is the data type of the value (as a tree). 901 If the precise function being called is known, FUNC is its FUNCTION_DECL; 902 otherwise, FUNC is 0. 903 For the SH, this is like LIBCALL_VALUE, except that we must change the 904 mode like PROMOTE_MODE does. 905 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types 906 tested here has to be kept in sync with the one in explow.c:promote_mode. */ 907 908#define FUNCTION_VALUE(VALTYPE, FUNC) \ 909 gen_rtx (REG, \ 910 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \ 911 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \ 912 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \ 913 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \ 914 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \ 915 || TREE_CODE (VALTYPE) == CHAR_TYPE \ 916 || TREE_CODE (VALTYPE) == REAL_TYPE \ 917 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \ 918 ? SImode : TYPE_MODE (VALTYPE)), \ 919 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE))) 920 921/* Define how to find the value returned by a library function 922 assuming the value has mode MODE. */ 923#define LIBCALL_VALUE(MODE) \ 924 gen_rtx (REG, (MODE), BASE_RETURN_VALUE_REG (MODE)) 925 926/* 1 if N is a possible register number for a function value. */ 927#define FUNCTION_VALUE_REGNO_P(REGNO) \ 928 ((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG)) 929 930/* 1 if N is a possible register number for function argument passing. */ 931#define FUNCTION_ARG_REGNO_P(REGNO) \ 932 (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG + 4)) \ 933 || (TARGET_SH3E \ 934 && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG + 8))) 935 936/* Define a data type for recording info about an argument list 937 during the scan of that argument list. This data type should 938 hold all necessary information about the function itself 939 and about the args processed so far, enough to enable macros 940 such as FUNCTION_ARG to determine where the next arg should go. 941 942 On SH, this is a single integer, which is a number of words 943 of arguments scanned so far (including the invisible argument, 944 if any, which holds the structure-value-address). 945 Thus NARGREGS or more means all following args should go on the stack. */ 946 947enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 }; 948struct sh_args { 949 int arg_count[2]; 950}; 951 952#define CUMULATIVE_ARGS struct sh_args 953 954#define GET_SH_ARG_CLASS(MODE) \ 955 ((TARGET_SH3E && (MODE) == SFmode) \ 956 ? SH_ARG_FLOAT \ 957 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 958 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ 959 ? SH_ARG_FLOAT : SH_ARG_INT) 960 961#define ROUND_ADVANCE(SIZE) \ 962 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 963 964/* Round a register number up to a proper boundary for an arg of mode 965 MODE. 966 967 The SH doesn't care about double alignment, so we only 968 round doubles to even regs when asked to explicitly. */ 969 970#define ROUND_REG(CUM, MODE) \ 971 (((TARGET_ALIGN_DOUBLE \ 972 || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode) \ 973 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\ 974 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \ 975 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \ 976 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \ 977 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)]) 978 979/* Initialize a variable CUM of type CUMULATIVE_ARGS 980 for a call to a function whose data type is FNTYPE. 981 For a library call, FNTYPE is 0. 982 983 On SH, the offset always starts at 0: the first parm reg is always 984 the same reg for a given argument class. */ 985 986#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ 987 do { \ 988 (CUM).arg_count[(int) SH_ARG_INT] = 0; \ 989 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \ 990 } while (0) 991 992/* Update the data in CUM to advance over an argument 993 of mode MODE and data type TYPE. 994 (TYPE is null for libcalls where that information may not be 995 available.) */ 996 997#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 998 if (! TARGET_SH4 || PASS_IN_REG_P ((CUM), (MODE), (TYPE))) \ 999 ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \ 1000 = (ROUND_REG ((CUM), (MODE)) \ 1001 + ((MODE) == BLKmode \ 1002 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \ 1003 : ROUND_ADVANCE (GET_MODE_SIZE (MODE))))) 1004 1005/* Return boolean indicating arg of mode MODE will be passed in a reg. 1006 This macro is only used in this file. */ 1007 1008#define PASS_IN_REG_P(CUM, MODE, TYPE) \ 1009 (((TYPE) == 0 \ 1010 || (! TREE_ADDRESSABLE ((tree)(TYPE))) \ 1011 && (! TARGET_HITACHI || ! AGGREGATE_TYPE_P (TYPE))) \ 1012 && (TARGET_SH3E \ 1013 ? ((MODE) == BLKmode \ 1014 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \ 1015 + int_size_in_bytes (TYPE)) \ 1016 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \ 1017 : ((ROUND_REG((CUM), (MODE)) \ 1018 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \ 1019 <= NPARM_REGS (MODE))) \ 1020 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE))) 1021 1022/* Define where to put the arguments to a function. 1023 Value is zero to push the argument on the stack, 1024 or a hard register in which to store the argument. 1025 1026 MODE is the argument's machine mode. 1027 TYPE is the data type of the argument (as a tree). 1028 This is null for libcalls where that information may 1029 not be available. 1030 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1031 the preceding args and about the function being called. 1032 NAMED is nonzero if this argument is a named parameter 1033 (otherwise it is an extra parameter matching an ellipsis). 1034 1035 On SH the first args are normally in registers 1036 and the rest are pushed. Any arg that starts within the first 1037 NPARM_REGS words is at least partially passed in a register unless 1038 its data type forbids. */ 1039 1040extern int current_function_varargs; 1041 1042#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1043 ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ 1044 && ((NAMED) \ 1045 || (! TARGET_HITACHI && (TARGET_SH3E || ! current_function_varargs)))) \ 1046 ? gen_rtx (REG, (MODE), \ 1047 ((BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))) \ 1048 ^ ((MODE) == SFmode && TARGET_SH4 \ 1049 && TARGET_LITTLE_ENDIAN != 0))) \ 1050 : 0) 1051 1052#define PRETEND_OUTGOING_VARARGS_NAMED (! TARGET_HITACHI) 1053 1054/* For an arg passed partly in registers and partly in memory, 1055 this is the number of registers used. 1056 For args passed entirely in registers or entirely in memory, zero. 1057 1058 We sometimes split args. */ 1059 1060#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 1061 ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ 1062 && ! TARGET_SH4 \ 1063 && (ROUND_REG ((CUM), (MODE)) \ 1064 + ((MODE) != BLKmode \ 1065 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \ 1066 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \ 1067 - NPARM_REGS (MODE) > 0)) \ 1068 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \ 1069 : 0) 1070 1071extern int current_function_anonymous_args; 1072 1073/* Perform any needed actions needed for a function that is receiving a 1074 variable number of arguments. */ 1075 1076#define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \ 1077 current_function_anonymous_args = 1; 1078 1079/* Call the function profiler with a given profile label. 1080 We use two .aligns, so as to make sure that both the .long is aligned 1081 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes) 1082 from the trapa instruction. */ 1083 1084#define FUNCTION_PROFILER(STREAM,LABELNO) \ 1085{ \ 1086 fprintf((STREAM), "\t.align\t2\n"); \ 1087 fprintf((STREAM), "\ttrapa\t#33\n"); \ 1088 fprintf((STREAM), "\t.align\t2\n"); \ 1089 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \ 1090} 1091 1092/* Define this macro if the code for function profiling should come 1093 before the function prologue. Normally, the profiling code comes 1094 after. */ 1095 1096#define PROFILE_BEFORE_PROLOGUE 1097 1098/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1099 the stack pointer does not matter. The value is tested only in 1100 functions that have frame pointers. 1101 No definition is equivalent to always zero. */ 1102 1103#define EXIT_IGNORE_STACK 1 1104 1105/* Generate the assembly code for function exit 1106 Just dump out any accumulated constant table. */ 1107 1108#define FUNCTION_EPILOGUE(STREAM, SIZE) function_epilogue ((STREAM), (SIZE)) 1109 1110/* 1111 On the SH, the trampoline looks like 1112 2 0002 DD02 mov.l l2,r13 1113 1 0000 D301 mov.l l1,r3 1114 3 0004 4D2B jmp @r13 1115 4 0006 0009 nop 1116 5 0008 00000000 l1: .long function 1117 6 000c 00000000 l2: .long area */ 1118 1119/* Length in units of the trampoline for entering a nested function. */ 1120#define TRAMPOLINE_SIZE 16 1121 1122/* Alignment required for a trampoline in bits . */ 1123#define TRAMPOLINE_ALIGNMENT \ 1124 ((CACHE_LOG < 3 || TARGET_SMALLCODE && ! TARGET_HARWARD) ? 32 : 64) 1125 1126/* Emit RTL insns to initialize the variable parts of a trampoline. 1127 FNADDR is an RTX for the address of the function's pure code. 1128 CXT is an RTX for the static chain value for the function. */ 1129 1130#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1131{ \ 1132 emit_move_insn (gen_rtx (MEM, SImode, (TRAMP)), \ 1133 GEN_INT (TARGET_LITTLE_ENDIAN ? 0xd301dd02 : 0xdd02d301));\ 1134 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 4)), \ 1135 GEN_INT (TARGET_LITTLE_ENDIAN ? 0x00094d2b : 0x4d2b0009));\ 1136 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \ 1137 (CXT)); \ 1138 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \ 1139 (FNADDR)); \ 1140 if (TARGET_HARWARD) \ 1141 emit_insn (gen_ic_invalidate_line (TRAMP)); \ 1142} 1143 1144/* A C expression whose value is RTL representing the value of the return 1145 address for the frame COUNT steps up from the current frame. 1146 FRAMEADDR is already the frame pointer of the COUNT frame, so we 1147 can ignore COUNT. */ 1148 1149#define RETURN_ADDR_RTX(COUNT, FRAME) \ 1150 (((COUNT) == 0) \ 1151 ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM)) \ 1152 : (rtx) 0) 1153 1154/* Generate necessary RTL for __builtin_saveregs(). 1155 ARGLIST is the argument list; see expr.c. */ 1156extern struct rtx_def *sh_builtin_saveregs (); 1157#define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sh_builtin_saveregs (ARGLIST) 1158 1159/* Addressing modes, and classification of registers for them. */ 1160#define HAVE_POST_INCREMENT 1 1161/*#define HAVE_PRE_INCREMENT 1*/ 1162/*#define HAVE_POST_DECREMENT 1*/ 1163#define HAVE_PRE_DECREMENT 1 1164 1165#define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \ 1166 ? 0 : 1) 1167#define USE_LOAD_PRE_DECREMENT(mode) 0 1168#define USE_STORE_POST_INCREMENT(mode) 0 1169#define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \ 1170 ? 0 : 1) 1171 1172#define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \ 1173 < (TARGET_SMALLCODE ? 2 : \ 1174 ((ALIGN >= 4) ? 16 : 2))) 1175 1176/* Macros to check register numbers against specific register classes. */ 1177 1178/* These assume that REGNO is a hard or pseudo reg number. 1179 They give nonzero only if REGNO is a hard reg of the suitable class 1180 or a pseudo reg currently allocated to a suitable hard reg. 1181 Since they use reg_renumber, they are safe only once reg_renumber 1182 has been allocated, which happens in local-alloc.c. */ 1183 1184#define REGNO_OK_FOR_BASE_P(REGNO) \ 1185 ((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG) 1186#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1187 ((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0) 1188 1189/* Maximum number of registers that can appear in a valid memory 1190 address. */ 1191 1192#define MAX_REGS_PER_ADDRESS 2 1193 1194/* Recognize any constant value that is a valid address. */ 1195 1196#define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF) 1197 1198/* Nonzero if the constant value X is a legitimate general operand. */ 1199 1200#define LEGITIMATE_CONSTANT_P(X) \ 1201 (GET_CODE (X) != CONST_DOUBLE \ 1202 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \ 1203 || (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X)))) 1204 1205/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1206 and check its validity for a certain class. 1207 We have two alternate definitions for each of them. 1208 The usual definition accepts all pseudo regs; the other rejects 1209 them unless they have been allocated suitable hard regs. 1210 The symbol REG_OK_STRICT causes the latter definition to be used. */ 1211 1212#ifndef REG_OK_STRICT 1213 1214/* Nonzero if X is a hard reg that can be used as a base reg 1215 or if it is a pseudo reg. */ 1216#define REG_OK_FOR_BASE_P(X) \ 1217 (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1218 1219/* Nonzero if X is a hard reg that can be used as an index 1220 or if it is a pseudo reg. */ 1221#define REG_OK_FOR_INDEX_P(X) \ 1222 (REGNO (X) == 0 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1223 1224/* Nonzero if X/OFFSET is a hard reg that can be used as an index 1225 or if X is a pseudo reg. */ 1226#define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \ 1227 ((REGNO (X) == 0 && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1228 1229#else 1230 1231/* Nonzero if X is a hard reg that can be used as a base reg. */ 1232#define REG_OK_FOR_BASE_P(X) \ 1233 REGNO_OK_FOR_BASE_P (REGNO (X)) 1234 1235/* Nonzero if X is a hard reg that can be used as an index. */ 1236#define REG_OK_FOR_INDEX_P(X) \ 1237 REGNO_OK_FOR_INDEX_P (REGNO (X)) 1238 1239/* Nonzero if X/OFFSET is a hard reg that can be used as an index. */ 1240#define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \ 1241 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0) 1242 1243#endif 1244 1245/* The 'Q' constraint is a pc relative load operand. */ 1246#define EXTRA_CONSTRAINT_Q(OP) \ 1247 (GET_CODE (OP) == MEM && \ 1248 ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \ 1249 || (GET_CODE (XEXP ((OP), 0)) == CONST \ 1250 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \ 1251 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \ 1252 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT))) 1253 1254#define EXTRA_CONSTRAINT(OP, C) \ 1255 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \ 1256 : 0) 1257 1258/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1259 that is a valid memory address for an instruction. 1260 The MODE argument is the machine mode for the MEM expression 1261 that wants to use this address. 1262 1263 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ 1264 1265#define MODE_DISP_OK_4(X,MODE) \ 1266(GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \ 1267 && ! (INTVAL (X) & 3) && ! (TARGET_SH3E && (MODE) == SFmode)) 1268 1269#define MODE_DISP_OK_8(X,MODE) \ 1270((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \ 1271 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode)) 1272 1273#define BASE_REGISTER_RTX_P(X) \ 1274 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ 1275 || (GET_CODE (X) == SUBREG \ 1276 && GET_CODE (SUBREG_REG (X)) == REG \ 1277 && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) 1278 1279/* Since this must be r0, which is a single register class, we must check 1280 SUBREGs more carefully, to be sure that we don't accept one that extends 1281 outside the class. */ 1282#define INDEX_REGISTER_RTX_P(X) \ 1283 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ 1284 || (GET_CODE (X) == SUBREG \ 1285 && GET_CODE (SUBREG_REG (X)) == REG \ 1286 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_WORD (X)))) 1287 1288/* Jump to LABEL if X is a valid address RTX. This must also take 1289 REG_OK_STRICT into account when deciding about valid registers, but it uses 1290 the above macros so we are in luck. 1291 1292 Allow REG 1293 REG+disp 1294 REG+r0 1295 REG++ 1296 --REG */ 1297 1298/* ??? The SH3e does not have the REG+disp addressing mode when loading values 1299 into the FRx registers. We implement this by setting the maximum offset 1300 to zero when the value is SFmode. This also restricts loading of SFmode 1301 values into the integer registers, but that can't be helped. */ 1302 1303/* The SH allows a displacement in a QI or HI amode, but only when the 1304 other operand is R0. GCC doesn't handle this very well, so we forgo 1305 all of that. 1306 1307 A legitimate index for a QI or HI is 0, SI can be any number 0..63, 1308 DI can be any number 0..60. */ 1309 1310#define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \ 1311 do { \ 1312 if (GET_CODE (OP) == CONST_INT) \ 1313 { \ 1314 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \ 1315 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \ 1316 } \ 1317 } while(0) 1318 1319#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ 1320{ \ 1321 if (BASE_REGISTER_RTX_P (X)) \ 1322 goto LABEL; \ 1323 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ 1324 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \ 1325 goto LABEL; \ 1326 else if (GET_CODE (X) == PLUS \ 1327 && ((MODE) != PSImode || reload_completed)) \ 1328 { \ 1329 rtx xop0 = XEXP ((X), 0); \ 1330 rtx xop1 = XEXP ((X), 1); \ 1331 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \ 1332 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \ 1333 if (GET_MODE_SIZE (MODE) <= 4 \ 1334 || TARGET_SH4 && TARGET_FMOVD && MODE == DFmode) \ 1335 { \ 1336 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\ 1337 goto LABEL; \ 1338 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\ 1339 goto LABEL; \ 1340 } \ 1341 } \ 1342} 1343 1344/* Try machine-dependent ways of modifying an illegitimate address 1345 to be legitimate. If we find one, return the new, valid address. 1346 This macro is used in only one place: `memory_address' in explow.c. 1347 1348 OLDX is the address as it was before break_out_memory_refs was called. 1349 In some cases it is useful to look at this to decide what needs to be done. 1350 1351 MODE and WIN are passed so that this macro can use 1352 GO_IF_LEGITIMATE_ADDRESS. 1353 1354 It is always safe for this macro to do nothing. It exists to recognize 1355 opportunities to optimize the output. 1356 1357 For the SH, if X is almost suitable for indexing, but the offset is 1358 out of range, convert it into a normal form so that cse has a chance 1359 of reducing the number of address registers used. */ 1360 1361#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 1362{ \ 1363 if (GET_CODE (X) == PLUS \ 1364 && (GET_MODE_SIZE (MODE) == 4 \ 1365 || GET_MODE_SIZE (MODE) == 8) \ 1366 && GET_CODE (XEXP ((X), 1)) == CONST_INT \ 1367 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \ 1368 && ! (TARGET_SH4 && (MODE) == DFmode) \ 1369 && ! (TARGET_SH3E && (MODE) == SFmode)) \ 1370 { \ 1371 rtx index_rtx = XEXP ((X), 1); \ 1372 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \ 1373 rtx sum; \ 1374 \ 1375 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \ 1376 /* On rare occasions, we might get an unaligned pointer \ 1377 that is indexed in a way to give an aligned address. \ 1378 Therefore, keep the lower two bits in offset_base. */ \ 1379 /* Instead of offset_base 128..131 use 124..127, so that \ 1380 simple add suffices. */ \ 1381 if (offset > 127) \ 1382 { \ 1383 offset_base = ((offset + 4) & ~60) - 4; \ 1384 } \ 1385 else \ 1386 offset_base = offset & ~60; \ 1387 /* Sometimes the normal form does not suit DImode. We \ 1388 could avoid that by using smaller ranges, but that \ 1389 would give less optimized code when SImode is \ 1390 prevalent. */ \ 1391 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \ 1392 { \ 1393 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \ 1394 GEN_INT (offset_base), NULL_RTX, 0, \ 1395 OPTAB_LIB_WIDEN); \ 1396 \ 1397 (X) = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base)); \ 1398 goto WIN; \ 1399 } \ 1400 } \ 1401} 1402 1403/* A C compound statement that attempts to replace X, which is an address 1404 that needs reloading, with a valid memory address for an operand of 1405 mode MODE. WIN is a C statement label elsewhere in the code. 1406 1407 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form 1408 of the address. That will allow inheritance of the address reloads. */ 1409 1410#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 1411{ \ 1412 if (GET_CODE (X) == PLUS \ 1413 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \ 1414 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 1415 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \ 1416 && ! (TARGET_SH4 && (MODE) == DFmode) \ 1417 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \ 1418 { \ 1419 rtx index_rtx = XEXP (X, 1); \ 1420 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \ 1421 rtx sum; \ 1422 \ 1423 if (TARGET_SH3E && MODE == SFmode) \ 1424 { \ 1425 X = copy_rtx (X); \ 1426 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL_PTR, \ 1427 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \ 1428 (TYPE)); \ 1429 goto WIN; \ 1430 } \ 1431 /* Instead of offset_base 128..131 use 124..127, so that \ 1432 simple add suffices. */ \ 1433 if (offset > 127) \ 1434 { \ 1435 offset_base = ((offset + 4) & ~60) - 4; \ 1436 } \ 1437 else \ 1438 offset_base = offset & ~60; \ 1439 /* Sometimes the normal form does not suit DImode. We \ 1440 could avoid that by using smaller ranges, but that \ 1441 would give less optimized code when SImode is \ 1442 prevalent. */ \ 1443 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \ 1444 { \ 1445 sum = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ 1446 GEN_INT (offset_base)); \ 1447 X = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base));\ 1448 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL_PTR, \ 1449 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \ 1450 (TYPE)); \ 1451 goto WIN; \ 1452 } \ 1453 } \ 1454 /* We must re-recognize what we created before. */ \ 1455 else if (GET_CODE (X) == PLUS \ 1456 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \ 1457 && GET_CODE (XEXP (X, 0)) == PLUS \ 1458 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ 1459 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \ 1460 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 1461 && ! (TARGET_SH3E && MODE == SFmode)) \ 1462 { \ 1463 /* Because this address is so complex, we know it must have \ 1464 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \ 1465 it is already unshared, and needs no further unsharing. */ \ 1466 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL_PTR, \ 1467 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\ 1468 goto WIN; \ 1469 } \ 1470} 1471 1472/* Go to LABEL if ADDR (a legitimate address expression) 1473 has an effect that depends on the machine mode it is used for. 1474 1475 ??? Strictly speaking, we should also include all indexed addressing, 1476 because the index scale factor is the length of the operand. 1477 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to 1478 high if we did that. So we rely on reload to fix things up. */ 1479 1480#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 1481{ \ 1482 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \ 1483 goto LABEL; \ 1484} 1485 1486/* Specify the machine mode that this machine uses 1487 for the index in the tablejump instruction. */ 1488#define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode) 1489 1490#define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \ 1491((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \ 1492 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \ 1493 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \ 1494 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \ 1495 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \ 1496 : SImode) 1497 1498/* Define as C expression which evaluates to nonzero if the tablejump 1499 instruction expects the table to contain offsets from the address of the 1500 table. 1501 Do not define this if the table should contain absolute addresses. */ 1502#define CASE_VECTOR_PC_RELATIVE 1 1503 1504/* Specify the tree operation to be used to convert reals to integers. */ 1505#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR 1506 1507/* This is the kind of divide that is easiest to do in the general case. */ 1508#define EASY_DIV_EXPR TRUNC_DIV_EXPR 1509 1510/* Since the SH3e has only `float' support, it is desirable to make all 1511 floating point types equivalent to `float'. */ 1512#define DOUBLE_TYPE_SIZE ((TARGET_SH3E && ! TARGET_SH4) ? 32 : 64) 1513 1514/* 'char' is signed by default. */ 1515#define DEFAULT_SIGNED_CHAR 1 1516 1517/* The type of size_t unsigned int. */ 1518#define SIZE_TYPE "unsigned int" 1519 1520#define WCHAR_TYPE "short unsigned int" 1521#define WCHAR_TYPE_SIZE 16 1522 1523/* Don't cse the address of the function being compiled. */ 1524/*#define NO_RECURSIVE_FUNCTION_CSE 1*/ 1525 1526/* Max number of bytes we can move from memory to memory 1527 in one reasonably fast instruction. */ 1528#define MOVE_MAX 4 1529 1530/* Max number of bytes we want move_by_pieces to be able to copy 1531 efficiently. */ 1532#define MOVE_MAX_PIECES (TARGET_SH4 ? 8 : 4) 1533 1534/* Define if operations between registers always perform the operation 1535 on the full register even if a narrower mode is specified. */ 1536#define WORD_REGISTER_OPERATIONS 1537 1538/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1539 will either zero-extend or sign-extend. The value of this macro should 1540 be the code that says which one of the two operations is implicitly 1541 done, NIL if none. */ 1542#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND 1543 1544/* Define if loading short immediate values into registers sign extends. */ 1545#define SHORT_IMMEDIATES_SIGN_EXTEND 1546 1547/* Define this if zero-extension is slow (more than one real instruction). 1548 On the SH, it's only one instruction. */ 1549/* #define SLOW_ZERO_EXTEND */ 1550 1551/* Nonzero if access to memory by bytes is no faster than for words. */ 1552#define SLOW_BYTE_ACCESS 1 1553 1554/* Force sizeof(bool) == 1 to maintain binary compatibility; otherwise, the 1555 change in SLOW_BYTE_ACCESS would have changed it to 4. */ 1556 1557#define BOOL_TYPE_SIZE (flag_new_abi ? INT_TYPE_SIZE : CHAR_TYPE_SIZE) 1558 1559/* We assume that the store-condition-codes instructions store 0 for false 1560 and some other value for true. This is the value stored for true. */ 1561 1562#define STORE_FLAG_VALUE 1 1563 1564/* Immediate shift counts are truncated by the output routines (or was it 1565 the assembler?). Shift counts in a register are truncated by SH. Note 1566 that the native compiler puts too large (> 32) immediate shift counts 1567 into a register and shifts by the register, letting the SH decide what 1568 to do instead of doing that itself. */ 1569/* ??? The library routines in lib1funcs.asm truncate the shift count. 1570 However, the SH3 has hardware shifts that do not truncate exactly as gcc 1571 expects - the sign bit is significant - so it appears that we need to 1572 leave this zero for correct SH3 code. */ 1573#define SHIFT_COUNT_TRUNCATED (! TARGET_SH3) 1574 1575/* All integers have the same format so truncation is easy. */ 1576#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 1577 1578/* Define this if addresses of constant functions 1579 shouldn't be put through pseudo regs where they can be cse'd. 1580 Desirable on machines where ordinary constants are expensive 1581 but a CALL with constant address is cheap. */ 1582/*#define NO_FUNCTION_CSE 1*/ 1583 1584/* Chars and shorts should be passed as ints. */ 1585#define PROMOTE_PROTOTYPES 1 1586 1587/* The machine modes of pointers and functions. */ 1588#define Pmode SImode 1589#define FUNCTION_MODE Pmode 1590 1591/* The relative costs of various types of constants. Note that cse.c defines 1592 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */ 1593 1594#define CONST_COSTS(RTX, CODE, OUTER_CODE) \ 1595 case CONST_INT: \ 1596 if (INTVAL (RTX) == 0) \ 1597 return 0; \ 1598 else if (CONST_OK_FOR_I (INTVAL (RTX))) \ 1599 return 1; \ 1600 else if (((OUTER_CODE) == AND || (OUTER_CODE) == IOR || (OUTER_CODE) == XOR) \ 1601 && CONST_OK_FOR_L (INTVAL (RTX))) \ 1602 return 1; \ 1603 else \ 1604 return 8; \ 1605 case CONST: \ 1606 case LABEL_REF: \ 1607 case SYMBOL_REF: \ 1608 return 5; \ 1609 case CONST_DOUBLE: \ 1610 return 10; 1611 1612#define RTX_COSTS(X, CODE, OUTER_CODE) \ 1613 case PLUS: \ 1614 return (COSTS_N_INSNS (1) \ 1615 + rtx_cost (XEXP ((X), 0), PLUS) \ 1616 + (rtx_equal_p (XEXP ((X), 0), XEXP ((X), 1))\ 1617 ? 0 : rtx_cost (XEXP ((X), 1), PLUS)));\ 1618 case AND: \ 1619 return COSTS_N_INSNS (andcosts (X)); \ 1620 case MULT: \ 1621 return COSTS_N_INSNS (multcosts (X)); \ 1622 case ASHIFT: \ 1623 case ASHIFTRT: \ 1624 case LSHIFTRT: \ 1625 /* Add one extra unit for the matching constraint. \ 1626 Otherwise loop strength reduction would think that\ 1627 a shift with different sourc and destination is \ 1628 as cheap as adding a constant to a register. */ \ 1629 return (COSTS_N_INSNS (shiftcosts (X)) \ 1630 + rtx_cost (XEXP ((X), 0), (CODE)) \ 1631 + 1); \ 1632 case DIV: \ 1633 case UDIV: \ 1634 case MOD: \ 1635 case UMOD: \ 1636 return COSTS_N_INSNS (20); \ 1637 case FLOAT: \ 1638 case FIX: \ 1639 return 100; 1640 1641/* The multiply insn on the SH1 and the divide insns on the SH1 and SH2 1642 are actually function calls with some special constraints on arguments 1643 and register usage. 1644 1645 These macros tell reorg that the references to arguments and 1646 register clobbers for insns of type sfunc do not appear to happen 1647 until after the millicode call. This allows reorg to put insns 1648 which set the argument registers into the delay slot of the millicode 1649 call -- thus they act more like traditional CALL_INSNs. 1650 1651 get_attr_is_sfunc will try to recognize the given insn, so make sure to 1652 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns 1653 in particular. */ 1654 1655#define INSN_SETS_ARE_DELAYED(X) \ 1656 ((GET_CODE (X) == INSN \ 1657 && GET_CODE (PATTERN (X)) != SEQUENCE \ 1658 && GET_CODE (PATTERN (X)) != USE \ 1659 && GET_CODE (PATTERN (X)) != CLOBBER \ 1660 && get_attr_is_sfunc (X))) 1661 1662#define INSN_REFERENCES_ARE_DELAYED(X) \ 1663 ((GET_CODE (X) == INSN \ 1664 && GET_CODE (PATTERN (X)) != SEQUENCE \ 1665 && GET_CODE (PATTERN (X)) != USE \ 1666 && GET_CODE (PATTERN (X)) != CLOBBER \ 1667 && get_attr_is_sfunc (X))) 1668 1669/* Compute the cost of an address. For the SH, all valid addresses are 1670 the same cost. */ 1671/* ??? Perhaps we should make reg+reg addresses have higher cost because 1672 they add to register pressure on r0. */ 1673 1674#define ADDRESS_COST(RTX) 1 1675 1676/* Compute extra cost of moving data between one register class 1677 and another. */ 1678 1679/* Regclass always uses 2 for moves in the same register class; 1680 If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, 1681 it uses this information. Hence, the general register <-> floating point 1682 register information here is not used for SFmode. */ 1683#define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \ 1684 ((((DSTCLASS) == T_REGS) || ((DSTCLASS) == PR_REG)) ? 10 \ 1685 : ((((DSTCLASS) == FP0_REGS || (DSTCLASS) == FP_REGS || (DSTCLASS) == DF_REGS) \ 1686 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \ 1687 || (((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS) \ 1688 && ((SRCCLASS) == FP0_REGS || (SRCCLASS) == FP_REGS \ 1689 || (SRCCLASS) == DF_REGS))) \ 1690 ? TARGET_FMOVD ? 8 : 12 \ 1691 : (((DSTCLASS) == FPUL_REGS \ 1692 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \ 1693 || (SRCCLASS == FPUL_REGS \ 1694 && ((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS))) \ 1695 ? 5 \ 1696 : (((DSTCLASS) == FPUL_REGS \ 1697 && ((SRCCLASS) == PR_REGS || (SRCCLASS) == MAC_REGS)) \ 1698 || ((SRCCLASS) == FPUL_REGS \ 1699 && ((DSTCLASS) == PR_REGS || (DSTCLASS) == MAC_REGS))) \ 1700 ? 7 \ 1701 : 2) 1702 1703/* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This 1704 would be so that people would slow memory systems could generate 1705 different code that does fewer memory accesses. */ 1706 1707/* Assembler output control. */ 1708 1709/* A C string constant describing how to begin a comment in the target 1710 assembler language. The compiler assumes that the comment will end at 1711 the end of the line. */ 1712#define ASM_COMMENT_START "!" 1713 1714/* The text to go at the start of the assembler file. */ 1715#define ASM_FILE_START(STREAM) \ 1716 output_file_start (STREAM) 1717 1718#define ASM_FILE_END(STREAM) 1719 1720#define ASM_APP_ON "" 1721#define ASM_APP_OFF "" 1722#define FILE_ASM_OP "\t.file\n" 1723#define IDENT_ASM_OP "\t.ident\n" 1724#define SET_ASM_OP ".set" 1725 1726/* How to change between sections. */ 1727 1728#define TEXT_SECTION_ASM_OP "\t.text" 1729#define DATA_SECTION_ASM_OP "\t.data" 1730#define CTORS_SECTION_ASM_OP "\t.section\t.ctors\n" 1731#define DTORS_SECTION_ASM_OP "\t.section\t.dtors\n" 1732#define EXTRA_SECTIONS in_ctors, in_dtors 1733#define EXTRA_SECTION_FUNCTIONS \ 1734void \ 1735ctors_section() \ 1736{ \ 1737 if (in_section != in_ctors) \ 1738 { \ 1739 fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \ 1740 in_section = in_ctors; \ 1741 } \ 1742} \ 1743void \ 1744dtors_section() \ 1745{ \ 1746 if (in_section != in_dtors) \ 1747 { \ 1748 fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \ 1749 in_section = in_dtors; \ 1750 } \ 1751} 1752 1753/* Define this so that jump tables go in same section as the current function, 1754 which could be text or it could be a user defined section. */ 1755#define JUMP_TABLES_IN_TEXT_SECTION 1 1756 1757/* A C statement to output something to the assembler file to switch to section 1758 NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or 1759 NULL_TREE. Some target formats do not support arbitrary sections. Do not 1760 define this macro in such cases. */ 1761 1762#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \ 1763 do { fprintf (FILE, ".section\t%s\n", NAME); } while (0) 1764 1765#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ 1766 do { ctors_section(); asm_fprintf((FILE),"\t.long\t%U%s\n", (NAME)); } while (0) 1767 1768#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ 1769 do { dtors_section(); asm_fprintf((FILE),"\t.long\t%U%s\n", (NAME)); } while (0) 1770 1771#undef DO_GLOBAL_CTORS_BODY 1772 1773#define DO_GLOBAL_CTORS_BODY \ 1774{ \ 1775 typedef (*pfunc)(); \ 1776 extern pfunc __ctors[]; \ 1777 extern pfunc __ctors_end[]; \ 1778 pfunc *p; \ 1779 for (p = __ctors_end; p > __ctors; ) \ 1780 { \ 1781 (*--p)(); \ 1782 } \ 1783} 1784 1785#undef DO_GLOBAL_DTORS_BODY 1786#define DO_GLOBAL_DTORS_BODY \ 1787{ \ 1788 typedef (*pfunc)(); \ 1789 extern pfunc __dtors[]; \ 1790 extern pfunc __dtors_end[]; \ 1791 pfunc *p; \ 1792 for (p = __dtors; p < __dtors_end; p++) \ 1793 { \ 1794 (*p)(); \ 1795 } \ 1796} 1797 1798#define ASM_OUTPUT_REG_PUSH(file, v) \ 1799 fprintf ((file), "\tmov.l\tr%s,-@r15\n", (v)); 1800 1801#define ASM_OUTPUT_REG_POP(file, v) \ 1802 fprintf ((file), "\tmov.l\t@r15+,r%s\n", (v)); 1803 1804/* The assembler's names for the registers. RFP need not always be used as 1805 the Real framepointer; it can also be used as a normal general register. 1806 Note that the name `fp' is horribly misleading since `fp' is in fact only 1807 the argument-and-return-context pointer. */ 1808 1809extern char fp_reg_names[][5]; 1810 1811#define REGISTER_NAMES \ 1812{ \ 1813 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 1814 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 1815 "ap", "pr", "t", "gbr", "mach","macl", fp_reg_names[16], "rap", \ 1816 fp_reg_names[0], fp_reg_names[1] , fp_reg_names[2], fp_reg_names[3], \ 1817 fp_reg_names[4], fp_reg_names[5], fp_reg_names[6], fp_reg_names[7], \ 1818 fp_reg_names[8], fp_reg_names[9], fp_reg_names[10], fp_reg_names[11], \ 1819 fp_reg_names[12], fp_reg_names[13], fp_reg_names[14], fp_reg_names[15], \ 1820 fp_reg_names[17], fp_reg_names[18], fp_reg_names[19], fp_reg_names[20], \ 1821 fp_reg_names[21], fp_reg_names[22], fp_reg_names[23], fp_reg_names[24], \ 1822 "fpscr", \ 1823} 1824 1825#define DEBUG_REGISTER_NAMES \ 1826{ \ 1827 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 1828 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 1829 "ap", "pr", "t", "gbr", "mach","macl", "fpul","rap", \ 1830 "fr0","fr1","fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \ 1831 "fr8","fr9","fr10","fr11","fr12","fr13","fr14","fr15",\ 1832 "xd0","xd2","xd4", "xd6", "xd8", "xd10","xd12","xd14", \ 1833 "fpscr", \ 1834} 1835 1836/* DBX register number for a given compiler register number. */ 1837/* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers 1838 to match gdb. */ 1839#define DBX_REGISTER_NUMBER(REGNO) \ 1840 (((REGNO) >= 22 && (REGNO) <= 39) ? ((REGNO) + 1) : (REGNO)) 1841 1842/* Output a label definition. */ 1843#define ASM_OUTPUT_LABEL(FILE,NAME) \ 1844 do { assemble_name ((FILE), (NAME)); fputs (":\n", (FILE)); } while (0) 1845 1846/* This is how to output an assembler line 1847 that says to advance the location counter 1848 to a multiple of 2**LOG bytes. */ 1849 1850#define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1851 if ((LOG) != 0) \ 1852 fprintf ((FILE), "\t.align %d\n", (LOG)) 1853 1854/* Output a function label definition. */ 1855#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \ 1856 ASM_OUTPUT_LABEL((STREAM), (NAME)) 1857 1858/* Output a globalising directive for a label. */ 1859#define ASM_GLOBALIZE_LABEL(STREAM,NAME) \ 1860 (fprintf ((STREAM), "\t.global\t"), \ 1861 assemble_name ((STREAM), (NAME)), \ 1862 fputc ('\n', (STREAM))) 1863 1864/* The prefix to add to user-visible assembler symbols. */ 1865 1866#define USER_LABEL_PREFIX "_" 1867 1868/* The prefix to add to an internally generated label. */ 1869 1870#define LOCAL_LABEL_PREFIX "" 1871 1872/* Make an internal label into a string. */ 1873#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ 1874 sprintf ((STRING), "*%s%s%d", LOCAL_LABEL_PREFIX, (PREFIX), (NUM)) 1875 1876/* Output an internal label definition. */ 1877#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ 1878 asm_fprintf ((FILE), "%L%s%d:\n", (PREFIX), (NUM)) 1879 1880/* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */ 1881 1882/* Construct a private name. */ 1883#define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \ 1884 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \ 1885 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER))) 1886 1887/* Output a relative address table. */ 1888 1889#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \ 1890 switch (GET_MODE (BODY)) \ 1891 { \ 1892 case SImode: \ 1893 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \ 1894 break; \ 1895 case HImode: \ 1896 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \ 1897 break; \ 1898 case QImode: \ 1899 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \ 1900 break; \ 1901 } 1902 1903/* Output an absolute table element. */ 1904 1905#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ 1906 if (TARGET_BIGTABLE) \ 1907 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \ 1908 else \ 1909 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE)); \ 1910 1911/* Output various types of constants. */ 1912 1913/* This is how to output an assembler line defining a `double'. */ 1914 1915#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ 1916do { char dstr[30]; \ 1917 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \ 1918 fprintf ((FILE), "\t.double %s\n", dstr); \ 1919 } while (0) 1920 1921/* This is how to output an assembler line defining a `float' constant. */ 1922#define ASM_OUTPUT_FLOAT(FILE,VALUE) \ 1923do { char dstr[30]; \ 1924 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \ 1925 fprintf ((FILE), "\t.float %s\n", dstr); \ 1926 } while (0) 1927 1928#define ASM_OUTPUT_INT(STREAM, EXP) \ 1929 (fprintf ((STREAM), "\t.long\t"), \ 1930 output_addr_const ((STREAM), (EXP)), \ 1931 fputc ('\n', (STREAM))) 1932 1933#define ASM_OUTPUT_SHORT(STREAM, EXP) \ 1934 (fprintf ((STREAM), "\t.short\t"), \ 1935 output_addr_const ((STREAM), (EXP)), \ 1936 fputc ('\n', (STREAM))) 1937 1938#define ASM_OUTPUT_CHAR(STREAM, EXP) \ 1939 (fprintf ((STREAM), "\t.byte\t"), \ 1940 output_addr_const ((STREAM), (EXP)), \ 1941 fputc ('\n', (STREAM))) 1942 1943#define ASM_OUTPUT_BYTE(STREAM, VALUE) \ 1944 fprintf ((STREAM), "\t.byte\t%d\n", (VALUE)) \ 1945 1946/* The next two are used for debug info when compiling with -gdwarf. */ 1947#define UNALIGNED_SHORT_ASM_OP ".uaword" 1948#define UNALIGNED_INT_ASM_OP ".ualong" 1949 1950/* Loop alignment is now done in machine_dependent_reorg, so that 1951 branch shortening can know about it. */ 1952 1953/* This is how to output an assembler line 1954 that says to advance the location counter by SIZE bytes. */ 1955 1956#define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1957 fprintf ((FILE), "\t.space %d\n", (SIZE)) 1958 1959/* This says how to output an assembler line 1960 to define a global common symbol. */ 1961 1962#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1963( fputs ("\t.comm ", (FILE)), \ 1964 assemble_name ((FILE), (NAME)), \ 1965 fprintf ((FILE), ",%d\n", (SIZE))) 1966 1967/* This says how to output an assembler line 1968 to define a local common symbol. */ 1969 1970#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 1971( fputs ("\t.lcomm ", (FILE)), \ 1972 assemble_name ((FILE), (NAME)), \ 1973 fprintf ((FILE), ",%d\n", (SIZE))) 1974 1975/* The assembler's parentheses characters. */ 1976#define ASM_OPEN_PAREN "(" 1977#define ASM_CLOSE_PAREN ")" 1978 1979/* Target characters. */ 1980#define TARGET_BELL 007 1981#define TARGET_BS 010 1982#define TARGET_TAB 011 1983#define TARGET_NEWLINE 012 1984#define TARGET_VT 013 1985#define TARGET_FF 014 1986#define TARGET_CR 015 1987 1988/* A C statement to be executed just prior to the output of 1989 assembler code for INSN, to modify the extracted operands so 1990 they will be output differently. 1991 1992 Here the argument OPVEC is the vector containing the operands 1993 extracted from INSN, and NOPERANDS is the number of elements of 1994 the vector which contain meaningful data for this insn. 1995 The contents of this vector are what will be used to convert the insn 1996 template into assembler code, so you can change the assembler output 1997 by changing the contents of the vector. */ 1998 1999#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2000 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS)) 2001 2002/* Print operand X (an rtx) in assembler syntax to file FILE. 2003 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2004 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2005 2006#define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE)) 2007 2008/* Print a memory address as an operand to reference that memory location. */ 2009 2010#define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X)) 2011 2012#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 2013 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \ 2014 || (CHAR) == '$') 2015 2016extern struct rtx_def *sh_compare_op0; 2017extern struct rtx_def *sh_compare_op1; 2018extern struct rtx_def *prepare_scc_operands(); 2019 2020/* Which processor to schedule for. The elements of the enumeration must 2021 match exactly the cpu attribute in the sh.md file. */ 2022 2023enum processor_type { 2024 PROCESSOR_SH1, 2025 PROCESSOR_SH2, 2026 PROCESSOR_SH3, 2027 PROCESSOR_SH3E, 2028 PROCESSOR_SH4 2029}; 2030 2031#define sh_cpu_attr ((enum attr_cpu)sh_cpu) 2032extern enum processor_type sh_cpu; 2033 2034extern enum machine_mode sh_addr_diff_vec_mode; 2035 2036extern int optimize; /* needed for gen_casesi. */ 2037 2038/* Declare functions defined in sh.c and used in templates. */ 2039 2040extern char *output_branch(); 2041extern char *output_ieee_ccmpeq(); 2042extern char *output_branchy_insn(); 2043extern char *output_shift(); 2044extern char *output_movedouble(); 2045extern char *output_movepcrel(); 2046extern char *output_jump_label_table(); 2047extern char *output_far_jump(); 2048 2049enum mdep_reorg_phase_e 2050{ 2051 SH_BEFORE_MDEP_REORG, 2052 SH_INSERT_USES_LABELS, 2053 SH_SHORTEN_BRANCHES0, 2054 SH_FIXUP_PCLOAD, 2055 SH_SHORTEN_BRANCHES1, 2056 SH_AFTER_MDEP_REORG 2057}; 2058 2059extern enum mdep_reorg_phase_e mdep_reorg_phase; 2060 2061void machine_dependent_reorg (); 2062struct rtx_def *sfunc_uses_reg (); 2063int barrier_align (); 2064 2065#define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X) 2066 2067/* Generate calls to memcpy, memcmp and memset. */ 2068 2069#define TARGET_MEM_FUNCTIONS 2070 2071/* Define this macro if you want to implement any pragmas. If defined, it 2072 is a C expression whose value is 1 if the pragma was handled by the 2073 macro, zero otherwise. */ 2074#define HANDLE_PRAGMA(GETC, UNGETC, NODE) sh_handle_pragma (GETC, UNGETC, NODE) 2075extern int sh_handle_pragma (); 2076 2077/* Set when processing a function with pragma interrupt turned on. */ 2078 2079extern int pragma_interrupt; 2080 2081/* Set to an RTX containing the address of the stack to switch to 2082 for interrupt functions. */ 2083extern struct rtx_def *sp_switch; 2084 2085/* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS 2086 is a valid machine specific attribute for DECL. 2087 The attributes in ATTRIBUTES have previously been assigned to DECL. */ 2088extern int sh_valid_machine_decl_attribute (); 2089#define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) \ 2090sh_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS) 2091 2092extern void sh_pragma_insert_attributes (); 2093#define PRAGMA_INSERT_ATTRIBUTES(node, pattr, prefix_attr) \ 2094 sh_pragma_insert_attributes (node, pattr, prefix_attr) 2095 2096extern int sh_flag_remove_dead_before_cse; 2097extern int rtx_equal_function_value_matters; 2098extern struct rtx_def *fpscr_rtx; 2099extern struct rtx_def *get_fpscr_rtx (); 2100 2101 2102/* Instructions with unfilled delay slots take up an extra two bytes for 2103 the nop in the delay slot. */ 2104 2105#define ADJUST_INSN_LENGTH(X, LENGTH) \ 2106 if (((GET_CODE (X) == INSN \ 2107 && GET_CODE (PATTERN (X)) != USE \ 2108 && GET_CODE (PATTERN (X)) != CLOBBER) \ 2109 || GET_CODE (X) == CALL_INSN \ 2110 || (GET_CODE (X) == JUMP_INSN \ 2111 && GET_CODE (PATTERN (X)) != ADDR_DIFF_VEC \ 2112 && GET_CODE (PATTERN (X)) != ADDR_VEC)) \ 2113 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (X)))) != SEQUENCE \ 2114 && get_attr_needs_delay_slot (X) == NEEDS_DELAY_SLOT_YES) \ 2115 (LENGTH) += 2; 2116 2117/* Define the codes that are matched by predicates in sh.c. */ 2118#define PREDICATE_CODES \ 2119 {"arith_operand", {SUBREG, REG, CONST_INT}}, \ 2120 {"arith_reg_operand", {SUBREG, REG}}, \ 2121 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \ 2122 {"binary_float_operator", {PLUS, MULT}}, \ 2123 {"commutative_float_operator", {PLUS, MULT}}, \ 2124 {"fp_arith_reg_operand", {SUBREG, REG}}, \ 2125 {"fp_extended_operand", {SUBREG, REG, FLOAT_EXTEND}}, \ 2126 {"fpscr_operand", {REG}}, \ 2127 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, MEM}}, \ 2128 {"general_movdst_operand", {SUBREG, REG, CONST_INT, MEM}}, \ 2129 {"logical_operand", {SUBREG, REG, CONST_INT}}, \ 2130 {"noncommutative_float_operator", {MINUS, DIV}}, \ 2131 {"register_operand", {SUBREG, REG}}, 2132 2133/* Define this macro if it is advisable to hold scalars in registers 2134 in a wider mode than that declared by the program. In such cases, 2135 the value is constrained to be within the bounds of the declared 2136 type, but kept valid in the wider mode. The signedness of the 2137 extension may differ from that of the type. 2138 2139 Leaving the unsignedp unchanged gives better code than always setting it 2140 to 0. This is despite the fact that we have only signed char and short 2141 load instructions. */ 2142#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 2143 if (GET_MODE_CLASS (MODE) == MODE_INT \ 2144 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 2145 (MODE) = SImode; 2146 2147/* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign 2148 extensions applied to char/short functions arguments. Defining 2149 PROMOTE_FUNCTION_RETURN does the same for function returns. */ 2150 2151#define PROMOTE_FUNCTION_ARGS 2152#define PROMOTE_FUNCTION_RETURN 2153 2154/* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing 2155 and poping arguments. However, we do have push/pop instructions, and 2156 rather limited offsets (4 bits) in load/store instructions, so it isn't 2157 clear if this would give better code. If implemented, should check for 2158 compatibility problems. */ 2159 2160/* A C statement (sans semicolon) to update the integer variable COST 2161 based on the relationship between INSN that is dependent on 2162 DEP_INSN through the dependence LINK. The default is to make no 2163 adjustment to COST. This can be used for example to specify to 2164 the scheduler that an output- or anti-dependence does not incur 2165 the same cost as a data-dependence. */ 2166 2167#define ADJUST_COST(insn,link,dep_insn,cost) \ 2168do { \ 2169 rtx reg; \ 2170 \ 2171 if (GET_CODE(insn) == CALL_INSN) \ 2172 { \ 2173 /* The only input for a call that is timing-critical is the \ 2174 function's address. */ \ 2175 rtx call = PATTERN (insn); \ 2176 \ 2177 if (GET_CODE (call) == PARALLEL) \ 2178 call = XVECEXP (call, 0 ,0); \ 2179 if (GET_CODE (call) == SET) \ 2180 call = SET_SRC (call); \ 2181 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM \ 2182 && ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)) \ 2183 (cost) = 0; \ 2184 } \ 2185 /* All sfunc calls are parallels with at least four components. \ 2186 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */ \ 2187 else if (GET_CODE (PATTERN (insn)) == PARALLEL \ 2188 && XVECLEN (PATTERN (insn), 0) >= 4 \ 2189 && (reg = sfunc_uses_reg (insn))) \ 2190 { \ 2191 /* Likewise, the most timing critical input for an sfuncs call \ 2192 is the function address. However, sfuncs typically start \ 2193 using their arguments pretty quickly. \ 2194 Assume a four cycle delay before they are needed. */ \ 2195 if (! reg_set_p (reg, dep_insn)) \ 2196 cost -= TARGET_SUPERSCALAR ? 40 : 4; \ 2197 } \ 2198 /* Adjust load_si / pcload_si type insns latency. Use the known \ 2199 nominal latency and form of the insn to speed up the check. */ \ 2200 else if (cost == 3 \ 2201 && GET_CODE (PATTERN (dep_insn)) == SET \ 2202 /* Latency for dmpy type insns is also 3, so check the that \ 2203 it's actually a move insn. */ \ 2204 && general_movsrc_operand (SET_SRC (PATTERN (dep_insn)), SImode))\ 2205 cost = 2; \ 2206 else if (cost == 30 \ 2207 && GET_CODE (PATTERN (dep_insn)) == SET \ 2208 && GET_MODE (SET_SRC (PATTERN (dep_insn))) == SImode) \ 2209 cost = 20; \ 2210} while (0) \ 2211 2212/* For the sake of libgcc2.c, indicate target supports atexit. */ 2213#define HAVE_ATEXIT 2214 2215#define SH_DYNAMIC_SHIFT_COST \ 2216 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20) 2217