1/* Subroutines used for code generation on intel 80960. 2 Copyright (C) 1992, 1995, 1996, 1997, 1998 Free Software Foundation, Inc. 3 Contributed by Steven McGeady, Intel Corp. 4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson 5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support. 6 7This file is part of GNU CC. 8 9GNU CC is free software; you can redistribute it and/or modify 10it under the terms of the GNU General Public License as published by 11the Free Software Foundation; either version 2, or (at your option) 12any later version. 13 14GNU CC is distributed in the hope that it will be useful, 15but WITHOUT ANY WARRANTY; without even the implied warranty of 16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17GNU General Public License for more details. 18 19You should have received a copy of the GNU General Public License 20along with GNU CC; see the file COPYING. If not, write to 21the Free Software Foundation, 59 Temple Place - Suite 330, 22Boston, MA 02111-1307, USA. */ 23 24#include "config.h" 25#include <stdio.h> 26#include "rtl.h" 27#include "regs.h" 28#include "hard-reg-set.h" 29#include "real.h" 30#include "insn-config.h" 31#include "conditions.h" 32#include "insn-flags.h" 33#include "output.h" 34#include "insn-attr.h" 35#include "flags.h" 36#include "tree.h" 37#include "insn-codes.h" 38#include "expr.h" 39#include "except.h" 40#include "function.h" 41#include "recog.h" 42#include <math.h> 43 44/* Save the operands last given to a compare for use when we 45 generate a scc or bcc insn. */ 46 47rtx i960_compare_op0, i960_compare_op1; 48 49/* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS 50 macro in i960.h. */ 51 52static int i960_maxbitalignment; 53static int i960_last_maxbitalignment; 54 55/* Used to implement switching between MEM and ALU insn types, for better 56 C series performance. */ 57 58enum insn_types i960_last_insn_type; 59 60/* The leaf-procedure return register. Set only if this is a leaf routine. */ 61 62static int i960_leaf_ret_reg; 63 64/* True if replacing tail calls with jumps is OK. */ 65 66static int tail_call_ok; 67 68/* A string containing a list of insns to emit in the epilogue so as to 69 restore all registers saved by the prologue. Created by the prologue 70 code as it saves registers away. */ 71 72char epilogue_string[1000]; 73 74/* A unique number (per function) for return labels. */ 75 76static int ret_label = 0; 77 78/* This is true if FNDECL is either a varargs or a stdarg function. 79 This is used to help identify functions that use an argument block. */ 80 81#define VARARGS_STDARG_FUNCTION(FNDECL) \ 82((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \ 83 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \ 84 || current_function_varargs) 85 86/* Handle pragmas for compatibility with Intel's compilers. */ 87 88/* ??? This is incomplete, since it does not handle all pragmas that the 89 intel compilers understand. */ 90 91int 92process_pragma (p_getc, p_ungetc, pname) 93 int (* p_getc) PROTO ((void)); 94 void (* p_ungetc) PROTO ((int)); 95 char * pname; 96{ 97 int i; 98 register int c; 99 char buf[20]; 100 char *s = buf; 101 int align; 102 103 /* Should be pragma 'far' or equivalent for callx/balx here. */ 104 if (strcmp (pname, "align") != 0) 105 return 0; 106 107 do 108 { 109 c = p_getc (); 110 } 111 while (c == ' ' || c == '\t'); 112 113 if (c == '(') 114 c = p_getc (); 115 116 while (c >= '0' && c <= '9') 117 { 118 if (s < buf + sizeof buf - 1) 119 *s++ = c; 120 c = p_getc (); 121 } 122 123 *s = '\0'; 124 125 /* We had to read a non-numerical character to get out of the 126 while loop---often a newline. So, we have to put it back to 127 make sure we continue to parse everything properly. */ 128 129 p_ungetc (c); 130 131 align = atoi (buf); 132 133 switch (align) 134 { 135 case 0: 136 /* Return to last alignment. */ 137 align = i960_last_maxbitalignment / 8; 138 /* Fall through. */ 139 case 16: 140 case 8: 141 case 4: 142 case 2: 143 case 1: 144 i960_last_maxbitalignment = i960_maxbitalignment; 145 i960_maxbitalignment = align * 8; 146 break; 147 148 default: 149 /* Silently ignore bad values. */ 150 break; 151 } 152 153 /* NOTE: ic960 R3.0 pragma align definition: 154 155 #pragma align [(size)] | (identifier=size[,...]) 156 #pragma noalign [(identifier)[,...]] 157 158 (all parens are optional) 159 160 - size is [1,2,4,8,16] 161 - noalign means size==1 162 - applies only to component elements of a struct (and union?) 163 - identifier applies to structure tag (only) 164 - missing identifier means next struct 165 166 - alignment rules for bitfields need more investigation */ 167 168 return 1; 169} 170 171/* Initialize variables before compiling any files. */ 172 173void 174i960_initialize () 175{ 176 if (TARGET_IC_COMPAT2_0) 177 { 178 i960_maxbitalignment = 8; 179 i960_last_maxbitalignment = 128; 180 } 181 else 182 { 183 i960_maxbitalignment = 128; 184 i960_last_maxbitalignment = 8; 185 } 186} 187 188/* Return true if OP can be used as the source of an fp move insn. */ 189 190int 191fpmove_src_operand (op, mode) 192 rtx op; 193 enum machine_mode mode; 194{ 195 return (GET_CODE (op) == CONST_DOUBLE || general_operand (op, mode)); 196} 197 198#if 0 199/* Return true if OP is a register or zero. */ 200 201int 202reg_or_zero_operand (op, mode) 203 rtx op; 204 enum machine_mode mode; 205{ 206 return register_operand (op, mode) || op == const0_rtx; 207} 208#endif 209 210/* Return truth value of whether OP can be used as an operands in a three 211 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */ 212 213int 214arith_operand (op, mode) 215 rtx op; 216 enum machine_mode mode; 217{ 218 return (register_operand (op, mode) || literal (op, mode)); 219} 220 221/* Return truth value of whether OP can be used as an operands in a three 222 address logic insn, possibly complementing OP, of mode MODE. */ 223 224int 225logic_operand (op, mode) 226 rtx op; 227 enum machine_mode mode; 228{ 229 return (register_operand (op, mode) 230 || (GET_CODE (op) == CONST_INT 231 && INTVAL(op) >= -32 && INTVAL(op) < 32)); 232} 233 234/* Return true if OP is a register or a valid floating point literal. */ 235 236int 237fp_arith_operand (op, mode) 238 rtx op; 239 enum machine_mode mode; 240{ 241 return (register_operand (op, mode) || fp_literal (op, mode)); 242} 243 244/* Return true is OP is a register or a valid signed integer literal. */ 245 246int 247signed_arith_operand (op, mode) 248 rtx op; 249 enum machine_mode mode; 250{ 251 return (register_operand (op, mode) || signed_literal (op, mode)); 252} 253 254/* Return truth value of whether OP is a integer which fits the 255 range constraining immediate operands in three-address insns. */ 256 257int 258literal (op, mode) 259 rtx op; 260 enum machine_mode mode; 261{ 262 return ((GET_CODE (op) == CONST_INT) && INTVAL(op) >= 0 && INTVAL(op) < 32); 263} 264 265/* Return true if OP is a float constant of 1. */ 266 267int 268fp_literal_one (op, mode) 269 rtx op; 270 enum machine_mode mode; 271{ 272 return (TARGET_NUMERICS && mode == GET_MODE (op) && op == CONST1_RTX (mode)); 273} 274 275/* Return true if OP is a float constant of 0. */ 276 277int 278fp_literal_zero (op, mode) 279 rtx op; 280 enum machine_mode mode; 281{ 282 return (TARGET_NUMERICS && mode == GET_MODE (op) && op == CONST0_RTX (mode)); 283} 284 285/* Return true if OP is a valid floating point literal. */ 286 287int 288fp_literal(op, mode) 289 rtx op; 290 enum machine_mode mode; 291{ 292 return fp_literal_zero (op, mode) || fp_literal_one (op, mode); 293} 294 295/* Return true if OP is a valid signed immediate constant. */ 296 297int 298signed_literal(op, mode) 299 rtx op; 300 enum machine_mode mode; 301{ 302 return ((GET_CODE (op) == CONST_INT) && INTVAL(op) > -32 && INTVAL(op) < 32); 303} 304 305/* Return truth value of statement that OP is a symbolic memory 306 operand of mode MODE. */ 307 308int 309symbolic_memory_operand (op, mode) 310 rtx op; 311 enum machine_mode mode; 312{ 313 if (GET_CODE (op) == SUBREG) 314 op = SUBREG_REG (op); 315 if (GET_CODE (op) != MEM) 316 return 0; 317 op = XEXP (op, 0); 318 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST 319 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF); 320} 321 322/* Return truth value of whether OP is EQ or NE. */ 323 324int 325eq_or_neq (op, mode) 326 rtx op; 327 enum machine_mode mode; 328{ 329 return (GET_CODE (op) == EQ || GET_CODE (op) == NE); 330} 331 332/* OP is an integer register or a constant. */ 333 334int 335arith32_operand (op, mode) 336 rtx op; 337 enum machine_mode mode; 338{ 339 if (register_operand (op, mode)) 340 return 1; 341 return (CONSTANT_P (op)); 342} 343 344/* Return true if OP is an integer constant which is a power of 2. */ 345 346int 347power2_operand (op,mode) 348 rtx op; 349 enum machine_mode mode; 350{ 351 if (GET_CODE (op) != CONST_INT) 352 return 0; 353 354 return exact_log2 (INTVAL (op)) >= 0; 355} 356 357/* Return true if OP is an integer constant which is the complement of a 358 power of 2. */ 359 360int 361cmplpower2_operand (op, mode) 362 rtx op; 363 enum machine_mode mode; 364{ 365 if (GET_CODE (op) != CONST_INT) 366 return 0; 367 368 return exact_log2 (~ INTVAL (op)) >= 0; 369} 370 371/* If VAL has only one bit set, return the index of that bit. Otherwise 372 return -1. */ 373 374int 375bitpos (val) 376 unsigned int val; 377{ 378 register int i; 379 380 for (i = 0; val != 0; i++, val >>= 1) 381 { 382 if (val & 1) 383 { 384 if (val != 1) 385 return -1; 386 return i; 387 } 388 } 389 return -1; 390} 391 392/* Return non-zero if OP is a mask, i.e. all one bits are consecutive. 393 The return value indicates how many consecutive non-zero bits exist 394 if this is a mask. This is the same as the next function, except that 395 it does not indicate what the start and stop bit positions are. */ 396 397int 398is_mask (val) 399 unsigned int val; 400{ 401 register int start, end, i; 402 403 start = -1; 404 for (i = 0; val != 0; val >>= 1, i++) 405 { 406 if (val & 1) 407 { 408 if (start < 0) 409 start = i; 410 411 end = i; 412 continue; 413 } 414 /* Still looking for the first bit. */ 415 if (start < 0) 416 continue; 417 418 /* We've seen the start of a bit sequence, and now a zero. There 419 must be more one bits, otherwise we would have exited the loop. 420 Therefore, it is not a mask. */ 421 if (val) 422 return 0; 423 } 424 425 /* The bit string has ones from START to END bit positions only. */ 426 return end - start + 1; 427} 428 429/* If VAL is a mask, then return nonzero, with S set to the starting bit 430 position and E set to the ending bit position of the mask. The return 431 value indicates how many consecutive bits exist in the mask. This is 432 the same as the previous function, except that it also indicates the 433 start and end bit positions of the mask. */ 434 435int 436bitstr (val, s, e) 437 unsigned int val; 438 int *s, *e; 439{ 440 register int start, end, i; 441 442 start = -1; 443 end = -1; 444 for (i = 0; val != 0; val >>= 1, i++) 445 { 446 if (val & 1) 447 { 448 if (start < 0) 449 start = i; 450 451 end = i; 452 continue; 453 } 454 455 /* Still looking for the first bit. */ 456 if (start < 0) 457 continue; 458 459 /* We've seen the start of a bit sequence, and now a zero. There 460 must be more one bits, otherwise we would have exited the loop. 461 Therefor, it is not a mask. */ 462 if (val) 463 { 464 start = -1; 465 end = -1; 466 break; 467 } 468 } 469 470 /* The bit string has ones from START to END bit positions only. */ 471 *s = start; 472 *e = end; 473 return ((start < 0) ? 0 : end - start + 1); 474} 475 476/* Return the machine mode to use for a comparison. */ 477 478enum machine_mode 479select_cc_mode (op, x) 480 RTX_CODE op; 481 rtx x; 482{ 483 if (op == GTU || op == LTU || op == GEU || op == LEU) 484 return CC_UNSmode; 485 return CCmode; 486} 487 488/* X and Y are two things to compare using CODE. Emit the compare insn and 489 return the rtx for register 36 in the proper mode. */ 490 491rtx 492gen_compare_reg (code, x, y) 493 enum rtx_code code; 494 rtx x, y; 495{ 496 rtx cc_reg; 497 enum machine_mode ccmode = SELECT_CC_MODE (code, x, y); 498 enum machine_mode mode 499 = GET_MODE (x) == VOIDmode ? GET_MODE (y) : GET_MODE (x); 500 501 if (mode == SImode) 502 { 503 if (! arith_operand (x, mode)) 504 x = force_reg (SImode, x); 505 if (! arith_operand (y, mode)) 506 y = force_reg (SImode, y); 507 } 508 509 cc_reg = gen_rtx (REG, ccmode, 36); 510 emit_insn (gen_rtx (SET, VOIDmode, cc_reg, 511 gen_rtx (COMPARE, ccmode, x, y))); 512 513 return cc_reg; 514} 515 516/* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2, 517 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar 518 are 4. Indexed addresses are cost 6. */ 519 520/* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */ 521 522int 523i960_address_cost (x) 524 rtx x; 525{ 526#if 0 527 /* Handled before calling here. */ 528 if (GET_CODE (x) == REG) 529 return 1; 530#endif 531 /* This is a MEMA operand -- it's free. */ 532 if (GET_CODE (x) == CONST_INT 533 && INTVAL (x) >= 0 534 && INTVAL (x) < 4096) 535 return 0; 536 537 if (GET_CODE (x) == PLUS) 538 { 539 rtx base = XEXP (x, 0); 540 rtx offset = XEXP (x, 1); 541 542 if (GET_CODE (base) == SUBREG) 543 base = SUBREG_REG (base); 544 if (GET_CODE (offset) == SUBREG) 545 offset = SUBREG_REG (offset); 546 547 if (GET_CODE (base) == REG) 548 { 549 if (GET_CODE (offset) == REG) 550 return 2; 551 if (GET_CODE (offset) == CONST_INT) 552 { 553 if ((unsigned)INTVAL (offset) < 2047) 554 return 2; 555 return 4; 556 } 557 if (CONSTANT_P (offset)) 558 return 4; 559 } 560 if (GET_CODE (base) == PLUS || GET_CODE (base) == MULT) 561 return 6; 562 563 /* This is an invalid address. The return value doesn't matter, but 564 for convenience we make this more expensive than anything else. */ 565 return 12; 566 } 567 if (GET_CODE (x) == MULT) 568 return 6; 569 570 /* Symbol_refs and other unrecognized addresses are cost 4. */ 571 return 4; 572} 573 574/* Emit insns to move operands[1] into operands[0]. 575 576 Return 1 if we have written out everything that needs to be done to 577 do the move. Otherwise, return 0 and the caller will emit the move 578 normally. */ 579 580int 581emit_move_sequence (operands, mode) 582 rtx *operands; 583 enum machine_mode mode; 584{ 585 /* We can only store registers to memory. */ 586 587 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) != REG 588 && (operands[1] != const0_rtx || current_function_args_size 589 || current_function_varargs || current_function_stdarg 590 || rtx_equal_function_value_matters)) 591 /* Here we use the same test as movsi+1 pattern -- see i960.md. */ 592 operands[1] = force_reg (mode, operands[1]); 593 594 /* Storing multi-word values in unaligned hard registers to memory may 595 require a scratch since we have to store them a register at a time and 596 adding 4 to the memory address may not yield a valid insn. */ 597 /* ??? We don't always need the scratch, but that would complicate things. 598 Maybe later. */ 599 /* ??? We must also handle stores to pseudos here, because the pseudo may be 600 replaced with a MEM later. This would be cleaner if we didn't have 601 a separate pattern for unaligned DImode/TImode stores. */ 602 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD 603 && (GET_CODE (operands[0]) == MEM 604 || (GET_CODE (operands[0]) == REG 605 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)) 606 && GET_CODE (operands[1]) == REG 607 && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER 608 && ! HARD_REGNO_MODE_OK (REGNO (operands[1]), mode)) 609 { 610 emit_insn (gen_rtx (PARALLEL, VOIDmode, 611 gen_rtvec (2, 612 gen_rtx (SET, VOIDmode, 613 operands[0], operands[1]), 614 gen_rtx (CLOBBER, VOIDmode, 615 gen_rtx (SCRATCH, Pmode))))); 616 return 1; 617 } 618 619 return 0; 620} 621 622/* Output assembler to move a double word value. */ 623 624char * 625i960_output_move_double (dst, src) 626 rtx dst, src; 627{ 628 rtx operands[5]; 629 630 if (GET_CODE (dst) == REG 631 && GET_CODE (src) == REG) 632 { 633 if ((REGNO (src) & 1) 634 || (REGNO (dst) & 1)) 635 { 636 /* We normally copy the low-numbered register first. However, if 637 the second source register is the same as the first destination 638 register, we must copy in the opposite order. */ 639 if (REGNO (src) + 1 == REGNO (dst)) 640 return "mov %D1,%D0\n\tmov %1,%0"; 641 else 642 return "mov %1,%0\n\tmov %D1,%D0"; 643 } 644 else 645 return "movl %1,%0"; 646 } 647 else if (GET_CODE (dst) == REG 648 && GET_CODE (src) == CONST_INT 649 && CONST_OK_FOR_LETTER_P (INTVAL (src), 'I')) 650 { 651 if (REGNO (dst) & 1) 652 return "mov %1,%0\n\tmov 0,%D0"; 653 else 654 return "movl %1,%0"; 655 } 656 else if (GET_CODE (dst) == REG 657 && GET_CODE (src) == MEM) 658 { 659 if (REGNO (dst) & 1) 660 { 661 /* One can optimize a few cases here, but you have to be 662 careful of clobbering registers used in the address and 663 edge conditions. */ 664 operands[0] = dst; 665 operands[1] = src; 666 operands[2] = gen_rtx (REG, Pmode, REGNO (dst) + 1); 667 operands[3] = gen_rtx (MEM, word_mode, operands[2]); 668 operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD); 669 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands); 670 return ""; 671 } 672 else 673 return "ldl %1,%0"; 674 } 675 else if (GET_CODE (dst) == MEM 676 && GET_CODE (src) == REG) 677 { 678 if (REGNO (src) & 1) 679 { 680 operands[0] = dst; 681 operands[1] = adj_offsettable_operand (dst, UNITS_PER_WORD); 682 if (! memory_address_p (word_mode, XEXP (operands[1], 0))) 683 abort (); 684 operands[2] = src; 685 output_asm_insn ("st %2,%0\n\tst %D2,%1", operands); 686 return ""; 687 } 688 return "stl %1,%0"; 689 } 690 else 691 abort (); 692} 693 694/* Output assembler to move a double word zero. */ 695 696char * 697i960_output_move_double_zero (dst) 698 rtx dst; 699{ 700 rtx operands[2]; 701 702 operands[0] = dst; 703 { 704 operands[1] = adj_offsettable_operand (dst, 4); 705 output_asm_insn ("st g14,%0\n\tst g14,%1", operands); 706 } 707 return ""; 708} 709 710/* Output assembler to move a quad word value. */ 711 712char * 713i960_output_move_quad (dst, src) 714 rtx dst, src; 715{ 716 rtx operands[7]; 717 718 if (GET_CODE (dst) == REG 719 && GET_CODE (src) == REG) 720 { 721 if ((REGNO (src) & 3) 722 || (REGNO (dst) & 3)) 723 { 724 /* We normally copy starting with the low numbered register. 725 However, if there is an overlap such that the first dest reg 726 is <= the last source reg but not < the first source reg, we 727 must copy in the opposite order. */ 728 if (REGNO (dst) <= REGNO (src) + 3 729 && REGNO (dst) >= REGNO (src)) 730 return "mov %F1,%F0\n\tmov %E1,%E0\n\tmov %D1,%D0\n\tmov %1,%0"; 731 else 732 return "mov %1,%0\n\tmov %D1,%D0\n\tmov %E1,%E0\n\tmov %F1,%F0"; 733 } 734 else 735 return "movq %1,%0"; 736 } 737 else if (GET_CODE (dst) == REG 738 && GET_CODE (src) == CONST_INT 739 && CONST_OK_FOR_LETTER_P (INTVAL (src), 'I')) 740 { 741 if (REGNO (dst) & 3) 742 return "mov %1,%0\n\tmov 0,%D0\n\tmov 0,%E0\n\tmov 0,%F0"; 743 else 744 return "movq %1,%0"; 745 } 746 else if (GET_CODE (dst) == REG 747 && GET_CODE (src) == MEM) 748 { 749 if (REGNO (dst) & 3) 750 { 751 /* One can optimize a few cases here, but you have to be 752 careful of clobbering registers used in the address and 753 edge conditions. */ 754 operands[0] = dst; 755 operands[1] = src; 756 operands[2] = gen_rtx (REG, Pmode, REGNO (dst) + 3); 757 operands[3] = gen_rtx (MEM, word_mode, operands[2]); 758 operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD); 759 operands[5] = adj_offsettable_operand (operands[4], UNITS_PER_WORD); 760 operands[6] = adj_offsettable_operand (operands[5], UNITS_PER_WORD); 761 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0\n\tld %5,%E0\n\tld %6,%F0", operands); 762 return ""; 763 } 764 else 765 return "ldq %1,%0"; 766 } 767 else if (GET_CODE (dst) == MEM 768 && GET_CODE (src) == REG) 769 { 770 if (REGNO (src) & 3) 771 { 772 operands[0] = dst; 773 operands[1] = adj_offsettable_operand (dst, UNITS_PER_WORD); 774 operands[2] = adj_offsettable_operand (dst, 2*UNITS_PER_WORD); 775 operands[3] = adj_offsettable_operand (dst, 3*UNITS_PER_WORD); 776 if (! memory_address_p (word_mode, XEXP (operands[3], 0))) 777 abort (); 778 operands[4] = src; 779 output_asm_insn ("st %4,%0\n\tst %D4,%1\n\tst %E4,%2\n\tst %F4,%3", operands); 780 return ""; 781 } 782 return "stq %1,%0"; 783 } 784 else 785 abort (); 786} 787 788/* Output assembler to move a quad word zero. */ 789 790char * 791i960_output_move_quad_zero (dst) 792 rtx dst; 793{ 794 rtx operands[4]; 795 796 operands[0] = dst; 797 { 798 operands[1] = adj_offsettable_operand (dst, 4); 799 operands[2] = adj_offsettable_operand (dst, 8); 800 operands[3] = adj_offsettable_operand (dst, 12); 801 output_asm_insn ("st g14,%0\n\tst g14,%1\n\tst g14,%2\n\tst g14,%3", operands); 802 } 803 return ""; 804} 805 806 807/* Emit insns to load a constant to non-floating point registers. 808 Uses several strategies to try to use as few insns as possible. */ 809 810char * 811i960_output_ldconst (dst, src) 812 register rtx dst, src; 813{ 814 register int rsrc1; 815 register unsigned rsrc2; 816 enum machine_mode mode = GET_MODE (dst); 817 rtx operands[4]; 818 819 operands[0] = operands[2] = dst; 820 operands[1] = operands[3] = src; 821 822 /* Anything that isn't a compile time constant, such as a SYMBOL_REF, 823 must be a ldconst insn. */ 824 825 if (GET_CODE (src) != CONST_INT && GET_CODE (src) != CONST_DOUBLE) 826 { 827 output_asm_insn ("ldconst %1,%0", operands); 828 return ""; 829 } 830 else if (mode == XFmode) 831 { 832 REAL_VALUE_TYPE d; 833 long value_long[3]; 834 int i; 835 836 if (fp_literal_zero (src, XFmode)) 837 return "movt 0,%0"; 838 839 REAL_VALUE_FROM_CONST_DOUBLE (d, src); 840 REAL_VALUE_TO_TARGET_LONG_DOUBLE (d, value_long); 841 842 output_asm_insn ("# ldconst %1,%0",operands); 843 844 for (i = 0; i < 3; i++) 845 { 846 operands[0] = gen_rtx (REG, SImode, REGNO (dst) + i); 847 operands[1] = GEN_INT (value_long[i]); 848 output_asm_insn (i960_output_ldconst (operands[0], operands[1]), 849 operands); 850 } 851 852 return ""; 853 } 854 else if (mode == DFmode) 855 { 856 rtx first, second; 857 858 if (fp_literal_zero (src, DFmode)) 859 return "movl 0,%0"; 860 861 split_double (src, &first, &second); 862 863 output_asm_insn ("# ldconst %1,%0",operands); 864 865 operands[0] = gen_rtx (REG, SImode, REGNO (dst)); 866 operands[1] = first; 867 output_asm_insn (i960_output_ldconst (operands[0], operands[1]), 868 operands); 869 operands[0] = gen_rtx (REG, SImode, REGNO (dst) + 1); 870 operands[1] = second; 871 output_asm_insn (i960_output_ldconst (operands[0], operands[1]), 872 operands); 873 return ""; 874 } 875 else if (mode == SFmode) 876 { 877 REAL_VALUE_TYPE d; 878 long value; 879 880 REAL_VALUE_FROM_CONST_DOUBLE (d, src); 881 REAL_VALUE_TO_TARGET_SINGLE (d, value); 882 883 output_asm_insn ("# ldconst %1,%0",operands); 884 operands[0] = gen_rtx (REG, SImode, REGNO (dst)); 885 operands[1] = GEN_INT (value); 886 output_asm_insn (i960_output_ldconst (operands[0], operands[1]), 887 operands); 888 return ""; 889 } 890 else if (mode == TImode) 891 { 892 /* ??? This is currently not handled at all. */ 893 abort (); 894 895 /* Note: lowest order word goes in lowest numbered reg. */ 896 rsrc1 = INTVAL (src); 897 if (rsrc1 >= 0 && rsrc1 < 32) 898 return "movq %1,%0"; 899 else 900 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands); 901 /* Go pick up the low-order word. */ 902 } 903 else if (mode == DImode) 904 { 905 rtx upperhalf, lowerhalf, xoperands[2]; 906 907 if (GET_CODE (src) == CONST_DOUBLE || GET_CODE (src) == CONST_INT) 908 split_double (src, &lowerhalf, &upperhalf); 909 910 else 911 abort (); 912 913 /* Note: lowest order word goes in lowest numbered reg. */ 914 /* Numbers from 0 to 31 can be handled with a single insn. */ 915 rsrc1 = INTVAL (lowerhalf); 916 if (upperhalf == const0_rtx && rsrc1 >= 0 && rsrc1 < 32) 917 return "movl %1,%0"; 918 919 /* Output the upper half with a recursive call. */ 920 xoperands[0] = gen_rtx (REG, SImode, REGNO (dst) + 1); 921 xoperands[1] = upperhalf; 922 output_asm_insn (i960_output_ldconst (xoperands[0], xoperands[1]), 923 xoperands); 924 /* The lower word is emitted as normally. */ 925 } 926 else 927 { 928 rsrc1 = INTVAL (src); 929 if (mode == QImode) 930 { 931 if (rsrc1 > 0xff) 932 rsrc1 &= 0xff; 933 } 934 else if (mode == HImode) 935 { 936 if (rsrc1 > 0xffff) 937 rsrc1 &= 0xffff; 938 } 939 } 940 941 if (rsrc1 >= 0) 942 { 943 /* ldconst 0..31,X -> mov 0..31,X */ 944 if (rsrc1 < 32) 945 { 946 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) 947 return "lda %1,%0"; 948 return "mov %1,%0"; 949 } 950 951 /* ldconst 32..63,X -> add 31,nn,X */ 952 if (rsrc1 < 63) 953 { 954 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) 955 return "lda %1,%0"; 956 operands[1] = GEN_INT (rsrc1 - 31); 957 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands); 958 return ""; 959 } 960 } 961 else if (rsrc1 < 0) 962 { 963 /* ldconst -1..-31 -> sub 0,0..31,X */ 964 if (rsrc1 >= -31) 965 { 966 /* return 'sub -(%1),0,%0' */ 967 operands[1] = GEN_INT (- rsrc1); 968 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands); 969 return ""; 970 } 971 972 /* ldconst -32 -> not 31,X */ 973 if (rsrc1 == -32) 974 { 975 operands[1] = GEN_INT (~rsrc1); 976 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands); 977 return ""; 978 } 979 } 980 981 /* If const is a single bit. */ 982 if (bitpos (rsrc1) >= 0) 983 { 984 operands[1] = GEN_INT (bitpos (rsrc1)); 985 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands); 986 return ""; 987 } 988 989 /* If const is a bit string of less than 6 bits (1..31 shifted). */ 990 if (is_mask (rsrc1)) 991 { 992 int s, e; 993 994 if (bitstr (rsrc1, &s, &e) < 6) 995 { 996 rsrc2 = ((unsigned int) rsrc1) >> s; 997 operands[1] = GEN_INT (rsrc2); 998 operands[2] = GEN_INT (s); 999 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands); 1000 return ""; 1001 } 1002 } 1003 1004 /* Unimplemented cases: 1005 const is in range 0..31 but rotated around end of word: 1006 ror 31,3,g0 -> ldconst 0xe0000003,g0 1007 1008 and any 2 instruction cases that might be worthwhile */ 1009 1010 output_asm_insn ("ldconst %1,%0", operands); 1011 return ""; 1012} 1013 1014/* Determine if there is an opportunity for a bypass optimization. 1015 Bypass succeeds on the 960K* if the destination of the previous 1016 instruction is the second operand of the current instruction. 1017 Bypass always succeeds on the C*. 1018 1019 Return 1 if the pattern should interchange the operands. 1020 1021 CMPBR_FLAG is true if this is for a compare-and-branch insn. 1022 OP1 and OP2 are the two source operands of a 3 operand insn. */ 1023 1024int 1025i960_bypass (insn, op1, op2, cmpbr_flag) 1026 register rtx insn, op1, op2; 1027 int cmpbr_flag; 1028{ 1029 register rtx prev_insn, prev_dest; 1030 1031 if (TARGET_C_SERIES) 1032 return 0; 1033 1034 /* Can't do this if op1 isn't a register. */ 1035 if (! REG_P (op1)) 1036 return 0; 1037 1038 /* Can't do this for a compare-and-branch if both ops aren't regs. */ 1039 if (cmpbr_flag && ! REG_P (op2)) 1040 return 0; 1041 1042 prev_insn = prev_real_insn (insn); 1043 1044 if (prev_insn && GET_CODE (prev_insn) == INSN 1045 && GET_CODE (PATTERN (prev_insn)) == SET) 1046 { 1047 prev_dest = SET_DEST (PATTERN (prev_insn)); 1048 if ((GET_CODE (prev_dest) == REG && REGNO (prev_dest) == REGNO (op1)) 1049 || (GET_CODE (prev_dest) == SUBREG 1050 && GET_CODE (SUBREG_REG (prev_dest)) == REG 1051 && REGNO (SUBREG_REG (prev_dest)) == REGNO (op1))) 1052 return 1; 1053 } 1054 return 0; 1055} 1056 1057/* Output the code which declares the function name. This also handles 1058 leaf routines, which have special requirements, and initializes some 1059 global variables. */ 1060 1061void 1062i960_function_name_declare (file, name, fndecl) 1063 FILE *file; 1064 char *name; 1065 tree fndecl; 1066{ 1067 register int i, j; 1068 int leaf_proc_ok; 1069 rtx insn; 1070 1071 /* Increment global return label. */ 1072 1073 ret_label++; 1074 1075 /* Compute whether tail calls and leaf routine optimizations can be performed 1076 for this function. */ 1077 1078 if (TARGET_TAILCALL) 1079 tail_call_ok = 1; 1080 else 1081 tail_call_ok = 0; 1082 1083 if (TARGET_LEAFPROC) 1084 leaf_proc_ok = 1; 1085 else 1086 leaf_proc_ok = 0; 1087 1088 /* Even if nobody uses extra parms, can't have leafproc or tail calls if 1089 argblock, because argblock uses g14 implicitly. */ 1090 1091 if (current_function_args_size != 0 || VARARGS_STDARG_FUNCTION (fndecl)) 1092 { 1093 tail_call_ok = 0; 1094 leaf_proc_ok = 0; 1095 } 1096 1097 /* See if caller passes in an address to return value. */ 1098 1099 if (aggregate_value_p (DECL_RESULT (fndecl))) 1100 { 1101 tail_call_ok = 0; 1102 leaf_proc_ok = 0; 1103 } 1104 1105 /* Can not use tail calls or make this a leaf routine if there is a non 1106 zero frame size. */ 1107 1108 if (get_frame_size () != 0) 1109 leaf_proc_ok = 0; 1110 1111 /* I don't understand this condition, and do not think that it is correct. 1112 Apparently this is just checking whether the frame pointer is used, and 1113 we can't trust regs_ever_live[fp] since it is (almost?) always set. */ 1114 1115 if (tail_call_ok) 1116 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 1117 if (GET_CODE (insn) == INSN 1118 && reg_mentioned_p (frame_pointer_rtx, insn)) 1119 { 1120 tail_call_ok = 0; 1121 break; 1122 } 1123 1124 /* Check for CALL insns. Can not be a leaf routine if there are any. */ 1125 1126 if (leaf_proc_ok) 1127 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 1128 if (GET_CODE (insn) == CALL_INSN) 1129 { 1130 leaf_proc_ok = 0; 1131 break; 1132 } 1133 1134 /* Can not be a leaf routine if any non-call clobbered registers are 1135 used in this function. */ 1136 1137 if (leaf_proc_ok) 1138 for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++) 1139 if (regs_ever_live[i] 1140 && ((! call_used_regs[i]) || (i > 7 && i < 12))) 1141 { 1142 /* Global registers. */ 1143 if (i < 16 && i > 7 && i != 13) 1144 leaf_proc_ok = 0; 1145 /* Local registers. */ 1146 else if (i < 32) 1147 leaf_proc_ok = 0; 1148 } 1149 1150 /* Now choose a leaf return register, if we can find one, and if it is 1151 OK for this to be a leaf routine. */ 1152 1153 i960_leaf_ret_reg = -1; 1154 1155 if (optimize && leaf_proc_ok) 1156 { 1157 for (i960_leaf_ret_reg = -1, i = 0; i < 8; i++) 1158 if (regs_ever_live[i] == 0) 1159 { 1160 i960_leaf_ret_reg = i; 1161 regs_ever_live[i] = 1; 1162 break; 1163 } 1164 } 1165 1166 /* Do this after choosing the leaf return register, so it will be listed 1167 if one was chosen. */ 1168 1169 fprintf (file, "\t# Function '%s'\n", (name[0] == '*' ? &name[1] : name)); 1170 fprintf (file, "\t# Registers used: "); 1171 1172 for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++) 1173 { 1174 if (regs_ever_live[i]) 1175 { 1176 fprintf (file, "%s%s ", reg_names[i], call_used_regs[i] ? "" : "*"); 1177 1178 if (i > 15 && j == 0) 1179 { 1180 fprintf (file,"\n\t#\t\t "); 1181 j++; 1182 } 1183 } 1184 } 1185 1186 fprintf (file, "\n"); 1187 1188 if (i960_leaf_ret_reg >= 0) 1189 { 1190 /* Make it a leaf procedure. */ 1191 1192 if (TREE_PUBLIC (fndecl)) 1193 fprintf (file,"\t.globl\t%s.lf\n", (name[0] == '*' ? &name[1] : name)); 1194 1195 fprintf (file, "\t.leafproc\t"); 1196 assemble_name (file, name); 1197 fprintf (file, ",%s.lf\n", (name[0] == '*' ? &name[1] : name)); 1198 ASM_OUTPUT_LABEL (file, name); 1199 fprintf (file, "\tlda LR%d,g14\n", ret_label); 1200 fprintf (file, "%s.lf:\n", (name[0] == '*' ? &name[1] : name)); 1201 fprintf (file, "\tmov g14,g%d\n", i960_leaf_ret_reg); 1202 1203 if (TARGET_C_SERIES) 1204 { 1205 fprintf (file, "\tlda 0,g14\n"); 1206 i960_last_insn_type = I_TYPE_MEM; 1207 } 1208 else 1209 { 1210 fprintf (file, "\tmov 0,g14\n"); 1211 i960_last_insn_type = I_TYPE_REG; 1212 } 1213 } 1214 else 1215 { 1216 ASM_OUTPUT_LABEL (file, name); 1217 i960_last_insn_type = I_TYPE_CTRL; 1218 } 1219} 1220 1221/* Compute and return the frame size. */ 1222 1223int 1224compute_frame_size (size) 1225 int size; 1226{ 1227 int actual_fsize; 1228 int outgoing_args_size = current_function_outgoing_args_size; 1229 1230 /* The STARTING_FRAME_OFFSET is totally hidden to us as far 1231 as size is concerned. */ 1232 actual_fsize = (size + 15) & -16; 1233 actual_fsize += (outgoing_args_size + 15) & -16; 1234 1235 return actual_fsize; 1236} 1237 1238/* Here register group is range of registers which can be moved by 1239 one i960 instruction. */ 1240 1241struct reg_group 1242{ 1243 char start_reg; 1244 char length; 1245}; 1246 1247/* The following functions forms the biggest as possible register 1248 groups with registers in STATE. REGS contain states of the 1249 registers in range [start, finish_reg). The function returns the 1250 number of groups formed. */ 1251static int 1252i960_form_reg_groups (start_reg, finish_reg, regs, state, reg_groups) 1253 int start_reg; 1254 int finish_reg; 1255 int *regs; 1256 int state; 1257 struct reg_group *reg_groups; 1258{ 1259 int i; 1260 int nw = 0; 1261 1262 for (i = start_reg; i < finish_reg; ) 1263 { 1264 if (regs [i] != state) 1265 { 1266 i++; 1267 continue; 1268 } 1269 else if (i % 2 != 0 || regs [i + 1] != state) 1270 reg_groups [nw].length = 1; 1271 else if (i % 4 != 0 || regs [i + 2] != state) 1272 reg_groups [nw].length = 2; 1273 else if (regs [i + 3] != state) 1274 reg_groups [nw].length = 3; 1275 else 1276 reg_groups [nw].length = 4; 1277 reg_groups [nw].start_reg = i; 1278 i += reg_groups [nw].length; 1279 nw++; 1280 } 1281 return nw; 1282} 1283 1284/* We sort register winodws in descending order by length. */ 1285static int 1286i960_reg_group_compare (group1, group2) 1287 void *group1; 1288 void *group2; 1289{ 1290 struct reg_group *w1 = group1; 1291 struct reg_group *w2 = group2; 1292 1293 if (w1->length > w2->length) 1294 return -1; 1295 else if (w1->length < w2->length) 1296 return 1; 1297 else 1298 return 0; 1299} 1300 1301/* Split the first register group in REG_GROUPS on subgroups one of 1302 which will contain SUBGROUP_LENGTH registers. The function 1303 returns new number of winodws. */ 1304static int 1305i960_split_reg_group (reg_groups, nw, subgroup_length) 1306 struct reg_group *reg_groups; 1307 int nw; 1308 int subgroup_length; 1309{ 1310 if (subgroup_length < reg_groups->length - subgroup_length) 1311 /* This guarantees correct alignments of the two subgroups for 1312 i960 (see spliting for the group length 2, 3, 4). More 1313 generalized algorithm would require splitting the group more 1314 two subgroups. */ 1315 subgroup_length = reg_groups->length - subgroup_length; 1316 /* More generalized algorithm would require to try merging 1317 subgroups here. But in case i960 it always results in failure 1318 because of register group alignment. */ 1319 reg_groups[nw].length = reg_groups->length - subgroup_length; 1320 reg_groups[nw].start_reg = reg_groups->start_reg + subgroup_length; 1321 nw++; 1322 reg_groups->length = subgroup_length; 1323 qsort (reg_groups, nw, sizeof (struct reg_group), i960_reg_group_compare); 1324 return nw; 1325} 1326 1327/* Output code for the function prologue. */ 1328 1329void 1330i960_function_prologue (file, size) 1331 FILE *file; 1332 unsigned int size; 1333{ 1334 register int i, j, nr; 1335 int n_iregs = 0; 1336 int rsize = 0; 1337 int actual_fsize, offset; 1338 int gnw, lnw; 1339 struct reg_group *g, *l; 1340 char tmpstr[1000]; 1341 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved 1342 somewhere. */ 1343 int regs[FIRST_PSEUDO_REGISTER]; 1344 /* All global registers (which must be saved) divided by groups. */ 1345 struct reg_group global_reg_groups [16]; 1346 /* All local registers (which are available) divided by groups. */ 1347 struct reg_group local_reg_groups [16]; 1348 1349 1350 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1351 if (regs_ever_live[i] 1352 && ((! call_used_regs[i]) || (i > 7 && i < 12)) 1353 /* No need to save the static chain pointer. */ 1354 && ! (i == STATIC_CHAIN_REGNUM && current_function_needs_context)) 1355 { 1356 regs[i] = -1; 1357 /* Count global registers that need saving. */ 1358 if (i < 16) 1359 n_iregs++; 1360 } 1361 else 1362 regs[i] = 0; 1363 1364 epilogue_string[0] = '\0'; 1365 1366 if (profile_flag || profile_block_flag) 1367 { 1368 /* When profiling, we may use registers 20 to 27 to save arguments, so 1369 they can't be used here for saving globals. J is the number of 1370 argument registers the mcount call will save. */ 1371 for (j = 7; j >= 0 && ! regs_ever_live[j]; j--) 1372 ; 1373 1374 for (i = 20; i <= j + 20; i++) 1375 regs[i] = -1; 1376 } 1377 1378 gnw = i960_form_reg_groups (0, 16, regs, -1, global_reg_groups); 1379 lnw = i960_form_reg_groups (19, 32, regs, 0, local_reg_groups); 1380 qsort (global_reg_groups, gnw, sizeof (struct reg_group), 1381 i960_reg_group_compare); 1382 qsort (local_reg_groups, lnw, sizeof (struct reg_group), 1383 i960_reg_group_compare); 1384 for (g = global_reg_groups, l = local_reg_groups; lnw != 0 && gnw != 0;) 1385 { 1386 if (g->length == l->length) 1387 { 1388 fprintf (file, "\tmov%s %s,%s\n", 1389 ((g->length == 4) ? "q" : 1390 (g->length == 3) ? "t" : 1391 (g->length == 2) ? "l" : ""), 1392 reg_names[g->start_reg], reg_names[l->start_reg]); 1393 sprintf (tmpstr, "\tmov%s %s,%s\n", 1394 ((g->length == 4) ? "q" : 1395 (g->length == 3) ? "t" : 1396 (g->length == 2) ? "l" : ""), 1397 reg_names[l->start_reg], reg_names[g->start_reg]); 1398 strcat (epilogue_string, tmpstr); 1399 n_iregs -= g->length; 1400 for (i = 0; i < g->length; i++) 1401 { 1402 regs [i + g->start_reg] = 1; 1403 regs [i + l->start_reg] = -1; 1404 regs_ever_live [i + l->start_reg] = 1; 1405 } 1406 g++; 1407 l++; 1408 gnw--; 1409 lnw--; 1410 } 1411 else if (g->length > l->length) 1412 gnw = i960_split_reg_group (g, gnw, l->length); 1413 else 1414 lnw = i960_split_reg_group (l, lnw, g->length); 1415 } 1416 1417 /* N_iregs is now the number of global registers that haven't been saved 1418 yet. */ 1419 1420 rsize = (n_iregs * 4); 1421 actual_fsize = compute_frame_size (size) + rsize; 1422#if 0 1423 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame 1424 size up to the nearest multiple of 16. I don't know whether this is 1425 necessary, or even desirable. 1426 1427 The frame pointer must be aligned, but the call instruction takes care of 1428 that. If we leave the stack pointer unaligned, we may save a little on 1429 dynamic stack allocation. And we don't lose, at least according to the 1430 i960CA manual. */ 1431 actual_fsize = (actual_fsize + 15) & ~0xF; 1432#endif 1433 1434 /* Allocate space for register save and locals. */ 1435 if (actual_fsize > 0) 1436 { 1437 if (actual_fsize < 32) 1438 fprintf (file, "\taddo %d,sp,sp\n", actual_fsize); 1439 else 1440 fprintf (file, "\tlda\t%d(sp),sp\n", actual_fsize); 1441 } 1442 1443 /* Take hardware register save area created by the call instruction 1444 into account, but store them before the argument block area. */ 1445 offset = 64 + actual_fsize - compute_frame_size (0) - rsize; 1446 /* Save registers on stack if needed. */ 1447 /* ??? Is it worth to use the same algorithm as one for saving 1448 global registers in local registers? */ 1449 for (i = 0, j = n_iregs; j > 0 && i < 16; i++) 1450 { 1451 if (regs[i] != -1) 1452 continue; 1453 1454 nr = 1; 1455 1456 if (i <= 14 && i % 2 == 0 && regs[i+1] == -1 && offset % 2 == 0) 1457 nr = 2; 1458 1459 if (nr == 2 && i <= 12 && i % 4 == 0 && regs[i+2] == -1 1460 && offset % 4 == 0) 1461 nr = 3; 1462 1463 if (nr == 3 && regs[i+3] == -1) 1464 nr = 4; 1465 1466 fprintf (file,"\tst%s %s,%d(fp)\n", 1467 ((nr == 4) ? "q" : 1468 (nr == 3) ? "t" : 1469 (nr == 2) ? "l" : ""), 1470 reg_names[i], offset); 1471 sprintf (tmpstr,"\tld%s %d(fp),%s\n", 1472 ((nr == 4) ? "q" : 1473 (nr == 3) ? "t" : 1474 (nr == 2) ? "l" : ""), 1475 offset, reg_names[i]); 1476 strcat (epilogue_string, tmpstr); 1477 i += nr-1; 1478 j -= nr; 1479 offset += nr * 4; 1480 } 1481 1482 if (actual_fsize == 0 && size == 0 && rsize == 0) 1483 return; 1484 1485 fprintf (file, "\t#Prologue stats:\n"); 1486 fprintf (file, "\t# Total Frame Size: %d bytes\n", actual_fsize); 1487 1488 if (size) 1489 fprintf (file, "\t# Local Variable Size: %d bytes\n", size); 1490 if (rsize) 1491 fprintf (file, "\t# Register Save Size: %d regs, %d bytes\n", 1492 n_iregs, rsize); 1493 fprintf (file, "\t#End Prologue#\n"); 1494} 1495 1496/* Output code for the function profiler. */ 1497 1498void 1499output_function_profiler (file, labelno) 1500 FILE *file; 1501 int labelno; 1502{ 1503 /* The last used parameter register. */ 1504 int last_parm_reg; 1505 int i, j, increment; 1506 int varargs_stdarg_function 1507 = VARARGS_STDARG_FUNCTION (current_function_decl); 1508 1509 /* Figure out the last used parameter register. The proper thing to do 1510 is to walk incoming args of the function. A function might have live 1511 parameter registers even if it has no incoming args. Note that we 1512 don't have to save parameter registers g8 to g11 because they are 1513 call preserved. */ 1514 1515 /* See also output_function_prologue, which tries to use local registers 1516 for preserved call-saved global registers. */ 1517 1518 for (last_parm_reg = 7; 1519 last_parm_reg >= 0 && ! regs_ever_live[last_parm_reg]; 1520 last_parm_reg--) 1521 ; 1522 1523 /* Save parameter registers in regs r4 (20) to r11 (27). */ 1524 1525 for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment) 1526 { 1527 if (i % 4 == 0 && (last_parm_reg - i) >= 3) 1528 increment = 4; 1529 else if (i % 4 == 0 && (last_parm_reg - i) >= 2) 1530 increment = 3; 1531 else if (i % 2 == 0 && (last_parm_reg - i) >= 1) 1532 increment = 2; 1533 else 1534 increment = 1; 1535 1536 fprintf (file, "\tmov%s g%d,r%d\n", 1537 (increment == 4 ? "q" : increment == 3 ? "t" 1538 : increment == 2 ? "l": ""), i, j); 1539 } 1540 1541 /* If this function uses the arg pointer, then save it in r3 and then 1542 set it to zero. */ 1543 1544 if (current_function_args_size != 0 || varargs_stdarg_function) 1545 fprintf (file, "\tmov g14,r3\n\tmov 0,g14\n"); 1546 1547 /* Load location address into g0 and call mcount. */ 1548 1549 fprintf (file, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno); 1550 1551 /* If this function uses the arg pointer, restore it. */ 1552 1553 if (current_function_args_size != 0 || varargs_stdarg_function) 1554 fprintf (file, "\tmov r3,g14\n"); 1555 1556 /* Restore parameter registers. */ 1557 1558 for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment) 1559 { 1560 if (i % 4 == 0 && (last_parm_reg - i) >= 3) 1561 increment = 4; 1562 else if (i % 4 == 0 && (last_parm_reg - i) >= 2) 1563 increment = 3; 1564 else if (i % 2 == 0 && (last_parm_reg - i) >= 1) 1565 increment = 2; 1566 else 1567 increment = 1; 1568 1569 fprintf (file, "\tmov%s r%d,g%d\n", 1570 (increment == 4 ? "q" : increment == 3 ? "t" 1571 : increment == 2 ? "l": ""), j, i); 1572 } 1573} 1574 1575/* Output code for the function epilogue. */ 1576 1577void 1578i960_function_epilogue (file, size) 1579 FILE *file; 1580 unsigned int size; 1581{ 1582 if (i960_leaf_ret_reg >= 0) 1583 { 1584 fprintf (file, "LR%d: ret\n", ret_label); 1585 return; 1586 } 1587 1588 if (*epilogue_string == 0) 1589 { 1590 register rtx tmp; 1591 1592 /* Emit a return insn, but only if control can fall through to here. */ 1593 1594 tmp = get_last_insn (); 1595 while (tmp) 1596 { 1597 if (GET_CODE (tmp) == BARRIER) 1598 return; 1599 if (GET_CODE (tmp) == CODE_LABEL) 1600 break; 1601 if (GET_CODE (tmp) == JUMP_INSN) 1602 { 1603 if (GET_CODE (PATTERN (tmp)) == RETURN) 1604 return; 1605 break; 1606 } 1607 if (GET_CODE (tmp) == NOTE) 1608 { 1609 tmp = PREV_INSN (tmp); 1610 continue; 1611 } 1612 break; 1613 } 1614 fprintf (file, "LR%d: ret\n", ret_label); 1615 return; 1616 } 1617 1618 fprintf (file, "LR%d:\n", ret_label); 1619 1620 fprintf (file, "\t#EPILOGUE#\n"); 1621 1622 /* Output the string created by the prologue which will restore all 1623 registers saved by the prologue. */ 1624 1625 if (epilogue_string[0] != '\0') 1626 fprintf (file, "%s", epilogue_string); 1627 1628 /* Must clear g14 on return if this function set it. 1629 Only varargs/stdarg functions modify g14. */ 1630 1631 if (VARARGS_STDARG_FUNCTION (current_function_decl)) 1632 fprintf (file, "\tmov 0,g14\n"); 1633 1634 fprintf (file, "\tret\n"); 1635 fprintf (file, "\t#End Epilogue#\n"); 1636} 1637 1638/* Output code for a call insn. */ 1639 1640char * 1641i960_output_call_insn (target, argsize_rtx, arg_pointer, insn) 1642 register rtx target, argsize_rtx, arg_pointer, insn; 1643{ 1644 int argsize = INTVAL (argsize_rtx); 1645 rtx nexti = next_real_insn (insn); 1646 rtx operands[2]; 1647 int varargs_stdarg_function 1648 = VARARGS_STDARG_FUNCTION (current_function_decl); 1649 1650 operands[0] = target; 1651 operands[1] = arg_pointer; 1652 1653 if (current_function_args_size != 0 || varargs_stdarg_function) 1654 output_asm_insn ("mov g14,r3", operands); 1655 1656 if (argsize > 48) 1657 output_asm_insn ("lda %a1,g14", operands); 1658 else if (current_function_args_size != 0 || varargs_stdarg_function) 1659 output_asm_insn ("mov 0,g14", operands); 1660 1661 /* The code used to assume that calls to SYMBOL_REFs could not be more 1662 than 24 bits away (b vs bx, callj vs callx). This is not true. This 1663 feature is now implemented by relaxing in the GNU linker. It can convert 1664 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */ 1665 1666 /* Nexti could be zero if the called routine is volatile. */ 1667 if (optimize && (*epilogue_string == 0) && argsize == 0 && tail_call_ok 1668 && (nexti == 0 || GET_CODE (PATTERN (nexti)) == RETURN)) 1669 { 1670 /* Delete following return insn. */ 1671 if (nexti && no_labels_between_p (insn, nexti)) 1672 delete_insn (nexti); 1673 output_asm_insn ("bx %0", operands); 1674 return "# notreached"; 1675 } 1676 1677 output_asm_insn ("callx %0", operands); 1678 1679 /* If the caller sets g14 to the address of the argblock, then the caller 1680 must clear it after the return. */ 1681 1682 if (current_function_args_size != 0 || varargs_stdarg_function) 1683 output_asm_insn ("mov r3,g14", operands); 1684 else if (argsize > 48) 1685 output_asm_insn ("mov 0,g14", operands); 1686 1687 return ""; 1688} 1689 1690/* Output code for a return insn. */ 1691 1692char * 1693i960_output_ret_insn (insn) 1694 register rtx insn; 1695{ 1696 static char lbuf[20]; 1697 1698 if (*epilogue_string != 0) 1699 { 1700 if (! TARGET_CODE_ALIGN && next_real_insn (insn) == 0) 1701 return ""; 1702 1703 sprintf (lbuf, "b LR%d", ret_label); 1704 return lbuf; 1705 } 1706 1707 /* Must clear g14 on return if this function set it. 1708 Only varargs/stdarg functions modify g14. */ 1709 1710 if (VARARGS_STDARG_FUNCTION (current_function_decl)) 1711 output_asm_insn ("mov 0,g14", 0); 1712 1713 if (i960_leaf_ret_reg >= 0) 1714 { 1715 sprintf (lbuf, "bx (%s)", reg_names[i960_leaf_ret_reg]); 1716 return lbuf; 1717 } 1718 return "ret"; 1719} 1720 1721#if 0 1722/* Return a character string representing the branch prediction 1723 opcode to be tacked on an instruction. This must at least 1724 return a null string. */ 1725 1726char * 1727i960_br_predict_opcode (lab_ref, insn) 1728 rtx lab_ref, insn; 1729{ 1730 if (TARGET_BRANCH_PREDICT) 1731 { 1732 unsigned long label_uid; 1733 1734 if (GET_CODE (lab_ref) == CODE_LABEL) 1735 label_uid = INSN_UID (lab_ref); 1736 else if (GET_CODE (lab_ref) == LABEL_REF) 1737 label_uid = INSN_UID (XEXP (lab_ref, 0)); 1738 else 1739 return ".f"; 1740 1741 /* If not optimizing, then the insn_addresses array will not be 1742 valid. In this case, always return ".t" since most branches 1743 are taken. If optimizing, return .t for backward branches 1744 and .f for forward branches. */ 1745 if (! optimize 1746 || insn_addresses[label_uid] < insn_addresses[INSN_UID (insn)]) 1747 return ".t"; 1748 return ".f"; 1749 } 1750 1751 return ""; 1752} 1753#endif 1754 1755/* Print the operand represented by rtx X formatted by code CODE. */ 1756 1757void 1758i960_print_operand (file, x, code) 1759 FILE *file; 1760 rtx x; 1761 char code; 1762{ 1763 enum rtx_code rtxcode = GET_CODE (x); 1764 1765 if (rtxcode == REG) 1766 { 1767 switch (code) 1768 { 1769 case 'D': 1770 /* Second reg of a double or quad. */ 1771 fprintf (file, "%s", reg_names[REGNO (x)+1]); 1772 break; 1773 1774 case 'E': 1775 /* Third reg of a quad. */ 1776 fprintf (file, "%s", reg_names[REGNO (x)+2]); 1777 break; 1778 1779 case 'F': 1780 /* Fourth reg of a quad. */ 1781 fprintf (file, "%s", reg_names[REGNO (x)+3]); 1782 break; 1783 1784 case 0: 1785 fprintf (file, "%s", reg_names[REGNO (x)]); 1786 break; 1787 1788 default: 1789 abort (); 1790 } 1791 return; 1792 } 1793 else if (rtxcode == MEM) 1794 { 1795 output_address (XEXP (x, 0)); 1796 return; 1797 } 1798 else if (rtxcode == CONST_INT) 1799 { 1800 HOST_WIDE_INT val = INTVAL (x); 1801 if (code == 'C') 1802 val = ~val; 1803 if (val > 9999 || val < -999) 1804 fprintf (file, "0x%x", val); 1805 else 1806 fprintf (file, "%d", val); 1807 return; 1808 } 1809 else if (rtxcode == CONST_DOUBLE) 1810 { 1811 REAL_VALUE_TYPE d; 1812 char dstr[30]; 1813 1814 if (x == CONST0_RTX (GET_MODE (x))) 1815 { 1816 fprintf (file, "0f0.0"); 1817 return; 1818 } 1819 else if (x == CONST1_RTX (GET_MODE (x))) 1820 { 1821 fprintf (file, "0f1.0"); 1822 return; 1823 } 1824 1825 REAL_VALUE_FROM_CONST_DOUBLE (d, x); 1826 REAL_VALUE_TO_DECIMAL (d, "%#g", dstr); 1827 fprintf (file, "0f%s", dstr); 1828 return; 1829 } 1830 1831 switch(code) 1832 { 1833 case 'B': 1834 /* Branch or jump, depending on assembler. */ 1835 if (TARGET_ASM_COMPAT) 1836 fputs ("j", file); 1837 else 1838 fputs ("b", file); 1839 break; 1840 1841 case 'S': 1842 /* Sign of condition. */ 1843 if ((rtxcode == EQ) || (rtxcode == NE) || (rtxcode == GTU) 1844 || (rtxcode == LTU) || (rtxcode == GEU) || (rtxcode == LEU)) 1845 fputs ("o", file); 1846 else if ((rtxcode == GT) || (rtxcode == LT) 1847 || (rtxcode == GE) || (rtxcode == LE)) 1848 fputs ("i", file); 1849 else 1850 abort(); 1851 break; 1852 1853 case 'I': 1854 /* Inverted condition. */ 1855 rtxcode = reverse_condition (rtxcode); 1856 goto normal; 1857 1858 case 'X': 1859 /* Inverted condition w/ reversed operands. */ 1860 rtxcode = reverse_condition (rtxcode); 1861 /* Fallthrough. */ 1862 1863 case 'R': 1864 /* Reversed operand condition. */ 1865 rtxcode = swap_condition (rtxcode); 1866 /* Fallthrough. */ 1867 1868 case 'C': 1869 /* Normal condition. */ 1870 normal: 1871 if (rtxcode == EQ) { fputs ("e", file); return; } 1872 else if (rtxcode == NE) { fputs ("ne", file); return; } 1873 else if (rtxcode == GT) { fputs ("g", file); return; } 1874 else if (rtxcode == GTU) { fputs ("g", file); return; } 1875 else if (rtxcode == LT) { fputs ("l", file); return; } 1876 else if (rtxcode == LTU) { fputs ("l", file); return; } 1877 else if (rtxcode == GE) { fputs ("ge", file); return; } 1878 else if (rtxcode == GEU) { fputs ("ge", file); return; } 1879 else if (rtxcode == LE) { fputs ("le", file); return; } 1880 else if (rtxcode == LEU) { fputs ("le", file); return; } 1881 else abort (); 1882 break; 1883 1884 case 0: 1885 output_addr_const (file, x); 1886 break; 1887 1888 default: 1889 abort (); 1890 } 1891 1892 return; 1893} 1894 1895/* Print a memory address as an operand to reference that memory location. 1896 1897 This is exactly the same as legitimate_address_p, except that it the prints 1898 addresses instead of recognizing them. */ 1899 1900void 1901i960_print_operand_addr (file, addr) 1902 FILE *file; 1903 register rtx addr; 1904{ 1905 rtx breg, ireg; 1906 rtx scale, offset; 1907 1908 ireg = 0; 1909 breg = 0; 1910 offset = 0; 1911 scale = const1_rtx; 1912 1913 if (GET_CODE (addr) == REG) 1914 breg = addr; 1915 else if (CONSTANT_P (addr)) 1916 offset = addr; 1917 else if (GET_CODE (addr) == PLUS) 1918 { 1919 rtx op0, op1; 1920 1921 op0 = XEXP (addr, 0); 1922 op1 = XEXP (addr, 1); 1923 1924 if (GET_CODE (op0) == REG) 1925 { 1926 breg = op0; 1927 if (GET_CODE (op1) == REG) 1928 ireg = op1; 1929 else if (CONSTANT_P (op1)) 1930 offset = op1; 1931 else 1932 abort (); 1933 } 1934 else if (GET_CODE (op0) == PLUS) 1935 { 1936 if (GET_CODE (XEXP (op0, 0)) == MULT) 1937 { 1938 ireg = XEXP (XEXP (op0, 0), 0); 1939 scale = XEXP (XEXP (op0, 0), 1); 1940 if (GET_CODE (XEXP (op0, 1)) == REG) 1941 { 1942 breg = XEXP (op0, 1); 1943 offset = op1; 1944 } 1945 else 1946 abort (); 1947 } 1948 else if (GET_CODE (XEXP (op0, 0)) == REG) 1949 { 1950 breg = XEXP (op0, 0); 1951 if (GET_CODE (XEXP (op0, 1)) == REG) 1952 { 1953 ireg = XEXP (op0, 1); 1954 offset = op1; 1955 } 1956 else 1957 abort (); 1958 } 1959 else 1960 abort (); 1961 } 1962 else if (GET_CODE (op0) == MULT) 1963 { 1964 ireg = XEXP (op0, 0); 1965 scale = XEXP (op0, 1); 1966 if (GET_CODE (op1) == REG) 1967 breg = op1; 1968 else if (CONSTANT_P (op1)) 1969 offset = op1; 1970 else 1971 abort (); 1972 } 1973 else 1974 abort (); 1975 } 1976 else if (GET_CODE (addr) == MULT) 1977 { 1978 ireg = XEXP (addr, 0); 1979 scale = XEXP (addr, 1); 1980 } 1981 else 1982 abort (); 1983 1984 if (offset) 1985 output_addr_const (file, offset); 1986 if (breg) 1987 fprintf (file, "(%s)", reg_names[REGNO (breg)]); 1988 if (ireg) 1989 fprintf (file, "[%s*%d]", reg_names[REGNO (ireg)], INTVAL (scale)); 1990} 1991 1992/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1993 that is a valid memory address for an instruction. 1994 The MODE argument is the machine mode for the MEM expression 1995 that wants to use this address. 1996 1997 On 80960, legitimate addresses are: 1998 base ld (g0),r0 1999 disp (12 or 32 bit) ld foo,r0 2000 base + index ld (g0)[g1*1],r0 2001 base + displ ld 0xf00(g0),r0 2002 base + index*scale + displ ld 0xf00(g0)[g1*4],r0 2003 index*scale + base ld (g0)[g1*4],r0 2004 index*scale + displ ld 0xf00[g1*4],r0 2005 index*scale ld [g1*4],r0 2006 index + base + displ ld 0xf00(g0)[g1*1],r0 2007 2008 In each case, scale can be 1, 2, 4, 8, or 16. */ 2009 2010/* This is exactly the same as i960_print_operand_addr, except that 2011 it recognizes addresses instead of printing them. 2012 2013 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should 2014 convert common non-canonical forms to canonical form so that they will 2015 be recognized. */ 2016 2017/* These two macros allow us to accept either a REG or a SUBREG anyplace 2018 where a register is valid. */ 2019 2020#define RTX_OK_FOR_BASE_P(X, STRICT) \ 2021 ((GET_CODE (X) == REG \ 2022 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \ 2023 || (GET_CODE (X) == SUBREG \ 2024 && GET_CODE (SUBREG_REG (X)) == REG \ 2025 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \ 2026 : REG_OK_FOR_BASE_P (SUBREG_REG (X))))) 2027 2028#define RTX_OK_FOR_INDEX_P(X, STRICT) \ 2029 ((GET_CODE (X) == REG \ 2030 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\ 2031 || (GET_CODE (X) == SUBREG \ 2032 && GET_CODE (SUBREG_REG (X)) == REG \ 2033 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \ 2034 : REG_OK_FOR_INDEX_P (SUBREG_REG (X))))) 2035 2036int 2037legitimate_address_p (mode, addr, strict) 2038 enum machine_mode mode; 2039 register rtx addr; 2040 int strict; 2041{ 2042 if (RTX_OK_FOR_BASE_P (addr, strict)) 2043 return 1; 2044 else if (CONSTANT_P (addr)) 2045 return 1; 2046 else if (GET_CODE (addr) == PLUS) 2047 { 2048 rtx op0, op1; 2049 2050 if (! TARGET_COMPLEX_ADDR && ! reload_completed) 2051 return 0; 2052 2053 op0 = XEXP (addr, 0); 2054 op1 = XEXP (addr, 1); 2055 2056 if (RTX_OK_FOR_BASE_P (op0, strict)) 2057 { 2058 if (RTX_OK_FOR_INDEX_P (op1, strict)) 2059 return 1; 2060 else if (CONSTANT_P (op1)) 2061 return 1; 2062 else 2063 return 0; 2064 } 2065 else if (GET_CODE (op0) == PLUS) 2066 { 2067 if (GET_CODE (XEXP (op0, 0)) == MULT) 2068 { 2069 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0, 0), 0), strict) 2070 && SCALE_TERM_P (XEXP (XEXP (op0, 0), 1)))) 2071 return 0; 2072 2073 if (RTX_OK_FOR_BASE_P (XEXP (op0, 1), strict) 2074 && CONSTANT_P (op1)) 2075 return 1; 2076 else 2077 return 0; 2078 } 2079 else if (RTX_OK_FOR_BASE_P (XEXP (op0, 0), strict)) 2080 { 2081 if (RTX_OK_FOR_INDEX_P (XEXP (op0, 1), strict) 2082 && CONSTANT_P (op1)) 2083 return 1; 2084 else 2085 return 0; 2086 } 2087 else 2088 return 0; 2089 } 2090 else if (GET_CODE (op0) == MULT) 2091 { 2092 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0, 0), strict) 2093 && SCALE_TERM_P (XEXP (op0, 1)))) 2094 return 0; 2095 2096 if (RTX_OK_FOR_BASE_P (op1, strict)) 2097 return 1; 2098 else if (CONSTANT_P (op1)) 2099 return 1; 2100 else 2101 return 0; 2102 } 2103 else 2104 return 0; 2105 } 2106 else if (GET_CODE (addr) == MULT) 2107 { 2108 if (! TARGET_COMPLEX_ADDR && ! reload_completed) 2109 return 0; 2110 2111 return (RTX_OK_FOR_INDEX_P (XEXP (addr, 0), strict) 2112 && SCALE_TERM_P (XEXP (addr, 1))); 2113 } 2114 else 2115 return 0; 2116} 2117 2118/* Try machine-dependent ways of modifying an illegitimate address 2119 to be legitimate. If we find one, return the new, valid address. 2120 This macro is used in only one place: `memory_address' in explow.c. 2121 2122 This converts some non-canonical addresses to canonical form so they 2123 can be recognized. */ 2124 2125rtx 2126legitimize_address (x, oldx, mode) 2127 register rtx x; 2128 register rtx oldx; 2129 enum machine_mode mode; 2130{ 2131 if (GET_CODE (x) == SYMBOL_REF) 2132 { 2133 abort (); 2134 x = copy_to_reg (x); 2135 } 2136 2137 if (! TARGET_COMPLEX_ADDR && ! reload_completed) 2138 return x; 2139 2140 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const))) 2141 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be 2142 created by virtual register instantiation, register elimination, and 2143 similar optimizations. */ 2144 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT 2145 && GET_CODE (XEXP (x, 1)) == PLUS) 2146 x = gen_rtx (PLUS, Pmode, 2147 gen_rtx (PLUS, Pmode, XEXP (x, 0), XEXP (XEXP (x, 1), 0)), 2148 XEXP (XEXP (x, 1), 1)); 2149 2150 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const) 2151 into (plus (plus (mult (reg) (const)) (reg)) (const)). */ 2152 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS 2153 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT 2154 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS 2155 && CONSTANT_P (XEXP (x, 1))) 2156 { 2157 rtx constant, other; 2158 2159 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 2160 { 2161 constant = XEXP (x, 1); 2162 other = XEXP (XEXP (XEXP (x, 0), 1), 1); 2163 } 2164 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT) 2165 { 2166 constant = XEXP (XEXP (XEXP (x, 0), 1), 1); 2167 other = XEXP (x, 1); 2168 } 2169 else 2170 constant = 0; 2171 2172 if (constant) 2173 x = gen_rtx (PLUS, Pmode, 2174 gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0), 2175 XEXP (XEXP (XEXP (x, 0), 1), 0)), 2176 plus_constant (other, INTVAL (constant))); 2177 } 2178 2179 return x; 2180} 2181 2182#if 0 2183/* Return the most stringent alignment that we are willing to consider 2184 objects of size SIZE and known alignment ALIGN as having. */ 2185 2186int 2187i960_alignment (size, align) 2188 int size; 2189 int align; 2190{ 2191 int i; 2192 2193 if (! TARGET_STRICT_ALIGN) 2194 if (TARGET_IC_COMPAT2_0 || align >= 4) 2195 { 2196 i = i960_object_bytes_bitalign (size) / BITS_PER_UNIT; 2197 if (i > align) 2198 align = i; 2199 } 2200 2201 return align; 2202} 2203#endif 2204 2205 2206int 2207hard_regno_mode_ok (regno, mode) 2208 int regno; 2209 enum machine_mode mode; 2210{ 2211 if (regno < 32) 2212 { 2213 switch (mode) 2214 { 2215 case CCmode: case CC_UNSmode: case CC_CHKmode: 2216 return 0; 2217 2218 case DImode: case DFmode: 2219 return (regno & 1) == 0; 2220 2221 case TImode: case XFmode: 2222 return (regno & 3) == 0; 2223 2224 default: 2225 return 1; 2226 } 2227 } 2228 else if (regno >= 32 && regno < 36) 2229 { 2230 switch (mode) 2231 { 2232 case SFmode: case DFmode: case XFmode: 2233 case SCmode: case DCmode: 2234 return 1; 2235 2236 default: 2237 return 0; 2238 } 2239 } 2240 else if (regno == 36) 2241 { 2242 switch (mode) 2243 { 2244 case CCmode: case CC_UNSmode: case CC_CHKmode: 2245 return 1; 2246 2247 default: 2248 return 0; 2249 } 2250 } 2251 else if (regno == 37) 2252 return 0; 2253 2254 abort (); 2255} 2256 2257 2258/* Return the minimum alignment of an expression rtx X in bytes. This takes 2259 advantage of machine specific facts, such as knowing that the frame pointer 2260 is always 16 byte aligned. */ 2261 2262int 2263i960_expr_alignment (x, size) 2264 rtx x; 2265 int size; 2266{ 2267 int align = 1; 2268 2269 if (x == 0) 2270 return 1; 2271 2272 switch (GET_CODE(x)) 2273 { 2274 case CONST_INT: 2275 align = INTVAL(x); 2276 2277 if ((align & 0xf) == 0) 2278 align = 16; 2279 else if ((align & 0x7) == 0) 2280 align = 8; 2281 else if ((align & 0x3) == 0) 2282 align = 4; 2283 else if ((align & 0x1) == 0) 2284 align = 2; 2285 else 2286 align = 1; 2287 break; 2288 2289 case PLUS: 2290 align = MIN (i960_expr_alignment (XEXP (x, 0), size), 2291 i960_expr_alignment (XEXP (x, 1), size)); 2292 break; 2293 2294 case SYMBOL_REF: 2295 /* If this is a valid program, objects are guaranteed to be 2296 correctly aligned for whatever size the reference actually is. */ 2297 align = i960_object_bytes_bitalign (size) / BITS_PER_UNIT; 2298 break; 2299 2300 case REG: 2301 if (REGNO (x) == FRAME_POINTER_REGNUM) 2302 align = 16; 2303 break; 2304 2305 case ASHIFT: 2306 align = i960_expr_alignment (XEXP (x, 0)); 2307 2308 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 2309 { 2310 align = align << INTVAL (XEXP (x, 1)); 2311 align = MIN (align, 16); 2312 } 2313 break; 2314 2315 case MULT: 2316 align = (i960_expr_alignment (XEXP (x, 0), size) * 2317 i960_expr_alignment (XEXP (x, 1), size)); 2318 2319 align = MIN (align, 16); 2320 break; 2321 } 2322 2323 return align; 2324} 2325 2326/* Return true if it is possible to reference both BASE and OFFSET, which 2327 have alignment at least as great as 4 byte, as if they had alignment valid 2328 for an object of size SIZE. */ 2329 2330int 2331i960_improve_align (base, offset, size) 2332 rtx base; 2333 rtx offset; 2334 int size; 2335{ 2336 int i, j; 2337 2338 /* We have at least a word reference to the object, so we know it has to 2339 be aligned at least to 4 bytes. */ 2340 2341 i = MIN (i960_expr_alignment (base, 4), 2342 i960_expr_alignment (offset, 4)); 2343 2344 i = MAX (i, 4); 2345 2346 /* We know the size of the request. If strict align is not enabled, we 2347 can guess that the alignment is OK for the requested size. */ 2348 2349 if (! TARGET_STRICT_ALIGN) 2350 if ((j = (i960_object_bytes_bitalign (size) / BITS_PER_UNIT)) > i) 2351 i = j; 2352 2353 return (i >= size); 2354} 2355 2356/* Return true if it is possible to access BASE and OFFSET, which have 4 byte 2357 (SImode) alignment as if they had 16 byte (TImode) alignment. */ 2358 2359int 2360i960_si_ti (base, offset) 2361 rtx base; 2362 rtx offset; 2363{ 2364 return i960_improve_align (base, offset, 16); 2365} 2366 2367/* Return true if it is possible to access BASE and OFFSET, which have 4 byte 2368 (SImode) alignment as if they had 8 byte (DImode) alignment. */ 2369 2370int 2371i960_si_di (base, offset) 2372 rtx base; 2373 rtx offset; 2374{ 2375 return i960_improve_align (base, offset, 8); 2376} 2377 2378/* Return raw values of size and alignment (in words) for the data 2379 type being accessed. These values will be rounded by the caller. */ 2380 2381static void 2382i960_arg_size_and_align (mode, type, size_out, align_out) 2383 enum machine_mode mode; 2384 tree type; 2385 int *size_out; 2386 int *align_out; 2387{ 2388 int size, align; 2389 2390 /* Use formal alignment requirements of type being passed, except make 2391 it at least a word. If we don't have a type, this is a library call, 2392 and the parm has to be of scalar type. In this case, consider its 2393 formal alignment requirement to be its size in words. */ 2394 2395 if (mode == BLKmode) 2396 size = (int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 2397 else if (mode == VOIDmode) 2398 { 2399 /* End of parm list. */ 2400 if (type == 0 || TYPE_MODE (type) != VOIDmode) 2401 abort (); 2402 size = 1; 2403 } 2404 else 2405 size = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 2406 2407 if (type == 0) 2408 { 2409 /* ??? This is a hack to properly correct the alignment of XFmode 2410 values without affecting anything else. */ 2411 if (size == 3) 2412 align = 4; 2413 else 2414 align = size; 2415 } 2416 else if (TYPE_ALIGN (type) >= BITS_PER_WORD) 2417 align = TYPE_ALIGN (type) / BITS_PER_WORD; 2418 else 2419 align = 1; 2420 2421 *size_out = size; 2422 *align_out = align; 2423} 2424 2425/* On the 80960 the first 12 args are in registers and the rest are pushed. 2426 Any arg that is bigger than 4 words is placed on the stack and all 2427 subsequent arguments are placed on the stack. 2428 2429 Additionally, parameters with an alignment requirement stronger than 2430 a word must be aligned appropriately. Note that this means that a 2431 64 bit object with a 32 bit alignment is not 64 bit aligned and may be 2432 passed in an odd/even register pair. */ 2433 2434/* Update CUM to advance past an argument described by MODE and TYPE. */ 2435 2436void 2437i960_function_arg_advance (cum, mode, type, named) 2438 CUMULATIVE_ARGS *cum; 2439 enum machine_mode mode; 2440 tree type; 2441 int named; 2442{ 2443 int size, align; 2444 2445 i960_arg_size_and_align (mode, type, &size, &align); 2446 2447 if (size > 4 || cum->ca_nstackparms != 0 2448 || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS 2449 || MUST_PASS_IN_STACK (mode, type)) 2450 { 2451 /* Indicate that all the registers are in use, even if all are not, 2452 so va_start will compute the right value. */ 2453 cum->ca_nregparms = NPARM_REGS; 2454 cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align) + size; 2455 } 2456 else 2457 cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align) + size; 2458} 2459 2460/* Return the register that the argument described by MODE and TYPE is 2461 passed in, or else return 0 if it is passed on the stack. */ 2462 2463rtx 2464i960_function_arg (cum, mode, type, named) 2465 CUMULATIVE_ARGS *cum; 2466 enum machine_mode mode; 2467 tree type; 2468 int named; 2469{ 2470 rtx ret; 2471 int size, align; 2472 2473 i960_arg_size_and_align (mode, type, &size, &align); 2474 2475 if (size > 4 || cum->ca_nstackparms != 0 2476 || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS 2477 || MUST_PASS_IN_STACK (mode, type)) 2478 { 2479 cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align); 2480 ret = 0; 2481 } 2482 else 2483 { 2484 cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align); 2485 ret = gen_rtx (REG, mode, cum->ca_nregparms); 2486 } 2487 2488 return ret; 2489} 2490 2491/* Floating-point support. */ 2492 2493void 2494i960_output_long_double (file, value) 2495 FILE *file; 2496 REAL_VALUE_TYPE value; 2497{ 2498 long value_long[3]; 2499 char dstr[30]; 2500 2501 REAL_VALUE_TO_TARGET_LONG_DOUBLE (value, value_long); 2502 REAL_VALUE_TO_DECIMAL (value, "%.20g", dstr); 2503 2504 fprintf (file, 2505 "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n\t.word\t0x%08lx\n", 2506 value_long[0], dstr, value_long[1], value_long[2]); 2507 fprintf (file, "\t.word\t0x0\n"); 2508} 2509 2510void 2511i960_output_double (file, value) 2512 FILE *file; 2513 REAL_VALUE_TYPE value; 2514{ 2515 long value_long[2]; 2516 char dstr[30]; 2517 2518 REAL_VALUE_TO_TARGET_DOUBLE (value, value_long); 2519 REAL_VALUE_TO_DECIMAL (value, "%.20g", dstr); 2520 2521 fprintf (file, "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n", 2522 value_long[0], dstr, value_long[1]); 2523} 2524 2525void 2526i960_output_float (file, value) 2527 FILE *file; 2528 REAL_VALUE_TYPE value; 2529{ 2530 long value_long; 2531 char dstr[30]; 2532 2533 REAL_VALUE_TO_TARGET_SINGLE (value, value_long); 2534 REAL_VALUE_TO_DECIMAL (value, "%.12g", dstr); 2535 2536 fprintf (file, "\t.word\t0x%08lx\t\t# %s (float)\n", value_long, dstr); 2537} 2538 2539/* Return the number of bits that an object of size N bytes is aligned to. */ 2540 2541int 2542i960_object_bytes_bitalign (n) 2543 int n; 2544{ 2545 if (n > 8) n = 128; 2546 else if (n > 4) n = 64; 2547 else if (n > 2) n = 32; 2548 else if (n > 1) n = 16; 2549 else n = 8; 2550 2551 return n; 2552} 2553 2554/* Compute the alignment for an aggregate type TSIZE. 2555 Alignment is MAX (greatest member alignment, 2556 MIN (pragma align, structure size alignment)). */ 2557 2558int 2559i960_round_align (align, tsize) 2560 int align; 2561 tree tsize; 2562{ 2563 int new_align; 2564 2565 if (TREE_CODE (tsize) != INTEGER_CST) 2566 return align; 2567 2568 new_align = i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize) 2569 / BITS_PER_UNIT); 2570 /* Handle #pragma align. */ 2571 if (new_align > i960_maxbitalignment) 2572 new_align = i960_maxbitalignment; 2573 2574 if (align < new_align) 2575 align = new_align; 2576 2577 return align; 2578} 2579 2580/* Do any needed setup for a varargs function. For the i960, we must 2581 create a register parameter block if one doesn't exist, and then copy 2582 all register parameters to memory. */ 2583 2584void 2585i960_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) 2586 CUMULATIVE_ARGS *cum; 2587 enum machine_mode mode; 2588 tree type; 2589 int *pretend_size; 2590 int no_rtl; 2591{ 2592 /* Note: for a varargs fn with only a va_alist argument, this is 0. */ 2593 int first_reg = cum->ca_nregparms; 2594 2595 /* Copy only unnamed register arguments to memory. If there are 2596 any stack parms, there are no unnamed arguments in registers, and 2597 an argument block was already allocated by the caller. 2598 Remember that any arg bigger than 4 words is passed on the stack as 2599 are all subsequent args. 2600 2601 If there are no stack arguments but there are exactly NPARM_REGS 2602 registers, either there were no extra arguments or the caller 2603 allocated an argument block. */ 2604 2605 if (cum->ca_nstackparms == 0 && first_reg < NPARM_REGS && !no_rtl) 2606 { 2607 rtx label = gen_label_rtx (); 2608 rtx regblock; 2609 2610 /* If arg_pointer_rtx == 0, no arguments were passed on the stack 2611 and we need to allocate a chunk to save the registers (if any 2612 arguments were passed on the stack the caller would allocate the 2613 48 bytes as well). We must allocate all 48 bytes (12*4) because 2614 va_start assumes it. */ 2615 emit_insn (gen_cmpsi (arg_pointer_rtx, const0_rtx)); 2616 emit_jump_insn (gen_bne (label)); 2617 emit_insn (gen_rtx (SET, VOIDmode, arg_pointer_rtx, 2618 stack_pointer_rtx)); 2619 emit_insn (gen_rtx (SET, VOIDmode, stack_pointer_rtx, 2620 memory_address (SImode, 2621 plus_constant (stack_pointer_rtx, 2622 48)))); 2623 emit_label (label); 2624 2625 /* ??? Note that we unnecessarily store one extra register for stdarg 2626 fns. We could optimize this, but it's kept as for now. */ 2627 regblock = gen_rtx (MEM, BLKmode, 2628 plus_constant (arg_pointer_rtx, 2629 first_reg * 4)); 2630 move_block_from_reg (first_reg, regblock, 2631 NPARM_REGS - first_reg, 2632 (NPARM_REGS - first_reg) * UNITS_PER_WORD); 2633 } 2634} 2635 2636/* Calculate the final size of the reg parm stack space for the current 2637 function, based on how many bytes would be allocated on the stack. */ 2638 2639int 2640i960_final_reg_parm_stack_space (const_size, var_size) 2641 int const_size; 2642 tree var_size; 2643{ 2644 if (var_size || const_size > 48) 2645 return 48; 2646 else 2647 return 0; 2648} 2649 2650/* Calculate the size of the reg parm stack space. This is a bit complicated 2651 on the i960. */ 2652 2653int 2654i960_reg_parm_stack_space (fndecl) 2655 tree fndecl; 2656{ 2657 /* In this case, we are called from emit_library_call, and we don't need 2658 to pretend we have more space for parameters than what's apparent. */ 2659 if (fndecl == 0) 2660 return 0; 2661 2662 /* In this case, we are called from locate_and_pad_parms when we're 2663 not IN_REGS, so we have an arg block. */ 2664 if (fndecl != current_function_decl) 2665 return 48; 2666 2667 /* Otherwise, we have an arg block if the current function has more than 2668 48 bytes of parameters. */ 2669 if (current_function_args_size != 0 || VARARGS_STDARG_FUNCTION (fndecl)) 2670 return 48; 2671 else 2672 return 0; 2673} 2674 2675/* Return the register class of a scratch register needed to copy IN into 2676 or out of a register in CLASS in MODE. If it can be done directly, 2677 NO_REGS is returned. */ 2678 2679enum reg_class 2680secondary_reload_class (class, mode, in) 2681 enum reg_class class; 2682 enum machine_mode mode; 2683 rtx in; 2684{ 2685 int regno = -1; 2686 2687 if (GET_CODE (in) == REG || GET_CODE (in) == SUBREG) 2688 regno = true_regnum (in); 2689 2690 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put 2691 LOCAL_OR_GLOBAL_REGS into anything. */ 2692 if (class == LOCAL_OR_GLOBAL_REGS || class == LOCAL_REGS 2693 || class == GLOBAL_REGS || (regno >= 0 && regno < 32)) 2694 return NO_REGS; 2695 2696 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */ 2697 if (class == FP_REGS 2698 && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER) 2699 || in == CONST0_RTX (mode) || in == CONST1_RTX (mode))) 2700 return NO_REGS; 2701 2702 return LOCAL_OR_GLOBAL_REGS; 2703} 2704 2705/* Look at the opcode P, and set i96_last_insn_type to indicate which 2706 function unit it executed on. */ 2707 2708/* ??? This would make more sense as an attribute. */ 2709 2710void 2711i960_scan_opcode (p) 2712 char *p; 2713{ 2714 switch (*p) 2715 { 2716 case 'a': 2717 case 'd': 2718 case 'e': 2719 case 'm': 2720 case 'n': 2721 case 'o': 2722 case 'r': 2723 /* Ret is not actually of type REG, but it won't matter, because no 2724 insn will ever follow it. */ 2725 case 'u': 2726 case 'x': 2727 i960_last_insn_type = I_TYPE_REG; 2728 break; 2729 2730 case 'b': 2731 if (p[1] == 'x' || p[3] == 'x') 2732 i960_last_insn_type = I_TYPE_MEM; 2733 i960_last_insn_type = I_TYPE_CTRL; 2734 break; 2735 2736 case 'f': 2737 case 't': 2738 i960_last_insn_type = I_TYPE_CTRL; 2739 break; 2740 2741 case 'c': 2742 if (p[1] == 'a') 2743 { 2744 if (p[4] == 'x') 2745 i960_last_insn_type = I_TYPE_MEM; 2746 else 2747 i960_last_insn_type = I_TYPE_CTRL; 2748 } 2749 else if (p[1] == 'm') 2750 { 2751 if (p[3] == 'd') 2752 i960_last_insn_type = I_TYPE_REG; 2753 else if (p[4] == 'b' || p[4] == 'j') 2754 i960_last_insn_type = I_TYPE_CTRL; 2755 else 2756 i960_last_insn_type = I_TYPE_REG; 2757 } 2758 else 2759 i960_last_insn_type = I_TYPE_REG; 2760 break; 2761 2762 case 'l': 2763 i960_last_insn_type = I_TYPE_MEM; 2764 break; 2765 2766 case 's': 2767 if (p[1] == 't') 2768 i960_last_insn_type = I_TYPE_MEM; 2769 else 2770 i960_last_insn_type = I_TYPE_REG; 2771 break; 2772 } 2773} 2774