1/* Definitions of target machine for GNU compiler, for Intel 860. 2 Copyright (C) 1989, 91, 93, 95, 96, 1997 Free Software Foundation, Inc. 3 Hacked substantially by Ron Guilmette (rfg@monkeys.com) to cater to 4 the whims of the System V Release 4 assembler. 5 6This file is part of GNU CC. 7 8GNU CC is free software; you can redistribute it and/or modify 9it under the terms of the GNU General Public License as published by 10the Free Software Foundation; either version 2, or (at your option) 11any later version. 12 13GNU CC is distributed in the hope that it will be useful, 14but WITHOUT ANY WARRANTY; without even the implied warranty of 15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16GNU General Public License for more details. 17 18You should have received a copy of the GNU General Public License 19along with GNU CC; see the file COPYING. If not, write to 20the Free Software Foundation, 59 Temple Place - Suite 330, 21Boston, MA 02111-1307, USA. */ 22 23 24/* Note that some other tm.h files include this one and then override 25 many of the definitions that relate to assembler syntax. */ 26 27 28/* Names to predefine in the preprocessor for this target machine. */ 29 30#define CPP_PREDEFINES "-Di860 -Dunix -Asystem(unix) -Asystem(svr4) -Acpu(i860) -Amachine(i860)" 31 32/* Print subsidiary information on the compiler version in use. */ 33#define TARGET_VERSION fprintf (stderr, " (i860)"); 34 35/* Run-time compilation parameters selecting different hardware subsets 36 or supersets. 37 38 On the i860, we have one: TARGET_XP. This option allows gcc to generate 39 additional instructions available only on the newer i860 XP (but not on 40 the older i860 XR). 41*/ 42 43extern int target_flags; 44 45/* Nonzero if we should generate code to use the fpu. */ 46#define TARGET_XP (target_flags & 1) 47 48/* Macro to define tables used to set the flags. 49 This is a list in braces of pairs in braces, 50 each pair being { "NAME", VALUE } 51 where VALUE is the bits to set or minus the bits to clear. 52 An empty string NAME is used to identify the default VALUE. */ 53 54#define TARGET_SWITCHES \ 55 { {"xp", 1, "Generate code which uses the FPU"}, \ 56 {"noxp", -1, "Do not generate code which uses the FPU"}, \ 57 {"xr", -1, "Do not generate code which uses the FPU"}, \ 58 { "", TARGET_DEFAULT, NULL}} 59 60#define TARGET_DEFAULT 0 61 62/* target machine storage layout */ 63 64/* Define this if most significant bit is lowest numbered 65 in instructions that operate on numbered bit-fields. 66 This is a moot question on the i860 due to the lack of bit-field insns. */ 67#define BITS_BIG_ENDIAN 0 68 69/* Define this if most significant byte of a word is the lowest numbered. */ 70/* That is not true on i860 in the mode we will use. */ 71#define BYTES_BIG_ENDIAN 0 72 73/* Define this if most significant word of a multiword number is the lowest 74 numbered. */ 75/* For the i860 this goes with BYTES_BIG_ENDIAN. */ 76/* NOTE: GCC probably cannot support a big-endian i860 77 because GCC fundamentally assumes that the order of words 78 in memory as the same as the order in registers. 79 That's not true for the big-endian i860. 80 The big-endian i860 isn't important enough to 81 justify the trouble of changing this assumption. */ 82#define WORDS_BIG_ENDIAN 0 83 84/* number of bits in an addressable storage unit */ 85#define BITS_PER_UNIT 8 86 87/* Width in bits of a "word", which is the contents of a machine register. 88 Note that this is not necessarily the width of data type `int'; 89 if using 16-bit ints on a 68000, this would still be 32. 90 But on a machine with 16-bit registers, this would be 16. */ 91#define BITS_PER_WORD 32 92 93/* Width of a word, in units (bytes). */ 94#define UNITS_PER_WORD 4 95 96/* Width in bits of a pointer. 97 See also the macro `Pmode' defined below. */ 98#define POINTER_SIZE 32 99 100/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 101#define PARM_BOUNDARY 32 102 103/* Boundary (in *bits*) on which stack pointer should be aligned. */ 104#define STACK_BOUNDARY 128 105 106/* Allocation boundary (in *bits*) for the code of a function. */ 107#define FUNCTION_BOUNDARY 64 108 109/* Alignment of field after `int : 0' in a structure. */ 110#define EMPTY_FIELD_BOUNDARY 32 111 112/* Every structure's size must be a multiple of this. */ 113#define STRUCTURE_SIZE_BOUNDARY 8 114 115/* Minimum size in bits of the largest boundary to which any 116 and all fundamental data types supported by the hardware 117 might need to be aligned. No data type wants to be aligned 118 rounder than this. The i860 supports 128-bit (long double) 119 floating point quantities, and the System V Release 4 i860 120 ABI requires these to be aligned to 16-byte (128-bit) 121 boundaries. */ 122#define BIGGEST_ALIGNMENT 128 123 124/* Set this nonzero if move instructions will actually fail to work 125 when given unaligned data. */ 126#define STRICT_ALIGNMENT 1 127 128/* If bit field type is int, dont let it cross an int, 129 and give entire struct the alignment of an int. */ 130#define PCC_BITFIELD_TYPE_MATTERS 1 131 132/* Standard register usage. */ 133 134/* Number of actual hardware registers. 135 The hardware registers are assigned numbers for the compiler 136 from 0 to just below FIRST_PSEUDO_REGISTER. 137 All registers that the compiler knows about must be given numbers, 138 even those that are not normally considered general registers. 139 140 i860 has 32 fullword registers and 32 floating point registers. */ 141 142#define FIRST_PSEUDO_REGISTER 64 143 144/* 1 for registers that have pervasive standard uses 145 and are not available for the register allocator. 146 On the i860, this includes the always-0 registers 147 and fp, sp, arg pointer, and the return address. 148 Also r31, used for special purposes for constant addresses. */ 149#define FIXED_REGISTERS \ 150 {1, 1, 1, 1, 0, 0, 0, 0, \ 151 0, 0, 0, 0, 0, 0, 0, 0, \ 152 0, 0, 0, 0, 0, 0, 0, 0, \ 153 0, 0, 0, 0, 0, 0, 0, 1, \ 154 1, 1, 0, 0, 0, 0, 0, 0, \ 155 0, 0, 0, 0, 0, 0, 0, 0, \ 156 0, 0, 0, 0, 0, 0, 0, 0, \ 157 0, 0, 0, 0, 0, 0, 0, 0} 158 159/* 1 for registers not available across function calls. 160 These must include the FIXED_REGISTERS and also any 161 registers that can be used without being saved. 162 On the i860, these are r0-r3, r16-r31, f0, f1, and f16-f31. */ 163#define CALL_USED_REGISTERS \ 164 {1, 1, 1, 1, 0, 0, 0, 0, \ 165 0, 0, 0, 0, 0, 0, 0, 0, \ 166 1, 1, 1, 1, 1, 1, 1, 1, \ 167 1, 1, 1, 1, 1, 1, 1, 1, \ 168 1, 1, 0, 0, 0, 0, 0, 0, \ 169 1, 1, 1, 1, 1, 1, 1, 1, \ 170 1, 1, 1, 1, 1, 1, 1, 1, \ 171 1, 1, 1, 1, 1, 1, 1, 1} 172 173/* Try to get a non-preserved register before trying to get one we will 174 have to preserve. Try to get an FP register only *after* trying to 175 get a general register, because it is relatively expensive to move 176 into or out of an FP register. */ 177 178#define REG_ALLOC_ORDER \ 179 {31, 30, 29, 28, 27, 26, 25, 24, \ 180 23, 22, 21, 20, 19, 18, 17, 16, \ 181 15, 14, 13, 12, 11, 10, 9, 8, \ 182 7, 6, 5, 4, 3, 2, 1, 0, \ 183 63, 62, 61, 60, 59, 58, 57, 56, \ 184 55, 54, 53, 52, 51, 50, 49, 48, \ 185 47, 46, 45, 44, 43, 42, 41, 40, \ 186 39, 38, 37, 36, 35, 34, 33, 32} 187 188/* Return number of consecutive hard regs needed starting at reg REGNO 189 to hold something of mode MODE. 190 This is ordinarily the length in words of a value of mode MODE 191 but can be less for certain modes in special long registers. 192 193 On the i860, all registers hold 32 bits worth. */ 194#define HARD_REGNO_NREGS(REGNO, MODE) \ 195 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 196 197#define REGNO_MODE_ALIGNED(REGNO, MODE) \ 198 (((REGNO) % ((GET_MODE_UNIT_SIZE (MODE) + 3) / 4)) == 0) 199 200/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 201 202 On the i860, we allow anything to go into any registers, but we require 203 any sort of value going into the FP registers to be properly aligned 204 (based on its size) within the FP register set. 205*/ 206#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 207 (((REGNO) < 32) \ 208 || (MODE) == VOIDmode || (MODE) == BLKmode \ 209 || REGNO_MODE_ALIGNED (REGNO, MODE)) 210 211/* Value is 1 if it is a good idea to tie two pseudo registers 212 when one has mode MODE1 and one has mode MODE2. 213 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 214 for any hard reg, then this must be 0 for correct output. */ 215/* I think that is not always true; alignment restrictions for doubles 216 should not prevent tying them with singles. So try allowing that. 217 On the other hand, don't let fixed and floating be tied; 218 this restriction is not necessary, but may make better code. */ 219#define MODES_TIEABLE_P(MODE1, MODE2) \ 220 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \ 221 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ 222 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \ 223 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)) 224 225/* Specify the registers used for certain standard purposes. 226 The values of these macros are register numbers. */ 227 228/* i860 pc isn't overloaded on a register that the compiler knows about. */ 229/* #define PC_REGNUM */ 230 231/* Register to use for pushing function arguments. */ 232#define STACK_POINTER_REGNUM 2 233 234/* Base register for access to local variables of the function. */ 235#define FRAME_POINTER_REGNUM 3 236 237/* Value should be nonzero if functions must have frame pointers. 238 Zero means the frame pointer need not be set up (and parms 239 may be accessed via the stack pointer) in functions that seem suitable. 240 This is computed in `reload', in reload1.c. */ 241#define FRAME_POINTER_REQUIRED 1 242 243/* Base register for access to arguments of the function. */ 244#define ARG_POINTER_REGNUM 28 245 246/* Register in which static-chain is passed to a function. */ 247#define STATIC_CHAIN_REGNUM 29 248 249/* Register in which address to store a structure value 250 is passed to a function. */ 251#define STRUCT_VALUE_REGNUM 16 252 253/* Register to use when a source of a floating-point zero is needed. */ 254#define F0_REGNUM 32 255 256/* Define the classes of registers for register constraints in the 257 machine description. Also define ranges of constants. 258 259 One of the classes must always be named ALL_REGS and include all hard regs. 260 If there is more than one class, another class must be named NO_REGS 261 and contain no registers. 262 263 The name GENERAL_REGS must be the name of a class (or an alias for 264 another name such as ALL_REGS). This is the class of registers 265 that is allowed by "g" or "r" in a register constraint. 266 Also, registers outside this class are allocated only when 267 instructions express preferences for them. 268 269 The classes must be numbered in nondecreasing order; that is, 270 a larger-numbered class must never be contained completely 271 in a smaller-numbered class. 272 273 For any two classes, it is very desirable that there be another 274 class that represents their union. */ 275 276/* The i860 has two kinds of registers, hence four classes. */ 277 278enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES }; 279 280#define N_REG_CLASSES (int) LIM_REG_CLASSES 281 282/* Give names of register classes as strings for dump file. */ 283 284#define REG_CLASS_NAMES \ 285 {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" } 286 287/* Define which registers fit in which classes. 288 This is an initializer for a vector of HARD_REG_SET 289 of length N_REG_CLASSES. */ 290 291#define REG_CLASS_CONTENTS \ 292 {{0, 0}, {0xffffffff, 0}, \ 293 {0, 0xffffffff}, {0xffffffff, 0xffffffff}} 294 295/* The same information, inverted: 296 Return the class number of the smallest class containing 297 reg number REGNO. This could be a conditional expression 298 or could index an array. */ 299 300#define REGNO_REG_CLASS(REGNO) \ 301 ((REGNO) >= 32 ? FP_REGS : GENERAL_REGS) 302 303/* The class value for index registers, and the one for base regs. */ 304#define INDEX_REG_CLASS GENERAL_REGS 305#define BASE_REG_CLASS GENERAL_REGS 306 307/* Get reg_class from a letter such as appears in the machine description. */ 308 309#define REG_CLASS_FROM_LETTER(C) \ 310 ((C) == 'f' ? FP_REGS : NO_REGS) 311 312/* The letters I, J, K, L and M in a register constraint string 313 can be used to stand for particular ranges of immediate operands. 314 This macro defines what the ranges are. 315 C is the letter, and VALUE is a constant value. 316 Return 1 if VALUE is in the range specified by C. 317 318 For the i860, `I' is used for the range of constants 319 an add/subtract insn can actually contain. 320 But not including -0x8000, since we need 321 to negate the constant sometimes. 322 `J' is used for the range which is just zero (since that is R0). 323 `K' is used for the range allowed in bte. 324 `L' is used for the range allowed in logical insns. */ 325 326#define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x7fff) < 0xffff) 327 328#define LOGIC_INT(X) ((unsigned) INTVAL (X) < 0x10000) 329 330#define SMALL_INTVAL(X) ((unsigned) ((X) + 0x7fff) < 0xffff) 331 332#define LOGIC_INTVAL(X) ((unsigned) (X) < 0x10000) 333 334#define CONST_OK_FOR_LETTER_P(VALUE, C) \ 335 ((C) == 'I' ? ((unsigned) (VALUE) + 0x7fff) < 0xffff \ 336 : (C) == 'J' ? (VALUE) == 0 \ 337 : (C) == 'K' ? (unsigned) (VALUE) < 0x20 \ 338 : (C) == 'L' ? (unsigned) (VALUE) < 0x10000 \ 339 : 0) 340 341/* Return non-zero if the given VALUE is acceptable for the 342 constraint letter C. For the i860, constraint letter 'G' 343 permits only a floating-point zero value. */ 344#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 345 ((C) == 'G' && CONST_DOUBLE_LOW ((VALUE)) == 0 \ 346 && CONST_DOUBLE_HIGH ((VALUE)) == 0) 347 348/* Given an rtx X being reloaded into a reg required to be 349 in class CLASS, return the class of reg to actually use. 350 In general this is just CLASS; but on some machines 351 in some cases it is preferable to use a more restrictive class. 352 353 If we are trying to put an integer constant into some register, prefer an 354 integer register to an FP register. If we are trying to put a 355 non-zero floating-point constant into some register, use an integer 356 register if the constant is SFmode and GENERAL_REGS is one of our options. 357 Otherwise, put the constant into memory. 358 359 When reloading something smaller than a word, use a general reg 360 rather than an FP reg. */ 361 362#define PREFERRED_RELOAD_CLASS(X,CLASS) \ 363 ((CLASS) == ALL_REGS && GET_CODE (X) == CONST_INT ? GENERAL_REGS \ 364 : ((GET_MODE (X) == HImode || GET_MODE (X) == QImode) \ 365 && (CLASS) == ALL_REGS) \ 366 ? GENERAL_REGS \ 367 : (GET_CODE (X) == CONST_DOUBLE \ 368 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ 369 && ! CONST_DOUBLE_OK_FOR_LETTER_P (X, 'G')) \ 370 ? ((CLASS) == ALL_REGS && GET_MODE (X) == SFmode ? GENERAL_REGS \ 371 : (CLASS) == GENERAL_REGS && GET_MODE (X) == SFmode ? (CLASS) \ 372 : NO_REGS) \ 373 : (CLASS)) 374 375/* Return the register class of a scratch register needed to copy IN into 376 a register in CLASS in MODE. If it can be done directly, NO_REGS is 377 returned. */ 378 379#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \ 380 ((CLASS) == FP_REGS && CONSTANT_P (IN) ? GENERAL_REGS : NO_REGS) 381 382/* Return the maximum number of consecutive registers 383 needed to represent mode MODE in a register of class CLASS. */ 384/* On the i860, this is the size of MODE in words. */ 385#define CLASS_MAX_NREGS(CLASS, MODE) \ 386 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 387 388/* Stack layout; function entry, exit and calling. */ 389 390/* Define this if pushing a word on the stack 391 makes the stack pointer a smaller address. */ 392#define STACK_GROWS_DOWNWARD 393 394/* Define this if the nominal address of the stack frame 395 is at the high-address end of the local variables; 396 that is, each additional local variable allocated 397 goes at a more negative offset in the frame. */ 398#define FRAME_GROWS_DOWNWARD 399 400/* Offset within stack frame to start allocating local variables at. 401 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 402 first local allocated. Otherwise, it is the offset to the BEGINNING 403 of the first local allocated. */ 404#define STARTING_FRAME_OFFSET 0 405 406/* If we generate an insn to push BYTES bytes, 407 this says how many the stack pointer really advances by. 408 On the i860, don't define this because there are no push insns. */ 409/* #define PUSH_ROUNDING(BYTES) */ 410 411/* Offset of first parameter from the argument pointer register value. */ 412#define FIRST_PARM_OFFSET(FNDECL) 0 413 414/* Value is the number of bytes of arguments automatically 415 popped when returning from a subroutine call. 416 FUNDECL is the declaration node of the function (as a tree), 417 FUNTYPE is the data type of the function (as a tree), 418 or for a library call it is an identifier node for the subroutine name. 419 SIZE is the number of bytes of arguments passed on the stack. */ 420 421#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 422 423/* Define how to find the value returned by a function. 424 VALTYPE is the data type of the value (as a tree). 425 If the precise function being called is known, FUNC is its FUNCTION_DECL; 426 otherwise, FUNC is 0. */ 427 428/* On the i860, the value register depends on the mode. */ 429 430#define FUNCTION_VALUE(VALTYPE, FUNC) \ 431 gen_rtx (REG, TYPE_MODE (VALTYPE), \ 432 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \ 433 ? 40 : 16)) 434 435/* Define how to find the value returned by a library function 436 assuming the value has mode MODE. */ 437 438#define LIBCALL_VALUE(MODE) \ 439 gen_rtx (REG, MODE, \ 440 (GET_MODE_CLASS ((MODE)) == MODE_FLOAT \ 441 ? 40 : 16)) 442 443/* 1 if N is a possible register number for a function value 444 as seen by the caller. */ 445 446#define FUNCTION_VALUE_REGNO_P(N) ((N) == 40 || (N) == 16) 447 448/* 1 if N is a possible register number for function argument passing. 449 On the i860, these are r16-r27 and f8-f15. */ 450 451#define FUNCTION_ARG_REGNO_P(N) \ 452 (((N) < 28 && (N) > 15) || ((N) < 48 && (N) >= 40)) 453 454/* Define a data type for recording info about an argument list 455 during the scan of that argument list. This data type should 456 hold all necessary information about the function itself 457 and about the args processed so far, enough to enable macros 458 such as FUNCTION_ARG to determine where the next arg should go. 459 460 On the i860, we must count separately the number of general registers used 461 and the number of float registers used. */ 462 463struct cumulative_args { int ints, floats; }; 464#define CUMULATIVE_ARGS struct cumulative_args 465 466/* Initialize a variable CUM of type CUMULATIVE_ARGS 467 for a call to a function whose data type is FNTYPE. 468 For a library call, FNTYPE is 0. 469 470 On the i860, the general-reg offset normally starts at 0, 471 but starts at 4 bytes 472 when the function gets a structure-value-address as an 473 invisible first argument. */ 474 475#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ 476 ((CUM).ints = ((FNTYPE) != 0 && aggregate_value_p (TREE_TYPE ((FNTYPE))) \ 477 ? 4 : 0), \ 478 (CUM).floats = 0) 479 480/* Machine-specific subroutines of the following macros. */ 481#define CEILING(X,Y) (((X) + (Y) - 1) / (Y)) 482#define ROUNDUP(X,Y) (CEILING ((X), (Y)) * (Y)) 483 484/* Update the data in CUM to advance over an argument 485 of mode MODE and data type TYPE. 486 (TYPE is null for libcalls where that information may not be available.) 487 Floats, and doubleword ints, are returned in f regs; 488 other ints, in r regs. 489 Aggregates, even short ones, are passed in memory. */ 490 491#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 492 ((TYPE) != 0 && (TREE_CODE ((TYPE)) == RECORD_TYPE \ 493 || TREE_CODE ((TYPE)) == UNION_TYPE) \ 494 ? 0 \ 495 : GET_MODE_CLASS ((MODE)) == MODE_FLOAT || (MODE) == DImode \ 496 ? ((CUM).floats = (ROUNDUP ((CUM).floats, GET_MODE_SIZE ((MODE))) \ 497 + ROUNDUP (GET_MODE_SIZE (MODE), 4))) \ 498 : GET_MODE_CLASS ((MODE)) == MODE_INT \ 499 ? ((CUM).ints = (ROUNDUP ((CUM).ints, GET_MODE_SIZE ((MODE))) \ 500 + ROUNDUP (GET_MODE_SIZE (MODE), 4))) \ 501 : 0) 502 503/* Determine where to put an argument to a function. 504 Value is zero to push the argument on the stack, 505 or a hard register in which to store the argument. 506 507 MODE is the argument's machine mode. 508 TYPE is the data type of the argument (as a tree). 509 This is null for libcalls where that information may 510 not be available. 511 CUM is a variable of type CUMULATIVE_ARGS which gives info about 512 the preceding args and about the function being called. 513 NAMED is nonzero if this argument is a named parameter 514 (otherwise it is an extra parameter matching an ellipsis). */ 515 516/* On the i860, the first 12 words of integer arguments go in r16-r27, 517 and the first 8 words of floating arguments go in f8-f15. 518 DImode values are treated as floats. */ 519 520#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 521 ((TYPE) != 0 && (TREE_CODE ((TYPE)) == RECORD_TYPE \ 522 || TREE_CODE ((TYPE)) == UNION_TYPE) \ 523 ? 0 \ 524 : GET_MODE_CLASS ((MODE)) == MODE_FLOAT || (MODE) == DImode \ 525 ? (ROUNDUP ((CUM).floats, GET_MODE_SIZE ((MODE))) < 32 \ 526 ? gen_rtx (REG, (MODE), \ 527 40+(ROUNDUP ((CUM).floats, \ 528 GET_MODE_SIZE ((MODE))) \ 529 / 4)) \ 530 : 0) \ 531 : GET_MODE_CLASS ((MODE)) == MODE_INT \ 532 ? (ROUNDUP ((CUM).ints, GET_MODE_SIZE ((MODE))) < 48 \ 533 ? gen_rtx (REG, (MODE), \ 534 16+(ROUNDUP ((CUM).ints, \ 535 GET_MODE_SIZE ((MODE))) \ 536 / 4)) \ 537 : 0) \ 538 : 0) 539 540/* For an arg passed partly in registers and partly in memory, 541 this is the number of registers used. 542 For args passed entirely in registers or entirely in memory, zero. */ 543 544#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 545 546/* If defined, a C expression that gives the alignment boundary, in 547 bits, of an argument with the specified mode and type. If it is 548 not defined, `PARM_BOUNDARY' is used for all arguments. */ 549 550#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 551 (((TYPE) != 0) \ 552 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \ 553 ? PARM_BOUNDARY \ 554 : TYPE_ALIGN(TYPE)) \ 555 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \ 556 ? PARM_BOUNDARY \ 557 : GET_MODE_ALIGNMENT(MODE))) 558 559/* This macro generates the assembly code for function entry. 560 561 FILE is a stdio stream to output the code to. 562 SIZE is an int: how many units of temporary storage to allocate. 563*/ 564 565#define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue ((FILE), (SIZE)) 566 567/* Output a no-op just before the beginning of the function, 568 to ensure that there does not appear to be a delayed branch there. 569 Such a thing would confuse interrupt recovery. */ 570#define ASM_OUTPUT_FUNCTION_PREFIX(FILE,NAME) \ 571 fprintf (FILE, "\tnop\n") 572 573/* Output assembler code to FILE to increment profiler label # LABELNO 574 for profiling a function entry. */ 575 576#define FUNCTION_PROFILER(FILE, LABELNO) \ 577 abort (); 578 579/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 580 the stack pointer does not matter. The value is tested only in 581 functions that have frame pointers. 582 No definition is equivalent to always zero. */ 583 584#define EXIT_IGNORE_STACK 1 585 586/* This macro generates the assembly code for function exit. 587 588 FILE is a stdio stream to output the code to. 589 SIZE is an int: how many units of temporary storage to allocate. 590 591 The function epilogue should not depend on the current stack pointer! 592 It should use the frame pointer only. This is mandatory because 593 of alloca; we also take advantage of it to omit stack adjustments 594 before returning. 595*/ 596 597#define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue ((FILE), (SIZE)) 598 599/* Store in the variable DEPTH the initial difference between the 600 frame pointer reg contents and the stack pointer reg contents, 601 as of the start of the function body. This depends on the layout 602 of the fixed parts of the stack frame and on how registers are saved. 603 604 On the i860, FRAME_POINTER_REQUIRED is always 1, so the definition of this 605 macro doesn't matter. But it must be defined. */ 606 607#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ 608 do { (DEPTH) = 0; } while (0) 609 610/* Output assembler code for a block containing the constant parts 611 of a trampoline, leaving space for the variable parts. */ 612 613/* On the i860, the trampoline contains five instructions: 614 orh #TOP_OF_FUNCTION,r0,r31 615 or #BOTTOM_OF_FUNCTION,r31,r31 616 orh #TOP_OF_STATIC,r0,r29 617 bri r31 618 or #BOTTOM_OF_STATIC,r29,r29 */ 619#define TRAMPOLINE_TEMPLATE(FILE) \ 620{ \ 621 ASM_OUTPUT_INT (FILE, GEN_INT (0xec1f0000)); \ 622 ASM_OUTPUT_INT (FILE, GEN_INT (0xe7ff0000)); \ 623 ASM_OUTPUT_INT (FILE, GEN_INT (0xec1d0000)); \ 624 ASM_OUTPUT_INT (FILE, GEN_INT (0x4000f800)); \ 625 ASM_OUTPUT_INT (FILE, GEN_INT (0xe7bd0000)); \ 626} 627 628/* Length in units of the trampoline for entering a nested function. */ 629 630#define TRAMPOLINE_SIZE 20 631 632/* Emit RTL insns to initialize the variable parts of a trampoline. 633 FNADDR is an RTX for the address of the function's pure code. 634 CXT is an RTX for the static chain value for the function. 635 636 Store hi function at +0, low function at +4, 637 hi static at +8, low static at +16 */ 638 639#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 640{ \ 641 rtx cxt = force_reg (Pmode, CXT); \ 642 rtx fn = force_reg (Pmode, FNADDR); \ 643 rtx hi_cxt = expand_shift (RSHIFT_EXPR, SImode, cxt, \ 644 size_int (16), 0, 0); \ 645 rtx hi_fn = expand_shift (RSHIFT_EXPR, SImode, fn, \ 646 size_int (16), 0, 0); \ 647 emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 16)), \ 648 gen_lowpart (HImode, cxt)); \ 649 emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 4)), \ 650 gen_lowpart (HImode, fn)); \ 651 emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 8)), \ 652 gen_lowpart (HImode, hi_cxt)); \ 653 emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 0)), \ 654 gen_lowpart (HImode, hi_fn)); \ 655} 656 657/* Addressing modes, and classification of registers for them. */ 658 659/* #define HAVE_POST_INCREMENT 0 */ 660/* #define HAVE_POST_DECREMENT 0 */ 661 662/* #define HAVE_PRE_DECREMENT 0 */ 663/* #define HAVE_PRE_INCREMENT 0 */ 664 665/* Macros to check register numbers against specific register classes. */ 666 667/* These assume that REGNO is a hard or pseudo reg number. 668 They give nonzero only if REGNO is a hard reg of the suitable class 669 or a pseudo reg currently allocated to a suitable hard reg. 670 Since they use reg_renumber, they are safe only once reg_renumber 671 has been allocated, which happens in local-alloc.c. */ 672 673#define REGNO_OK_FOR_INDEX_P(REGNO) \ 674((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) 675#define REGNO_OK_FOR_BASE_P(REGNO) \ 676((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) 677#define REGNO_OK_FOR_FP_P(REGNO) \ 678(((REGNO) ^ 0x20) < 32 || (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32) 679 680/* Now macros that check whether X is a register and also, 681 strictly, whether it is in a specified class. 682 683 These macros are specific to the i860, and may be used only 684 in code for printing assembler insns and in conditions for 685 define_optimization. */ 686 687/* 1 if X is an fp register. */ 688 689#define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) 690 691/* Maximum number of registers that can appear in a valid memory address. */ 692 693#define MAX_REGS_PER_ADDRESS 2 694 695/* Recognize any constant value that is a valid address. */ 696 697#define CONSTANT_ADDRESS_P(X) \ 698 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 699 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 700 || GET_CODE (X) == HIGH) 701 702/* Nonzero if the constant value X is a legitimate general operand. 703 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. 704 705 On the Sparc, this is anything but a CONST_DOUBLE. 706 Let's try permitting CONST_DOUBLEs and see what happens. */ 707 708#define LEGITIMATE_CONSTANT_P(X) 1 709 710/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 711 and check its validity for a certain class. 712 We have two alternate definitions for each of them. 713 The usual definition accepts all pseudo regs; the other rejects 714 them unless they have been allocated suitable hard regs. 715 The symbol REG_OK_STRICT causes the latter definition to be used. 716 717 Most source files want to accept pseudo regs in the hope that 718 they will get allocated to the class that the insn wants them to be in. 719 Source files for reload pass need to be strict. 720 After reload, it makes no difference, since pseudo regs have 721 been eliminated by then. */ 722 723#ifndef REG_OK_STRICT 724 725/* Nonzero if X is a hard reg that can be used as an index 726 or if it is a pseudo reg. */ 727#define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 14) 728/* Nonzero if X is a hard reg that can be used as a base reg 729 or if it is a pseudo reg. */ 730#define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 14) 731 732#else 733 734/* Nonzero if X is a hard reg that can be used as an index. */ 735#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 736/* Nonzero if X is a hard reg that can be used as a base reg. */ 737#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 738 739#endif 740 741/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 742 that is a valid memory address for an instruction. 743 The MODE argument is the machine mode for the MEM expression 744 that wants to use this address. 745 746 On the i860, the actual addresses must be REG+REG or REG+SMALLINT. 747 But we can treat a SYMBOL_REF as legitimate if it is part of this 748 function's constant-pool, because such addresses can actually 749 be output as REG+SMALLINT. 750 751 The displacement in an address must be a multiple of the alignment. 752 753 Try making SYMBOL_REF (and other things which are CONSTANT_ADDRESS_P) 754 a legitimate address, regardless. Because the only insns which can use 755 memory are load or store insns, the added hair in the machine description 756 is not that bad. It should also speed up the compiler by halving the number 757 of insns it must manage for each (MEM (SYMBOL_REF ...)) involved. */ 758 759#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 760{ if (GET_CODE (X) == REG) \ 761 { if (REG_OK_FOR_BASE_P (X)) goto ADDR; } \ 762 else if (GET_CODE (X) == PLUS) \ 763 { \ 764 if (GET_CODE (XEXP (X, 0)) == REG \ 765 && REG_OK_FOR_BASE_P (XEXP (X, 0))) \ 766 { \ 767 if (GET_CODE (XEXP (X, 1)) == CONST_INT \ 768 && INTVAL (XEXP (X, 1)) >= -0x8000 \ 769 && INTVAL (XEXP (X, 1)) < 0x8000 \ 770 && (INTVAL (XEXP (X, 1)) & (GET_MODE_SIZE (MODE) - 1)) == 0) \ 771 goto ADDR; \ 772 } \ 773 else if (GET_CODE (XEXP (X, 1)) == REG \ 774 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \ 775 { \ 776 if (GET_CODE (XEXP (X, 0)) == CONST_INT \ 777 && INTVAL (XEXP (X, 0)) >= -0x8000 \ 778 && INTVAL (XEXP (X, 0)) < 0x8000 \ 779 && (INTVAL (XEXP (X, 0)) & (GET_MODE_SIZE (MODE) - 1)) == 0) \ 780 goto ADDR; \ 781 } \ 782 } \ 783 else if (CONSTANT_ADDRESS_P (X)) \ 784 goto ADDR; \ 785} 786 787/* Try machine-dependent ways of modifying an illegitimate address 788 to be legitimate. If we find one, return the new, valid address. 789 This macro is used in only one place: `memory_address' in explow.c. 790 791 OLDX is the address as it was before break_out_memory_refs was called. 792 In some cases it is useful to look at this to decide what needs to be done. 793 794 MODE and WIN are passed so that this macro can use 795 GO_IF_LEGITIMATE_ADDRESS. 796 797 It is always safe for this macro to do nothing. It exists to recognize 798 opportunities to optimize the output. */ 799 800/* On the i860, change COMPLICATED + CONSTANT to REG+CONSTANT. 801 Also change a symbolic constant to a REG, 802 though that may not be necessary. */ 803 804#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 805{ if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \ 806 (X) = gen_rtx (PLUS, SImode, XEXP (X, 1), \ 807 force_operand (XEXP (X, 0), 0)); \ 808 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \ 809 (X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \ 810 force_operand (XEXP (X, 1), 0)); \ 811 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \ 812 (X) = gen_rtx (PLUS, SImode, XEXP (X, 1), \ 813 force_operand (XEXP (X, 0), 0)); \ 814 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \ 815 (X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \ 816 force_operand (XEXP (X, 1), 0)); \ 817 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) != REG \ 818 && GET_CODE (XEXP (X, 0)) != CONST_INT) \ 819 (X) = gen_rtx (PLUS, SImode, XEXP (X, 1), \ 820 copy_to_mode_reg (SImode, XEXP (X, 0))); \ 821 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) != REG \ 822 && GET_CODE (XEXP (X, 1)) != CONST_INT) \ 823 (X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \ 824 copy_to_mode_reg (SImode, XEXP (X, 1))); \ 825 if (GET_CODE (x) == SYMBOL_REF) \ 826 (X) = copy_to_reg (X); \ 827 if (GET_CODE (x) == CONST) \ 828 (X) = copy_to_reg (X); \ 829 if (memory_address_p (MODE, X)) \ 830 goto WIN; } 831 832/* Go to LABEL if ADDR (a legitimate address expression) 833 has an effect that depends on the machine mode it is used for. 834 On the i860 this is never true. 835 There are some addresses that are invalid in wide modes 836 but valid for narrower modes, but they shouldn't affect 837 the places that use this macro. */ 838 839#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) 840 841/* Specify the machine mode that this machine uses 842 for the index in the tablejump instruction. */ 843#define CASE_VECTOR_MODE SImode 844 845/* Define as C expression which evaluates to nonzero if the tablejump 846 instruction expects the table to contain offsets from the address of the 847 table. 848 Do not define this if the table should contain absolute addresses. */ 849/* #define CASE_VECTOR_PC_RELATIVE 1 */ 850 851/* Specify the tree operation to be used to convert reals to integers. */ 852#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR 853 854/* This is the kind of divide that is easiest to do in the general case. */ 855#define EASY_DIV_EXPR TRUNC_DIV_EXPR 856 857/* Must pass floats to libgcc functions as doubles. */ 858#define LIBGCC_NEEDS_DOUBLE 1 859 860#define DIVSI3_LIBCALL "*.div" 861#define UDIVSI3_LIBCALL "*.udiv" 862#define REMSI3_LIBCALL "*.rem" 863#define UREMSI3_LIBCALL "*.urem" 864 865/* Define this as 1 if `char' should by default be signed; else as 0. */ 866#define DEFAULT_SIGNED_CHAR 1 867 868/* Max number of bytes we can move from memory to memory 869 in one reasonably fast instruction. */ 870#define MOVE_MAX 16 871 872/* Nonzero if access to memory by bytes is slow and undesirable. */ 873#define SLOW_BYTE_ACCESS 0 874 875/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 876 is done just by pretending it is already truncated. */ 877#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 878 879/* Value is 1 if it generates better code to perform an unsigned comparison 880 on the given literal integer value in the given mode when we are only 881 looking for an equal/non-equal result. */ 882/* For the i860, if the immediate value has its high-order 27 bits zero, 883 then we want to engineer an unsigned comparison for EQ/NE because 884 such values can fit in the 5-bit immediate field of a bte or btne 885 instruction (which gets zero extended before comparing). For all 886 other immediate values on the i860, we will use signed compares 887 because that avoids the need for doing explicit xor's to zero_extend 888 the non-constant operand in cases where it was (mem:QI ...) or a 889 (mem:HI ...) which always gets automatically sign-extended by the 890 hardware upon loading. */ 891 892#define LITERAL_COMPARE_BETTER_UNSIGNED(intval, mode) \ 893 (((unsigned) (intval) & 0x1f) == (unsigned) (intval)) 894 895/* Specify the machine mode that pointers have. 896 After generation of rtl, the compiler makes no further distinction 897 between pointers and any other objects of this machine mode. */ 898#define Pmode SImode 899 900/* A function address in a call instruction 901 is a byte address (for indexing purposes) 902 so give the MEM rtx a byte's mode. */ 903#define FUNCTION_MODE SImode 904 905/* Define this if addresses of constant functions 906 shouldn't be put through pseudo regs where they can be cse'd. 907 Desirable on machines where ordinary constants are expensive 908 but a CALL with constant address is cheap. */ 909#define NO_FUNCTION_CSE 910 911/* Compute the cost of computing a constant rtl expression RTX 912 whose rtx-code is CODE. The body of this macro is a portion 913 of a switch statement. If the code is computed here, 914 return it with a return statement. Otherwise, break from the switch. */ 915 916#define CONST_COSTS(RTX,CODE, OUTER_CODE) \ 917 case CONST_INT: \ 918 if (INTVAL (RTX) == 0) \ 919 return 0; \ 920 if (INTVAL (RTX) < 0x2000 && INTVAL (RTX) >= -0x2000) return 1; \ 921 case CONST: \ 922 case LABEL_REF: \ 923 case SYMBOL_REF: \ 924 return 4; \ 925 case CONST_DOUBLE: \ 926 return 6; 927 928/* Specify the cost of a branch insn; roughly the number of extra insns that 929 should be added to avoid a branch. 930 931 Set this to 3 on the i860 since branches may often take three cycles. */ 932 933#define BRANCH_COST 3 934 935/* Tell final.c how to eliminate redundant test instructions. */ 936 937/* Here we define machine-dependent flags and fields in cc_status 938 (see `conditions.h'). */ 939 940/* This holds the value sourcing h%r31. We keep this info 941 around so that mem/mem ops, such as increment and decrement, 942 etc, can be performed reasonably. */ 943#define CC_STATUS_MDEP rtx 944 945#define CC_STATUS_MDEP_INIT (cc_status.mdep = 0) 946 947#define CC_NEGATED 01000 948 949/* We use this macro in those places in the i860.md file where we would 950 normally just do a CC_STATUS_INIT (for other machines). This macro 951 differs from CC_STATUS_INIT in that it doesn't mess with the special 952 bits or fields which describe what is currently in the special r31 953 scratch register, but it does clear out everything that actually 954 relates to the condition code bit of the i860. */ 955 956#define CC_STATUS_PARTIAL_INIT \ 957 (cc_status.flags &= (CC_KNOW_HI_R31 | CC_HI_R31_ADJ), \ 958 cc_status.value1 = 0, \ 959 cc_status.value2 = 0) 960 961/* Nonzero if we know the value of h%r31. */ 962#define CC_KNOW_HI_R31 0100000 963 964/* Nonzero if h%r31 is actually ha%something, rather than h%something. */ 965#define CC_HI_R31_ADJ 0200000 966 967/* Store in cc_status the expressions 968 that the condition codes will describe 969 after execution of an instruction whose pattern is EXP. 970 Do not alter them if the instruction would not alter the cc's. */ 971 972/* On the i860, only compare insns set a useful condition code. */ 973 974#define NOTICE_UPDATE_CC(EXP, INSN) \ 975{ cc_status.flags &= (CC_KNOW_HI_R31 | CC_HI_R31_ADJ); \ 976 cc_status.value1 = 0; cc_status.value2 = 0; } 977 978/* Control the assembler format that we output. */ 979 980/* Assembler pseudos to introduce constants of various size. */ 981 982#define ASM_BYTE_OP "\t.byte" 983#define ASM_SHORT "\t.short" 984#define ASM_LONG "\t.long" 985#define ASM_DOUBLE "\t.double" 986 987/* Output at beginning of assembler file. */ 988/* The .file command should always begin the output. */ 989 990#define ASM_FILE_START(FILE) 991#if 0 992#define ASM_FILE_START(FILE) \ 993 do { output_file_directive ((FILE), main_input_filename); \ 994 if (optimize) ASM_FILE_START_1 (FILE); \ 995 } while (0) 996#endif 997 998#define ASM_FILE_START_1(FILE) 999 1000/* Output to assembler file text saying following lines 1001 may contain character constants, extra white space, comments, etc. */ 1002 1003#define ASM_APP_ON "" 1004 1005/* Output to assembler file text saying following lines 1006 no longer contain unusual constructs. */ 1007 1008#define ASM_APP_OFF "" 1009 1010/* Output before read-only data. */ 1011 1012#define TEXT_SECTION_ASM_OP ".text" 1013 1014/* Output before writable data. */ 1015 1016#define DATA_SECTION_ASM_OP ".data" 1017 1018/* How to refer to registers in assembler output. 1019 This sequence is indexed by compiler's hard-register-number (see above). */ 1020 1021#define REGISTER_NAMES \ 1022{"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7", "r8", "r9", \ 1023 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \ 1024 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \ 1025 "r30", "r31", \ 1026 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \ 1027 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \ 1028 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \ 1029 "f30", "f31" } 1030 1031/* How to renumber registers for dbx and gdb. */ 1032 1033#define DBX_REGISTER_NUMBER(REGNO) (REGNO) 1034 1035/* This is how to output the definition of a user-level label named NAME, 1036 such as the label on a static function or variable NAME. */ 1037 1038#define ASM_OUTPUT_LABEL(FILE,NAME) \ 1039 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) 1040 1041/* This is how to output a command to make the user-level label named NAME 1042 defined for reference from other files. */ 1043 1044#define ASM_GLOBALIZE_LABEL(FILE,NAME) \ 1045 do { fputs (".globl ", FILE); \ 1046 assemble_name (FILE, NAME); \ 1047 fputs ("\n", FILE); \ 1048 } while (0) 1049 1050/* The prefix to add to user-visible assembler symbols. 1051 1052 This definition is overridden in i860v4.h because under System V 1053 Release 4, user-level symbols are *not* prefixed with underscores in 1054 the generated assembly code. */ 1055 1056#define USER_LABEL_PREFIX "_" 1057 1058/* This is how to output an internal numbered label where 1059 PREFIX is the class of label and NUM is the number within the class. */ 1060 1061#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ 1062 fprintf (FILE, ".%s%d:\n", PREFIX, NUM) 1063 1064/* This is how to output an internal numbered label which 1065 labels a jump table. */ 1066 1067#undef ASM_OUTPUT_CASE_LABEL 1068#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \ 1069do { ASM_OUTPUT_ALIGN ((FILE), 2); \ 1070 ASM_OUTPUT_INTERNAL_LABEL ((FILE), PREFIX, NUM); \ 1071 } while (0) 1072 1073/* Output at the end of a jump table. */ 1074 1075#define ASM_OUTPUT_CASE_END(FILE,NUM,INSN) \ 1076 fprintf (FILE, ".text\n") 1077 1078/* This is how to store into the string LABEL 1079 the symbol_ref name of an internal numbered label where 1080 PREFIX is the class of label and NUM is the number within the class. 1081 This is suitable for output with `assemble_name'. */ 1082 1083#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 1084 sprintf (LABEL, "*.%s%d", PREFIX, NUM) 1085 1086/* This is how to output an assembler line defining a `double' constant. */ 1087 1088#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ 1089 fprintf (FILE, "\t.double %.20e\n", (VALUE)) 1090 1091/* This is how to output an assembler line defining a `float' constant. */ 1092 1093#define ASM_OUTPUT_FLOAT(FILE,VALUE) \ 1094 fprintf (FILE, "\t.float %.12e\n", (VALUE)) 1095 1096/* This is how to output an assembler line defining an `int' constant. */ 1097 1098#define ASM_OUTPUT_INT(FILE,VALUE) \ 1099( fprintf (FILE, "\t.long "), \ 1100 output_addr_const (FILE, (VALUE)), \ 1101 fprintf (FILE, "\n")) 1102 1103/* Likewise for `char' and `short' constants. */ 1104 1105#define ASM_OUTPUT_SHORT(FILE,VALUE) \ 1106( fprintf (FILE, "\t.short "), \ 1107 output_addr_const (FILE, (VALUE)), \ 1108 fprintf (FILE, "\n")) 1109 1110#define ASM_OUTPUT_CHAR(FILE,VALUE) \ 1111( fprintf (FILE, "\t.byte "), \ 1112 output_addr_const (FILE, (VALUE)), \ 1113 fprintf (FILE, "\n")) 1114 1115/* This is how to output an assembler line for a numeric constant byte. */ 1116 1117#define ASM_OUTPUT_BYTE(FILE,VALUE) \ 1118 fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) 1119 1120/* This is how to output code to push a register on the stack. 1121 It need not be very fast code. */ 1122 1123#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ 1124 fprintf (FILE, "\taddu -16,%ssp,%ssp\n\t%sst.l %s%s,0(%ssp)\n", \ 1125 i860_reg_prefix, i860_reg_prefix, \ 1126 ((REGNO) < 32 ? "" : "f"), \ 1127 i860_reg_prefix, reg_names[REGNO], \ 1128 i860_reg_prefix) 1129 1130/* This is how to output an insn to pop a register from the stack. 1131 It need not be very fast code. */ 1132 1133#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ 1134 fprintf (FILE, "\t%sld.l 0(%ssp),%s%s\n\taddu 16,%ssp,%ssp\n", \ 1135 ((REGNO) < 32 ? "" : "f"), \ 1136 i860_reg_prefix, \ 1137 i860_reg_prefix, reg_names[REGNO], \ 1138 i860_reg_prefix, i860_reg_prefix) 1139 1140/* This is how to output an element of a case-vector that is absolute. */ 1141 1142#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1143 fprintf (FILE, "\t.long .L%d\n", VALUE) 1144 1145/* This is how to output an element of a case-vector that is relative. 1146 (The i860 does not use such vectors, 1147 but we must define this macro anyway.) */ 1148 1149#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1150 fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL) 1151 1152/* This is how to output an assembler line 1153 that says to advance the location counter 1154 to a multiple of 2**LOG bytes. */ 1155 1156#define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1157 if ((LOG) != 0) \ 1158 fprintf (FILE, "\t.align %d\n", 1 << (LOG)) 1159 1160#define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1161 fprintf (FILE, "\t.blkb %u\n", (SIZE)) 1162 1163/* This says how to output an assembler line 1164 to define a global common symbol. */ 1165 1166#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1167( fputs (".comm ", (FILE)), \ 1168 assemble_name ((FILE), (NAME)), \ 1169 fprintf ((FILE), ",%u\n", (ROUNDED))) 1170 1171/* This says how to output an assembler line 1172 to define a local common symbol. */ 1173 1174#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 1175( fputs (".lcomm ", (FILE)), \ 1176 assemble_name ((FILE), (NAME)), \ 1177 fprintf ((FILE), ",%u\n", (ROUNDED))) 1178 1179/* Store in OUTPUT a string (made with alloca) containing 1180 an assembler-name for a local static variable named NAME. 1181 LABELNO is an integer which is different for each call. */ 1182 1183#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 1184( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 1185 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) 1186 1187/* Define the parentheses used to group arithmetic operations 1188 in assembler code. */ 1189 1190#define ASM_OPEN_PAREN "(" 1191#define ASM_CLOSE_PAREN ")" 1192 1193/* Define results of standard character escape sequences. */ 1194#define TARGET_BELL 007 1195#define TARGET_BS 010 1196#define TARGET_TAB 011 1197#define TARGET_NEWLINE 012 1198#define TARGET_VT 013 1199#define TARGET_FF 014 1200#define TARGET_CR 015 1201 1202/* Print operand X (an rtx) in assembler syntax to file FILE. 1203 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 1204 For `%' followed by punctuation, CODE is the punctuation and X is null. 1205 1206 In the following comments, the term "constant address" is used frequently. 1207 For an exact definition of what constitutes a "constant address" see the 1208 output_addr_const routine in final.c 1209 1210 On the i860, the following target-specific special codes are recognized: 1211 1212 `r' The operand can be anything, but if it is an immediate zero 1213 value (either integer or floating point) then it will be 1214 represented as `r0' or as `f0' (respectively). 1215 1216 `m' The operand is a memory ref (to a constant address) but print 1217 its address as a constant. 1218 1219 `L' The operand is a numeric constant, a constant address, or 1220 a memory ref to a constant address. Print the correct 1221 notation to yield the low part of the given value or 1222 address or the low part of the address of the referred 1223 to memory object. 1224 1225 `H' The operand is a numeric constant, a constant address, or 1226 a memory ref to a constant address. Print the correct 1227 notation to yield the high part of the given value or 1228 address or the high part of the address of the referred 1229 to memory object. 1230 1231 `h' The operand is a numeric constant, a constant address, or 1232 a memory ref to a constant address. Either print the 1233 correct notation to yield the plain high part of the 1234 given value or address (or the plain high part of the 1235 address of the memory object) or else print the correct 1236 notation to yield the "adjusted" high part of the given 1237 address (or of the address of the referred to memory object). 1238 1239 The choice of what to print depends upon whether the address 1240 in question is relocatable or not. If it is relocatable, 1241 print the notation to get the adjusted high part. Otherwise 1242 just print the notation to get the plain high part. Note 1243 that "adjusted" high parts are generally used *only* when 1244 the next following instruction uses the low part of the 1245 address as an offset, as in `offset(reg)'. 1246 1247 `R' The operand is a floating-pointer register. Print the 1248 name of the next following (32-bit) floating-point register. 1249 (This is used when moving a value into just the most 1250 significant part of a floating-point register pair.) 1251 1252 `?' (takes no operand) Substitute the value of i860_reg_prefix 1253 at this point. The value of i860_reg_prefix is typically 1254 a null string for most i860 targets, but for System V 1255 Release 4 the i860 assembler syntax requires that all 1256 names of registers be prefixed with a percent-sign, so 1257 for SVR4, the value of i860_reg_prefix is initialized to 1258 "%" in i860.c. 1259*/ 1260 1261extern char *i860_reg_prefix; 1262extern unsigned long sfmode_constant_to_ulong (); 1263 1264#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '?') 1265 1266/* The following macro definition is overridden in i860v4.h 1267 because the svr4 i860 assembler required a different syntax 1268 for getting parts of constant/relocatable values. */ 1269 1270#define PRINT_OPERAND_PART(FILE, X, PART_CODE) \ 1271 do { fprintf (FILE, "%s%%", PART_CODE); \ 1272 output_address (X); \ 1273 } while (0) 1274 1275#define OPERAND_LOW_PART "l" 1276#define OPERAND_HIGH_PART "h" 1277/* NOTE: All documentation available for the i860 sez that you must 1278 use "ha" to get the relocated high part of a relocatable, but 1279 reality sez different. */ 1280#define OPERAND_HIGH_ADJ_PART "ha" 1281 1282#define PRINT_OPERAND(FILE, X, CODE) \ 1283{ if ((CODE) == '?') \ 1284 fprintf (FILE, "%s", i860_reg_prefix); \ 1285 else if (CODE == 'R') \ 1286 fprintf (FILE, "%s%s", i860_reg_prefix, reg_names[REGNO (X) + 1]); \ 1287 else if (GET_CODE (X) == REG) \ 1288 fprintf (FILE, "%s%s", i860_reg_prefix, reg_names[REGNO (X)]); \ 1289 else if ((CODE) == 'm') \ 1290 output_address (XEXP (X, 0)); \ 1291 else if ((CODE) == 'L') \ 1292 { \ 1293 if (GET_CODE (X) == MEM) \ 1294 PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_LOW_PART); \ 1295 else \ 1296 PRINT_OPERAND_PART (FILE, X, OPERAND_LOW_PART); \ 1297 } \ 1298 else if ((CODE) == 'H') \ 1299 { \ 1300 if (GET_CODE (X) == MEM) \ 1301 PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_HIGH_PART); \ 1302 else \ 1303 PRINT_OPERAND_PART (FILE, X, OPERAND_HIGH_PART); \ 1304 } \ 1305 else if ((CODE) == 'h') \ 1306 { \ 1307 if (GET_CODE (X) == MEM) \ 1308 PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_HIGH_ADJ_PART); \ 1309 else \ 1310 PRINT_OPERAND_PART (FILE, X, OPERAND_HIGH_ADJ_PART); \ 1311 } \ 1312 else if (GET_CODE (X) == MEM) \ 1313 output_address (XEXP (X, 0)); \ 1314 else if ((CODE) == 'r' && (X) == const0_rtx) \ 1315 fprintf (FILE, "%sr0", i860_reg_prefix); \ 1316 else if ((CODE) == 'r' && (X) == CONST0_RTX (GET_MODE (X))) \ 1317 fprintf (FILE, "%sf0", i860_reg_prefix); \ 1318 else if (GET_CODE (X) == CONST_DOUBLE) \ 1319 fprintf (FILE, "0x%x", sfmode_constant_to_ulong (X)); \ 1320 else \ 1321 output_addr_const (FILE, X); } 1322 1323/* Print a memory address as an operand to reference that memory location. */ 1324 1325#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 1326{ register rtx base, index = 0; \ 1327 int offset = 0; \ 1328 register rtx addr = ADDR; \ 1329 if (GET_CODE (addr) == REG) \ 1330 { \ 1331 fprintf (FILE, "0(%s%s)", \ 1332 i860_reg_prefix, reg_names[REGNO (addr)]); \ 1333 } \ 1334 else if (GET_CODE (addr) == CONST_DOUBLE \ 1335 && GET_MODE (addr) == SFmode) \ 1336 fprintf (FILE, "0x%x", sfmode_constant_to_ulong (addr)); \ 1337 else if (GET_CODE (addr) == PLUS) \ 1338 { \ 1339 if ((GET_CODE (XEXP (addr, 0)) == CONST_INT) \ 1340 && (GET_CODE (XEXP (addr, 1)) == REG)) \ 1341 fprintf (FILE, "%d(%s%s)", INTVAL (XEXP (addr, 0)), \ 1342 i860_reg_prefix, reg_names[REGNO (XEXP (addr, 1))]);\ 1343 else if ((GET_CODE (XEXP (addr, 1)) == CONST_INT) \ 1344 && (GET_CODE (XEXP (addr, 0)) == REG)) \ 1345 fprintf (FILE, "%d(%s%s)", INTVAL (XEXP (addr, 1)), \ 1346 i860_reg_prefix, reg_names[REGNO (XEXP (addr, 0))]);\ 1347 else if ((GET_CODE (XEXP (addr, 0)) == REG) \ 1348 && (GET_CODE (XEXP (addr, 1)) == REG)) \ 1349 fprintf (FILE, "%s%s(%s%s)", \ 1350 i860_reg_prefix, reg_names[REGNO (XEXP (addr, 0))], \ 1351 i860_reg_prefix, reg_names[REGNO (XEXP (addr, 1))]);\ 1352 else \ 1353 output_addr_const (FILE, addr); \ 1354 } \ 1355 else \ 1356 { \ 1357 output_addr_const (FILE, addr); \ 1358 } \ 1359} 1360 1361/* The following #defines are used when compiling the routines in 1362 libgcc1.c. Since the i860 calling conventions require single 1363 precision floats to be passed in the floating-point registers 1364 (rather than in the general registers) we have to build the 1365 libgcc1.c routines in such a way that they know the actual types 1366 of their formal arguments and the actual types of their return 1367 values. Otherwise, gcc will generate calls to the libgcc1.c 1368 routines, passing arguments in the floating-point registers, 1369 but the libgcc1.c routines will expect their arguments on the 1370 stack (where the i860 calling conventions require structs & 1371 unions to be passed). */ 1372 1373#define FLOAT_VALUE_TYPE float 1374#define INTIFY(FLOATVAL) (FLOATVAL) 1375#define FLOATIFY(INTVAL) (INTVAL) 1376#define FLOAT_ARG_TYPE float 1377 1378 1379/* Optionally define this if you have added predicates to 1380 `MACHINE.c'. This macro is called within an initializer of an 1381 array of structures. The first field in the structure is the 1382 name of a predicate and the second field is an array of rtl 1383 codes. For each predicate, list all rtl codes that can be in 1384 expressions matched by the predicate. The list should have a 1385 trailing comma. Here is an example of two entries in the list 1386 for a typical RISC machine: 1387 1388 #define PREDICATE_CODES \ 1389 {"gen_reg_rtx_operand", {SUBREG, REG}}, \ 1390 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}}, 1391 1392 Defining this macro does not affect the generated code (however, 1393 incorrect definitions that omit an rtl code that may be matched 1394 by the predicate can cause the compiler to malfunction). 1395 Instead, it allows the table built by `genrecog' to be more 1396 compact and efficient, thus speeding up the compiler. The most 1397 important predicates to include in the list specified by this 1398 macro are thoses used in the most insn patterns. */ 1399 1400#define PREDICATE_CODES \ 1401 {"reg_or_0_operand", {REG, SUBREG, CONST_INT}}, \ 1402 {"arith_operand", {REG, SUBREG, CONST_INT}}, \ 1403 {"logic_operand", {REG, SUBREG, CONST_INT}}, \ 1404 {"shift_operand", {REG, SUBREG, CONST_INT}}, \ 1405 {"compare_operand", {REG, SUBREG, CONST_INT}}, \ 1406 {"arith_const_operand", {CONST_INT}}, \ 1407 {"logic_const_operand", {CONST_INT}}, \ 1408 {"bte_operand", {REG, SUBREG, CONST_INT}}, \ 1409 {"indexed_operand", {MEM}}, \ 1410 {"load_operand", {MEM}}, \ 1411 {"small_int", {CONST_INT}}, \ 1412 {"logic_int", {CONST_INT}}, \ 1413 {"call_insn_operand", {MEM}}, 1414 1415/* Define the information needed to generate branch insns. This is stored 1416 from the compare operation. Note that we can't use "rtx" here since it 1417 hasn't been defined! */ 1418 1419extern struct rtx_def *i860_compare_op0, *i860_compare_op1; 1420 1421/* Declare things which are defined in i860.c but called from 1422 insn-output.c. */ 1423 1424extern unsigned long sfmode_constant_to_ulong (); 1425extern char *output_load (); 1426extern char *output_store (); 1427extern char *output_move_double (); 1428extern char *output_fp_move_double (); 1429extern char *output_block_move (); 1430extern char *output_delay_insn (); 1431extern char *output_delayed_branch (); 1432extern void output_load_address (); 1433