1/* Subroutines for insn-output.c for Intel X86. 2 Copyright (C) 1988, 92, 94-98, 1999 Free Software Foundation, Inc. 3 4This file is part of GNU CC. 5 6GNU CC is free software; you can redistribute it and/or modify 7it under the terms of the GNU General Public License as published by 8the Free Software Foundation; either version 2, or (at your option) 9any later version. 10 11GNU CC is distributed in the hope that it will be useful, 12but WITHOUT ANY WARRANTY; without even the implied warranty of 13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14GNU General Public License for more details. 15 16You should have received a copy of the GNU General Public License 17along with GNU CC; see the file COPYING. If not, write to 18the Free Software Foundation, 59 Temple Place - Suite 330, 19Boston, MA 02111-1307, USA. */ 20 21#include <setjmp.h> 22#include "config.h" 23#include "system.h" 24#include "rtl.h" 25#include "regs.h" 26#include "hard-reg-set.h" 27#include "real.h" 28#include "insn-config.h" 29#include "conditions.h" 30#include "insn-flags.h" 31#include "output.h" 32#include "insn-attr.h" 33#include "tree.h" 34#include "flags.h" 35#include "except.h" 36#include "function.h" 37#include "recog.h" 38#include "expr.h" 39#include "toplev.h" 40 41#ifdef EXTRA_CONSTRAINT 42/* If EXTRA_CONSTRAINT is defined, then the 'S' 43 constraint in REG_CLASS_FROM_LETTER will no longer work, and various 44 asm statements that need 'S' for class SIREG will break. */ 45 error EXTRA_CONSTRAINT conflicts with S constraint letter 46/* The previous line used to be #error, but some compilers barf 47 even if the conditional was untrue. */ 48#endif 49 50#ifndef CHECK_STACK_LIMIT 51#define CHECK_STACK_LIMIT -1 52#endif 53 54/* Type of an operand for ix86_{binary,unary}_operator_ok */ 55enum reg_mem 56{ 57 reg_p, 58 mem_p, 59 imm_p 60}; 61 62/* Processor costs (relative to an add) */ 63struct processor_costs i386_cost = { /* 386 specific costs */ 64 1, /* cost of an add instruction */ 65 1, /* cost of a lea instruction */ 66 3, /* variable shift costs */ 67 2, /* constant shift costs */ 68 6, /* cost of starting a multiply */ 69 1, /* cost of multiply per each bit set */ 70 23 /* cost of a divide/mod */ 71}; 72 73struct processor_costs i486_cost = { /* 486 specific costs */ 74 1, /* cost of an add instruction */ 75 1, /* cost of a lea instruction */ 76 3, /* variable shift costs */ 77 2, /* constant shift costs */ 78 12, /* cost of starting a multiply */ 79 1, /* cost of multiply per each bit set */ 80 40 /* cost of a divide/mod */ 81}; 82 83struct processor_costs pentium_cost = { 84 1, /* cost of an add instruction */ 85 1, /* cost of a lea instruction */ 86 4, /* variable shift costs */ 87 1, /* constant shift costs */ 88 11, /* cost of starting a multiply */ 89 0, /* cost of multiply per each bit set */ 90 25 /* cost of a divide/mod */ 91}; 92 93struct processor_costs pentiumpro_cost = { 94 1, /* cost of an add instruction */ 95 1, /* cost of a lea instruction */ 96 3, /* variable shift costs */ 97 1, /* constant shift costs */ 98 4, /* cost of starting a multiply */ 99 0, /* cost of multiply per each bit set */ 100 17 /* cost of a divide/mod */ 101}; 102 103/* We use decoding time together with execution time. 104 To get correct vale add 1 for short decodable, 2 for long decodable 105 and 4 for vector decodable instruction to execution time and divide 106 by two (because CPU is able to do two insns at a time). */ 107 108struct processor_costs k6_cost = { 109 1, /* cost of an add instruction */ 110 1, /* cost of a lea instruction */ 111 1, /* variable shift costs */ 112 1, /* constant shift costs */ 113 3, /* cost of starting a multiply */ 114 0, /* cost of multiply per each bit set */ 115 20 /* cost of a divide/mod */ 116}; 117 118struct processor_costs *ix86_cost = &pentium_cost; 119 120/* Processor feature/optimization bitmasks. */ 121#define m_386 (1<<PROCESSOR_I386) 122#define m_486 (1<<PROCESSOR_I486) 123#define m_PENT (1<<PROCESSOR_PENTIUM) 124#define m_PPRO (1<<PROCESSOR_PENTIUMPRO) 125#define m_K6 (1<<PROCESSOR_K6) 126 127const int x86_use_leave = m_386 | m_K6; 128const int x86_push_memory = m_386 | m_K6; 129const int x86_zero_extend_with_and = m_486 | m_PENT; 130const int x86_movx = m_386 | m_PPRO | m_K6; 131const int x86_double_with_add = ~(m_386 | m_PENT | m_PPRO); 132const int x86_use_bit_test = m_386; 133const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO; 134const int x86_use_q_reg = m_PENT | m_PPRO | m_K6; 135const int x86_use_any_reg = m_486; 136const int x86_cmove = m_PPRO; 137const int x86_deep_branch = m_PPRO| m_K6; 138 139#define AT_BP(mode) (gen_rtx_MEM ((mode), frame_pointer_rtx)) 140 141extern FILE *asm_out_file; 142#ifndef __APPLE__ 143extern char *strcat (); 144#endif 145 146static void ix86_epilogue PROTO((int)); 147static void ix86_prologue PROTO((int)); 148 149char *singlemove_string (); 150char *output_move_const_single (); 151char *output_fp_cc0_set (); 152 153char *hi_reg_name[] = HI_REGISTER_NAMES; 154char *qi_reg_name[] = QI_REGISTER_NAMES; 155char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES; 156 157/* Array of the smallest class containing reg number REGNO, indexed by 158 REGNO. Used by REGNO_REG_CLASS in i386.h. */ 159 160enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] = 161{ 162 /* ax, dx, cx, bx */ 163 AREG, DREG, CREG, BREG, 164 /* si, di, bp, sp */ 165 SIREG, DIREG, INDEX_REGS, GENERAL_REGS, 166 /* FP registers */ 167 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS, 168 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, 169 /* arg pointer */ 170 INDEX_REGS 171}; 172 173/* Test and compare insns in i386.md store the information needed to 174 generate branch and scc insns here. */ 175 176struct rtx_def *i386_compare_op0 = NULL_RTX; 177struct rtx_def *i386_compare_op1 = NULL_RTX; 178struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)(); 179 180/* which cpu are we scheduling for */ 181enum processor_type ix86_cpu; 182 183/* which instruction set architecture to use. */ 184int ix86_arch; 185 186/* Strings to hold which cpu and instruction set architecture to use. */ 187char *ix86_cpu_string; /* for -mcpu=<xxx> */ 188char *ix86_arch_string; /* for -march=<xxx> */ 189 190/* Register allocation order */ 191char *i386_reg_alloc_order; 192static char regs_allocated[FIRST_PSEUDO_REGISTER]; 193 194/* # of registers to use to pass arguments. */ 195char *i386_regparm_string; 196 197/* i386_regparm_string as a number */ 198int i386_regparm; 199 200/* Alignment to use for loops and jumps: */ 201 202/* Power of two alignment for loops. */ 203char *i386_align_loops_string; 204 205/* Power of two alignment for non-loop jumps. */ 206char *i386_align_jumps_string; 207 208/* Power of two alignment for stack boundary in bytes. */ 209char *i386_preferred_stack_boundary_string; 210 211/* Preferred alignment for stack boundary in bits. */ 212int i386_preferred_stack_boundary; 213 214/* Values 1-5: see jump.c */ 215int i386_branch_cost; 216char *i386_branch_cost_string; 217 218/* Power of two alignment for functions. */ 219int i386_align_funcs; 220char *i386_align_funcs_string; 221 222/* Power of two alignment for loops. */ 223int i386_align_loops; 224 225/* Power of two alignment for non-loop jumps. */ 226int i386_align_jumps; 227 228/* Sometimes certain combinations of command options do not make 229 sense on a particular target machine. You can define a macro 230 `OVERRIDE_OPTIONS' to take account of this. This macro, if 231 defined, is executed once just after all the command options have 232 been parsed. 233 234 Don't use this macro to turn on various extra optimizations for 235 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 236 237void 238override_options () 239{ 240 int ch, i, j; 241 int def_align; 242 243 static struct ptt 244 { 245 char *name; /* Canonical processor name. */ 246 enum processor_type processor; /* Processor type enum value. */ 247 struct processor_costs *cost; /* Processor costs */ 248 int target_enable; /* Target flags to enable. */ 249 int target_disable; /* Target flags to disable. */ 250 } processor_target_table[] = { 251 {PROCESSOR_I386_STRING, PROCESSOR_I386, &i386_cost, 0, 0}, 252 {PROCESSOR_I486_STRING, PROCESSOR_I486, &i486_cost, 0, 0}, 253 {PROCESSOR_I586_STRING, PROCESSOR_PENTIUM, &pentium_cost, 0, 0}, 254 {PROCESSOR_PENTIUM_STRING, PROCESSOR_PENTIUM, &pentium_cost, 0, 0}, 255 {PROCESSOR_I686_STRING, PROCESSOR_PENTIUMPRO, &pentiumpro_cost, 0, 0}, 256 {PROCESSOR_PENTIUMPRO_STRING, PROCESSOR_PENTIUMPRO, 257 &pentiumpro_cost, 0, 0}, 258 {PROCESSOR_K6_STRING, PROCESSOR_K6, &k6_cost, 0, 0} 259 }; 260 261 int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt); 262 263#ifdef SUBTARGET_OVERRIDE_OPTIONS 264 SUBTARGET_OVERRIDE_OPTIONS; 265#endif 266 267 /* Validate registers in register allocation order. */ 268 if (i386_reg_alloc_order) 269 { 270 for (i = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++) 271 { 272 int regno = 0; 273 274 switch (ch) 275 { 276 case 'a': regno = 0; break; 277 case 'd': regno = 1; break; 278 case 'c': regno = 2; break; 279 case 'b': regno = 3; break; 280 case 'S': regno = 4; break; 281 case 'D': regno = 5; break; 282 case 'B': regno = 6; break; 283 284 default: fatal ("Register '%c' is unknown", ch); 285 } 286 287 if (regs_allocated[regno]) 288 fatal ("Register '%c' already specified in allocation order", ch); 289 290 regs_allocated[regno] = 1; 291 } 292 } 293 294 if (ix86_arch_string == 0) 295 { 296 ix86_arch_string = PROCESSOR_PENTIUM_STRING; 297 if (ix86_cpu_string == 0) 298 ix86_cpu_string = PROCESSOR_DEFAULT_STRING; 299 } 300 301 for (i = 0; i < ptt_size; i++) 302 if (! strcmp (ix86_arch_string, processor_target_table[i].name)) 303 { 304 ix86_arch = processor_target_table[i].processor; 305 if (ix86_cpu_string == 0) 306 ix86_cpu_string = processor_target_table[i].name; 307 break; 308 } 309 310 if (i == ptt_size) 311 { 312 error ("bad value (%s) for -march= switch", ix86_arch_string); 313 ix86_arch_string = PROCESSOR_PENTIUM_STRING; 314 ix86_arch = PROCESSOR_DEFAULT; 315 } 316 317 if (ix86_cpu_string == 0) 318 ix86_cpu_string = PROCESSOR_DEFAULT_STRING; 319 320 for (j = 0; j < ptt_size; j++) 321 if (! strcmp (ix86_cpu_string, processor_target_table[j].name)) 322 { 323 ix86_cpu = processor_target_table[j].processor; 324 ix86_cost = processor_target_table[j].cost; 325 if (i > j && (int) ix86_arch >= (int) PROCESSOR_K6) 326 error ("-mcpu=%s does not support -march=%s", 327 ix86_cpu_string, ix86_arch_string); 328 329 target_flags |= processor_target_table[j].target_enable; 330 target_flags &= ~processor_target_table[j].target_disable; 331 break; 332 } 333 334 if (j == ptt_size) 335 { 336 error ("bad value (%s) for -mcpu= switch", ix86_cpu_string); 337 ix86_cpu_string = PROCESSOR_DEFAULT_STRING; 338 ix86_cpu = PROCESSOR_DEFAULT; 339 } 340 341 /* Validate -mregparm= value. */ 342 if (i386_regparm_string) 343 { 344 i386_regparm = atoi (i386_regparm_string); 345 if (i386_regparm < 0 || i386_regparm > REGPARM_MAX) 346 fatal ("-mregparm=%d is not between 0 and %d", 347 i386_regparm, REGPARM_MAX); 348 } 349 350 /* The 486 suffers more from non-aligned cache line fills, and the 351 larger code size results in a larger cache foot-print and more misses. 352 The 486 has a 16 byte cache line, pentium and pentiumpro have a 32 byte 353 cache line. */ 354 def_align = (TARGET_486) ? 4 : 2; 355 356 /* Validate -malign-loops= value, or provide default. */ 357#ifdef ASM_OUTPUT_MAX_SKIP_ALIGN 358 i386_align_loops = 4; 359#else 360 i386_align_loops = 2; 361#endif 362 if (i386_align_loops_string) 363 { 364 i386_align_loops = atoi (i386_align_loops_string); 365 if (i386_align_loops < 0 || i386_align_loops > MAX_CODE_ALIGN) 366 fatal ("-malign-loops=%d is not between 0 and %d", 367 i386_align_loops, MAX_CODE_ALIGN); 368 } 369 370 /* Validate -malign-jumps= value, or provide default. */ 371#ifdef ASM_OUTPUT_MAX_SKIP_ALIGN 372 i386_align_jumps = 4; 373#else 374 i386_align_jumps = def_align; 375#endif 376 if (i386_align_jumps_string) 377 { 378 i386_align_jumps = atoi (i386_align_jumps_string); 379 if (i386_align_jumps < 0 || i386_align_jumps > MAX_CODE_ALIGN) 380 fatal ("-malign-jumps=%d is not between 0 and %d", 381 i386_align_jumps, MAX_CODE_ALIGN); 382 } 383 384 /* Validate -malign-functions= value, or provide default. */ 385 i386_align_funcs = def_align; 386 if (i386_align_funcs_string) 387 { 388 i386_align_funcs = atoi (i386_align_funcs_string); 389 if (i386_align_funcs < 0 || i386_align_funcs > MAX_CODE_ALIGN) 390 fatal ("-malign-functions=%d is not between 0 and %d", 391 i386_align_funcs, MAX_CODE_ALIGN); 392 } 393 394 /* Validate -mpreferred_stack_boundary= value, or provide default. 395 The default of 128 bits is for Pentium III's SSE __m128. */ 396 i386_preferred_stack_boundary = 128; 397 if (i386_preferred_stack_boundary_string) 398 { 399 i = atoi (i386_preferred_stack_boundary_string); 400 if (i < 2 || i > 31) 401 fatal ("-mpreferred_stack_boundary=%d is not between 2 and 31", i); 402 i386_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT; 403 } 404 405 /* Validate -mbranch-cost= value, or provide default. */ 406 i386_branch_cost = 1; 407 if (i386_branch_cost_string) 408 { 409 i386_branch_cost = atoi (i386_branch_cost_string); 410 if (i386_branch_cost < 0 || i386_branch_cost > 5) 411 fatal ("-mbranch-cost=%d is not between 0 and 5", i386_branch_cost); 412 } 413 414 /* Keep nonleaf frame pointers. */ 415 if (TARGET_OMIT_LEAF_FRAME_POINTER) 416 flag_omit_frame_pointer = 1; 417} 418 419/* A C statement (sans semicolon) to choose the order in which to 420 allocate hard registers for pseudo-registers local to a basic 421 block. 422 423 Store the desired register order in the array `reg_alloc_order'. 424 Element 0 should be the register to allocate first; element 1, the 425 next register; and so on. 426 427 The macro body should not assume anything about the contents of 428 `reg_alloc_order' before execution of the macro. 429 430 On most machines, it is not necessary to define this macro. */ 431 432void 433order_regs_for_local_alloc () 434{ 435 int i, ch, order; 436 437 /* User specified the register allocation order. */ 438 439 if (i386_reg_alloc_order) 440 { 441 for (i = order = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++) 442 { 443 int regno = 0; 444 445 switch (ch) 446 { 447 case 'a': regno = 0; break; 448 case 'd': regno = 1; break; 449 case 'c': regno = 2; break; 450 case 'b': regno = 3; break; 451 case 'S': regno = 4; break; 452 case 'D': regno = 5; break; 453 case 'B': regno = 6; break; 454 } 455 456 reg_alloc_order[order++] = regno; 457 } 458 459 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 460 { 461 if (! regs_allocated[i]) 462 reg_alloc_order[order++] = i; 463 } 464 } 465 466 /* If user did not specify a register allocation order, use natural order. */ 467 else 468 { 469 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 470 reg_alloc_order[i] = i; 471 } 472} 473 474void 475optimization_options (level, size) 476 int level; 477 int size ATTRIBUTE_UNUSED; 478{ 479 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to 480 make the problem with not enough registers even worse. */ 481#ifdef INSN_SCHEDULING 482 if (level > 1) 483 flag_schedule_insns = 0; 484#endif 485} 486 487/* Sign-extend a 16-bit constant */ 488 489struct rtx_def * 490i386_sext16_if_const (op) 491 struct rtx_def *op; 492{ 493 if (GET_CODE (op) == CONST_INT) 494 { 495 HOST_WIDE_INT val = INTVAL (op); 496 HOST_WIDE_INT sext_val; 497 if (val & 0x8000) 498 sext_val = val | ~0xffff; 499 else 500 sext_val = val & 0xffff; 501 if (sext_val != val) 502 op = GEN_INT (sext_val); 503 } 504 return op; 505} 506 507/* Return nonzero if the rtx is aligned */ 508 509static int 510i386_aligned_reg_p (regno) 511 int regno; 512{ 513 return (regno == STACK_POINTER_REGNUM 514 || (! flag_omit_frame_pointer && regno == FRAME_POINTER_REGNUM)); 515} 516 517int 518i386_aligned_p (op) 519 rtx op; 520{ 521 /* Registers and immediate operands are always "aligned". */ 522 if (GET_CODE (op) != MEM) 523 return 1; 524 525 /* Don't even try to do any aligned optimizations with volatiles. */ 526 if (MEM_VOLATILE_P (op)) 527 return 0; 528 529 /* Get address of memory operand. */ 530 op = XEXP (op, 0); 531 532 switch (GET_CODE (op)) 533 { 534 case CONST_INT: 535 if (INTVAL (op) & 3) 536 break; 537 return 1; 538 539 /* Match "reg + offset" */ 540 case PLUS: 541 if (GET_CODE (XEXP (op, 1)) != CONST_INT) 542 break; 543 if (INTVAL (XEXP (op, 1)) & 3) 544 break; 545 546 op = XEXP (op, 0); 547 if (GET_CODE (op) != REG) 548 break; 549 550 /* ... fall through ... */ 551 552 case REG: 553 return i386_aligned_reg_p (REGNO (op)); 554 555 default: 556 break; 557 } 558 559 return 0; 560} 561 562/* Return nonzero if INSN looks like it won't compute useful cc bits 563 as a side effect. This information is only a hint. */ 564 565int 566i386_cc_probably_useless_p (insn) 567 rtx insn; 568{ 569 return ! next_cc0_user (insn); 570} 571 572/* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific 573 attribute for DECL. The attributes in ATTRIBUTES have previously been 574 assigned to DECL. */ 575 576int 577i386_valid_decl_attribute_p (decl, attributes, identifier, args) 578 tree decl ATTRIBUTE_UNUSED; 579 tree attributes ATTRIBUTE_UNUSED; 580 tree identifier ATTRIBUTE_UNUSED; 581 tree args ATTRIBUTE_UNUSED; 582{ 583 return 0; 584} 585 586/* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific 587 attribute for TYPE. The attributes in ATTRIBUTES have previously been 588 assigned to TYPE. */ 589 590int 591i386_valid_type_attribute_p (type, attributes, identifier, args) 592 tree type; 593 tree attributes ATTRIBUTE_UNUSED; 594 tree identifier; 595 tree args; 596{ 597 if (TREE_CODE (type) != FUNCTION_TYPE 598 && TREE_CODE (type) != METHOD_TYPE 599 && TREE_CODE (type) != FIELD_DECL 600 && TREE_CODE (type) != TYPE_DECL) 601 return 0; 602 603 /* Stdcall attribute says callee is responsible for popping arguments 604 if they are not variable. */ 605 if (is_attribute_p ("stdcall", identifier)) 606 return (args == NULL_TREE); 607 608 /* Cdecl attribute says the callee is a normal C declaration. */ 609 if (is_attribute_p ("cdecl", identifier)) 610 return (args == NULL_TREE); 611 612 /* Regparm attribute specifies how many integer arguments are to be 613 passed in registers. */ 614 if (is_attribute_p ("regparm", identifier)) 615 { 616 tree cst; 617 618 if (! args || TREE_CODE (args) != TREE_LIST 619 || TREE_CHAIN (args) != NULL_TREE 620 || TREE_VALUE (args) == NULL_TREE) 621 return 0; 622 623 cst = TREE_VALUE (args); 624 if (TREE_CODE (cst) != INTEGER_CST) 625 return 0; 626 627 if (TREE_INT_CST_HIGH (cst) != 0 628 || TREE_INT_CST_LOW (cst) < 0 629 || TREE_INT_CST_LOW (cst) > REGPARM_MAX) 630 return 0; 631 632 return 1; 633 } 634 635 return 0; 636} 637 638/* Return 0 if the attributes for two types are incompatible, 1 if they 639 are compatible, and 2 if they are nearly compatible (which causes a 640 warning to be generated). */ 641 642int 643i386_comp_type_attributes (type1, type2) 644 tree type1; 645 tree type2; 646{ 647 /* Check for mismatch of non-default calling convention. */ 648 char *rtdstr = TARGET_RTD ? "cdecl" : "stdcall"; 649 650 if (TREE_CODE (type1) != FUNCTION_TYPE) 651 return 1; 652 653 /* Check for mismatched return types (cdecl vs stdcall). */ 654 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1)) 655 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2))) 656 return 0; 657 return 1; 658} 659 660 661/* Value is the number of bytes of arguments automatically 662 popped when returning from a subroutine call. 663 FUNDECL is the declaration node of the function (as a tree), 664 FUNTYPE is the data type of the function (as a tree), 665 or for a library call it is an identifier node for the subroutine name. 666 SIZE is the number of bytes of arguments passed on the stack. 667 668 On the 80386, the RTD insn may be used to pop them if the number 669 of args is fixed, but if the number is variable then the caller 670 must pop them all. RTD can't be used for library calls now 671 because the library is compiled with the Unix compiler. 672 Use of RTD is a selectable option, since it is incompatible with 673 standard Unix calling sequences. If the option is not selected, 674 the caller must always pop the args. 675 676 The attribute stdcall is equivalent to RTD on a per module basis. */ 677 678int 679i386_return_pops_args (fundecl, funtype, size) 680 tree fundecl; 681 tree funtype; 682 int size; 683{ 684 int rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE); 685 686 /* Cdecl functions override -mrtd, and never pop the stack. */ 687 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype))) { 688 689 /* Stdcall functions will pop the stack if not variable args. */ 690 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))) 691 rtd = 1; 692 693 if (rtd 694 && (TYPE_ARG_TYPES (funtype) == NULL_TREE 695 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype))) 696 == void_type_node))) 697 return size; 698 } 699 700 /* Lose any fake structure return argument. */ 701 if (aggregate_value_p (TREE_TYPE (funtype))) 702 return GET_MODE_SIZE (Pmode); 703 704 return 0; 705} 706 707 708/* Argument support functions. */ 709 710/* Initialize a variable CUM of type CUMULATIVE_ARGS 711 for a call to a function whose data type is FNTYPE. 712 For a library call, FNTYPE is 0. */ 713 714void 715init_cumulative_args (cum, fntype, libname) 716 CUMULATIVE_ARGS *cum; /* Argument info to initialize */ 717 tree fntype; /* tree ptr for function decl */ 718 rtx libname; /* SYMBOL_REF of library name or 0 */ 719{ 720 static CUMULATIVE_ARGS zero_cum; 721 tree param, next_param; 722 723 if (TARGET_DEBUG_ARG) 724 { 725 fprintf (stderr, "\ninit_cumulative_args ("); 726 if (fntype) 727 fprintf (stderr, "fntype code = %s, ret code = %s", 728 tree_code_name[(int) TREE_CODE (fntype)], 729 tree_code_name[(int) TREE_CODE (TREE_TYPE (fntype))]); 730 else 731 fprintf (stderr, "no fntype"); 732 733 if (libname) 734 fprintf (stderr, ", libname = %s", XSTR (libname, 0)); 735 } 736 737 *cum = zero_cum; 738 739 /* Set up the number of registers to use for passing arguments. */ 740 cum->nregs = i386_regparm; 741 if (fntype) 742 { 743 tree attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (fntype)); 744 745 if (attr) 746 cum->nregs = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr))); 747 } 748 749 /* Determine if this function has variable arguments. This is 750 indicated by the last argument being 'void_type_mode' if there 751 are no variable arguments. If there are variable arguments, then 752 we won't pass anything in registers */ 753 754 if (cum->nregs) 755 { 756 for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0; 757 param != 0; param = next_param) 758 { 759 next_param = TREE_CHAIN (param); 760 if (next_param == 0 && TREE_VALUE (param) != void_type_node) 761 cum->nregs = 0; 762 } 763 } 764 765 if (TARGET_DEBUG_ARG) 766 fprintf (stderr, ", nregs=%d )\n", cum->nregs); 767 768 return; 769} 770 771/* Update the data in CUM to advance over an argument 772 of mode MODE and data type TYPE. 773 (TYPE is null for libcalls where that information may not be available.) */ 774 775void 776function_arg_advance (cum, mode, type, named) 777 CUMULATIVE_ARGS *cum; /* current arg information */ 778 enum machine_mode mode; /* current arg mode */ 779 tree type; /* type of the argument or 0 if lib support */ 780 int named; /* whether or not the argument was named */ 781{ 782 int bytes 783 = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); 784 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 785 786 if (TARGET_DEBUG_ARG) 787 fprintf (stderr, 788 "function_adv (sz=%d, wds=%2d, nregs=%d, mode=%s, named=%d)\n\n", 789 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named); 790 791 cum->words += words; 792 cum->nregs -= words; 793 cum->regno += words; 794 795 if (cum->nregs <= 0) 796 { 797 cum->nregs = 0; 798 cum->regno = 0; 799 } 800 801 return; 802} 803 804/* Define where to put the arguments to a function. 805 Value is zero to push the argument on the stack, 806 or a hard register in which to store the argument. 807 808 MODE is the argument's machine mode. 809 TYPE is the data type of the argument (as a tree). 810 This is null for libcalls where that information may 811 not be available. 812 CUM is a variable of type CUMULATIVE_ARGS which gives info about 813 the preceding args and about the function being called. 814 NAMED is nonzero if this argument is a named parameter 815 (otherwise it is an extra parameter matching an ellipsis). */ 816 817struct rtx_def * 818function_arg (cum, mode, type, named) 819 CUMULATIVE_ARGS *cum; /* current arg information */ 820 enum machine_mode mode; /* current arg mode */ 821 tree type; /* type of the argument or 0 if lib support */ 822 int named; /* != 0 for normal args, == 0 for ... args */ 823{ 824 rtx ret = NULL_RTX; 825 int bytes 826 = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); 827 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 828 829 switch (mode) 830 { 831 /* For now, pass fp/complex values on the stack. */ 832 default: 833 break; 834 835 case BLKmode: 836 case DImode: 837 case SImode: 838 case HImode: 839 case QImode: 840 if (words <= cum->nregs) 841 ret = gen_rtx_REG (mode, cum->regno); 842 break; 843 } 844 845 if (TARGET_DEBUG_ARG) 846 { 847 fprintf (stderr, 848 "function_arg (size=%d, wds=%2d, nregs=%d, mode=%4s, named=%d", 849 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named); 850 851 if (ret) 852 fprintf (stderr, ", reg=%%e%s", reg_names[ REGNO(ret) ]); 853 else 854 fprintf (stderr, ", stack"); 855 856 fprintf (stderr, " )\n"); 857 } 858 859 return ret; 860} 861 862/* For an arg passed partly in registers and partly in memory, 863 this is the number of registers used. 864 For args passed entirely in registers or entirely in memory, zero. */ 865 866int 867function_arg_partial_nregs (cum, mode, type, named) 868 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; /* current arg information */ 869 enum machine_mode mode ATTRIBUTE_UNUSED; /* current arg mode */ 870 tree type ATTRIBUTE_UNUSED; /* type of the argument or 0 if lib support */ 871 int named ATTRIBUTE_UNUSED; /* != 0 for normal args, == 0 for ... args */ 872{ 873 return 0; 874} 875 876char * 877singlemove_string (operands) 878 rtx *operands; 879{ 880 rtx x; 881 if (GET_CODE (operands[0]) == MEM 882 && GET_CODE (x = XEXP (operands[0], 0)) == PRE_DEC) 883 { 884 if (XEXP (x, 0) != stack_pointer_rtx) 885 abort (); 886 return "push%L1 %1"; 887 } 888 else if (GET_CODE (operands[1]) == CONST_DOUBLE) 889 return output_move_const_single (operands); 890 else if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG) 891 return AS2 (mov%L0,%1,%0); 892 else if (CONSTANT_P (operands[1])) 893 return AS2 (mov%L0,%1,%0); 894 else 895 { 896 output_asm_insn ("push%L1 %1", operands); 897 return "pop%L0 %0"; 898 } 899} 900 901/* Output an insn to add the constant N to the register X. */ 902 903static void 904asm_add (n, x) 905 int n; 906 rtx x; 907{ 908 rtx xops[2]; 909 xops[0] = x; 910 911 if (n == -1) 912 output_asm_insn (AS1 (dec%L0,%0), xops); 913 else if (n == 1) 914 output_asm_insn (AS1 (inc%L0,%0), xops); 915 else if (n < 0 || n == 128) 916 { 917 xops[1] = GEN_INT (-n); 918 output_asm_insn (AS2 (sub%L0,%1,%0), xops); 919 } 920 else if (n > 0) 921 { 922 xops[1] = GEN_INT (n); 923 output_asm_insn (AS2 (add%L0,%1,%0), xops); 924 } 925} 926 927/* Output assembler code to perform a doubleword move insn 928 with operands OPERANDS. */ 929 930char * 931output_move_double (operands) 932 rtx *operands; 933{ 934 enum {REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1; 935 rtx latehalf[2]; 936 rtx middlehalf[2]; 937 rtx xops[2]; 938 int dest_overlapped_low = 0; 939 int size = GET_MODE_SIZE (GET_MODE (operands[0])); 940 941 middlehalf[0] = 0; 942 middlehalf[1] = 0; 943 944 /* First classify both operands. */ 945 946 if (REG_P (operands[0])) 947 optype0 = REGOP; 948 else if (offsettable_memref_p (operands[0])) 949 optype0 = OFFSOP; 950 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) 951 optype0 = POPOP; 952 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) 953 optype0 = PUSHOP; 954 else if (GET_CODE (operands[0]) == MEM) 955 optype0 = MEMOP; 956 else 957 optype0 = RNDOP; 958 959 if (REG_P (operands[1])) 960 optype1 = REGOP; 961 else if (CONSTANT_P (operands[1])) 962 optype1 = CNSTOP; 963 else if (offsettable_memref_p (operands[1])) 964 optype1 = OFFSOP; 965 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) 966 optype1 = POPOP; 967 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) 968 optype1 = PUSHOP; 969 else if (GET_CODE (operands[1]) == MEM) 970 optype1 = MEMOP; 971 else 972 optype1 = RNDOP; 973 974 /* Check for the cases that are not supposed to happen 975 either due to the operand constraints or the fact 976 that all memory operands on the x86 are offsettable. 977 Abort if we get one, because generating code for these 978 cases is painful. */ 979 980 if (optype0 == RNDOP || optype1 == RNDOP 981 || optype0 == MEMOP || optype1 == MEMOP) 982 abort (); 983 984 /* If one operand is decrementing and one is incrementing 985 decrement the former register explicitly 986 and change that operand into ordinary indexing. */ 987 988 if (optype0 == PUSHOP && optype1 == POPOP) 989 { 990 /* ??? Can this ever happen on i386? */ 991 operands[0] = XEXP (XEXP (operands[0], 0), 0); 992 asm_add (-size, operands[0]); 993 if (GET_MODE (operands[1]) == XFmode) 994 operands[0] = gen_rtx_MEM (XFmode, operands[0]); 995 else if (GET_MODE (operands[0]) == DFmode) 996 operands[0] = gen_rtx_MEM (DFmode, operands[0]); 997 else 998 operands[0] = gen_rtx_MEM (DImode, operands[0]); 999 optype0 = OFFSOP; 1000 } 1001 1002 if (optype0 == POPOP && optype1 == PUSHOP) 1003 { 1004 /* ??? Can this ever happen on i386? */ 1005 operands[1] = XEXP (XEXP (operands[1], 0), 0); 1006 asm_add (-size, operands[1]); 1007 if (GET_MODE (operands[1]) == XFmode) 1008 operands[1] = gen_rtx_MEM (XFmode, operands[1]); 1009 else if (GET_MODE (operands[1]) == DFmode) 1010 operands[1] = gen_rtx_MEM (DFmode, operands[1]); 1011 else 1012 operands[1] = gen_rtx_MEM (DImode, operands[1]); 1013 optype1 = OFFSOP; 1014 } 1015 1016 /* Ok, we can do one word at a time. 1017 Normally we do the low-numbered word first, 1018 but if either operand is autodecrementing then we 1019 do the high-numbered word first. 1020 1021 In either case, set up in LATEHALF the operands to use 1022 for the high-numbered word and in some cases alter the 1023 operands in OPERANDS to be suitable for the low-numbered word. */ 1024 1025 if (size == 12) 1026 { 1027 if (optype0 == REGOP) 1028 { 1029 middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 1030 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2); 1031 } 1032 else if (optype0 == OFFSOP) 1033 { 1034 middlehalf[0] = adj_offsettable_operand (operands[0], 4); 1035 latehalf[0] = adj_offsettable_operand (operands[0], 8); 1036 } 1037 else 1038 { 1039 middlehalf[0] = operands[0]; 1040 latehalf[0] = operands[0]; 1041 } 1042 1043 if (optype1 == REGOP) 1044 { 1045 middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); 1046 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2); 1047 } 1048 else if (optype1 == OFFSOP) 1049 { 1050 middlehalf[1] = adj_offsettable_operand (operands[1], 4); 1051 latehalf[1] = adj_offsettable_operand (operands[1], 8); 1052 } 1053 else if (optype1 == CNSTOP) 1054 { 1055 if (GET_CODE (operands[1]) == CONST_DOUBLE) 1056 { 1057 REAL_VALUE_TYPE r; long l[3]; 1058 1059 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); 1060 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); 1061 operands[1] = GEN_INT (l[0]); 1062 middlehalf[1] = GEN_INT (l[1]); 1063 latehalf[1] = GEN_INT (l[2]); 1064 } 1065 else if (CONSTANT_P (operands[1])) 1066 /* No non-CONST_DOUBLE constant should ever appear here. */ 1067 abort (); 1068 } 1069 else 1070 { 1071 middlehalf[1] = operands[1]; 1072 latehalf[1] = operands[1]; 1073 } 1074 } 1075 1076 else 1077 { 1078 /* Size is not 12. */ 1079 1080 if (optype0 == REGOP) 1081 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 1082 else if (optype0 == OFFSOP) 1083 latehalf[0] = adj_offsettable_operand (operands[0], 4); 1084 else 1085 latehalf[0] = operands[0]; 1086 1087 if (optype1 == REGOP) 1088 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); 1089 else if (optype1 == OFFSOP) 1090 latehalf[1] = adj_offsettable_operand (operands[1], 4); 1091 else if (optype1 == CNSTOP) 1092 split_double (operands[1], &operands[1], &latehalf[1]); 1093 else 1094 latehalf[1] = operands[1]; 1095 } 1096 1097 /* If insn is effectively movd N (sp),-(sp) then we will do the 1098 high word first. We should use the adjusted operand 1 1099 (which is N+4 (sp) or N+8 (sp)) 1100 for the low word and middle word as well, 1101 to compensate for the first decrement of sp. */ 1102 if (optype0 == PUSHOP 1103 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM 1104 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) 1105 middlehalf[1] = operands[1] = latehalf[1]; 1106 1107 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), 1108 if the upper part of reg N does not appear in the MEM, arrange to 1109 emit the move late-half first. Otherwise, compute the MEM address 1110 into the upper part of N and use that as a pointer to the memory 1111 operand. */ 1112 if (optype0 == REGOP && optype1 == OFFSOP) 1113 { 1114 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)) 1115 && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0))) 1116 { 1117 /* If both halves of dest are used in the src memory address, 1118 compute the address into latehalf of dest. */ 1119 compadr: 1120 xops[0] = latehalf[0]; 1121 xops[1] = XEXP (operands[1], 0); 1122 output_asm_insn (AS2 (lea%L0,%a1,%0), xops); 1123 if (GET_MODE (operands[1]) == XFmode) 1124 { 1125 operands[1] = gen_rtx_MEM (XFmode, latehalf[0]); 1126 middlehalf[1] = adj_offsettable_operand (operands[1], size-8); 1127 latehalf[1] = adj_offsettable_operand (operands[1], size-4); 1128 } 1129 else 1130 { 1131 operands[1] = gen_rtx_MEM (DImode, latehalf[0]); 1132 latehalf[1] = adj_offsettable_operand (operands[1], size-4); 1133 } 1134 } 1135 1136 else if (size == 12 1137 && reg_mentioned_p (middlehalf[0], XEXP (operands[1], 0))) 1138 { 1139 /* Check for two regs used by both source and dest. */ 1140 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)) 1141 || reg_mentioned_p (latehalf[0], XEXP (operands[1], 0))) 1142 goto compadr; 1143 1144 /* Only the middle reg conflicts; simply put it last. */ 1145 output_asm_insn (singlemove_string (operands), operands); 1146 output_asm_insn (singlemove_string (latehalf), latehalf); 1147 output_asm_insn (singlemove_string (middlehalf), middlehalf); 1148 return ""; 1149 } 1150 1151 else if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))) 1152 /* If the low half of dest is mentioned in the source memory 1153 address, the arrange to emit the move late half first. */ 1154 dest_overlapped_low = 1; 1155 } 1156 1157 /* If one or both operands autodecrementing, 1158 do the two words, high-numbered first. */ 1159 1160 /* Likewise, the first move would clobber the source of the second one, 1161 do them in the other order. This happens only for registers; 1162 such overlap can't happen in memory unless the user explicitly 1163 sets it up, and that is an undefined circumstance. */ 1164 1165#if 0 1166 if (optype0 == PUSHOP || optype1 == PUSHOP 1167 || (optype0 == REGOP && optype1 == REGOP 1168 && REGNO (operands[0]) == REGNO (latehalf[1])) 1169 || dest_overlapped_low) 1170#endif 1171 1172 if (optype0 == PUSHOP || optype1 == PUSHOP 1173 || (optype0 == REGOP && optype1 == REGOP 1174 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1])) 1175 || REGNO (operands[0]) == REGNO (latehalf[1]))) 1176 || dest_overlapped_low) 1177 { 1178 /* Do the high-numbered word. */ 1179 output_asm_insn (singlemove_string (latehalf), latehalf); 1180 1181 if (size == 12) 1182 output_asm_insn (singlemove_string (middlehalf), middlehalf); 1183 1184 /* Do low-numbered word. */ 1185 return singlemove_string (operands); 1186 } 1187 1188 /* Normal case: do the two words, low-numbered first. */ 1189 1190 output_asm_insn (singlemove_string (operands), operands); 1191 1192 /* Do the middle one of the three words for long double */ 1193 if (size == 12) 1194 output_asm_insn (singlemove_string (middlehalf), middlehalf); 1195 1196 /* Do the high-numbered word. */ 1197 output_asm_insn (singlemove_string (latehalf), latehalf); 1198 1199 return ""; 1200} 1201 1202#define MAX_TMPS 2 /* max temporary registers used */ 1203 1204/* Output the appropriate code to move push memory on the stack */ 1205 1206char * 1207output_move_pushmem (operands, insn, length, tmp_start, n_operands) 1208 rtx operands[]; 1209 rtx insn; 1210 int length; 1211 int tmp_start; 1212 int n_operands; 1213{ 1214 struct 1215 { 1216 char *load; 1217 char *push; 1218 rtx xops[2]; 1219 } tmp_info[MAX_TMPS]; 1220 1221 rtx src = operands[1]; 1222 int max_tmps = 0; 1223 int offset = 0; 1224 int stack_p = reg_overlap_mentioned_p (stack_pointer_rtx, src); 1225 int stack_offset = 0; 1226 int i, num_tmps; 1227 rtx xops[1]; 1228 1229 if (! offsettable_memref_p (src)) 1230 fatal_insn ("Source is not offsettable", insn); 1231 1232 if ((length & 3) != 0) 1233 fatal_insn ("Pushing non-word aligned size", insn); 1234 1235 /* Figure out which temporary registers we have available */ 1236 for (i = tmp_start; i < n_operands; i++) 1237 { 1238 if (GET_CODE (operands[i]) == REG) 1239 { 1240 if (reg_overlap_mentioned_p (operands[i], src)) 1241 continue; 1242 1243 tmp_info[ max_tmps++ ].xops[1] = operands[i]; 1244 if (max_tmps == MAX_TMPS) 1245 break; 1246 } 1247 } 1248 1249 if (max_tmps == 0) 1250 for (offset = length - 4; offset >= 0; offset -= 4) 1251 { 1252 xops[0] = adj_offsettable_operand (src, offset + stack_offset); 1253 output_asm_insn (AS1(push%L0,%0), xops); 1254 if (stack_p) 1255 stack_offset += 4; 1256 } 1257 1258 else 1259 for (offset = length - 4; offset >= 0; ) 1260 { 1261 for (num_tmps = 0; num_tmps < max_tmps && offset >= 0; num_tmps++) 1262 { 1263 tmp_info[num_tmps].load = AS2(mov%L0,%0,%1); 1264 tmp_info[num_tmps].push = AS1(push%L0,%1); 1265 tmp_info[num_tmps].xops[0] 1266 = adj_offsettable_operand (src, offset + stack_offset); 1267 offset -= 4; 1268 } 1269 1270 for (i = 0; i < num_tmps; i++) 1271 output_asm_insn (tmp_info[i].load, tmp_info[i].xops); 1272 1273 for (i = 0; i < num_tmps; i++) 1274 output_asm_insn (tmp_info[i].push, tmp_info[i].xops); 1275 1276 if (stack_p) 1277 stack_offset += 4*num_tmps; 1278 } 1279 1280 return ""; 1281} 1282 1283int 1284standard_80387_constant_p (x) 1285 rtx x; 1286{ 1287#if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) 1288 REAL_VALUE_TYPE d; 1289 jmp_buf handler; 1290 int is0, is1; 1291 1292 if (setjmp (handler)) 1293 return 0; 1294 1295 set_float_handler (handler); 1296 REAL_VALUE_FROM_CONST_DOUBLE (d, x); 1297 is0 = REAL_VALUES_EQUAL (d, dconst0) && !REAL_VALUE_MINUS_ZERO (d); 1298 is1 = REAL_VALUES_EQUAL (d, dconst1); 1299 set_float_handler (NULL_PTR); 1300 1301 if (is0) 1302 return 1; 1303 1304 if (is1) 1305 return 2; 1306 1307 /* Note that on the 80387, other constants, such as pi, 1308 are much slower to load as standard constants 1309 than to load from doubles in memory! */ 1310 /* ??? Not true on K6: all constants are equal cost. */ 1311#endif 1312 1313 return 0; 1314} 1315 1316char * 1317output_move_const_single (operands) 1318 rtx *operands; 1319{ 1320 if (FP_REG_P (operands[0])) 1321 { 1322 int conval = standard_80387_constant_p (operands[1]); 1323 1324 if (conval == 1) 1325 return "fldz"; 1326 1327 if (conval == 2) 1328 return "fld1"; 1329 } 1330 1331 if (GET_CODE (operands[1]) == CONST_DOUBLE) 1332 { 1333 REAL_VALUE_TYPE r; long l; 1334 1335 if (GET_MODE (operands[1]) == XFmode) 1336 abort (); 1337 1338 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); 1339 REAL_VALUE_TO_TARGET_SINGLE (r, l); 1340 operands[1] = GEN_INT (l); 1341 } 1342 1343 return singlemove_string (operands); 1344} 1345 1346/* Returns 1 if OP is either a symbol reference or a sum of a symbol 1347 reference and a constant. */ 1348 1349int 1350symbolic_operand (op, mode) 1351 register rtx op; 1352 enum machine_mode mode ATTRIBUTE_UNUSED; 1353{ 1354 switch (GET_CODE (op)) 1355 { 1356 case SYMBOL_REF: 1357 case LABEL_REF: 1358 return 1; 1359 1360 case CONST: 1361 op = XEXP (op, 0); 1362 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF 1363 || GET_CODE (XEXP (op, 0)) == LABEL_REF) 1364 && GET_CODE (XEXP (op, 1)) == CONST_INT); 1365 1366 default: 1367 return 0; 1368 } 1369} 1370 1371/* Return nonzero if OP is a constant shift count small enough to 1372 encode into an lea instruction. */ 1373 1374int 1375small_shift_operand (op, mode) 1376 rtx op; 1377 enum machine_mode mode ATTRIBUTE_UNUSED; 1378{ 1379 return (GET_CODE (op) == CONST_INT && INTVAL (op) > 0 && INTVAL (op) < 4); 1380} 1381 1382/* Test for a valid operand for a call instruction. 1383 Don't allow the arg pointer register or virtual regs 1384 since they may change into reg + const, which the patterns 1385 can't handle yet. */ 1386 1387int 1388call_insn_operand (op, mode) 1389 rtx op; 1390 enum machine_mode mode ATTRIBUTE_UNUSED; 1391{ 1392 if (GET_CODE (op) == MEM 1393 && ((CONSTANT_ADDRESS_P (XEXP (op, 0)) 1394 /* This makes a difference for PIC. */ 1395 && general_operand (XEXP (op, 0), Pmode)) 1396 || (GET_CODE (XEXP (op, 0)) == REG 1397 && XEXP (op, 0) != arg_pointer_rtx 1398 && ! (REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER 1399 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER)))) 1400 return 1; 1401 1402 return 0; 1403} 1404 1405/* Like call_insn_operand but allow (mem (symbol_ref ...)) 1406 even if pic. */ 1407 1408int 1409expander_call_insn_operand (op, mode) 1410 rtx op; 1411 enum machine_mode mode ATTRIBUTE_UNUSED; 1412{ 1413 if (GET_CODE (op) == MEM 1414 && (CONSTANT_ADDRESS_P (XEXP (op, 0)) 1415 || (GET_CODE (XEXP (op, 0)) == REG 1416 && XEXP (op, 0) != arg_pointer_rtx 1417 && ! (REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER 1418 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER)))) 1419 return 1; 1420 1421 return 0; 1422} 1423 1424/* Return 1 if OP is a comparison operator that can use the condition code 1425 generated by an arithmetic operation. */ 1426 1427int 1428arithmetic_comparison_operator (op, mode) 1429 register rtx op; 1430 enum machine_mode mode; 1431{ 1432 enum rtx_code code; 1433 1434 if (mode != VOIDmode && mode != GET_MODE (op)) 1435 return 0; 1436 1437 code = GET_CODE (op); 1438 if (GET_RTX_CLASS (code) != '<') 1439 return 0; 1440 1441 return (code != GT && code != LE); 1442} 1443 1444int 1445ix86_logical_operator (op, mode) 1446 register rtx op; 1447 enum machine_mode mode ATTRIBUTE_UNUSED; 1448{ 1449 return GET_CODE (op) == AND || GET_CODE (op) == IOR || GET_CODE (op) == XOR; 1450} 1451 1452 1453/* Returns 1 if OP contains a symbol reference */ 1454 1455int 1456symbolic_reference_mentioned_p (op) 1457 rtx op; 1458{ 1459 register char *fmt; 1460 register int i; 1461 1462 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF) 1463 return 1; 1464 1465 fmt = GET_RTX_FORMAT (GET_CODE (op)); 1466 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--) 1467 { 1468 if (fmt[i] == 'E') 1469 { 1470 register int j; 1471 1472 for (j = XVECLEN (op, i) - 1; j >= 0; j--) 1473 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j))) 1474 return 1; 1475 } 1476 1477 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i))) 1478 return 1; 1479 } 1480 1481 return 0; 1482} 1483 1484/* Attempt to expand a binary operator. Make the expansion closer to the 1485 actual machine, then just general_operand, which will allow 3 separate 1486 memory references (one output, two input) in a single insn. Return 1487 whether the insn fails, or succeeds. */ 1488 1489int 1490ix86_expand_binary_operator (code, mode, operands) 1491 enum rtx_code code; 1492 enum machine_mode mode; 1493 rtx operands[]; 1494{ 1495 int modified; 1496 1497 /* Recognize <var1> = <value> <op> <var1> for commutative operators */ 1498 if (GET_RTX_CLASS (code) == 'c' 1499 && (rtx_equal_p (operands[0], operands[2]) 1500 || immediate_operand (operands[1], mode))) 1501 { 1502 rtx temp = operands[1]; 1503 operands[1] = operands[2]; 1504 operands[2] = temp; 1505 } 1506 1507 /* If optimizing, copy to regs to improve CSE */ 1508 if (TARGET_PSEUDO && optimize 1509 && ((reload_in_progress | reload_completed) == 0)) 1510 { 1511 if (GET_CODE (operands[1]) == MEM 1512 && ! rtx_equal_p (operands[0], operands[1])) 1513 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 1514 1515 if (GET_CODE (operands[2]) == MEM) 1516 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); 1517 1518 if (GET_CODE (operands[1]) == CONST_INT && code == MINUS) 1519 { 1520 rtx temp = gen_reg_rtx (GET_MODE (operands[0])); 1521 1522 emit_move_insn (temp, operands[1]); 1523 operands[1] = temp; 1524 return TRUE; 1525 } 1526 } 1527 1528 if (!ix86_binary_operator_ok (code, mode, operands)) 1529 { 1530 /* If not optimizing, try to make a valid insn (optimize code 1531 previously did this above to improve chances of CSE) */ 1532 1533 if ((! TARGET_PSEUDO || !optimize) 1534 && ((reload_in_progress | reload_completed) == 0) 1535 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)) 1536 { 1537 modified = FALSE; 1538 if (GET_CODE (operands[1]) == MEM 1539 && ! rtx_equal_p (operands[0], operands[1])) 1540 { 1541 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 1542 modified = TRUE; 1543 } 1544 1545 if (GET_CODE (operands[2]) == MEM) 1546 { 1547 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); 1548 modified = TRUE; 1549 } 1550 1551 if (GET_CODE (operands[1]) == CONST_INT && code == MINUS) 1552 { 1553 rtx temp = gen_reg_rtx (GET_MODE (operands[0])); 1554 1555 emit_move_insn (temp, operands[1]); 1556 operands[1] = temp; 1557 return TRUE; 1558 } 1559 1560 if (modified && ! ix86_binary_operator_ok (code, mode, operands)) 1561 return FALSE; 1562 } 1563 else 1564 return FALSE; 1565 } 1566 1567 return TRUE; 1568} 1569 1570/* Return TRUE or FALSE depending on whether the binary operator meets the 1571 appropriate constraints. */ 1572 1573int 1574ix86_binary_operator_ok (code, mode, operands) 1575 enum rtx_code code; 1576 enum machine_mode mode ATTRIBUTE_UNUSED; 1577 rtx operands[3]; 1578{ 1579 return (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM) 1580 && (GET_CODE (operands[1]) != CONST_INT || GET_RTX_CLASS (code) == 'c'); 1581} 1582 1583/* Attempt to expand a unary operator. Make the expansion closer to the 1584 actual machine, then just general_operand, which will allow 2 separate 1585 memory references (one output, one input) in a single insn. Return 1586 whether the insn fails, or succeeds. */ 1587 1588int 1589ix86_expand_unary_operator (code, mode, operands) 1590 enum rtx_code code; 1591 enum machine_mode mode; 1592 rtx operands[]; 1593{ 1594 /* If optimizing, copy to regs to improve CSE */ 1595 if (TARGET_PSEUDO 1596 && optimize 1597 && ((reload_in_progress | reload_completed) == 0) 1598 && GET_CODE (operands[1]) == MEM) 1599 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 1600 1601 if (! ix86_unary_operator_ok (code, mode, operands)) 1602 { 1603 if ((! TARGET_PSEUDO || optimize == 0) 1604 && ((reload_in_progress | reload_completed) == 0) 1605 && GET_CODE (operands[1]) == MEM) 1606 { 1607 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 1608 if (! ix86_unary_operator_ok (code, mode, operands)) 1609 return FALSE; 1610 } 1611 else 1612 return FALSE; 1613 } 1614 1615 return TRUE; 1616} 1617 1618/* Return TRUE or FALSE depending on whether the unary operator meets the 1619 appropriate constraints. */ 1620 1621int 1622ix86_unary_operator_ok (code, mode, operands) 1623 enum rtx_code code ATTRIBUTE_UNUSED; 1624 enum machine_mode mode ATTRIBUTE_UNUSED; 1625 rtx operands[2] ATTRIBUTE_UNUSED; 1626{ 1627 return TRUE; 1628} 1629 1630static rtx pic_label_rtx; 1631static char pic_label_name [256]; 1632static int pic_label_no = 0; 1633 1634/* This function generates code for -fpic that loads %ebx with 1635 the return address of the caller and then returns. */ 1636 1637void 1638asm_output_function_prefix (file, name) 1639 FILE *file; 1640 char *name ATTRIBUTE_UNUSED; 1641{ 1642 rtx xops[2]; 1643 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table 1644 || current_function_uses_const_pool); 1645 xops[0] = pic_offset_table_rtx; 1646 xops[1] = stack_pointer_rtx; 1647 1648 /* Deep branch prediction favors having a return for every call. */ 1649 if (pic_reg_used && TARGET_DEEP_BRANCH_PREDICTION) 1650 { 1651 tree prologue_node; 1652 1653 if (pic_label_rtx == 0) 1654 { 1655 pic_label_rtx = gen_label_rtx (); 1656 ASM_GENERATE_INTERNAL_LABEL (pic_label_name, "LPR", pic_label_no++); 1657 LABEL_NAME (pic_label_rtx) = pic_label_name; 1658 } 1659 1660 prologue_node = make_node (FUNCTION_DECL); 1661 DECL_RESULT (prologue_node) = 0; 1662 1663 /* This used to call ASM_DECLARE_FUNCTION_NAME() but since it's an 1664 internal (non-global) label that's being emitted, it didn't make 1665 sense to have .type information for local labels. This caused 1666 the SCO OpenServer 5.0.4 ELF assembler grief (why are you giving 1667 me debug info for a label that you're declaring non-global?) this 1668 was changed to call ASM_OUTPUT_LABEL() instead. */ 1669 1670 1671 ASM_OUTPUT_LABEL (file, pic_label_name); 1672 output_asm_insn ("movl (%1),%0", xops); 1673 output_asm_insn ("ret", xops); 1674 } 1675} 1676 1677/* Generate the assembly code for function entry. 1678 FILE is an stdio stream to output the code to. 1679 SIZE is an int: how many units of temporary storage to allocate. */ 1680 1681void 1682function_prologue (file, size) 1683 FILE *file ATTRIBUTE_UNUSED; 1684 int size ATTRIBUTE_UNUSED; 1685{ 1686 if (TARGET_SCHEDULE_PROLOGUE) 1687 { 1688 pic_label_rtx = 0; 1689 return; 1690 } 1691 1692 ix86_prologue (0); 1693} 1694 1695/* Expand the prologue into a bunch of separate insns. */ 1696 1697void 1698ix86_expand_prologue () 1699{ 1700 if (! TARGET_SCHEDULE_PROLOGUE) 1701 return; 1702 1703 ix86_prologue (1); 1704} 1705 1706void 1707load_pic_register (do_rtl) 1708 int do_rtl; 1709{ 1710 rtx xops[4]; 1711 1712 if (TARGET_DEEP_BRANCH_PREDICTION) 1713 { 1714 xops[0] = pic_offset_table_rtx; 1715 if (pic_label_rtx == 0) 1716 { 1717 pic_label_rtx = gen_label_rtx (); 1718 ASM_GENERATE_INTERNAL_LABEL (pic_label_name, "LPR", pic_label_no++); 1719 LABEL_NAME (pic_label_rtx) = pic_label_name; 1720 } 1721 1722 xops[1] = gen_rtx_MEM (QImode, 1723 gen_rtx (SYMBOL_REF, Pmode, 1724 LABEL_NAME (pic_label_rtx))); 1725 1726 if (do_rtl) 1727 { 1728 emit_insn (gen_prologue_get_pc (xops[0], xops[1])); 1729 emit_insn (gen_prologue_set_got (xops[0], 1730#ifdef YES_UNDERSCORES 1731 gen_rtx_SYMBOL_REF (Pmode, 1732 "$__GLOBAL_OFFSET_TABLE_"), 1733#else 1734 gen_rtx_SYMBOL_REF (Pmode, 1735 "$_GLOBAL_OFFSET_TABLE_"), 1736#endif 1737 xops[1])); 1738 } 1739 else 1740 { 1741 output_asm_insn (AS1 (call,%X1), xops); 1742 output_asm_insn ("addl $%__GLOBAL_OFFSET_TABLE_,%0", xops); 1743 pic_label_rtx = 0; 1744 } 1745 } 1746 1747 else 1748 { 1749 xops[0] = pic_offset_table_rtx; 1750 xops[1] = gen_label_rtx (); 1751 1752 if (do_rtl) 1753 { 1754 /* We can't put a raw CODE_LABEL into the RTL, and we can't emit 1755 a new CODE_LABEL after reload, so we need a single pattern to 1756 emit the 3 necessary instructions. */ 1757 emit_insn (gen_prologue_get_pc_and_set_got (xops[0])); 1758 } 1759 else 1760 { 1761 output_asm_insn (AS1 (call,%P1), xops); 1762 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", 1763 CODE_LABEL_NUMBER (xops[1])); 1764 output_asm_insn (AS1 (pop%L0,%0), xops); 1765 output_asm_insn ("addl $%__GLOBAL_OFFSET_TABLE_+[.-%P1],%0", xops); 1766 } 1767 } 1768 1769 /* When -fpic, we must emit a scheduling barrier, so that the instruction 1770 that restores %ebx (which is PIC_OFFSET_TABLE_REGNUM), does not get 1771 moved before any instruction which implicitly uses the got. */ 1772 1773 if (do_rtl) 1774 emit_insn (gen_blockage ()); 1775} 1776 1777/* Compute the size of local storage taking into consideration the 1778 desired stack alignment which is to be maintained. Also determine 1779 the number of registers saved below the local storage. */ 1780 1781HOST_WIDE_INT 1782ix86_compute_frame_size (size, nregs_on_stack) 1783 HOST_WIDE_INT size; 1784 int *nregs_on_stack; 1785{ 1786 int limit; 1787 int nregs; 1788 int regno; 1789 int padding; 1790 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table 1791 || current_function_uses_const_pool); 1792 HOST_WIDE_INT total_size; 1793 1794 limit = frame_pointer_needed 1795 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM; 1796 1797 nregs = 0; 1798 1799 for (regno = limit - 1; regno >= 0; regno--) 1800 if ((regs_ever_live[regno] && ! call_used_regs[regno]) 1801 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) 1802 nregs++; 1803 1804 padding = 0; 1805 total_size = size + (nregs * UNITS_PER_WORD); 1806 1807#ifdef PREFERRED_STACK_BOUNDARY 1808 { 1809 int offset; 1810 int preferred_alignment = PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT; 1811 1812 offset = 4; 1813 if (frame_pointer_needed) 1814 offset += UNITS_PER_WORD; 1815 1816 total_size += offset; 1817 1818 padding = ((total_size + preferred_alignment - 1) 1819 & -preferred_alignment) - total_size; 1820 1821 if (padding < (((offset + preferred_alignment - 1) 1822 & -preferred_alignment) - offset)) 1823 padding += preferred_alignment; 1824 1825 /* Don't bother aligning the stack of a leaf function 1826 which doesn't allocate any stack slots. */ 1827 if (size == 0 && current_function_is_leaf) 1828 padding = 0; 1829 } 1830#endif 1831 1832 if (nregs_on_stack) 1833 *nregs_on_stack = nregs; 1834 1835 return size + padding; 1836} 1837 1838static void 1839ix86_prologue (do_rtl) 1840 int do_rtl; 1841{ 1842 register int regno; 1843 int limit; 1844 rtx xops[4]; 1845 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table 1846 || current_function_uses_const_pool); 1847 HOST_WIDE_INT tsize = ix86_compute_frame_size (get_frame_size (), (int *)0); 1848 rtx insn; 1849 int cfa_offset = INCOMING_FRAME_SP_OFFSET, cfa_store_offset = cfa_offset; 1850 1851 xops[0] = stack_pointer_rtx; 1852 xops[1] = frame_pointer_rtx; 1853 xops[2] = GEN_INT (tsize); 1854 1855 if (frame_pointer_needed) 1856 { 1857 if (do_rtl) 1858 { 1859 insn = emit_insn (gen_rtx (SET, VOIDmode, 1860 gen_rtx_MEM (SImode, 1861 gen_rtx (PRE_DEC, SImode, 1862 stack_pointer_rtx)), 1863 frame_pointer_rtx)); 1864 1865 RTX_FRAME_RELATED_P (insn) = 1; 1866 insn = emit_move_insn (xops[1], xops[0]); 1867 RTX_FRAME_RELATED_P (insn) = 1; 1868 } 1869 1870 else 1871 { 1872 output_asm_insn ("push%L1 %1", xops); 1873#ifdef INCOMING_RETURN_ADDR_RTX 1874 if (dwarf2out_do_frame ()) 1875 { 1876 char *l = dwarf2out_cfi_label (); 1877 1878 cfa_store_offset += 4; 1879 cfa_offset = cfa_store_offset; 1880 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset); 1881 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, - cfa_store_offset); 1882 } 1883#endif 1884 1885 output_asm_insn (AS2 (mov%L0,%0,%1), xops); 1886#ifdef INCOMING_RETURN_ADDR_RTX 1887 if (dwarf2out_do_frame ()) 1888 dwarf2out_def_cfa ("", FRAME_POINTER_REGNUM, cfa_offset); 1889#endif 1890 } 1891 } 1892 1893 if (tsize == 0) 1894 ; 1895 else if (! TARGET_STACK_PROBE || tsize < CHECK_STACK_LIMIT) 1896 { 1897 if (do_rtl) 1898 { 1899 insn = emit_insn (gen_prologue_set_stack_ptr (xops[2])); 1900 RTX_FRAME_RELATED_P (insn) = 1; 1901 } 1902 else 1903 { 1904 output_asm_insn (AS2 (sub%L0,%2,%0), xops); 1905#ifdef INCOMING_RETURN_ADDR_RTX 1906 if (dwarf2out_do_frame ()) 1907 { 1908 cfa_store_offset += tsize; 1909 if (! frame_pointer_needed) 1910 { 1911 cfa_offset = cfa_store_offset; 1912 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, cfa_offset); 1913 } 1914 } 1915#endif 1916 } 1917 } 1918 else 1919 { 1920 xops[3] = gen_rtx_REG (SImode, 0); 1921 if (do_rtl) 1922 emit_move_insn (xops[3], xops[2]); 1923 else 1924 output_asm_insn (AS2 (mov%L0,%2,%3), xops); 1925 1926 xops[3] = gen_rtx_MEM (FUNCTION_MODE, 1927 gen_rtx (SYMBOL_REF, Pmode, "_alloca")); 1928 1929 if (do_rtl) 1930 emit_call_insn (gen_rtx (CALL, VOIDmode, xops[3], const0_rtx)); 1931 else 1932 output_asm_insn (AS1 (call,%P3), xops); 1933 } 1934 1935 /* Note If use enter it is NOT reversed args. 1936 This one is not reversed from intel!! 1937 I think enter is slower. Also sdb doesn't like it. 1938 But if you want it the code is: 1939 { 1940 xops[3] = const0_rtx; 1941 output_asm_insn ("enter %2,%3", xops); 1942 } 1943 */ 1944 1945 limit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM); 1946 for (regno = limit - 1; regno >= 0; regno--) 1947 if ((regs_ever_live[regno] && ! call_used_regs[regno]) 1948 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) 1949 { 1950 xops[0] = gen_rtx_REG (SImode, regno); 1951 if (do_rtl) 1952 { 1953 insn = emit_insn (gen_rtx (SET, VOIDmode, 1954 gen_rtx_MEM (SImode, 1955 gen_rtx (PRE_DEC, SImode, 1956 stack_pointer_rtx)), 1957 xops[0])); 1958 1959 RTX_FRAME_RELATED_P (insn) = 1; 1960 } 1961 else 1962 { 1963 output_asm_insn ("push%L0 %0", xops); 1964#ifdef INCOMING_RETURN_ADDR_RTX 1965 if (dwarf2out_do_frame ()) 1966 { 1967 char *l = dwarf2out_cfi_label (); 1968 1969 cfa_store_offset += 4; 1970 if (! frame_pointer_needed) 1971 { 1972 cfa_offset = cfa_store_offset; 1973 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset); 1974 } 1975 1976 dwarf2out_reg_save (l, regno, - cfa_store_offset); 1977 } 1978#endif 1979 } 1980 } 1981 1982#ifdef SUBTARGET_PROLOGUE 1983 SUBTARGET_PROLOGUE; 1984#endif 1985 1986 if (pic_reg_used) 1987 load_pic_register (do_rtl); 1988 1989 /* If we are profiling, make sure no instructions are scheduled before 1990 the call to mcount. However, if -fpic, the above call will have 1991 done that. */ 1992 if ((profile_flag || profile_block_flag) 1993 && ! pic_reg_used && do_rtl) 1994 emit_insn (gen_blockage ()); 1995} 1996 1997/* Return 1 if it is appropriate to emit `ret' instructions in the 1998 body of a function. Do this only if the epilogue is simple, needing a 1999 couple of insns. Prior to reloading, we can't tell how many registers 2000 must be saved, so return 0 then. Return 0 if there is no frame 2001 marker to de-allocate. 2002 2003 If NON_SAVING_SETJMP is defined and true, then it is not possible 2004 for the epilogue to be simple, so return 0. This is a special case 2005 since NON_SAVING_SETJMP will not cause regs_ever_live to change 2006 until final, but jump_optimize may need to know sooner if a 2007 `return' is OK. */ 2008 2009int 2010ix86_can_use_return_insn_p () 2011{ 2012 int regno; 2013 int nregs = 0; 2014 int reglimit = (frame_pointer_needed 2015 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM); 2016 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table 2017 || current_function_uses_const_pool); 2018 2019#ifdef NON_SAVING_SETJMP 2020 if (NON_SAVING_SETJMP && current_function_calls_setjmp) 2021 return 0; 2022#endif 2023 2024 if (! reload_completed) 2025 return 0; 2026 2027 for (regno = reglimit - 1; regno >= 0; regno--) 2028 if ((regs_ever_live[regno] && ! call_used_regs[regno]) 2029 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) 2030 nregs++; 2031 2032 return nregs == 0 || ! frame_pointer_needed; 2033} 2034 2035/* This function generates the assembly code for function exit. 2036 FILE is an stdio stream to output the code to. 2037 SIZE is an int: how many units of temporary storage to deallocate. */ 2038 2039void 2040function_epilogue (file, size) 2041 FILE *file ATTRIBUTE_UNUSED; 2042 int size ATTRIBUTE_UNUSED; 2043{ 2044 return; 2045} 2046 2047/* Restore function stack, frame, and registers. */ 2048 2049void 2050ix86_expand_epilogue () 2051{ 2052 ix86_epilogue (1); 2053} 2054 2055static void 2056ix86_epilogue (do_rtl) 2057 int do_rtl; 2058{ 2059 register int regno; 2060 register int limit; 2061 int nregs; 2062 rtx xops[3]; 2063 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table 2064 || current_function_uses_const_pool); 2065 int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging; 2066 HOST_WIDE_INT offset; 2067 HOST_WIDE_INT tsize = ix86_compute_frame_size (get_frame_size (), &nregs); 2068 2069 /* sp is often unreliable so we may have to go off the frame pointer. */ 2070 2071 offset = -(tsize + nregs * UNITS_PER_WORD); 2072 2073 xops[2] = stack_pointer_rtx; 2074 2075 /* When -fpic, we must emit a scheduling barrier, so that the instruction 2076 that restores %ebx (which is PIC_OFFSET_TABLE_REGNUM), does not get 2077 moved before any instruction which implicitly uses the got. This 2078 includes any instruction which uses a SYMBOL_REF or a LABEL_REF. 2079 2080 Alternatively, this could be fixed by making the dependence on the 2081 PIC_OFFSET_TABLE_REGNUM explicit in the RTL. */ 2082 2083 if (flag_pic || profile_flag || profile_block_flag) 2084 emit_insn (gen_blockage ()); 2085 2086 /* If we're only restoring one register and sp is not valid then 2087 using a move instruction to restore the register since it's 2088 less work than reloading sp and popping the register. Otherwise, 2089 restore sp (if necessary) and pop the registers. */ 2090 2091 limit = frame_pointer_needed 2092 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM; 2093 2094 if (nregs > 1 || sp_valid) 2095 { 2096 if ( !sp_valid ) 2097 { 2098 xops[0] = adj_offsettable_operand (AT_BP (QImode), offset); 2099 if (do_rtl) 2100 emit_insn (gen_movsi_lea (xops[2], XEXP (xops[0], 0))); 2101 else 2102 output_asm_insn (AS2 (lea%L2,%0,%2), xops); 2103 } 2104 2105 for (regno = 0; regno < limit; regno++) 2106 if ((regs_ever_live[regno] && ! call_used_regs[regno]) 2107 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) 2108 { 2109 xops[0] = gen_rtx_REG (SImode, regno); 2110 2111 if (do_rtl) 2112 emit_insn (gen_pop (xops[0])); 2113 else 2114 output_asm_insn ("pop%L0 %0", xops); 2115 } 2116 } 2117 2118 else 2119 for (regno = 0; regno < limit; regno++) 2120 if ((regs_ever_live[regno] && ! call_used_regs[regno]) 2121 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) 2122 { 2123 xops[0] = gen_rtx_REG (SImode, regno); 2124 xops[1] = adj_offsettable_operand (AT_BP (Pmode), offset); 2125 2126 if (do_rtl) 2127 emit_move_insn (xops[0], xops[1]); 2128 else 2129 output_asm_insn (AS2 (mov%L0,%1,%0), xops); 2130 2131 offset += 4; 2132 } 2133 2134 if (frame_pointer_needed) 2135 { 2136 /* If not an i386, mov & pop is faster than "leave". */ 2137 2138 if (TARGET_USE_LEAVE) 2139 { 2140 if (do_rtl) 2141 emit_insn (gen_leave()); 2142 else 2143 output_asm_insn ("leave", xops); 2144 } 2145 else 2146 { 2147 xops[0] = frame_pointer_rtx; 2148 xops[1] = stack_pointer_rtx; 2149 2150 if (do_rtl) 2151 { 2152 emit_insn (gen_epilogue_set_stack_ptr()); 2153 emit_insn (gen_pop (xops[0])); 2154 } 2155 else 2156 { 2157 output_asm_insn (AS2 (mov%L2,%0,%2), xops); 2158 output_asm_insn ("pop%L0 %0", xops); 2159 } 2160 } 2161 } 2162 2163 else if (tsize) 2164 { 2165 /* Intel's docs say that for 4 or 8 bytes of stack frame one should 2166 use `pop' and not `add'. */ 2167 int use_pop = tsize == 4; 2168 2169 /* Use two pops only for the Pentium processors. */ 2170 if (tsize == 8 && !TARGET_386 && !TARGET_486) 2171 { 2172 rtx retval = current_function_return_rtx; 2173 2174 xops[1] = gen_rtx_REG (SImode, 1); /* %edx */ 2175 2176 /* This case is a bit more complex. Since we cannot pop into 2177 %ecx twice we need a second register. But this is only 2178 available if the return value is not of DImode in which 2179 case the %edx register is not available. */ 2180 use_pop = (retval == NULL 2181 || ! reg_overlap_mentioned_p (xops[1], retval)); 2182 } 2183 2184 if (use_pop) 2185 { 2186 xops[0] = gen_rtx_REG (SImode, 2); /* %ecx */ 2187 2188 if (do_rtl) 2189 { 2190 /* We have to prevent the two pops here from being scheduled. 2191 GCC otherwise would try in some situation to put other 2192 instructions in between them which has a bad effect. */ 2193 emit_insn (gen_blockage ()); 2194 emit_insn (gen_pop (xops[0])); 2195 if (tsize == 8) 2196 emit_insn (gen_pop (xops[1])); 2197 } 2198 else 2199 { 2200 output_asm_insn ("pop%L0 %0", xops); 2201 if (tsize == 8) 2202 output_asm_insn ("pop%L1 %1", xops); 2203 } 2204 } 2205 else 2206 { 2207 /* If there is no frame pointer, we must still release the frame. */ 2208 xops[0] = GEN_INT (tsize); 2209 2210 if (do_rtl) 2211 emit_insn (gen_rtx (SET, VOIDmode, xops[2], 2212 gen_rtx (PLUS, SImode, xops[2], xops[0]))); 2213 else 2214 output_asm_insn (AS2 (add%L2,%0,%2), xops); 2215 } 2216 } 2217 2218#ifdef FUNCTION_BLOCK_PROFILER_EXIT 2219 if (profile_block_flag == 2) 2220 { 2221 FUNCTION_BLOCK_PROFILER_EXIT(file); 2222 } 2223#endif 2224 2225 if (current_function_pops_args && current_function_args_size) 2226 { 2227 xops[1] = GEN_INT (current_function_pops_args); 2228 2229 /* i386 can only pop 32K bytes (maybe 64K? Is it signed?). If 2230 asked to pop more, pop return address, do explicit add, and jump 2231 indirectly to the caller. */ 2232 2233 if (current_function_pops_args >= 32768) 2234 { 2235 /* ??? Which register to use here? */ 2236 xops[0] = gen_rtx_REG (SImode, 2); 2237 2238 if (do_rtl) 2239 { 2240 emit_insn (gen_pop (xops[0])); 2241 emit_insn (gen_rtx (SET, VOIDmode, xops[2], 2242 gen_rtx (PLUS, SImode, xops[1], xops[2]))); 2243 emit_jump_insn (xops[0]); 2244 } 2245 else 2246 { 2247 output_asm_insn ("pop%L0 %0", xops); 2248 output_asm_insn (AS2 (add%L2,%1,%2), xops); 2249 output_asm_insn ("jmp %*%0", xops); 2250 } 2251 } 2252 else 2253 { 2254 if (do_rtl) 2255 emit_jump_insn (gen_return_pop_internal (xops[1])); 2256 else 2257 output_asm_insn ("ret %1", xops); 2258 } 2259 } 2260 else 2261 { 2262 if (do_rtl) 2263 emit_jump_insn (gen_return_internal ()); 2264 else 2265 output_asm_insn ("ret", xops); 2266 } 2267} 2268 2269/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 2270 that is a valid memory address for an instruction. 2271 The MODE argument is the machine mode for the MEM expression 2272 that wants to use this address. 2273 2274 On x86, legitimate addresses are: 2275 base movl (base),reg 2276 displacement movl disp,reg 2277 base + displacement movl disp(base),reg 2278 index + base movl (base,index),reg 2279 (index + base) + displacement movl disp(base,index),reg 2280 index*scale movl (,index,scale),reg 2281 index*scale + disp movl disp(,index,scale),reg 2282 index*scale + base movl (base,index,scale),reg 2283 (index*scale + base) + disp movl disp(base,index,scale),reg 2284 2285 In each case, scale can be 1, 2, 4, 8. */ 2286 2287/* This is exactly the same as print_operand_addr, except that 2288 it recognizes addresses instead of printing them. 2289 2290 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should 2291 convert common non-canonical forms to canonical form so that they will 2292 be recognized. */ 2293 2294#define ADDR_INVALID(msg,insn) \ 2295do { \ 2296 if (TARGET_DEBUG_ADDR) \ 2297 { \ 2298 fprintf (stderr, msg); \ 2299 debug_rtx (insn); \ 2300 } \ 2301} while (0) 2302 2303int 2304legitimate_pic_address_disp_p (disp) 2305 register rtx disp; 2306{ 2307 if (GET_CODE (disp) != CONST) 2308 return 0; 2309 disp = XEXP (disp, 0); 2310 2311 if (GET_CODE (disp) == PLUS) 2312 { 2313 if (GET_CODE (XEXP (disp, 1)) != CONST_INT) 2314 return 0; 2315 disp = XEXP (disp, 0); 2316 } 2317 2318 if (GET_CODE (disp) != UNSPEC 2319 || XVECLEN (disp, 0) != 1) 2320 return 0; 2321 2322 /* Must be @GOT or @GOTOFF. */ 2323 if (XINT (disp, 1) != 6 2324 && XINT (disp, 1) != 7) 2325 return 0; 2326 2327 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF 2328 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF) 2329 return 0; 2330 2331 return 1; 2332} 2333 2334int 2335legitimate_address_p (mode, addr, strict) 2336 enum machine_mode mode; 2337 register rtx addr; 2338 int strict; 2339{ 2340 rtx base = NULL_RTX; 2341 rtx indx = NULL_RTX; 2342 rtx scale = NULL_RTX; 2343 rtx disp = NULL_RTX; 2344 2345 if (TARGET_DEBUG_ADDR) 2346 { 2347 fprintf (stderr, 2348 "\n======\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n", 2349 GET_MODE_NAME (mode), strict); 2350 2351 debug_rtx (addr); 2352 } 2353 2354 if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG) 2355 base = addr; 2356 2357 else if (GET_CODE (addr) == PLUS) 2358 { 2359 rtx op0 = XEXP (addr, 0); 2360 rtx op1 = XEXP (addr, 1); 2361 enum rtx_code code0 = GET_CODE (op0); 2362 enum rtx_code code1 = GET_CODE (op1); 2363 2364 if (code0 == REG || code0 == SUBREG) 2365 { 2366 if (code1 == REG || code1 == SUBREG) 2367 { 2368 indx = op0; /* index + base */ 2369 base = op1; 2370 } 2371 2372 else 2373 { 2374 base = op0; /* base + displacement */ 2375 disp = op1; 2376 } 2377 } 2378 2379 else if (code0 == MULT) 2380 { 2381 indx = XEXP (op0, 0); 2382 scale = XEXP (op0, 1); 2383 2384 if (code1 == REG || code1 == SUBREG) 2385 base = op1; /* index*scale + base */ 2386 2387 else 2388 disp = op1; /* index*scale + disp */ 2389 } 2390 2391 else if (code0 == PLUS && GET_CODE (XEXP (op0, 0)) == MULT) 2392 { 2393 indx = XEXP (XEXP (op0, 0), 0); /* index*scale + base + disp */ 2394 scale = XEXP (XEXP (op0, 0), 1); 2395 base = XEXP (op0, 1); 2396 disp = op1; 2397 } 2398 2399 else if (code0 == PLUS) 2400 { 2401 indx = XEXP (op0, 0); /* index + base + disp */ 2402 base = XEXP (op0, 1); 2403 disp = op1; 2404 } 2405 2406 else 2407 { 2408 ADDR_INVALID ("PLUS subcode is not valid.\n", op0); 2409 return FALSE; 2410 } 2411 } 2412 2413 else if (GET_CODE (addr) == MULT) 2414 { 2415 indx = XEXP (addr, 0); /* index*scale */ 2416 scale = XEXP (addr, 1); 2417 } 2418 2419 else 2420 disp = addr; /* displacement */ 2421 2422 /* Allow arg pointer and stack pointer as index if there is not scaling */ 2423 if (base && indx && !scale 2424 && (indx == arg_pointer_rtx || indx == stack_pointer_rtx)) 2425 { 2426 rtx tmp = base; 2427 base = indx; 2428 indx = tmp; 2429 } 2430 2431 /* Validate base register: 2432 2433 Don't allow SUBREG's here, it can lead to spill failures when the base 2434 is one word out of a two word structure, which is represented internally 2435 as a DImode int. */ 2436 2437 if (base) 2438 { 2439 if (GET_CODE (base) != REG) 2440 { 2441 ADDR_INVALID ("Base is not a register.\n", base); 2442 return FALSE; 2443 } 2444 2445 if (GET_MODE (base) != Pmode) 2446 { 2447 ADDR_INVALID ("Base is not in Pmode.\n", base); 2448 return FALSE; 2449 } 2450 2451 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (base)) 2452 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (base))) 2453 { 2454 ADDR_INVALID ("Base is not valid.\n", base); 2455 return FALSE; 2456 } 2457 } 2458 2459 /* Validate index register: 2460 2461 Don't allow SUBREG's here, it can lead to spill failures when the index 2462 is one word out of a two word structure, which is represented internally 2463 as a DImode int. */ 2464 if (indx) 2465 { 2466 if (GET_CODE (indx) != REG) 2467 { 2468 ADDR_INVALID ("Index is not a register.\n", indx); 2469 return FALSE; 2470 } 2471 2472 if (GET_MODE (indx) != Pmode) 2473 { 2474 ADDR_INVALID ("Index is not in Pmode.\n", indx); 2475 return FALSE; 2476 } 2477 2478 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (indx)) 2479 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (indx))) 2480 { 2481 ADDR_INVALID ("Index is not valid.\n", indx); 2482 return FALSE; 2483 } 2484 } 2485 else if (scale) 2486 abort (); /* scale w/o index invalid */ 2487 2488 /* Validate scale factor: */ 2489 if (scale) 2490 { 2491 HOST_WIDE_INT value; 2492 2493 if (GET_CODE (scale) != CONST_INT) 2494 { 2495 ADDR_INVALID ("Scale is not valid.\n", scale); 2496 return FALSE; 2497 } 2498 2499 value = INTVAL (scale); 2500 if (value != 1 && value != 2 && value != 4 && value != 8) 2501 { 2502 ADDR_INVALID ("Scale is not a good multiplier.\n", scale); 2503 return FALSE; 2504 } 2505 } 2506 2507 /* Validate displacement. */ 2508 if (disp) 2509 { 2510 if (!CONSTANT_ADDRESS_P (disp)) 2511 { 2512 ADDR_INVALID ("Displacement is not valid.\n", disp); 2513 return FALSE; 2514 } 2515 2516 else if (GET_CODE (disp) == CONST_DOUBLE) 2517 { 2518 ADDR_INVALID ("Displacement is a const_double.\n", disp); 2519 return FALSE; 2520 } 2521 2522 if (flag_pic && SYMBOLIC_CONST (disp)) 2523 { 2524 if (! legitimate_pic_address_disp_p (disp)) 2525 { 2526 ADDR_INVALID ("Displacement is an invalid PIC construct.\n", 2527 disp); 2528 return FALSE; 2529 } 2530 2531 if (base != pic_offset_table_rtx 2532 && (indx != pic_offset_table_rtx || scale != NULL_RTX)) 2533 { 2534 ADDR_INVALID ("PIC displacement against invalid base.\n", disp); 2535 return FALSE; 2536 } 2537 } 2538 2539 else if (HALF_PIC_P ()) 2540 { 2541 if (! HALF_PIC_ADDRESS_P (disp) 2542 || (base != NULL_RTX || indx != NULL_RTX)) 2543 { 2544 ADDR_INVALID ("Displacement is an invalid half-pic reference.\n", 2545 disp); 2546 return FALSE; 2547 } 2548 } 2549 } 2550 2551 if (TARGET_DEBUG_ADDR) 2552 fprintf (stderr, "Address is valid.\n"); 2553 2554 /* Everything looks valid, return true */ 2555 return TRUE; 2556} 2557 2558/* Return a legitimate reference for ORIG (an address) using the 2559 register REG. If REG is 0, a new pseudo is generated. 2560 2561 There are two types of references that must be handled: 2562 2563 1. Global data references must load the address from the GOT, via 2564 the PIC reg. An insn is emitted to do this load, and the reg is 2565 returned. 2566 2567 2. Static data references, constant pool addresses, and code labels 2568 compute the address as an offset from the GOT, whose base is in 2569 the PIC reg. Static data objects have SYMBOL_REF_FLAG set to 2570 differentiate them from global data objects. The returned 2571 address is the PIC reg + an unspec constant. 2572 2573 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC 2574 reg also appears in the address. */ 2575 2576rtx 2577legitimize_pic_address (orig, reg) 2578 rtx orig; 2579 rtx reg; 2580{ 2581 rtx addr = orig; 2582 rtx new = orig; 2583 rtx base; 2584 2585 if (GET_CODE (addr) == LABEL_REF 2586 || (GET_CODE (addr) == SYMBOL_REF 2587 && (CONSTANT_POOL_ADDRESS_P (addr) 2588 || SYMBOL_REF_FLAG (addr)))) 2589 { 2590 /* This symbol may be referenced via a displacement from the PIC 2591 base address (@GOTOFF). */ 2592 2593 current_function_uses_pic_offset_table = 1; 2594 new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, addr), 7); 2595 new = gen_rtx_CONST (VOIDmode, new); 2596 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new); 2597 2598 if (reg != 0) 2599 { 2600 emit_move_insn (reg, new); 2601 new = reg; 2602 } 2603 } 2604 else if (GET_CODE (addr) == SYMBOL_REF) 2605 { 2606 /* This symbol must be referenced via a load from the 2607 Global Offset Table (@GOT). */ 2608 2609 current_function_uses_pic_offset_table = 1; 2610 new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, addr), 6); 2611 new = gen_rtx_CONST (VOIDmode, new); 2612 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new); 2613 new = gen_rtx_MEM (Pmode, new); 2614 RTX_UNCHANGING_P (new) = 1; 2615 2616 if (reg == 0) 2617 reg = gen_reg_rtx (Pmode); 2618 emit_move_insn (reg, new); 2619 new = reg; 2620 } 2621 else 2622 { 2623 if (GET_CODE (addr) == CONST) 2624 { 2625 addr = XEXP (addr, 0); 2626 if (GET_CODE (addr) == UNSPEC) 2627 { 2628 /* Check that the unspec is one of the ones we generate? */ 2629 } 2630 else if (GET_CODE (addr) != PLUS) 2631 abort(); 2632 } 2633 if (GET_CODE (addr) == PLUS) 2634 { 2635 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1); 2636 2637 /* Check first to see if this is a constant offset from a @GOTOFF 2638 symbol reference. */ 2639 if ((GET_CODE (op0) == LABEL_REF 2640 || (GET_CODE (op0) == SYMBOL_REF 2641 && (CONSTANT_POOL_ADDRESS_P (op0) 2642 || SYMBOL_REF_FLAG (op0)))) 2643 && GET_CODE (op1) == CONST_INT) 2644 { 2645 current_function_uses_pic_offset_table = 1; 2646 new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, op0), 7); 2647 new = gen_rtx_PLUS (VOIDmode, new, op1); 2648 new = gen_rtx_CONST (VOIDmode, new); 2649 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new); 2650 2651 if (reg != 0) 2652 { 2653 emit_move_insn (reg, new); 2654 new = reg; 2655 } 2656 } 2657 else 2658 { 2659 base = legitimize_pic_address (XEXP (addr, 0), reg); 2660 new = legitimize_pic_address (XEXP (addr, 1), 2661 base == reg ? NULL_RTX : reg); 2662 2663 if (GET_CODE (new) == CONST_INT) 2664 new = plus_constant (base, INTVAL (new)); 2665 else 2666 { 2667 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1))) 2668 { 2669 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0)); 2670 new = XEXP (new, 1); 2671 } 2672 new = gen_rtx_PLUS (Pmode, base, new); 2673 } 2674 } 2675 } 2676 } 2677 return new; 2678} 2679 2680/* Emit insns to move operands[1] into operands[0]. */ 2681 2682void 2683emit_pic_move (operands, mode) 2684 rtx *operands; 2685 enum machine_mode mode ATTRIBUTE_UNUSED; 2686{ 2687 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); 2688 2689 if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1])) 2690 operands[1] = force_reg (Pmode, operands[1]); 2691 else 2692 operands[1] = legitimize_pic_address (operands[1], temp); 2693} 2694 2695/* Try machine-dependent ways of modifying an illegitimate address 2696 to be legitimate. If we find one, return the new, valid address. 2697 This macro is used in only one place: `memory_address' in explow.c. 2698 2699 OLDX is the address as it was before break_out_memory_refs was called. 2700 In some cases it is useful to look at this to decide what needs to be done. 2701 2702 MODE and WIN are passed so that this macro can use 2703 GO_IF_LEGITIMATE_ADDRESS. 2704 2705 It is always safe for this macro to do nothing. It exists to recognize 2706 opportunities to optimize the output. 2707 2708 For the 80386, we handle X+REG by loading X into a register R and 2709 using R+REG. R will go in a general reg and indexing will be used. 2710 However, if REG is a broken-out memory address or multiplication, 2711 nothing needs to be done because REG can certainly go in a general reg. 2712 2713 When -fpic is used, special handling is needed for symbolic references. 2714 See comments by legitimize_pic_address in i386.c for details. */ 2715 2716rtx 2717legitimize_address (x, oldx, mode) 2718 register rtx x; 2719 register rtx oldx ATTRIBUTE_UNUSED; 2720 enum machine_mode mode; 2721{ 2722 int changed = 0; 2723 unsigned log; 2724 2725 if (TARGET_DEBUG_ADDR) 2726 { 2727 fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n", 2728 GET_MODE_NAME (mode)); 2729 debug_rtx (x); 2730 } 2731 2732 if (flag_pic && SYMBOLIC_CONST (x)) 2733 return legitimize_pic_address (x, 0); 2734 2735 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */ 2736 if (GET_CODE (x) == ASHIFT 2737 && GET_CODE (XEXP (x, 1)) == CONST_INT 2738 && (log = (unsigned)exact_log2 (INTVAL (XEXP (x, 1)))) < 4) 2739 { 2740 changed = 1; 2741 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)), 2742 GEN_INT (1 << log)); 2743 } 2744 2745 if (GET_CODE (x) == PLUS) 2746 { 2747 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */ 2748 2749 if (GET_CODE (XEXP (x, 0)) == ASHIFT 2750 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 2751 && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) < 4) 2752 { 2753 changed = 1; 2754 XEXP (x, 0) = gen_rtx (MULT, Pmode, 2755 force_reg (Pmode, XEXP (XEXP (x, 0), 0)), 2756 GEN_INT (1 << log)); 2757 } 2758 2759 if (GET_CODE (XEXP (x, 1)) == ASHIFT 2760 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT 2761 && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1)))) < 4) 2762 { 2763 changed = 1; 2764 XEXP (x, 1) = gen_rtx (MULT, Pmode, 2765 force_reg (Pmode, XEXP (XEXP (x, 1), 0)), 2766 GEN_INT (1 << log)); 2767 } 2768 2769 /* Put multiply first if it isn't already. */ 2770 if (GET_CODE (XEXP (x, 1)) == MULT) 2771 { 2772 rtx tmp = XEXP (x, 0); 2773 XEXP (x, 0) = XEXP (x, 1); 2774 XEXP (x, 1) = tmp; 2775 changed = 1; 2776 } 2777 2778 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const))) 2779 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be 2780 created by virtual register instantiation, register elimination, and 2781 similar optimizations. */ 2782 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS) 2783 { 2784 changed = 1; 2785 x = gen_rtx (PLUS, Pmode, 2786 gen_rtx (PLUS, Pmode, XEXP (x, 0), 2787 XEXP (XEXP (x, 1), 0)), 2788 XEXP (XEXP (x, 1), 1)); 2789 } 2790 2791 /* Canonicalize 2792 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const) 2793 into (plus (plus (mult (reg) (const)) (reg)) (const)). */ 2794 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS 2795 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT 2796 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS 2797 && CONSTANT_P (XEXP (x, 1))) 2798 { 2799 rtx constant; 2800 rtx other = NULL_RTX; 2801 2802 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 2803 { 2804 constant = XEXP (x, 1); 2805 other = XEXP (XEXP (XEXP (x, 0), 1), 1); 2806 } 2807 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT) 2808 { 2809 constant = XEXP (XEXP (XEXP (x, 0), 1), 1); 2810 other = XEXP (x, 1); 2811 } 2812 else 2813 constant = 0; 2814 2815 if (constant) 2816 { 2817 changed = 1; 2818 x = gen_rtx (PLUS, Pmode, 2819 gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0), 2820 XEXP (XEXP (XEXP (x, 0), 1), 0)), 2821 plus_constant (other, INTVAL (constant))); 2822 } 2823 } 2824 2825 if (changed && legitimate_address_p (mode, x, FALSE)) 2826 return x; 2827 2828 if (GET_CODE (XEXP (x, 0)) == MULT) 2829 { 2830 changed = 1; 2831 XEXP (x, 0) = force_operand (XEXP (x, 0), 0); 2832 } 2833 2834 if (GET_CODE (XEXP (x, 1)) == MULT) 2835 { 2836 changed = 1; 2837 XEXP (x, 1) = force_operand (XEXP (x, 1), 0); 2838 } 2839 2840 if (changed 2841 && GET_CODE (XEXP (x, 1)) == REG 2842 && GET_CODE (XEXP (x, 0)) == REG) 2843 return x; 2844 2845 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1))) 2846 { 2847 changed = 1; 2848 x = legitimize_pic_address (x, 0); 2849 } 2850 2851 if (changed && legitimate_address_p (mode, x, FALSE)) 2852 return x; 2853 2854 if (GET_CODE (XEXP (x, 0)) == REG) 2855 { 2856 register rtx temp = gen_reg_rtx (Pmode); 2857 register rtx val = force_operand (XEXP (x, 1), temp); 2858 if (val != temp) 2859 emit_move_insn (temp, val); 2860 2861 XEXP (x, 1) = temp; 2862 return x; 2863 } 2864 2865 else if (GET_CODE (XEXP (x, 1)) == REG) 2866 { 2867 register rtx temp = gen_reg_rtx (Pmode); 2868 register rtx val = force_operand (XEXP (x, 0), temp); 2869 if (val != temp) 2870 emit_move_insn (temp, val); 2871 2872 XEXP (x, 0) = temp; 2873 return x; 2874 } 2875 } 2876 2877 return x; 2878} 2879 2880/* Print an integer constant expression in assembler syntax. Addition 2881 and subtraction are the only arithmetic that may appear in these 2882 expressions. FILE is the stdio stream to write to, X is the rtx, and 2883 CODE is the operand print code from the output string. */ 2884 2885static void 2886output_pic_addr_const (file, x, code) 2887 FILE *file; 2888 rtx x; 2889 int code; 2890{ 2891 char buf[256]; 2892 2893 switch (GET_CODE (x)) 2894 { 2895 case PC: 2896 if (flag_pic) 2897 putc ('.', file); 2898 else 2899 abort (); 2900 break; 2901 2902 case SYMBOL_REF: 2903 assemble_name (file, XSTR (x, 0)); 2904 if (code == 'P' && ! SYMBOL_REF_FLAG (x)) 2905 fputs ("@PLT", file); 2906 break; 2907 2908 case LABEL_REF: 2909 x = XEXP (x, 0); 2910 /* FALLTHRU */ 2911 case CODE_LABEL: 2912 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x)); 2913 assemble_name (asm_out_file, buf); 2914 break; 2915 2916 case CONST_INT: 2917 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); 2918 break; 2919 2920 case CONST: 2921 /* This used to output parentheses around the expression, 2922 but that does not work on the 386 (either ATT or BSD assembler). */ 2923 output_pic_addr_const (file, XEXP (x, 0), code); 2924 break; 2925 2926 case CONST_DOUBLE: 2927 if (GET_MODE (x) == VOIDmode) 2928 { 2929 /* We can use %d if the number is <32 bits and positive. */ 2930 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0) 2931 fprintf (file, "0x%lx%08lx", 2932 (unsigned long) CONST_DOUBLE_HIGH (x), 2933 (unsigned long) CONST_DOUBLE_LOW (x)); 2934 else 2935 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x)); 2936 } 2937 else 2938 /* We can't handle floating point constants; 2939 PRINT_OPERAND must handle them. */ 2940 output_operand_lossage ("floating constant misused"); 2941 break; 2942 2943 case PLUS: 2944 /* Some assemblers need integer constants to appear first. */ 2945 if (GET_CODE (XEXP (x, 0)) == CONST_INT) 2946 { 2947 output_pic_addr_const (file, XEXP (x, 0), code); 2948 fprintf (file, "+"); 2949 output_pic_addr_const (file, XEXP (x, 1), code); 2950 } 2951 else if (GET_CODE (XEXP (x, 1)) == CONST_INT) 2952 { 2953 output_pic_addr_const (file, XEXP (x, 1), code); 2954 fprintf (file, "+"); 2955 output_pic_addr_const (file, XEXP (x, 0), code); 2956 } 2957 else 2958 abort (); 2959 break; 2960 2961 case MINUS: 2962 output_pic_addr_const (file, XEXP (x, 0), code); 2963 fprintf (file, "-"); 2964 output_pic_addr_const (file, XEXP (x, 1), code); 2965 break; 2966 2967 case UNSPEC: 2968 if (XVECLEN (x, 0) != 1) 2969 abort (); 2970 output_pic_addr_const (file, XVECEXP (x, 0, 0), code); 2971 switch (XINT (x, 1)) 2972 { 2973 case 6: 2974 fputs ("@GOT", file); 2975 break; 2976 case 7: 2977 fputs ("@GOTOFF", file); 2978 break; 2979 case 8: 2980 fputs ("@PLT", file); 2981 break; 2982 default: 2983 output_operand_lossage ("invalid UNSPEC as operand"); 2984 break; 2985 } 2986 break; 2987 2988 default: 2989 output_operand_lossage ("invalid expression as operand"); 2990 } 2991} 2992 2993static void 2994put_jump_code (code, reverse, file) 2995 enum rtx_code code; 2996 int reverse; 2997 FILE *file; 2998{ 2999 int flags = cc_prev_status.flags; 3000 int ieee = (TARGET_IEEE_FP && (flags & CC_IN_80387) 3001 && !(cc_prev_status.flags & CC_FCOMI)); 3002 const char *suffix; 3003 3004 if (flags & CC_Z_IN_NOT_C) 3005 switch (code) 3006 { 3007 case EQ: 3008 fputs (reverse ? "c" : "nc", file); 3009 return; 3010 3011 case NE: 3012 fputs (reverse ? "nc" : "c", file); 3013 return; 3014 3015 default: 3016 abort (); 3017 } 3018 if (ieee) 3019 { 3020 switch (code) 3021 { 3022 case LE: 3023 suffix = reverse ? "ae" : "b"; 3024 break; 3025 case GT: 3026 case LT: 3027 case GE: 3028 suffix = reverse ? "ne" : "e"; 3029 break; 3030 case EQ: 3031 suffix = reverse ? "ne" : "e"; 3032 break; 3033 case NE: 3034 suffix = reverse ? "e" : "ne"; 3035 break; 3036 default: 3037 abort (); 3038 } 3039 fputs (suffix, file); 3040 return; 3041 } 3042 if (flags & CC_TEST_AX) 3043 abort(); 3044 if ((flags & CC_NO_OVERFLOW) && (code == LE || code == GT)) 3045 abort (); 3046 if (reverse) 3047 code = reverse_condition (code); 3048 switch (code) 3049 { 3050 case EQ: 3051 suffix = "e"; 3052 break; 3053 3054 case NE: 3055 suffix = "ne"; 3056 break; 3057 3058 case GT: 3059 suffix = flags & CC_IN_80387 ? "a" : "g"; 3060 break; 3061 3062 case GTU: 3063 suffix = "a"; 3064 break; 3065 3066 case LT: 3067 if (flags & CC_NO_OVERFLOW) 3068 suffix = "s"; 3069 else 3070 suffix = flags & CC_IN_80387 ? "b" : "l"; 3071 break; 3072 3073 case LTU: 3074 suffix = "b"; 3075 break; 3076 3077 case GE: 3078 if (flags & CC_NO_OVERFLOW) 3079 suffix = "ns"; 3080 else 3081 suffix = flags & CC_IN_80387 ? "ae" : "ge"; 3082 break; 3083 3084 case GEU: 3085 suffix = "ae"; 3086 break; 3087 3088 case LE: 3089 suffix = flags & CC_IN_80387 ? "be" : "le"; 3090 break; 3091 3092 case LEU: 3093 suffix = "be"; 3094 break; 3095 3096 default: 3097 abort (); 3098 } 3099 fputs (suffix, file); 3100} 3101 3102/* Append the correct conditional move suffix which corresponds to CODE. */ 3103 3104static void 3105put_condition_code (code, reverse_cc, mode, file) 3106 enum rtx_code code; 3107 int reverse_cc; 3108 enum mode_class mode; 3109 FILE * file; 3110{ 3111 int ieee = (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387) 3112 && ! (cc_prev_status.flags & CC_FCOMI)); 3113 if (reverse_cc && ! ieee) 3114 code = reverse_condition (code); 3115 3116 if (mode == MODE_INT) 3117 switch (code) 3118 { 3119 case NE: 3120 if (cc_prev_status.flags & CC_Z_IN_NOT_C) 3121 fputs ("b", file); 3122 else 3123 fputs ("ne", file); 3124 return; 3125 3126 case EQ: 3127 if (cc_prev_status.flags & CC_Z_IN_NOT_C) 3128 fputs ("ae", file); 3129 else 3130 fputs ("e", file); 3131 return; 3132 3133 case GE: 3134 if (cc_prev_status.flags & CC_NO_OVERFLOW) 3135 fputs ("ns", file); 3136 else 3137 fputs ("ge", file); 3138 return; 3139 3140 case GT: 3141 fputs ("g", file); 3142 return; 3143 3144 case LE: 3145 fputs ("le", file); 3146 return; 3147 3148 case LT: 3149 if (cc_prev_status.flags & CC_NO_OVERFLOW) 3150 fputs ("s", file); 3151 else 3152 fputs ("l", file); 3153 return; 3154 3155 case GEU: 3156 fputs ("ae", file); 3157 return; 3158 3159 case GTU: 3160 fputs ("a", file); 3161 return; 3162 3163 case LEU: 3164 fputs ("be", file); 3165 return; 3166 3167 case LTU: 3168 fputs ("b", file); 3169 return; 3170 3171 default: 3172 output_operand_lossage ("Invalid %%C operand"); 3173 } 3174 3175 else if (mode == MODE_FLOAT) 3176 switch (code) 3177 { 3178 case NE: 3179 fputs (ieee ? (reverse_cc ? "ne" : "e") : "ne", file); 3180 return; 3181 case EQ: 3182 fputs (ieee ? (reverse_cc ? "ne" : "e") : "e", file); 3183 return; 3184 case GE: 3185 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nb", file); 3186 return; 3187 case GT: 3188 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nbe", file); 3189 return; 3190 case LE: 3191 fputs (ieee ? (reverse_cc ? "nb" : "b") : "be", file); 3192 return; 3193 case LT: 3194 fputs (ieee ? (reverse_cc ? "ne" : "e") : "b", file); 3195 return; 3196 case GEU: 3197 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nb", file); 3198 return; 3199 case GTU: 3200 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nbe", file); 3201 return; 3202 case LEU: 3203 fputs (ieee ? (reverse_cc ? "nb" : "b") : "be", file); 3204 return; 3205 case LTU: 3206 fputs (ieee ? (reverse_cc ? "ne" : "e") : "b", file); 3207 return; 3208 default: 3209 output_operand_lossage ("Invalid %%C operand"); 3210 } 3211} 3212 3213/* Meaning of CODE: 3214 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand. 3215 C -- print opcode suffix for set/cmov insn. 3216 c -- like C, but print reversed condition 3217 F -- print opcode suffix for fcmov insn. 3218 f -- like F, but print reversed condition 3219 D -- print the opcode suffix for a jump 3220 d -- like D, but print reversed condition 3221 R -- print the prefix for register names. 3222 z -- print the opcode suffix for the size of the current operand. 3223 * -- print a star (in certain assembler syntax) 3224 w -- print the operand as if it's a "word" (HImode) even if it isn't. 3225 J -- print the appropriate jump operand. 3226 s -- print a shift double count, followed by the assemblers argument 3227 delimiter. 3228 b -- print the QImode name of the register for the indicated operand. 3229 %b0 would print %al if operands[0] is reg 0. 3230 w -- likewise, print the HImode name of the register. 3231 k -- likewise, print the SImode name of the register. 3232 h -- print the QImode name for a "high" register, either ah, bh, ch or dh. 3233 y -- print "st(0)" instead of "st" as a register. 3234 P -- print as a PIC constant 3235 _ -- output "_" if YES_UNDERSCORES */ 3236 3237void 3238print_operand (file, x, code) 3239 FILE *file; 3240 rtx x; 3241 int code; 3242{ 3243 if (code) 3244 { 3245 switch (code) 3246 { 3247 case '*': 3248 if (USE_STAR) 3249 putc ('*', file); 3250 return; 3251 3252 case '_': 3253#ifdef YES_UNDERSCORES 3254 putc ('_', file); 3255#endif 3256 return; 3257 3258 case 'L': 3259 PUT_OP_SIZE (code, 'l', file); 3260 return; 3261 3262 case 'W': 3263 PUT_OP_SIZE (code, 'w', file); 3264 return; 3265 3266 case 'B': 3267 PUT_OP_SIZE (code, 'b', file); 3268 return; 3269 3270 case 'Q': 3271 PUT_OP_SIZE (code, 'l', file); 3272 return; 3273 3274 case 'S': 3275 PUT_OP_SIZE (code, 's', file); 3276 return; 3277 3278 case 'T': 3279 PUT_OP_SIZE (code, 't', file); 3280 return; 3281 3282 case 'z': 3283 /* 387 opcodes don't get size suffixes if the operands are 3284 registers. */ 3285 3286 if (STACK_REG_P (x)) 3287 return; 3288 3289 /* this is the size of op from size of operand */ 3290 switch (GET_MODE_SIZE (GET_MODE (x))) 3291 { 3292 case 2: 3293#ifdef HAVE_GAS_FILDS_FISTS 3294 PUT_OP_SIZE ('W', 's', file); 3295#endif 3296 return; 3297 3298 case 4: 3299 if (GET_MODE (x) == SFmode) 3300 { 3301 PUT_OP_SIZE ('S', 's', file); 3302 return; 3303 } 3304 else 3305 PUT_OP_SIZE ('L', 'l', file); 3306 return; 3307 3308 case 12: 3309 PUT_OP_SIZE ('T', 't', file); 3310 return; 3311 3312 case 8: 3313 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT) 3314 { 3315#ifdef GAS_MNEMONICS 3316 PUT_OP_SIZE ('Q', 'q', file); 3317 return; 3318#else 3319 PUT_OP_SIZE ('Q', 'l', file); /* Fall through */ 3320#endif 3321 } 3322 3323 PUT_OP_SIZE ('Q', 'l', file); 3324 return; 3325 3326 default: 3327 abort (); 3328 } 3329 3330 case 'b': 3331 case 'w': 3332 case 'k': 3333 case 'h': 3334 case 'y': 3335 case 'P': 3336 case 'X': 3337 break; 3338 3339 case 'J': 3340 switch (GET_CODE (x)) 3341 { 3342 /* These conditions are appropriate for testing the result 3343 of an arithmetic operation, not for a compare operation. 3344 Cases GE, LT assume CC_NO_OVERFLOW true. All cases assume 3345 CC_Z_IN_NOT_C false and not floating point. */ 3346 case NE: fputs ("jne", file); return; 3347 case EQ: fputs ("je", file); return; 3348 case GE: fputs ("jns", file); return; 3349 case LT: fputs ("js", file); return; 3350 case GEU: fputs ("jmp", file); return; 3351 case GTU: fputs ("jne", file); return; 3352 case LEU: fputs ("je", file); return; 3353 case LTU: fputs ("#branch never", file); return; 3354 3355 /* no matching branches for GT nor LE */ 3356 3357 default: 3358 abort (); 3359 } 3360 3361 case 's': 3362 if (GET_CODE (x) == CONST_INT || ! SHIFT_DOUBLE_OMITS_COUNT) 3363 { 3364 PRINT_OPERAND (file, x, 0); 3365 fputs (AS2C (,) + 1, file); 3366 } 3367 3368 return; 3369 3370 case 'D': 3371 put_jump_code (GET_CODE (x), 0, file); 3372 return; 3373 3374 case 'd': 3375 put_jump_code (GET_CODE (x), 1, file); 3376 return; 3377 3378 /* This is used by the conditional move instructions. */ 3379 case 'C': 3380 put_condition_code (GET_CODE (x), 0, MODE_INT, file); 3381 return; 3382 3383 /* Like above, but reverse condition */ 3384 case 'c': 3385 put_condition_code (GET_CODE (x), 1, MODE_INT, file); return; 3386 3387 case 'F': 3388 put_condition_code (GET_CODE (x), 0, MODE_FLOAT, file); 3389 return; 3390 3391 /* Like above, but reverse condition */ 3392 case 'f': 3393 put_condition_code (GET_CODE (x), 1, MODE_FLOAT, file); 3394 return; 3395 3396 default: 3397 { 3398 char str[50]; 3399 3400 sprintf (str, "invalid operand code `%c'", code); 3401 output_operand_lossage (str); 3402 } 3403 } 3404 } 3405 3406 if (GET_CODE (x) == REG) 3407 { 3408 PRINT_REG (x, code, file); 3409 } 3410 3411 else if (GET_CODE (x) == MEM) 3412 { 3413 PRINT_PTR (x, file); 3414 if (CONSTANT_ADDRESS_P (XEXP (x, 0))) 3415 { 3416 if (flag_pic) 3417 output_pic_addr_const (file, XEXP (x, 0), code); 3418 else 3419 output_addr_const (file, XEXP (x, 0)); 3420 } 3421 else 3422 output_address (XEXP (x, 0)); 3423 } 3424 3425 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) 3426 { 3427 REAL_VALUE_TYPE r; 3428 long l; 3429 3430 REAL_VALUE_FROM_CONST_DOUBLE (r, x); 3431 REAL_VALUE_TO_TARGET_SINGLE (r, l); 3432 PRINT_IMMED_PREFIX (file); 3433 fprintf (file, "0x%lx", l); 3434 } 3435 3436 /* These float cases don't actually occur as immediate operands. */ 3437 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) 3438 { 3439 REAL_VALUE_TYPE r; 3440 char dstr[30]; 3441 3442 REAL_VALUE_FROM_CONST_DOUBLE (r, x); 3443 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr); 3444 fprintf (file, "%s", dstr); 3445 } 3446 3447 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode) 3448 { 3449 REAL_VALUE_TYPE r; 3450 char dstr[30]; 3451 3452 REAL_VALUE_FROM_CONST_DOUBLE (r, x); 3453 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr); 3454 fprintf (file, "%s", dstr); 3455 } 3456 else 3457 { 3458 if (code != 'P') 3459 { 3460 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) 3461 PRINT_IMMED_PREFIX (file); 3462 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF 3463 || GET_CODE (x) == LABEL_REF) 3464 PRINT_OFFSET_PREFIX (file); 3465 } 3466 if (flag_pic) 3467 output_pic_addr_const (file, x, code); 3468 else 3469 output_addr_const (file, x); 3470 } 3471} 3472 3473/* Print a memory operand whose address is ADDR. */ 3474 3475void 3476print_operand_address (file, addr) 3477 FILE *file; 3478 register rtx addr; 3479{ 3480 register rtx reg1, reg2, breg, ireg; 3481 rtx offset; 3482 3483 switch (GET_CODE (addr)) 3484 { 3485 case REG: 3486 /* ESI addressing makes instruction vector decoded on the K6. We can 3487 avoid this by ESI+0 addressing. */ 3488 if (REGNO_REG_CLASS (REGNO (addr)) == SIREG 3489 && ix86_cpu == PROCESSOR_K6 && !optimize_size) 3490 output_addr_const (file, const0_rtx); 3491 ADDR_BEG (file); 3492 fprintf (file, "%se", RP); 3493 fputs (hi_reg_name[REGNO (addr)], file); 3494 ADDR_END (file); 3495 break; 3496 3497 case PLUS: 3498 reg1 = 0; 3499 reg2 = 0; 3500 ireg = 0; 3501 breg = 0; 3502 offset = 0; 3503 if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) 3504 { 3505 offset = XEXP (addr, 0); 3506 addr = XEXP (addr, 1); 3507 } 3508 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) 3509 { 3510 offset = XEXP (addr, 1); 3511 addr = XEXP (addr, 0); 3512 } 3513 3514 if (GET_CODE (addr) != PLUS) 3515 ; 3516 else if (GET_CODE (XEXP (addr, 0)) == MULT) 3517 reg1 = XEXP (addr, 0), addr = XEXP (addr, 1); 3518 else if (GET_CODE (XEXP (addr, 1)) == MULT) 3519 reg1 = XEXP (addr, 1), addr = XEXP (addr, 0); 3520 else if (GET_CODE (XEXP (addr, 0)) == REG) 3521 reg1 = XEXP (addr, 0), addr = XEXP (addr, 1); 3522 else if (GET_CODE (XEXP (addr, 1)) == REG) 3523 reg1 = XEXP (addr, 1), addr = XEXP (addr, 0); 3524 3525 if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT) 3526 { 3527 if (reg1 == 0) 3528 reg1 = addr; 3529 else 3530 reg2 = addr; 3531 3532 addr = 0; 3533 } 3534 3535 if (offset != 0) 3536 { 3537 if (addr != 0) 3538 abort (); 3539 addr = offset; 3540 } 3541 3542 if ((reg1 && GET_CODE (reg1) == MULT) 3543 || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) 3544 { 3545 breg = reg2; 3546 ireg = reg1; 3547 } 3548 else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) 3549 { 3550 breg = reg1; 3551 ireg = reg2; 3552 } 3553 3554 if (ireg != 0 || breg != 0) 3555 { 3556 int scale = 1; 3557 3558 if (addr != 0) 3559 { 3560 if (flag_pic) 3561 output_pic_addr_const (file, addr, 0); 3562 else if (GET_CODE (addr) == LABEL_REF) 3563 output_asm_label (addr); 3564 else 3565 output_addr_const (file, addr); 3566 } 3567 3568 if (ireg != 0 && GET_CODE (ireg) == MULT) 3569 { 3570 scale = INTVAL (XEXP (ireg, 1)); 3571 ireg = XEXP (ireg, 0); 3572 } 3573 3574 /* The stack pointer can only appear as a base register, 3575 never an index register, so exchange the regs if it is wrong. */ 3576 3577 if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM) 3578 { 3579 rtx tmp; 3580 3581 tmp = breg; 3582 breg = ireg; 3583 ireg = tmp; 3584 } 3585 3586 /* output breg+ireg*scale */ 3587 PRINT_B_I_S (breg, ireg, scale, file); 3588 break; 3589 } 3590 3591 case MULT: 3592 { 3593 int scale; 3594 3595 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) 3596 { 3597 scale = INTVAL (XEXP (addr, 0)); 3598 ireg = XEXP (addr, 1); 3599 } 3600 else 3601 { 3602 scale = INTVAL (XEXP (addr, 1)); 3603 ireg = XEXP (addr, 0); 3604 } 3605 3606 /* (reg,reg,) is shorter than (,reg,2). */ 3607 if (scale == 2) 3608 { 3609 PRINT_B_I_S (ireg, ireg, 1, file); 3610 } 3611 else 3612 { 3613 output_addr_const (file, const0_rtx); 3614 PRINT_B_I_S (NULL_RTX, ireg, scale, file); 3615 } 3616 } 3617 break; 3618 3619 default: 3620 if (GET_CODE (addr) == CONST_INT 3621 && INTVAL (addr) < 0x8000 3622 && INTVAL (addr) >= -0x8000) 3623 fprintf (file, "%d", (int) INTVAL (addr)); 3624 else 3625 { 3626 if (flag_pic) 3627 output_pic_addr_const (file, addr, 0); 3628 else 3629 output_addr_const (file, addr); 3630 } 3631 } 3632} 3633 3634/* Set the cc_status for the results of an insn whose pattern is EXP. 3635 On the 80386, we assume that only test and compare insns, as well 3636 as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, BSF, ASHIFT, 3637 ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully. 3638 Also, we assume that jumps, moves and sCOND don't affect the condition 3639 codes. All else clobbers the condition codes, by assumption. 3640 3641 We assume that ALL integer add, minus, etc. instructions effect the 3642 condition codes. This MUST be consistent with i386.md. 3643 3644 We don't record any float test or compare - the redundant test & 3645 compare check in final.c does not handle stack-like regs correctly. */ 3646 3647void 3648notice_update_cc (exp) 3649 rtx exp; 3650{ 3651 if (GET_CODE (exp) == SET) 3652 { 3653 /* Jumps do not alter the cc's. */ 3654 if (SET_DEST (exp) == pc_rtx) 3655 return; 3656 3657 /* Moving register or memory into a register: 3658 it doesn't alter the cc's, but it might invalidate 3659 the RTX's which we remember the cc's came from. 3660 (Note that moving a constant 0 or 1 MAY set the cc's). */ 3661 if (REG_P (SET_DEST (exp)) 3662 && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM 3663 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<' 3664 || GET_CODE (SET_SRC (exp)) == IF_THEN_ELSE)) 3665 { 3666 if (cc_status.value1 3667 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1)) 3668 cc_status.value1 = 0; 3669 3670 if (cc_status.value2 3671 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2)) 3672 cc_status.value2 = 0; 3673 3674 return; 3675 } 3676 3677 /* Moving register into memory doesn't alter the cc's. 3678 It may invalidate the RTX's which we remember the cc's came from. */ 3679 if (GET_CODE (SET_DEST (exp)) == MEM 3680 && (REG_P (SET_SRC (exp)) 3681 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<')) 3682 { 3683 if (cc_status.value1 3684 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1)) 3685 cc_status.value1 = 0; 3686 if (cc_status.value2 3687 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2)) 3688 cc_status.value2 = 0; 3689 3690 return; 3691 } 3692 3693 /* Function calls clobber the cc's. */ 3694 else if (GET_CODE (SET_SRC (exp)) == CALL) 3695 { 3696 CC_STATUS_INIT; 3697 return; 3698 } 3699 3700 /* Tests and compares set the cc's in predictable ways. */ 3701 else if (SET_DEST (exp) == cc0_rtx) 3702 { 3703 CC_STATUS_INIT; 3704 cc_status.value1 = SET_SRC (exp); 3705 return; 3706 } 3707 3708 /* Certain instructions effect the condition codes. */ 3709 else if (GET_MODE (SET_SRC (exp)) == SImode 3710 || GET_MODE (SET_SRC (exp)) == HImode 3711 || GET_MODE (SET_SRC (exp)) == QImode) 3712 switch (GET_CODE (SET_SRC (exp))) 3713 { 3714 case ASHIFTRT: case LSHIFTRT: case ASHIFT: 3715 /* Shifts on the 386 don't set the condition codes if the 3716 shift count is zero. */ 3717 if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT) 3718 { 3719 CC_STATUS_INIT; 3720 break; 3721 } 3722 3723 /* We assume that the CONST_INT is non-zero (this rtx would 3724 have been deleted if it were zero. */ 3725 3726 case PLUS: case MINUS: case NEG: 3727 case AND: case IOR: case XOR: 3728 cc_status.flags = CC_NO_OVERFLOW; 3729 cc_status.value1 = SET_SRC (exp); 3730 cc_status.value2 = SET_DEST (exp); 3731 break; 3732 3733 /* This is the bsf pattern used by ffs. */ 3734 case UNSPEC: 3735 if (XINT (SET_SRC (exp), 1) == 5) 3736 { 3737 /* Only the Z flag is defined after bsf. */ 3738 cc_status.flags 3739 = CC_NOT_POSITIVE | CC_NOT_NEGATIVE | CC_NO_OVERFLOW; 3740 cc_status.value1 = XVECEXP (SET_SRC (exp), 0, 0); 3741 cc_status.value2 = 0; 3742 break; 3743 } 3744 /* FALLTHRU */ 3745 3746 default: 3747 CC_STATUS_INIT; 3748 } 3749 else 3750 { 3751 CC_STATUS_INIT; 3752 } 3753 } 3754 else if (GET_CODE (exp) == PARALLEL 3755 && GET_CODE (XVECEXP (exp, 0, 0)) == SET) 3756 { 3757 if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx) 3758 return; 3759 if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx) 3760 3761 { 3762 CC_STATUS_INIT; 3763 if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0)))) 3764 { 3765 cc_status.flags |= CC_IN_80387; 3766 if (TARGET_CMOVE && stack_regs_mentioned_p 3767 (XEXP (SET_SRC (XVECEXP (exp, 0, 0)), 1))) 3768 cc_status.flags |= CC_FCOMI; 3769 } 3770 else 3771 cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0)); 3772 return; 3773 } 3774 3775 CC_STATUS_INIT; 3776 } 3777 else 3778 { 3779 CC_STATUS_INIT; 3780 } 3781} 3782 3783/* Split one or more DImode RTL references into pairs of SImode 3784 references. The RTL can be REG, offsettable MEM, integer constant, or 3785 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to 3786 split and "num" is its length. lo_half and hi_half are output arrays 3787 that parallel "operands". */ 3788 3789void 3790split_di (operands, num, lo_half, hi_half) 3791 rtx operands[]; 3792 int num; 3793 rtx lo_half[], hi_half[]; 3794{ 3795 while (num--) 3796 { 3797 rtx op = operands[num]; 3798 if (! reload_completed) 3799 { 3800 lo_half[num] = gen_lowpart (SImode, op); 3801 hi_half[num] = gen_highpart (SImode, op); 3802 } 3803 else if (GET_CODE (op) == REG) 3804 { 3805 lo_half[num] = gen_rtx_REG (SImode, REGNO (op)); 3806 hi_half[num] = gen_rtx_REG (SImode, REGNO (op) + 1); 3807 } 3808 else if (CONSTANT_P (op)) 3809 split_double (op, &lo_half[num], &hi_half[num]); 3810 else if (offsettable_memref_p (op)) 3811 { 3812 rtx lo_addr = XEXP (op, 0); 3813 rtx hi_addr = XEXP (adj_offsettable_operand (op, 4), 0); 3814 lo_half[num] = change_address (op, SImode, lo_addr); 3815 hi_half[num] = change_address (op, SImode, hi_addr); 3816 } 3817 else 3818 abort(); 3819 } 3820} 3821 3822/* Return 1 if this is a valid binary operation on a 387. 3823 OP is the expression matched, and MODE is its mode. */ 3824 3825int 3826binary_387_op (op, mode) 3827 register rtx op; 3828 enum machine_mode mode; 3829{ 3830 if (mode != VOIDmode && mode != GET_MODE (op)) 3831 return 0; 3832 3833 switch (GET_CODE (op)) 3834 { 3835 case PLUS: 3836 case MINUS: 3837 case MULT: 3838 case DIV: 3839 return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT; 3840 3841 default: 3842 return 0; 3843 } 3844} 3845 3846/* Return 1 if this is a valid shift or rotate operation on a 386. 3847 OP is the expression matched, and MODE is its mode. */ 3848 3849int 3850shift_op (op, mode) 3851 register rtx op; 3852 enum machine_mode mode; 3853{ 3854 rtx operand = XEXP (op, 0); 3855 3856 if (mode != VOIDmode && mode != GET_MODE (op)) 3857 return 0; 3858 3859 if (GET_MODE (operand) != GET_MODE (op) 3860 || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT) 3861 return 0; 3862 3863 return (GET_CODE (op) == ASHIFT 3864 || GET_CODE (op) == ASHIFTRT 3865 || GET_CODE (op) == LSHIFTRT 3866 || GET_CODE (op) == ROTATE 3867 || GET_CODE (op) == ROTATERT); 3868} 3869 3870/* Return 1 if OP is COMPARE rtx with mode VOIDmode. 3871 MODE is not used. */ 3872 3873int 3874VOIDmode_compare_op (op, mode) 3875 register rtx op; 3876 enum machine_mode mode ATTRIBUTE_UNUSED; 3877{ 3878 return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode; 3879} 3880 3881/* Output code to perform a 387 binary operation in INSN, one of PLUS, 3882 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3] 3883 is the expression of the binary operation. The output may either be 3884 emitted here, or returned to the caller, like all output_* functions. 3885 3886 There is no guarantee that the operands are the same mode, as they 3887 might be within FLOAT or FLOAT_EXTEND expressions. */ 3888 3889char * 3890output_387_binary_op (insn, operands) 3891 rtx insn; 3892 rtx *operands; 3893{ 3894 rtx temp; 3895 char *base_op; 3896 static char buf[100]; 3897 3898 switch (GET_CODE (operands[3])) 3899 { 3900 case PLUS: 3901 base_op = "fadd"; 3902 break; 3903 3904 case MINUS: 3905 base_op = "fsub"; 3906 break; 3907 3908 case MULT: 3909 base_op = "fmul"; 3910 break; 3911 3912 case DIV: 3913 base_op = "fdiv"; 3914 break; 3915 3916 default: 3917 abort (); 3918 } 3919 3920 strcpy (buf, base_op); 3921 3922 switch (GET_CODE (operands[3])) 3923 { 3924 case MULT: 3925 case PLUS: 3926 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2])) 3927 { 3928 temp = operands[2]; 3929 operands[2] = operands[1]; 3930 operands[1] = temp; 3931 } 3932 3933 if (GET_CODE (operands[2]) == MEM) 3934 return strcat (buf, AS1 (%z2,%2)); 3935 3936 if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2])) 3937 abort (); 3938 3939 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2]))) 3940 { 3941 if (STACK_TOP_P (operands[0])) 3942 return strcat (buf, AS2 (p,%0,%2)); 3943 else 3944 return strcat (buf, AS2 (p,%2,%0)); 3945 } 3946 3947 if (STACK_TOP_P (operands[0])) 3948 return strcat (buf, AS2C (%y2,%0)); 3949 else 3950 return strcat (buf, AS2C (%2,%0)); 3951 3952 case MINUS: 3953 case DIV: 3954 if (GET_CODE (operands[1]) == MEM) 3955 return strcat (buf, AS1 (r%z1,%1)); 3956 3957 if (GET_CODE (operands[2]) == MEM) 3958 return strcat (buf, AS1 (%z2,%2)); 3959 3960 if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2])) 3961 abort (); 3962 3963 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2]))) 3964 { 3965 if (STACK_TOP_P (operands[0])) 3966 return strcat (buf, AS2 (p,%0,%2)); 3967 else 3968 return strcat (buf, AS2 (rp,%2,%0)); 3969 } 3970 3971 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3972 { 3973 if (STACK_TOP_P (operands[0])) 3974 return strcat (buf, AS2 (rp,%0,%1)); 3975 else 3976 return strcat (buf, AS2 (p,%1,%0)); 3977 } 3978 3979 if (STACK_TOP_P (operands[0])) 3980 { 3981 if (STACK_TOP_P (operands[1])) 3982 return strcat (buf, AS2C (%y2,%0)); 3983 else 3984 return strcat (buf, AS2 (r,%y1,%0)); 3985 } 3986 else if (STACK_TOP_P (operands[1])) 3987 return strcat (buf, AS2C (%1,%0)); 3988 else 3989 return strcat (buf, AS2 (r,%2,%0)); 3990 3991 default: 3992 abort (); 3993 } 3994} 3995 3996/* Output code for INSN to convert a float to a signed int. OPERANDS 3997 are the insn operands. The input may be SFmode, DFmode, or XFmode 3998 and the output operand may be SImode or DImode. As a special case, 3999 make sure that the 387 stack top dies if the output mode is DImode, 4000 because the hardware requires this. */ 4001 4002char * 4003output_fix_trunc (insn, operands) 4004 rtx insn; 4005 rtx *operands; 4006{ 4007 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 4008 rtx xops[2]; 4009 4010 if (! STACK_TOP_P (operands[1])) 4011 abort (); 4012 4013 if (GET_MODE (operands[0]) == DImode && ! stack_top_dies) 4014 abort (); 4015 4016 xops[0] = GEN_INT (0x0c00); 4017 xops[1] = operands[5]; 4018 4019 output_asm_insn (AS1 (fnstc%W2,%2), operands); 4020 output_asm_insn (AS2 (mov%W5,%2,%w5), operands); 4021 output_asm_insn (AS2 (or%W1,%0,%w1), xops); 4022 output_asm_insn (AS2 (mov%W3,%w5,%3), operands); 4023 output_asm_insn (AS1 (fldc%W3,%3), operands); 4024 4025 xops[0] = NON_STACK_REG_P (operands[0]) ? operands[4] : operands[0]; 4026 4027 if (stack_top_dies) 4028 output_asm_insn (AS1 (fistp%z0,%y0), xops); 4029 else 4030 output_asm_insn (AS1 (fist%z0,%y0), xops); 4031 4032 if (NON_STACK_REG_P (operands[0])) 4033 { 4034 if (GET_MODE (operands[0]) == SImode) 4035 output_asm_insn (AS2 (mov%L0,%4,%0), operands); 4036 else 4037 { 4038 xops[0] = operands[0]; 4039 xops[1] = operands[4]; 4040 output_asm_insn (output_move_double (xops), xops); 4041 } 4042 } 4043 4044 return AS1 (fldc%W2,%2); 4045} 4046 4047/* Output code for INSN to extend a float. OPERANDS are the insn 4048 operands. The output may be DFmode or XFmode and the input operand 4049 may be SFmode or DFmode. Operands 2 and 3 are scratch memory and 4050 are only necessary if operands 0 or 1 are non-stack registers. */ 4051 4052void 4053output_float_extend (insn, operands) 4054 rtx insn; 4055 rtx *operands; 4056{ 4057 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 4058 rtx xops[2]; 4059 4060 if (! STACK_TOP_P (operands[0]) && ! STACK_TOP_P (operands[1])) 4061 abort (); 4062 4063 if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1]) && stack_top_dies) 4064 return; 4065 4066 if (STACK_TOP_P (operands[0]) ) 4067 { 4068 if (NON_STACK_REG_P (operands[1])) 4069 { 4070 if (GET_MODE (operands[1]) == SFmode) 4071 output_asm_insn (AS2 (mov%L0,%1,%2), operands); 4072 else 4073 { 4074 xops[0] = operands[2]; 4075 xops[1] = operands[1]; 4076 output_asm_insn (output_move_double (xops), xops); 4077 } 4078 } 4079 4080 xops[0] = NON_STACK_REG_P (operands[1]) ? operands[2] : operands[1]; 4081 4082 output_asm_insn (AS1 (fld%z0,%y0), xops); 4083 } 4084 else 4085 { 4086 xops[0] = NON_STACK_REG_P (operands[0]) ? operands[3] : operands[0]; 4087 4088 if (stack_top_dies 4089 || (GET_CODE (xops[0]) == MEM && GET_MODE (xops[0]) == XFmode)) 4090 { 4091 output_asm_insn (AS1 (fstp%z0,%y0), xops); 4092 if (! stack_top_dies) 4093 output_asm_insn (AS1 (fld%z0,%y0), xops); 4094 } 4095 else 4096 output_asm_insn (AS1 (fst%z0,%y0), xops); 4097 4098 if (NON_STACK_REG_P (operands[0])) 4099 { 4100 xops[0] = operands[0]; 4101 xops[1] = operands[3]; 4102 output_asm_insn (output_move_double (xops), xops); 4103 } 4104 } 4105} 4106 4107/* Output code for INSN to compare OPERANDS. The two operands might 4108 not have the same mode: one might be within a FLOAT or FLOAT_EXTEND 4109 expression. If the compare is in mode CCFPEQmode, use an opcode that 4110 will not fault if a qNaN is present. */ 4111 4112char * 4113output_float_compare (insn, operands) 4114 rtx insn; 4115 rtx *operands; 4116{ 4117 int stack_top_dies; 4118 rtx body = XVECEXP (PATTERN (insn), 0, 0); 4119 int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode; 4120 rtx tmp; 4121 int cc0_set = 1; 4122 int i; 4123 4124 if (TARGET_CMOVE && STACK_REG_P (operands[1]) 4125 && STACK_REG_P (operands[0])) 4126 { 4127 cc_status.flags |= CC_FCOMI; 4128 cc_prev_status.flags &= ~CC_TEST_AX; 4129 } 4130 4131 if (! STACK_TOP_P (operands[0])) 4132 { 4133 tmp = operands[0]; 4134 operands[0] = operands[1]; 4135 operands[1] = tmp; 4136 cc_status.flags |= CC_REVERSED; 4137 } 4138 4139 if (! STACK_TOP_P (operands[0])) 4140 abort (); 4141 4142 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 4143 4144 if (STACK_REG_P (operands[1]) 4145 && stack_top_dies 4146 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])) 4147 && REGNO (operands[1]) == FIRST_STACK_REG + 1) 4148 { 4149 /* If both the top of the 387 stack dies, and the other operand 4150 is also a stack register that dies, then this must be a 4151 `fcompp' float compare */ 4152 4153 if (unordered_compare) 4154 { 4155 if (cc_status.flags & CC_FCOMI) 4156 { 4157 output_asm_insn (AS2 (fucomip,%y1,%0), operands); 4158 output_asm_insn (AS1 (fstp, %y0), operands); 4159 if (!TARGET_IEEE_FP) 4160 cc0_set = 0; 4161 } 4162 else 4163 output_asm_insn ("fucompp", operands); 4164 } 4165 else 4166 { 4167 if (cc_status.flags & CC_FCOMI) 4168 { 4169 output_asm_insn (AS2 (fcomip, %y1,%0), operands); 4170 output_asm_insn (AS1 (fstp, %y0), operands); 4171 if (!TARGET_IEEE_FP) 4172 cc0_set = 0; 4173 } 4174 else 4175 output_asm_insn ("fcompp", operands); 4176 } 4177 } 4178 else 4179 { 4180 static char buf[100]; 4181 4182 /* Decide if this is a float compare or an unordered float compare. */ 4183 4184 if (unordered_compare) 4185 strcpy (buf, (cc_status.flags & CC_FCOMI) ? "fucomi" : "fucom"); 4186 else 4187 strcpy (buf, (cc_status.flags & CC_FCOMI) ? "fcomi" : "fcom"); 4188 4189 /* Modify the opcode if the 387 stack is to be popped. */ 4190 4191 if (stack_top_dies) 4192 strcat (buf, "p"); 4193 4194 if (cc_status.flags & CC_FCOMI) 4195 { 4196 output_asm_insn (strcat (buf, AS2 (%z1,%y1,%0)), operands); 4197 if (!TARGET_IEEE_FP) 4198 cc0_set = 0; 4199 } 4200 else 4201 output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands); 4202 } 4203 4204 /* Now retrieve the condition code. */ 4205 if (cc0_set) 4206 { 4207 char *r = output_fp_cc0_set (insn); 4208 if (r[0]) output_asm_insn (r, operands); 4209 } 4210 4211 4212 /* We emit fstp instruction after integer comparsions to improve 4213 scheduling. */ 4214 for (i = 0; i < 2 ; i++) 4215 { 4216 if (STACK_REG_P (operands[i]) 4217 && find_regno_note (insn, REG_DEAD, REGNO (operands[i])) 4218 && REGNO (operands[i]) != FIRST_STACK_REG 4219 && (!stack_top_dies || REGNO (operands[i]) != FIRST_STACK_REG + 1)) 4220 { 4221 rtx xexp[2]; 4222 xexp[0] = gen_rtx_REG (DFmode, 4223 REGNO (operands[i]) - (stack_top_dies != 0)); 4224 output_asm_insn (AS1 (fstp, %y0), xexp); 4225 } 4226 } 4227 4228 return ""; 4229 4230 4231} 4232 4233/* Output opcodes to transfer the results of FP compare or test INSN 4234 from the FPU to the CPU flags. If TARGET_IEEE_FP, ensure that if the 4235 result of the compare or test is unordered, no comparison operator 4236 succeeds except NE. Return an output template, if any. */ 4237 4238char * 4239output_fp_cc0_set (insn) 4240 rtx insn; 4241{ 4242 rtx xops[3]; 4243 rtx next; 4244 enum rtx_code code; 4245 4246 if (!(cc_status.flags & CC_FCOMI)) 4247 { 4248 xops[0] = gen_rtx_REG (HImode, 0); 4249 output_asm_insn (AS1 (fnsts%W0,%0), xops); 4250 } 4251 4252 if (! TARGET_IEEE_FP) 4253 { 4254 if (!(cc_status.flags & CC_REVERSED)) 4255 { 4256 next = next_cc0_user (insn); 4257 4258 if (GET_CODE (PATTERN (next)) == SET 4259 && SET_DEST (PATTERN (next)) == pc_rtx 4260 && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE) 4261 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)); 4262 else if (GET_CODE (PATTERN (next)) == SET) 4263 code = GET_CODE (SET_SRC (PATTERN (next))); 4264 else 4265 return "sahf"; 4266 4267 if (code == GT || code == LT || code == EQ || code == NE 4268 || code == LE || code == GE) 4269 { 4270 /* We will test eax directly. */ 4271 cc_status.flags |= CC_TEST_AX; 4272 return ""; 4273 } 4274 } 4275 4276 return "sahf"; 4277 } 4278 4279 next = next_cc0_user (insn); 4280 if (next == NULL_RTX) 4281 abort (); 4282 4283 if (GET_CODE (PATTERN (next)) == SET 4284 && SET_DEST (PATTERN (next)) == pc_rtx 4285 && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE) 4286 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)); 4287 else if (GET_CODE (PATTERN (next)) == SET) 4288 { 4289 if (GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE) 4290 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)); 4291 else 4292 code = GET_CODE (SET_SRC (PATTERN (next))); 4293 } 4294 4295 else if (GET_CODE (PATTERN (next)) == PARALLEL 4296 && GET_CODE (XVECEXP (PATTERN (next), 0, 0)) == SET) 4297 { 4298 if (GET_CODE (SET_SRC (XVECEXP (PATTERN (next), 0, 0))) == IF_THEN_ELSE) 4299 code = GET_CODE (XEXP (SET_SRC (XVECEXP (PATTERN (next), 0, 0)), 0)); 4300 else 4301 code = GET_CODE (SET_SRC (XVECEXP (PATTERN (next), 0, 0))); 4302 } 4303 else 4304 abort (); 4305 4306 if (cc_status.flags & CC_FCOMI) 4307 { 4308 /* It is very tricky. We have to do it right. */ 4309 4310 xops [0] = gen_rtx_REG (QImode, 0); 4311 4312 switch (code) 4313 { 4314 case GT: 4315 case GE: 4316 break; 4317 4318 case LT: 4319 output_asm_insn (AS1 (setb,%b0), xops); 4320 output_asm_insn (AS1 (setp,%h0), xops); 4321 output_asm_insn (AS2 (cmp%B0,%b0,%h0), xops); 4322 break; 4323 4324 case LE: 4325 output_asm_insn (AS1 (setbe,%b0), xops); 4326 output_asm_insn (AS1 (setnp,%h0), xops); 4327 output_asm_insn (AS2 (xor%B0,%b0,%h0), xops); 4328 break; 4329 4330 case EQ: 4331 case NE: 4332 output_asm_insn (AS1 (setne,%b0), xops); 4333 output_asm_insn (AS1 (setp,%h0), xops); 4334 output_asm_insn (AS2 (or%B0,%b0,%h0), xops); 4335 break; 4336 4337 case GTU: 4338 case LTU: 4339 case GEU: 4340 case LEU: 4341 default: 4342 abort (); 4343 } 4344 } 4345 else 4346 { 4347 xops[0] = gen_rtx_REG (QImode, 0); 4348 4349 switch (code) 4350 { 4351 case GT: 4352 xops[1] = GEN_INT (0x45); 4353 output_asm_insn (AS2 (and%B0,%1,%h0), xops); 4354 /* je label */ 4355 break; 4356 4357 case LT: 4358 xops[1] = GEN_INT (0x45); 4359 xops[2] = GEN_INT (0x01); 4360 output_asm_insn (AS2 (and%B0,%1,%h0), xops); 4361 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); 4362 /* je label */ 4363 break; 4364 4365 case GE: 4366 xops[1] = GEN_INT (0x05); 4367 output_asm_insn (AS2 (and%B0,%1,%h0), xops); 4368 /* je label */ 4369 break; 4370 4371 case LE: 4372 xops[1] = GEN_INT (0x45); 4373 xops[2] = GEN_INT (0x40); 4374 output_asm_insn (AS2 (and%B0,%1,%h0), xops); 4375 output_asm_insn (AS1 (dec%B0,%h0), xops); 4376 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); 4377 /* jb label */ 4378 break; 4379 4380 case EQ: 4381 xops[1] = GEN_INT (0x45); 4382 xops[2] = GEN_INT (0x40); 4383 output_asm_insn (AS2 (and%B0,%1,%h0), xops); 4384 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); 4385 /* je label */ 4386 break; 4387 4388 case NE: 4389 xops[1] = GEN_INT (0x44); 4390 xops[2] = GEN_INT (0x40); 4391 output_asm_insn (AS2 (and%B0,%1,%h0), xops); 4392 output_asm_insn (AS2 (xor%B0,%2,%h0), xops); 4393 /* jne label */ 4394 break; 4395 4396 case GTU: 4397 case LTU: 4398 case GEU: 4399 case LEU: 4400 default: 4401 abort (); 4402 } 4403 } 4404 4405 return ""; 4406} 4407 4408#define MAX_386_STACK_LOCALS 2 4409 4410static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS]; 4411 4412/* Define the structure for the machine field in struct function. */ 4413struct machine_function 4414{ 4415 rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS]; 4416 rtx pic_label_rtx; 4417 char pic_label_name[256]; 4418}; 4419 4420/* Functions to save and restore i386_stack_locals. 4421 These will be called, via pointer variables, 4422 from push_function_context and pop_function_context. */ 4423 4424void 4425save_386_machine_status (p) 4426 struct function *p; 4427{ 4428 p->machine 4429 = (struct machine_function *) xmalloc (sizeof (struct machine_function)); 4430 bcopy ((char *) i386_stack_locals, (char *) p->machine->i386_stack_locals, 4431 sizeof i386_stack_locals); 4432 p->machine->pic_label_rtx = pic_label_rtx; 4433 bcopy (pic_label_name, p->machine->pic_label_name, 256); 4434} 4435 4436void 4437restore_386_machine_status (p) 4438 struct function *p; 4439{ 4440 bcopy ((char *) p->machine->i386_stack_locals, (char *) i386_stack_locals, 4441 sizeof i386_stack_locals); 4442 pic_label_rtx = p->machine->pic_label_rtx; 4443 bcopy (p->machine->pic_label_name, pic_label_name, 256); 4444 free (p->machine); 4445 p->machine = NULL; 4446} 4447 4448/* Clear stack slot assignments remembered from previous functions. 4449 This is called from INIT_EXPANDERS once before RTL is emitted for each 4450 function. */ 4451 4452void 4453clear_386_stack_locals () 4454{ 4455 enum machine_mode mode; 4456 int n; 4457 4458 for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE; 4459 mode = (enum machine_mode) ((int) mode + 1)) 4460 for (n = 0; n < MAX_386_STACK_LOCALS; n++) 4461 i386_stack_locals[(int) mode][n] = NULL_RTX; 4462 4463 pic_label_rtx = NULL_RTX; 4464 bzero (pic_label_name, 256); 4465 /* Arrange to save and restore i386_stack_locals around nested functions. */ 4466 save_machine_status = save_386_machine_status; 4467 restore_machine_status = restore_386_machine_status; 4468} 4469 4470/* Return a MEM corresponding to a stack slot with mode MODE. 4471 Allocate a new slot if necessary. 4472 4473 The RTL for a function can have several slots available: N is 4474 which slot to use. */ 4475 4476rtx 4477assign_386_stack_local (mode, n) 4478 enum machine_mode mode; 4479 int n; 4480{ 4481 if (n < 0 || n >= MAX_386_STACK_LOCALS) 4482 abort (); 4483 4484 if (i386_stack_locals[(int) mode][n] == NULL_RTX) 4485 i386_stack_locals[(int) mode][n] 4486 = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); 4487 4488 return i386_stack_locals[(int) mode][n]; 4489} 4490 4491int is_mul(op,mode) 4492 register rtx op; 4493 enum machine_mode mode ATTRIBUTE_UNUSED; 4494{ 4495 return (GET_CODE (op) == MULT); 4496} 4497 4498int is_div(op,mode) 4499 register rtx op; 4500 enum machine_mode mode ATTRIBUTE_UNUSED; 4501{ 4502 return (GET_CODE (op) == DIV); 4503} 4504 4505#ifdef NOTYET 4506/* Create a new copy of an rtx. 4507 Recursively copies the operands of the rtx, 4508 except for those few rtx codes that are sharable. 4509 Doesn't share CONST */ 4510 4511rtx 4512copy_all_rtx (orig) 4513 register rtx orig; 4514{ 4515 register rtx copy; 4516 register int i, j; 4517 register RTX_CODE code; 4518 register char *format_ptr; 4519 4520 code = GET_CODE (orig); 4521 4522 switch (code) 4523 { 4524 case REG: 4525 case QUEUED: 4526 case CONST_INT: 4527 case CONST_DOUBLE: 4528 case SYMBOL_REF: 4529 case CODE_LABEL: 4530 case PC: 4531 case CC0: 4532 case SCRATCH: 4533 /* SCRATCH must be shared because they represent distinct values. */ 4534 return orig; 4535 4536#if 0 4537 case CONST: 4538 /* CONST can be shared if it contains a SYMBOL_REF. If it contains 4539 a LABEL_REF, it isn't sharable. */ 4540 if (GET_CODE (XEXP (orig, 0)) == PLUS 4541 && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF 4542 && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT) 4543 return orig; 4544 break; 4545#endif 4546 /* A MEM with a constant address is not sharable. The problem is that 4547 the constant address may need to be reloaded. If the mem is shared, 4548 then reloading one copy of this mem will cause all copies to appear 4549 to have been reloaded. */ 4550 } 4551 4552 copy = rtx_alloc (code); 4553 PUT_MODE (copy, GET_MODE (orig)); 4554 copy->in_struct = orig->in_struct; 4555 copy->volatil = orig->volatil; 4556 copy->unchanging = orig->unchanging; 4557 copy->integrated = orig->integrated; 4558 /* intel1 */ 4559 copy->is_spill_rtx = orig->is_spill_rtx; 4560 4561 format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); 4562 4563 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) 4564 { 4565 switch (*format_ptr++) 4566 { 4567 case 'e': 4568 XEXP (copy, i) = XEXP (orig, i); 4569 if (XEXP (orig, i) != NULL) 4570 XEXP (copy, i) = copy_rtx (XEXP (orig, i)); 4571 break; 4572 4573 case '0': 4574 case 'u': 4575 XEXP (copy, i) = XEXP (orig, i); 4576 break; 4577 4578 case 'E': 4579 case 'V': 4580 XVEC (copy, i) = XVEC (orig, i); 4581 if (XVEC (orig, i) != NULL) 4582 { 4583 XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); 4584 for (j = 0; j < XVECLEN (copy, i); j++) 4585 XVECEXP (copy, i, j) = copy_rtx (XVECEXP (orig, i, j)); 4586 } 4587 break; 4588 4589 case 'w': 4590 XWINT (copy, i) = XWINT (orig, i); 4591 break; 4592 4593 case 'i': 4594 XINT (copy, i) = XINT (orig, i); 4595 break; 4596 4597 case 's': 4598 case 'S': 4599 XSTR (copy, i) = XSTR (orig, i); 4600 break; 4601 4602 default: 4603 abort (); 4604 } 4605 } 4606 return copy; 4607} 4608 4609 4610/* Try to rewrite a memory address to make it valid */ 4611 4612void 4613rewrite_address (mem_rtx) 4614 rtx mem_rtx; 4615{ 4616 rtx index_rtx, base_rtx, offset_rtx, scale_rtx, ret_rtx; 4617 int scale = 1; 4618 int offset_adjust = 0; 4619 int was_only_offset = 0; 4620 rtx mem_addr = XEXP (mem_rtx, 0); 4621 char *storage = oballoc (0); 4622 int in_struct = 0; 4623 int is_spill_rtx = 0; 4624 4625 in_struct = MEM_IN_STRUCT_P (mem_rtx); 4626 is_spill_rtx = RTX_IS_SPILL_P (mem_rtx); 4627 4628 if (GET_CODE (mem_addr) == PLUS 4629 && GET_CODE (XEXP (mem_addr, 1)) == PLUS 4630 && GET_CODE (XEXP (XEXP (mem_addr, 1), 0)) == REG) 4631 { 4632 /* This part is utilized by the combiner. */ 4633 ret_rtx 4634 = gen_rtx (PLUS, GET_MODE (mem_addr), 4635 gen_rtx (PLUS, GET_MODE (XEXP (mem_addr, 1)), 4636 XEXP (mem_addr, 0), XEXP (XEXP (mem_addr, 1), 0)), 4637 XEXP (XEXP (mem_addr, 1), 1)); 4638 4639 if (memory_address_p (GET_MODE (mem_rtx), ret_rtx)) 4640 { 4641 XEXP (mem_rtx, 0) = ret_rtx; 4642 RTX_IS_SPILL_P (ret_rtx) = is_spill_rtx; 4643 return; 4644 } 4645 4646 obfree (storage); 4647 } 4648 4649 /* This part is utilized by loop.c. 4650 If the address contains PLUS (reg,const) and this pattern is invalid 4651 in this case - try to rewrite the address to make it valid. */ 4652 storage = oballoc (0); 4653 index_rtx = base_rtx = offset_rtx = NULL; 4654 4655 /* Find the base index and offset elements of the memory address. */ 4656 if (GET_CODE (mem_addr) == PLUS) 4657 { 4658 if (GET_CODE (XEXP (mem_addr, 0)) == REG) 4659 { 4660 if (GET_CODE (XEXP (mem_addr, 1)) == REG) 4661 base_rtx = XEXP (mem_addr, 1), index_rtx = XEXP (mem_addr, 0); 4662 else 4663 base_rtx = XEXP (mem_addr, 0), offset_rtx = XEXP (mem_addr, 1); 4664 } 4665 4666 else if (GET_CODE (XEXP (mem_addr, 0)) == MULT) 4667 { 4668 index_rtx = XEXP (mem_addr, 0); 4669 if (GET_CODE (XEXP (mem_addr, 1)) == REG) 4670 base_rtx = XEXP (mem_addr, 1); 4671 else 4672 offset_rtx = XEXP (mem_addr, 1); 4673 } 4674 4675 else if (GET_CODE (XEXP (mem_addr, 0)) == PLUS) 4676 { 4677 if (GET_CODE (XEXP (XEXP (mem_addr, 0), 0)) == PLUS 4678 && GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0)) == MULT 4679 && (GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 0)) 4680 == REG) 4681 && (GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 1)) 4682 == CONST_INT) 4683 && (GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1)) 4684 == CONST_INT) 4685 && GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) == REG 4686 && GET_CODE (XEXP (mem_addr, 1)) == SYMBOL_REF) 4687 { 4688 index_rtx = XEXP (XEXP (XEXP (mem_addr, 0), 0), 0); 4689 offset_rtx = XEXP (mem_addr, 1); 4690 base_rtx = XEXP (XEXP (mem_addr, 0), 1); 4691 offset_adjust = INTVAL (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1)); 4692 } 4693 else 4694 { 4695 offset_rtx = XEXP (mem_addr, 1); 4696 index_rtx = XEXP (XEXP (mem_addr, 0), 0); 4697 base_rtx = XEXP (XEXP (mem_addr, 0), 1); 4698 } 4699 } 4700 4701 else if (GET_CODE (XEXP (mem_addr, 0)) == CONST_INT) 4702 { 4703 was_only_offset = 1; 4704 index_rtx = NULL; 4705 base_rtx = NULL; 4706 offset_rtx = XEXP (mem_addr, 1); 4707 offset_adjust = INTVAL (XEXP (mem_addr, 0)); 4708 if (offset_adjust == 0) 4709 { 4710 XEXP (mem_rtx, 0) = offset_rtx; 4711 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx; 4712 return; 4713 } 4714 } 4715 else 4716 { 4717 obfree (storage); 4718 return; 4719 } 4720 } 4721 else if (GET_CODE (mem_addr) == MULT) 4722 index_rtx = mem_addr; 4723 else 4724 { 4725 obfree (storage); 4726 return; 4727 } 4728 4729 if (index_rtx != 0 && GET_CODE (index_rtx) == MULT) 4730 { 4731 if (GET_CODE (XEXP (index_rtx, 1)) != CONST_INT) 4732 { 4733 obfree (storage); 4734 return; 4735 } 4736 4737 scale_rtx = XEXP (index_rtx, 1); 4738 scale = INTVAL (scale_rtx); 4739 index_rtx = copy_all_rtx (XEXP (index_rtx, 0)); 4740 } 4741 4742 /* Now find which of the elements are invalid and try to fix them. */ 4743 if (index_rtx && GET_CODE (index_rtx) == CONST_INT && base_rtx == NULL) 4744 { 4745 offset_adjust = INTVAL (index_rtx) * scale; 4746 4747 if (offset_rtx != 0 && CONSTANT_P (offset_rtx)) 4748 offset_rtx = plus_constant (offset_rtx, offset_adjust); 4749 else if (offset_rtx == 0) 4750 offset_rtx = const0_rtx; 4751 4752 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx; 4753 XEXP (mem_rtx, 0) = offset_rtx; 4754 return; 4755 } 4756 4757 if (base_rtx && GET_CODE (base_rtx) == PLUS 4758 && GET_CODE (XEXP (base_rtx, 0)) == REG 4759 && GET_CODE (XEXP (base_rtx, 1)) == CONST_INT) 4760 { 4761 offset_adjust += INTVAL (XEXP (base_rtx, 1)); 4762 base_rtx = copy_all_rtx (XEXP (base_rtx, 0)); 4763 } 4764 4765 else if (base_rtx && GET_CODE (base_rtx) == CONST_INT) 4766 { 4767 offset_adjust += INTVAL (base_rtx); 4768 base_rtx = NULL; 4769 } 4770 4771 if (index_rtx && GET_CODE (index_rtx) == PLUS 4772 && GET_CODE (XEXP (index_rtx, 0)) == REG 4773 && GET_CODE (XEXP (index_rtx, 1)) == CONST_INT) 4774 { 4775 offset_adjust += INTVAL (XEXP (index_rtx, 1)) * scale; 4776 index_rtx = copy_all_rtx (XEXP (index_rtx, 0)); 4777 } 4778 4779 if (index_rtx) 4780 { 4781 if (! LEGITIMATE_INDEX_P (index_rtx) 4782 && ! (index_rtx == stack_pointer_rtx && scale == 1 4783 && base_rtx == NULL)) 4784 { 4785 obfree (storage); 4786 return; 4787 } 4788 } 4789 4790 if (base_rtx) 4791 { 4792 if (! LEGITIMATE_INDEX_P (base_rtx) && GET_CODE (base_rtx) != REG) 4793 { 4794 obfree (storage); 4795 return; 4796 } 4797 } 4798 4799 if (offset_adjust != 0) 4800 { 4801 if (offset_rtx != 0 && CONSTANT_P (offset_rtx)) 4802 offset_rtx = plus_constant (offset_rtx, offset_adjust); 4803 else 4804 offset_rtx = const0_rtx; 4805 4806 if (index_rtx) 4807 { 4808 if (base_rtx) 4809 { 4810 if (scale != 1) 4811 { 4812 ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx), 4813 gen_rtx (MULT, GET_MODE (index_rtx), 4814 index_rtx, scale_rtx), 4815 base_rtx); 4816 4817 if (GET_CODE (offset_rtx) != CONST_INT 4818 || INTVAL (offset_rtx) != 0) 4819 ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx), 4820 ret_rtx, offset_rtx); 4821 } 4822 else 4823 { 4824 ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx), 4825 index_rtx, base_rtx); 4826 4827 if (GET_CODE (offset_rtx) != CONST_INT 4828 || INTVAL (offset_rtx) != 0) 4829 ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx), 4830 ret_rtx, offset_rtx); 4831 } 4832 } 4833 else 4834 { 4835 if (scale != 1) 4836 { 4837 ret_rtx = gen_rtx (MULT, GET_MODE (index_rtx), 4838 index_rtx, scale_rtx); 4839 4840 if (GET_CODE (offset_rtx) != CONST_INT 4841 || INTVAL (offset_rtx) != 0) 4842 ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx), 4843 ret_rtx, offset_rtx); 4844 } 4845 else 4846 { 4847 if (GET_CODE (offset_rtx) == CONST_INT 4848 && INTVAL (offset_rtx) == 0) 4849 ret_rtx = index_rtx; 4850 else 4851 ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx), 4852 index_rtx, offset_rtx); 4853 } 4854 } 4855 } 4856 else 4857 { 4858 if (base_rtx) 4859 { 4860 if (GET_CODE (offset_rtx) == CONST_INT 4861 && INTVAL (offset_rtx) == 0) 4862 ret_rtx = base_rtx; 4863 else 4864 ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx), base_rtx, 4865 offset_rtx); 4866 } 4867 else if (was_only_offset) 4868 ret_rtx = offset_rtx; 4869 else 4870 { 4871 obfree (storage); 4872 return; 4873 } 4874 } 4875 4876 XEXP (mem_rtx, 0) = ret_rtx; 4877 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx; 4878 return; 4879 } 4880 else 4881 { 4882 obfree (storage); 4883 return; 4884 } 4885} 4886#endif /* NOTYET */ 4887 4888/* Return 1 if the first insn to set cc before INSN also sets the register 4889 REG_RTX; otherwise return 0. */ 4890int 4891last_to_set_cc (reg_rtx, insn) 4892 rtx reg_rtx, insn; 4893{ 4894 rtx prev_insn = PREV_INSN (insn); 4895 4896 while (prev_insn) 4897 { 4898 if (GET_CODE (prev_insn) == NOTE) 4899 ; 4900 4901 else if (GET_CODE (prev_insn) == INSN) 4902 { 4903 if (GET_CODE (PATTERN (prev_insn)) != SET) 4904 return (0); 4905 4906 if (rtx_equal_p (SET_DEST (PATTERN (prev_insn)), reg_rtx)) 4907 { 4908 if (sets_condition_code (SET_SRC (PATTERN (prev_insn)))) 4909 return (1); 4910 4911 return (0); 4912 } 4913 4914 else if (! doesnt_set_condition_code (SET_SRC (PATTERN (prev_insn)))) 4915 return (0); 4916 } 4917 4918 else 4919 return (0); 4920 4921 prev_insn = PREV_INSN (prev_insn); 4922 } 4923 4924 return (0); 4925} 4926 4927int 4928doesnt_set_condition_code (pat) 4929 rtx pat; 4930{ 4931 switch (GET_CODE (pat)) 4932 { 4933 case MEM: 4934 case REG: 4935 return 1; 4936 4937 default: 4938 return 0; 4939 4940 } 4941} 4942 4943int 4944sets_condition_code (pat) 4945 rtx pat; 4946{ 4947 switch (GET_CODE (pat)) 4948 { 4949 case PLUS: 4950 case MINUS: 4951 case AND: 4952 case IOR: 4953 case XOR: 4954 case NOT: 4955 case NEG: 4956 case MULT: 4957 case DIV: 4958 case MOD: 4959 case UDIV: 4960 case UMOD: 4961 return 1; 4962 4963 default: 4964 return (0); 4965 } 4966} 4967 4968int 4969str_immediate_operand (op, mode) 4970 register rtx op; 4971 enum machine_mode mode ATTRIBUTE_UNUSED; 4972{ 4973 if (GET_CODE (op) == CONST_INT && INTVAL (op) <= 32 && INTVAL (op) >= 0) 4974 return 1; 4975 4976 return 0; 4977} 4978 4979int 4980is_fp_insn (insn) 4981 rtx insn; 4982{ 4983 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET 4984 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode 4985 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode 4986 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode)) 4987 return 1; 4988 4989 return 0; 4990} 4991 4992/* Return 1 if the mode of the SET_DEST of insn is floating point 4993 and it is not an fld or a move from memory to memory. 4994 Otherwise return 0 */ 4995 4996int 4997is_fp_dest (insn) 4998 rtx insn; 4999{ 5000 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET 5001 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode 5002 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode 5003 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode) 5004 && GET_CODE (SET_DEST (PATTERN (insn))) == REG 5005 && REGNO (SET_DEST (PATTERN (insn))) >= FIRST_FLOAT_REG 5006 && GET_CODE (SET_SRC (PATTERN (insn))) != MEM) 5007 return 1; 5008 5009 return 0; 5010} 5011 5012/* Return 1 if the mode of the SET_DEST of INSN is floating point and is 5013 memory and the source is a register. */ 5014 5015int 5016is_fp_store (insn) 5017 rtx insn; 5018{ 5019 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET 5020 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode 5021 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode 5022 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode) 5023 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM 5024 && GET_CODE (SET_SRC (PATTERN (insn))) == REG) 5025 return 1; 5026 5027 return 0; 5028} 5029 5030/* Return 1 if DEP_INSN sets a register which INSN uses as a base 5031 or index to reference memory. 5032 otherwise return 0 */ 5033 5034int 5035agi_dependent (insn, dep_insn) 5036 rtx insn, dep_insn; 5037{ 5038 int push = 0, push_dep = 0; 5039 if (GET_CODE (dep_insn) == INSN 5040 && GET_CODE (PATTERN (dep_insn)) == SET 5041 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG 5042 && reg_mentioned_in_mem (SET_DEST (PATTERN (dep_insn)), insn)) 5043 return 1; 5044 5045 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET 5046 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM 5047 && push_operand (SET_DEST (PATTERN (insn)), 5048 GET_MODE (SET_DEST (PATTERN (insn))))) 5049 push = 1; 5050 5051 if (GET_CODE (dep_insn) == INSN && GET_CODE (PATTERN (dep_insn)) == SET 5052 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == MEM 5053 && push_operand (SET_DEST (PATTERN (dep_insn)), 5054 GET_MODE (SET_DEST (PATTERN (dep_insn))))) 5055 push_dep = 1; 5056 5057 /* CPUs contain special hardware to allow two pushes. */ 5058 if (push && push_dep) 5059 return 0; 5060 5061 /* Push operation implicitly change stack pointer causing AGI stalls. */ 5062 if (push_dep && reg_mentioned_in_mem (stack_pointer_rtx, insn)) 5063 return 1; 5064 5065 /* Push also implicitly read stack pointer. */ 5066 if (push && modified_in_p (stack_pointer_rtx, dep_insn)) 5067 return 1; 5068 5069 return 0; 5070} 5071 5072/* Return 1 if reg is used in rtl as a base or index for a memory ref 5073 otherwise return 0. */ 5074 5075int 5076reg_mentioned_in_mem (reg, rtl) 5077 rtx reg, rtl; 5078{ 5079 register char *fmt; 5080 register int i, j; 5081 register enum rtx_code code; 5082 5083 if (rtl == NULL) 5084 return 0; 5085 5086 code = GET_CODE (rtl); 5087 5088 switch (code) 5089 { 5090 case HIGH: 5091 case CONST_INT: 5092 case CONST: 5093 case CONST_DOUBLE: 5094 case SYMBOL_REF: 5095 case LABEL_REF: 5096 case PC: 5097 case CC0: 5098 case SUBREG: 5099 return 0; 5100 default: 5101 break; 5102 } 5103 5104 if (code == MEM && reg_mentioned_p (reg, rtl)) 5105 return 1; 5106 5107 fmt = GET_RTX_FORMAT (code); 5108 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 5109 { 5110 if (fmt[i] == 'E') 5111 { 5112 for (j = XVECLEN (rtl, i) - 1; j >= 0; j--) 5113 if (reg_mentioned_in_mem (reg, XVECEXP (rtl, i, j))) 5114 return 1; 5115 } 5116 5117 else if (fmt[i] == 'e' && reg_mentioned_in_mem (reg, XEXP (rtl, i))) 5118 return 1; 5119 } 5120 5121 return 0; 5122} 5123 5124/* Output the appropriate insns for doing strlen if not just doing repnz; scasb 5125 5126 operands[0] = result, initialized with the startaddress 5127 operands[1] = alignment of the address. 5128 operands[2] = scratch register, initialized with the startaddress when 5129 not aligned, otherwise undefined 5130 5131 This is just the body. It needs the initialisations mentioned above and 5132 some address computing at the end. These things are done in i386.md. */ 5133 5134char * 5135output_strlen_unroll (operands) 5136 rtx operands[]; 5137{ 5138 rtx xops[18]; 5139 5140 xops[0] = operands[0]; /* Result */ 5141 /* operands[1]; * Alignment */ 5142 xops[1] = operands[2]; /* Scratch */ 5143 xops[2] = GEN_INT (0); 5144 xops[3] = GEN_INT (2); 5145 xops[4] = GEN_INT (3); 5146 xops[5] = GEN_INT (4); 5147 /* xops[6] = gen_label_rtx (); * label when aligned to 3-byte */ 5148 /* xops[7] = gen_label_rtx (); * label when aligned to 2-byte */ 5149 xops[8] = gen_label_rtx (); /* label of main loop */ 5150 5151 if (TARGET_USE_Q_REG && QI_REG_P (xops[1])) 5152 xops[9] = gen_label_rtx (); /* pentium optimisation */ 5153 5154 xops[10] = gen_label_rtx (); /* end label 2 */ 5155 xops[11] = gen_label_rtx (); /* end label 1 */ 5156 xops[12] = gen_label_rtx (); /* end label */ 5157 /* xops[13] * Temporary used */ 5158 xops[14] = GEN_INT (0xff); 5159 xops[15] = GEN_INT (0xff00); 5160 xops[16] = GEN_INT (0xff0000); 5161 xops[17] = GEN_INT (0xff000000); 5162 5163 /* Loop to check 1..3 bytes for null to get an aligned pointer. */ 5164 5165 /* Is there a known alignment and is it less than 4? */ 5166 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) < 4) 5167 { 5168 /* Is there a known alignment and is it not 2? */ 5169 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2) 5170 { 5171 xops[6] = gen_label_rtx (); /* Label when aligned to 3-byte */ 5172 xops[7] = gen_label_rtx (); /* Label when aligned to 2-byte */ 5173 5174 /* Leave just the 3 lower bits. 5175 If this is a q-register, then the high part is used later 5176 therefore use andl rather than andb. */ 5177 output_asm_insn (AS2 (and%L1,%4,%1), xops); 5178 5179 /* Is aligned to 4-byte address when zero */ 5180 output_asm_insn (AS1 (je,%l8), xops); 5181 5182 /* Side-effect even Parity when %eax == 3 */ 5183 output_asm_insn (AS1 (jp,%6), xops); 5184 5185 /* Is it aligned to 2 bytes ? */ 5186 if (QI_REG_P (xops[1])) 5187 output_asm_insn (AS2 (cmp%L1,%3,%1), xops); 5188 else 5189 output_asm_insn (AS2 (cmp%L1,%3,%1), xops); 5190 5191 output_asm_insn (AS1 (je,%7), xops); 5192 } 5193 else 5194 { 5195 /* Since the alignment is 2, we have to check 2 or 0 bytes; 5196 check if is aligned to 4 - byte. */ 5197 output_asm_insn (AS2 (and%L1,%3,%1), xops); 5198 5199 /* Is aligned to 4-byte address when zero */ 5200 output_asm_insn (AS1 (je,%l8), xops); 5201 } 5202 5203 xops[13] = gen_rtx_MEM (QImode, xops[0]); 5204 5205 /* Now compare the bytes; compare with the high part of a q-reg 5206 gives shorter code. */ 5207 if (QI_REG_P (xops[1])) 5208 { 5209 /* Compare the first n unaligned byte on a byte per byte basis. */ 5210 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops); 5211 5212 /* When zero we reached the end. */ 5213 output_asm_insn (AS1 (je,%l12), xops); 5214 5215 /* Increment the address. */ 5216 output_asm_insn (AS1 (inc%L0,%0), xops); 5217 5218 /* Not needed with an alignment of 2 */ 5219 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2) 5220 { 5221 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", 5222 CODE_LABEL_NUMBER (xops[7])); 5223 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops); 5224 output_asm_insn (AS1 (je,%l12), xops); 5225 output_asm_insn (AS1 (inc%L0,%0), xops); 5226 5227 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", 5228 CODE_LABEL_NUMBER (xops[6])); 5229 } 5230 5231 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops); 5232 } 5233 else 5234 { 5235 output_asm_insn (AS2 (cmp%B13,%2,%13), xops); 5236 output_asm_insn (AS1 (je,%l12), xops); 5237 output_asm_insn (AS1 (inc%L0,%0), xops); 5238 5239 /* Not needed with an alignment of 2 */ 5240 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2) 5241 { 5242 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", 5243 CODE_LABEL_NUMBER (xops[7])); 5244 output_asm_insn (AS2 (cmp%B13,%2,%13), xops); 5245 output_asm_insn (AS1 (je,%l12), xops); 5246 output_asm_insn (AS1 (inc%L0,%0), xops); 5247 5248 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", 5249 CODE_LABEL_NUMBER (xops[6])); 5250 } 5251 5252 output_asm_insn (AS2 (cmp%B13,%2,%13), xops); 5253 } 5254 5255 output_asm_insn (AS1 (je,%l12), xops); 5256 output_asm_insn (AS1 (inc%L0,%0), xops); 5257 } 5258 5259 /* Generate loop to check 4 bytes at a time. It is not a good idea to 5260 align this loop. It gives only huge programs, but does not help to 5261 speed up. */ 5262 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[8])); 5263 5264 xops[13] = gen_rtx_MEM (SImode, xops[0]); 5265 output_asm_insn (AS2 (mov%L1,%13,%1), xops); 5266 5267 if (QI_REG_P (xops[1])) 5268 { 5269 /* On i586 it is faster to combine the hi- and lo- part as 5270 a kind of lookahead. If anding both yields zero, then one 5271 of both *could* be zero, otherwise none of both is zero; 5272 this saves one instruction, on i486 this is slower 5273 tested with P-90, i486DX2-66, AMD486DX2-66 */ 5274 if (TARGET_PENTIUM) 5275 { 5276 output_asm_insn (AS2 (test%B1,%h1,%b1), xops); 5277 output_asm_insn (AS1 (jne,%l9), xops); 5278 } 5279 5280 /* Check first byte. */ 5281 output_asm_insn (AS2 (test%B1,%b1,%b1), xops); 5282 output_asm_insn (AS1 (je,%l12), xops); 5283 5284 /* Check second byte. */ 5285 output_asm_insn (AS2 (test%B1,%h1,%h1), xops); 5286 output_asm_insn (AS1 (je,%l11), xops); 5287 5288 if (TARGET_PENTIUM) 5289 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", 5290 CODE_LABEL_NUMBER (xops[9])); 5291 } 5292 5293 else 5294 { 5295 /* Check first byte. */ 5296 output_asm_insn (AS2 (test%L1,%14,%1), xops); 5297 output_asm_insn (AS1 (je,%l12), xops); 5298 5299 /* Check second byte. */ 5300 output_asm_insn (AS2 (test%L1,%15,%1), xops); 5301 output_asm_insn (AS1 (je,%l11), xops); 5302 } 5303 5304 /* Check third byte. */ 5305 output_asm_insn (AS2 (test%L1,%16,%1), xops); 5306 output_asm_insn (AS1 (je,%l10), xops); 5307 5308 /* Check fourth byte and increment address. */ 5309 output_asm_insn (AS2 (add%L0,%5,%0), xops); 5310 output_asm_insn (AS2 (test%L1,%17,%1), xops); 5311 output_asm_insn (AS1 (jne,%l8), xops); 5312 5313 /* Now generate fixups when the compare stops within a 4-byte word. */ 5314 output_asm_insn (AS2 (sub%L0,%4,%0), xops); 5315 5316 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[10])); 5317 output_asm_insn (AS1 (inc%L0,%0), xops); 5318 5319 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[11])); 5320 output_asm_insn (AS1 (inc%L0,%0), xops); 5321 5322 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[12])); 5323 5324 return ""; 5325} 5326 5327char * 5328output_fp_conditional_move (which_alternative, operands) 5329 int which_alternative; 5330 rtx operands[]; 5331{ 5332 enum rtx_code code = GET_CODE (operands[1]); 5333 5334 /* This should never happen. */ 5335 if (!(cc_prev_status.flags & CC_IN_80387) 5336 && (code == GT || code == LE || code == GE || code == LT)) 5337 abort (); 5338 5339 switch (which_alternative) 5340 { 5341 case 0: 5342 /* r <- cond ? arg : r */ 5343 output_asm_insn (AS2 (fcmov%F1,%2,%0), operands); 5344 break; 5345 5346 case 1: 5347 /* r <- cond ? r : arg */ 5348 output_asm_insn (AS2 (fcmov%f1,%3,%0), operands); 5349 break; 5350 5351 default: 5352 abort (); 5353 } 5354 5355 return ""; 5356} 5357 5358char * 5359output_int_conditional_move (which_alternative, operands) 5360 int which_alternative; 5361 rtx operands[]; 5362{ 5363 enum rtx_code code = GET_CODE (operands[1]); 5364 5365 /* This is very tricky. We have to do it right. For a code segement 5366 like: 5367 5368 int foo, bar; 5369 .... 5370 foo = foo - x; 5371 if (foo >= 0) 5372 bar = y; 5373 5374 final_scan_insn () may delete the insn which sets CC. We have to 5375 tell final_scan_insn () if it should be reinserted. When CODE is 5376 GT or LE, we have to check the CC_NO_OVERFLOW bit and return 5377 NULL_PTR to tell final to reinsert the test insn because the 5378 conditional move cannot be handled properly without it. */ 5379 if ((code == GT || code == LE) 5380 && (cc_prev_status.flags & CC_NO_OVERFLOW)) 5381 return NULL_PTR; 5382 5383 switch (which_alternative) 5384 { 5385 case 0: 5386 /* r <- cond ? arg : r */ 5387 output_asm_insn (AS2 (cmov%C1,%2,%0), operands); 5388 break; 5389 5390 case 1: 5391 /* r <- cond ? r : arg */ 5392 output_asm_insn (AS2 (cmov%c1,%3,%0), operands); 5393 break; 5394 5395 default: 5396 abort (); 5397 } 5398 5399 return ""; 5400} 5401 5402int 5403x86_adjust_cost (insn, link, dep_insn, cost) 5404 rtx insn, link, dep_insn; 5405 int cost; 5406{ 5407 rtx next_inst; 5408 5409 if (GET_CODE (dep_insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN) 5410 return 0; 5411 5412 if (GET_CODE (dep_insn) == INSN 5413 && GET_CODE (PATTERN (dep_insn)) == SET 5414 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG 5415 && GET_CODE (insn) == INSN 5416 && GET_CODE (PATTERN (insn)) == SET 5417 && !reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn)), 5418 SET_SRC (PATTERN (insn)))) 5419 return 0; /* ??? */ 5420 5421 5422 switch (ix86_cpu) 5423 { 5424 case PROCESSOR_PENTIUM: 5425 if (cost != 0 && is_fp_insn (insn) && is_fp_insn (dep_insn) 5426 && !is_fp_dest (dep_insn)) 5427 return 0; 5428 5429 if (agi_dependent (insn, dep_insn)) 5430 return cost ? cost + 1 : 2; 5431 5432 if (GET_CODE (insn) == INSN 5433 && GET_CODE (PATTERN (insn)) == SET 5434 && SET_DEST (PATTERN (insn)) == cc0_rtx 5435 && (next_inst = next_nonnote_insn (insn)) 5436 && GET_CODE (next_inst) == JUMP_INSN) 5437 /* compare probably paired with jump */ 5438 return 0; 5439 5440 /* Stores stalls one cycle longer than other insns. */ 5441 if (is_fp_insn (insn) && cost && is_fp_store (dep_insn)) 5442 cost++; 5443 break; 5444 case PROCESSOR_K6: 5445 default: 5446 if (!is_fp_dest (dep_insn)) 5447 { 5448 if(!agi_dependent (insn, dep_insn)) 5449 return 0; 5450 if (TARGET_486) 5451 return 2; 5452 } 5453 else 5454 if (is_fp_store (insn) && is_fp_insn (dep_insn) 5455 && NEXT_INSN (insn) && NEXT_INSN (NEXT_INSN (insn)) 5456 && NEXT_INSN (NEXT_INSN (NEXT_INSN (insn))) 5457 && (GET_CODE (NEXT_INSN (insn)) == INSN) 5458 && (GET_CODE (NEXT_INSN (NEXT_INSN (insn))) == JUMP_INSN) 5459 && (GET_CODE (NEXT_INSN (NEXT_INSN (NEXT_INSN (insn)))) == NOTE) 5460 && (NOTE_LINE_NUMBER (NEXT_INSN (NEXT_INSN (NEXT_INSN (insn)))) 5461 == NOTE_INSN_LOOP_END)) 5462 return 3; 5463 break; 5464 } 5465 5466 return cost; 5467} 5468 5469/* Output assembly code for a left shift. 5470 5471 Always use "sal" when shifting a memory operand or for a non constant 5472 shift count. 5473 5474 When optimizing for size, we know that src == dest, and we should always 5475 use "sal". If src != dest, then copy src to dest and use "sal". 5476 5477 Pentium and PPro (speed): 5478 5479 When src == dest, use "add" for a shift counts of one, else use 5480 "sal". If we modeled Pentium AGI stalls and U/V pipelining better we 5481 would want to generate lea for some shifts on the Pentium. 5482 5483 When src != dest, use "lea" for small shift counts. Otherwise, 5484 copy src to dest and use the normal shifting code. Exception for 5485 TARGET_DOUBLE_WITH_ADD. */ 5486 5487char * 5488output_ashl (insn, operands) 5489 rtx insn, *operands; 5490{ 5491 /* Handle case where srcreg != dstreg. */ 5492 if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1])) 5493 { 5494 if (TARGET_DOUBLE_WITH_ADD && INTVAL (operands[2]) == 1) 5495 switch (GET_MODE (operands[0])) 5496 { 5497 case SImode: 5498 output_asm_insn (AS2 (mov%L0,%1,%0), operands); 5499 return AS2 (add%L0,%1,%0); 5500 case HImode: 5501 output_asm_insn (AS2 (mov%L0,%k1,%k0), operands); 5502 if (i386_cc_probably_useless_p (insn)) 5503 { 5504 CC_STATUS_INIT; 5505 return AS2 (add%L0,%k1,%k0); 5506 } 5507 return AS2 (add%W0,%k1,%k0); 5508 case QImode: 5509 output_asm_insn (AS2 (mov%B0,%1,%0), operands); 5510 return AS2 (add%B0,%1,%0); 5511 default: 5512 abort (); 5513 } 5514 else 5515 { 5516 CC_STATUS_INIT; 5517 5518 /* This should be extremely rare (impossible?). We can not encode a 5519 shift of the stack pointer using an lea instruction. So copy the 5520 stack pointer into the destination register and use an lea. */ 5521 if (operands[1] == stack_pointer_rtx) 5522 { 5523 output_asm_insn (AS2 (mov%L0,%k1,%k0), operands); 5524 operands[1] = operands[0]; 5525 } 5526 5527 /* For shifts up to and including 3 bits, use lea. */ 5528 operands[1] = gen_rtx_MULT (SImode, 5529 gen_rtx_REG (SImode, REGNO (operands[1])), 5530 GEN_INT (1 << INTVAL (operands[2]))); 5531 return AS2 (lea%L0,%a1,%k0); 5532 } 5533 } 5534 5535 /* Source and destination match. */ 5536 5537 /* Handle variable shift. */ 5538 if (REG_P (operands[2])) 5539 switch (GET_MODE (operands[0])) 5540 { 5541 case SImode: 5542 return AS2 (sal%L0,%b2,%0); 5543 case HImode: 5544 if (REG_P (operands[0]) && i386_cc_probably_useless_p (insn)) 5545 { 5546 CC_STATUS_INIT; 5547 return AS2 (sal%L0,%b2,%k0); 5548 } 5549 else 5550 return AS2 (sal%W0,%b2,%0); 5551 case QImode: 5552 return AS2 (sal%B0,%b2,%0); 5553 default: 5554 abort (); 5555 } 5556 5557 /* Always perform shift by 1 using an add instruction. */ 5558 if (REG_P (operands[0]) && operands[2] == const1_rtx) 5559 switch (GET_MODE (operands[0])) 5560 { 5561 case SImode: 5562 return AS2 (add%L0,%0,%0); 5563 case HImode: 5564 if (REG_P (operands[0]) && i386_cc_probably_useless_p (insn)) 5565 { 5566 CC_STATUS_INIT; 5567 return AS2 (add%L0,%k0,%k0); 5568 } 5569 else 5570 return AS2 (add%W0,%0,%0); 5571 case QImode: 5572 return AS2 (add%B0,%0,%0); 5573 default: 5574 abort (); 5575 } 5576 5577#if 0 5578 /* ??? Currently disabled. Because our model of Pentium is far from being 5579 exact, this change will need some benchmarking. */ 5580 /* Shift reg by 2 or 3 use an lea instruction for Pentium if this is 5581 insn is expected to issue into the V pipe (the insn's mode will be 5582 TImode for a U pipe, and !TImode for a V pipe instruction). */ 5583 if (! optimize_size 5584 && REG_P (operands[0]) 5585 && GET_CODE (operands[2]) == CONST_INT 5586 && INTVAL (operands[2]) <= 3 5587 && (int)ix86_cpu == (int)PROCESSOR_PENTIUM 5588 && GET_MODE (insn) != TImode) 5589 { 5590 CC_STATUS_INIT; 5591 operands[1] = gen_rtx_MULT (SImode, gen_rtx_REG (SImode, REGNO (operands[1])), 5592 GEN_INT (1 << INTVAL (operands[2]))); 5593 return AS2 (lea%L0,%a1,%0); 5594 } 5595#endif 5596 5597 /* Otherwise use a shift instruction. */ 5598 switch (GET_MODE (operands[0])) 5599 { 5600 case SImode: 5601 return AS2 (sal%L0,%2,%0); 5602 case HImode: 5603 if (REG_P (operands[0]) && i386_cc_probably_useless_p (insn)) 5604 { 5605 CC_STATUS_INIT; 5606 return AS2 (sal%L0,%2,%k0); 5607 } 5608 else 5609 return AS2 (sal%W0,%2,%0); 5610 case QImode: 5611 return AS2 (sal%B0,%2,%0); 5612 default: 5613 abort (); 5614 } 5615} 5616 5617/* Given the memory address ADDR, calculate the length of the address or 5618 the length of just the displacement (controlled by DISP_LENGTH). 5619 5620 The length returned does not include the one-byte modrm, opcode, 5621 or prefix. */ 5622 5623int 5624memory_address_info (addr, disp_length) 5625 rtx addr; 5626 int disp_length; 5627{ 5628 rtx base, index, disp, scale; 5629 rtx op0, op1; 5630 int len; 5631 5632 if (GET_CODE (addr) == PRE_DEC 5633 || GET_CODE (addr) == POST_INC) 5634 return 0; 5635 5636 /* Register Indirect. */ 5637 if (register_operand (addr, Pmode)) 5638 { 5639 /* Special cases: ebp and esp need the two-byte modrm form. 5640 5641 We change [ESI] to [ESI+0] on the K6 when not optimizing 5642 for size. */ 5643 if (addr == stack_pointer_rtx 5644 || addr == arg_pointer_rtx 5645 || addr == frame_pointer_rtx 5646 || (REGNO_REG_CLASS (REGNO (addr)) == SIREG 5647 && ix86_cpu == PROCESSOR_K6 && !optimize_size)) 5648 return 1; 5649 else 5650 return 0; 5651 } 5652 5653 /* Direct Addressing. */ 5654 if (CONSTANT_P (addr)) 5655 return 4; 5656 5657 index = base = disp = scale = NULL_RTX; 5658 op0 = XEXP (addr, 0); 5659 op1 = XEXP (addr, 1); 5660 5661 if (GET_CODE (addr) == PLUS) 5662 { 5663 if (register_operand (op0, Pmode)) 5664 { 5665 if (register_operand (op1, Pmode)) 5666 index = op0, base = op1; 5667 else 5668 base = op0, disp = op1; 5669 } 5670 else if (GET_CODE (op0) == MULT) 5671 { 5672 index = XEXP (op0, 0); 5673 scale = XEXP (op0, 1); 5674 if (register_operand (op1, Pmode)) 5675 base = op1; 5676 else 5677 disp = op1; 5678 } 5679 else if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 0)) == MULT) 5680 { 5681 index = XEXP (XEXP (op0, 0), 0); 5682 scale = XEXP (XEXP (op0, 0), 1); 5683 base = XEXP (op0, 1); 5684 disp = op1; 5685 } 5686 else if (GET_CODE (op0) == PLUS) 5687 { 5688 index = XEXP (op0, 0); 5689 base = XEXP (op0, 1); 5690 disp = op1; 5691 } 5692 else 5693 abort (); 5694 } 5695 else if (GET_CODE (addr) == MULT 5696 /* We're called for lea too, which implements ashift on occasion. */ 5697 || GET_CODE (addr) == ASHIFT) 5698 { 5699 index = XEXP (addr, 0); 5700 scale = XEXP (addr, 1); 5701 } 5702 else 5703 abort (); 5704 5705 /* Allow arg pointer and stack pointer as index if there is not scaling */ 5706 if (base && index && !scale 5707 && (index == stack_pointer_rtx 5708 || index == arg_pointer_rtx 5709 || index == frame_pointer_rtx)) 5710 { 5711 rtx tmp = base; 5712 base = index; 5713 index = tmp; 5714 } 5715 5716 /* Special case: ebp cannot be encoded as a base without a displacement. */ 5717 if (base == frame_pointer_rtx && !disp) 5718 disp = const0_rtx; 5719 5720 /* Scaling can not be encoded without base or displacement. 5721 Except for scale == 1 where we can encode reg + reg instead of reg * 2. */ 5722 if (!base && index 5723 && (!scale || GET_CODE (scale) != CONST_INT || (INTVAL (scale) != 1))) 5724 disp = const0_rtx; 5725 5726 /* Find the length of the displacement constant. */ 5727 len = 0; 5728 if (disp) 5729 { 5730 if (GET_CODE (disp) == CONST_INT 5731 && CONST_OK_FOR_LETTER_P (INTVAL (disp), 'K')) 5732 len = 1; 5733 else 5734 len = 4; 5735 } 5736 5737 /* An index requires the two-byte modrm form. Not important 5738 if we are computing just length of the displacement. */ 5739 if (index && ! disp_length) 5740 len += 1; 5741 5742 return len; 5743} 5744