1/* Definitions of target machine for GNU compiler, for ARM/Thumb. 2 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. 3 The basis of this contribution was generated by 4 Richard Earnshaw, Advanced RISC Machines Ltd 5 6This file is part of GNU CC. 7 8GNU CC is free software; you can redistribute it and/or modify 9it under the terms of the GNU General Public License as published by 10the Free Software Foundation; either version 2, or (at your option) 11any later version. 12 13GNU CC is distributed in the hope that it will be useful, 14but WITHOUT ANY WARRANTY; without even the implied warranty of 15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16GNU General Public License for more details. 17 18You should have received a copy of the GNU General Public License 19along with GNU CC; see the file COPYING. If not, write to 20the Free Software Foundation, 59 Temple Place - Suite 330, 21Boston, MA 02111-1307, USA. */ 22 23/* ??? The files thumb.{c,h,md} are all seriously lacking comments. */ 24 25/* ??? The files thumb.{c,h,md} need to be reviewed by an experienced 26 gcc hacker in their entirety. */ 27 28/* ??? The files thumb.{c,h,md} and tcoff.h are all separate from the arm 29 files, which will lead to many maintenance problems. These files are 30 likely missing all bug fixes made to the arm port since they diverged. */ 31 32/* ??? Many patterns in the md file accept operands that will require a 33 reload. These should be eliminated if possible by tightening the 34 predicates and/or constraints. This will give faster/smaller code. */ 35 36/* ??? There is no pattern for the TST instuction. Check for other unsupported 37 instructions. */ 38 39/* Run Time Target Specifications */ 40#ifndef CPP_PREDEFINES 41#define CPP_PREDEFINES "-Dthumb -D__thumb -Acpu(arm) -Amachine(arm)" 42#endif 43 44#ifndef CPP_SPEC 45#define CPP_SPEC "\ 46%{mbig-endian:-D__ARMEB__ -D__THUMBEB__} \ 47%{mbe:-D__ARMEB__ -D__THUMBEB__} \ 48%{!mbe: %{!mbig-endian:-D__ARMEL__ -D__THUMBEL__}} \ 49" 50#endif 51 52#define ASM_SPEC "-marm7tdmi %{mthumb-interwork:-mthumb-interwork} %{mbig-endian:-EB}" 53#define LINK_SPEC "%{mbig-endian:-EB} -X" 54 55#define TARGET_VERSION fputs (" (ARM/THUMB:generic)", stderr); 56 57/* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */ 58#define THUMB_FLAG_BIG_END 0x0001 59#define THUMB_FLAG_BACKTRACE 0x0002 60#define THUMB_FLAG_LEAF_BACKTRACE 0x0004 61#define ARM_FLAG_THUMB 0x1000 /* same as in arm.h */ 62#define THUMB_FLAG_CALLEE_SUPER_INTERWORKING 0x40000 63#define THUMB_FLAG_CALLER_SUPER_INTERWORKING 0x80000 64 65 66/* Run-time compilation parameters selecting different hardware/software subsets. */ 67extern int target_flags; 68#define TARGET_DEFAULT 0 /* ARM_FLAG_THUMB */ 69#define TARGET_BIG_END (target_flags & THUMB_FLAG_BIG_END) 70#define TARGET_THUMB_INTERWORK (target_flags & ARM_FLAG_THUMB) 71#define TARGET_BACKTRACE (leaf_function_p() \ 72 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \ 73 : (target_flags & THUMB_FLAG_BACKTRACE)) 74 75/* Set if externally visable functions should assume that they 76 might be called in ARM mode, from a non-thumb aware code. */ 77#define TARGET_CALLEE_INTERWORKING \ 78 (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING) 79 80/* Set if calls via function pointers should assume that their 81 destination is non-Thumb aware. */ 82#define TARGET_CALLER_INTERWORKING \ 83 (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING) 84 85/* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */ 86#ifndef SUBTARGET_SWITCHES 87#define SUBTARGET_SWITCHES 88#endif 89 90#define TARGET_SWITCHES \ 91{ \ 92 {"big-endian", THUMB_FLAG_BIG_END}, \ 93 {"little-endian", -THUMB_FLAG_BIG_END}, \ 94 {"thumb-interwork", ARM_FLAG_THUMB}, \ 95 {"no-thumb-interwork", -ARM_FLAG_THUMB}, \ 96 {"tpcs-frame", THUMB_FLAG_BACKTRACE}, \ 97 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE}, \ 98 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE}, \ 99 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE}, \ 100 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING}, \ 101 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING}, \ 102 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING}, \ 103 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING}, \ 104 SUBTARGET_SWITCHES \ 105 {"", TARGET_DEFAULT} \ 106} 107 108#define TARGET_OPTIONS \ 109{ \ 110 { "structure-size-boundary=", & structure_size_string }, \ 111} 112 113#define REGISTER_PREFIX "" 114 115#define CAN_DEBUG_WITHOUT_FP 1 116 117#define ASM_APP_ON "" 118#define ASM_APP_OFF "\t.code\t16\n" 119 120/* Output a gap. In fact we fill it with nulls. */ 121#define ASM_OUTPUT_SKIP(STREAM, NBYTES) \ 122 fprintf ((STREAM), "\t.space\t%u\n", (NBYTES)) 123 124/* This is how to output an assembler line 125 that says to advance the location counter 126 to a multiple of 2**LOG bytes. */ 127#define ASM_OUTPUT_ALIGN(STREAM,LOG) \ 128{ \ 129 fprintf (STREAM, "\t.align\t%d\n", (LOG)); \ 130} 131 132/* Output a common block */ 133#define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \ 134 (fprintf ((STREAM), "\t.comm\t"), \ 135 assemble_name ((STREAM), (NAME)), \ 136 fprintf((STREAM), ", %d\t%s %d\n", (ROUNDED), (ASM_COMMENT_START), (SIZE))) 137 138#define ASM_GENERATE_INTERNAL_LABEL(STRING,PREFIX,NUM) \ 139 sprintf ((STRING), "*%s%s%d", (LOCAL_LABEL_PREFIX), (PREFIX), (NUM)) 140 141/* This is how to output an internal numbered label where 142 PREFIX is the class of label and NUM is the number within the class. */ 143#define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \ 144 fprintf ((STREAM), "%s%s%d:\n", (LOCAL_LABEL_PREFIX), (PREFIX), (NUM)) 145 146/* This is how to output a label which precedes a jumptable. Since 147 instructions are 2 bytes, we need explicit alignment here. */ 148 149#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,JUMPTABLE) \ 150 do { \ 151 ASM_OUTPUT_ALIGN (FILE, 2); \ 152 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \ 153 } while (0) 154 155/* This says how to define a local common symbol (ie, not visible to 156 linker). */ 157#define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \ 158 (fprintf((STREAM),"\n\t.lcomm\t"), \ 159 assemble_name((STREAM),(NAME)), \ 160 fprintf((STREAM),",%u\n",(SIZE))) 161 162/* Output a reference to a label. */ 163#define ASM_OUTPUT_LABELREF(STREAM,NAME) \ 164 fprintf ((STREAM), "%s%s", user_label_prefix, (NAME)) 165 166/* This is how to output an assembler line for a numeric constant byte. */ 167#define ASM_OUTPUT_BYTE(STREAM,VALUE) \ 168 fprintf ((STREAM), "\t.byte\t0x%x\n", (VALUE)) 169 170#define ASM_OUTPUT_INT(STREAM,VALUE) \ 171{ \ 172 fprintf (STREAM, "\t.word\t"); \ 173 output_addr_const (STREAM, (VALUE)); \ 174 fprintf (STREAM, "\n"); \ 175} 176 177#define ASM_OUTPUT_SHORT(STREAM,VALUE) \ 178{ \ 179 fprintf (STREAM, "\t.short\t"); \ 180 output_addr_const (STREAM, (VALUE)); \ 181 fprintf (STREAM, "\n"); \ 182} 183 184#define ASM_OUTPUT_CHAR(STREAM,VALUE) \ 185{ \ 186 fprintf (STREAM, "\t.byte\t"); \ 187 output_addr_const (STREAM, (VALUE)); \ 188 fprintf (STREAM, "\n"); \ 189} 190 191#define ASM_OUTPUT_LONG_DOUBLE(STREAM,VALUE) \ 192do { char dstr[30]; \ 193 long l[3]; \ 194 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \ 195 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ 196 fprintf (STREAM, "\t.long 0x%lx,0x%lx,0x%lx\t%s long double %s\n", \ 197 l[0], l[1], l[2], ASM_COMMENT_START, dstr); \ 198 } while (0) 199 200#define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \ 201do { char dstr[30]; \ 202 long l[2]; \ 203 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \ 204 REAL_VALUE_TO_DECIMAL (VALUE, "%.14g", dstr); \ 205 fprintf (STREAM, "\t.long 0x%lx, 0x%lx\t%s double %s\n", l[0], \ 206 l[1], ASM_COMMENT_START, dstr); \ 207 } while (0) 208 209#define ASM_OUTPUT_FLOAT(STREAM, VALUE) \ 210do { char dstr[30]; \ 211 long l; \ 212 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ 213 REAL_VALUE_TO_DECIMAL (VALUE, "%.7g", dstr); \ 214 fprintf (STREAM, "\t.word 0x%lx\t%s float %s\n", l, \ 215 ASM_COMMENT_START, dstr); \ 216 } while (0); 217 218/* Define results of standard character escape sequences. */ 219#define TARGET_BELL 007 220#define TARGET_BS 010 221#define TARGET_TAB 011 222#define TARGET_NEWLINE 012 223#define TARGET_VT 013 224#define TARGET_FF 014 225#define TARGET_CR 015 226 227/* This is how to output a string. */ 228#define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \ 229do { \ 230 register int i, c, len = (LEN), cur_pos = 17; \ 231 register unsigned char *string = (unsigned char *)(STRING); \ 232 fprintf ((STREAM), "\t.ascii\t\""); \ 233 for (i = 0; i < len; i++) \ 234 { \ 235 register int c = string[i]; \ 236 \ 237 switch (c) \ 238 { \ 239 case '\"': \ 240 case '\\': \ 241 putc ('\\', (STREAM)); \ 242 putc (c, (STREAM)); \ 243 cur_pos += 2; \ 244 break; \ 245 \ 246 case TARGET_NEWLINE: \ 247 fputs ("\\n", (STREAM)); \ 248 if (i+1 < len \ 249 && (((c = string[i+1]) >= '\040' && c <= '~') \ 250 || c == TARGET_TAB)) \ 251 cur_pos = 32767; /* break right here */ \ 252 else \ 253 cur_pos += 2; \ 254 break; \ 255 \ 256 case TARGET_TAB: \ 257 fputs ("\\t", (STREAM)); \ 258 cur_pos += 2; \ 259 break; \ 260 \ 261 case TARGET_FF: \ 262 fputs ("\\f", (STREAM)); \ 263 cur_pos += 2; \ 264 break; \ 265 \ 266 case TARGET_BS: \ 267 fputs ("\\b", (STREAM)); \ 268 cur_pos += 2; \ 269 break; \ 270 \ 271 case TARGET_CR: \ 272 fputs ("\\r", (STREAM)); \ 273 cur_pos += 2; \ 274 break; \ 275 \ 276 default: \ 277 if (c >= ' ' && c < 0177) \ 278 { \ 279 putc (c, (STREAM)); \ 280 cur_pos++; \ 281 } \ 282 else \ 283 { \ 284 fprintf ((STREAM), "\\%03o", c); \ 285 cur_pos += 4; \ 286 } \ 287 } \ 288 \ 289 if (cur_pos > 72 && i+1 < len) \ 290 { \ 291 cur_pos = 17; \ 292 fprintf ((STREAM), "\"\n\t.ascii\t\""); \ 293 } \ 294 } \ 295 fprintf ((STREAM), "\"\n"); \ 296} while (0) 297 298/* Output and Generation of Labels */ 299#define ASM_OUTPUT_LABEL(STREAM,NAME) \ 300 (assemble_name ((STREAM), (NAME)), \ 301 fprintf ((STREAM), ":\n")) 302 303#define ASM_GLOBALIZE_LABEL(STREAM,NAME) \ 304 (fprintf ((STREAM), "\t.globl\t"), \ 305 assemble_name ((STREAM), (NAME)), \ 306 fputc ('\n', (STREAM))) 307 308/* Construct a private name. */ 309#define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \ 310 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \ 311 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER))) 312 313/* Switch to the text or data segment. */ 314#define TEXT_SECTION_ASM_OP ".text" 315#define DATA_SECTION_ASM_OP ".data" 316#define BSS_SECTION_ASM_OP ".bss" 317 318/* The assembler's names for the registers. */ 319#ifndef REGISTER_NAMES 320#define REGISTER_NAMES \ 321{ \ 322 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 323 "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc", "ap" \ 324} 325#endif 326 327#ifndef ADDITIONAL_REGISTER_NAMES 328#define ADDITIONAL_REGISTER_NAMES \ 329{ \ 330 {"a1", 0}, \ 331 {"a2", 1}, \ 332 {"a3", 2}, \ 333 {"a4", 3}, \ 334 {"v1", 4}, \ 335 {"v2", 5}, \ 336 {"v3", 6}, \ 337 {"v4", 7}, \ 338 {"v5", 8}, \ 339 {"v6", 9}, \ 340 {"sb", 9}, \ 341 {"v7", 10}, \ 342 {"r10", 10}, /* sl */ \ 343 {"r11", 11}, /* fp */ \ 344 {"r12", 12}, /* ip */ \ 345 {"r13", 13}, /* sp */ \ 346 {"r14", 14}, /* lr */ \ 347 {"r15", 15} /* pc */ \ 348} 349#endif 350 351/* The assembler's parentheses characters. */ 352#define ASM_OPEN_PAREN "(" 353#define ASM_CLOSE_PAREN ")" 354 355#ifndef ASM_COMMENT_START 356#define ASM_COMMENT_START "@" 357#endif 358 359/* Output an element of a dispatch table. */ 360#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ 361 fprintf (STREAM, "\t.word\t%sL%d\n", (LOCAL_LABEL_PREFIX), (VALUE)) 362 363#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \ 364 fprintf (STREAM, "\tb\t%sL%d\n", (LOCAL_LABEL_PREFIX), (VALUE)) 365 366/* Storage Layout */ 367 368/* Define this is most significant bit is lowest numbered in 369 instructions that operate on numbered bit-fields. */ 370#define BITS_BIG_ENDIAN 0 371 372/* Define this if most significant byte of a word is the lowest 373 numbered. */ 374#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 375 376#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 377 378/* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based 379 on processor pre-defineds when compiling libgcc2.c. */ 380#if defined(__THUMBEB__) && !defined(__THUMBEL__) 381#define LIBGCC2_WORDS_BIG_ENDIAN 1 382#else 383#define LIBGCC2_WORDS_BIG_ENDIAN 0 384#endif 385 386#define FLOAT_WORDS_BIG_ENDIAN 1 387 388#define BITS_PER_UNIT 8 389#define BITS_PER_WORD 32 390 391#define UNITS_PER_WORD 4 392 393#define POINTER_SIZE 32 394 395#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 396{ \ 397 if (GET_MODE_CLASS (MODE) == MODE_INT \ 398 && GET_MODE_SIZE (MODE) < 4) \ 399 { \ 400 (UNSIGNEDP) = 1; \ 401 (MODE) = SImode; \ 402 } \ 403} 404 405#define PARM_BOUNDARY 32 406#define STACK_BOUNDARY 32 407 408#define FUNCTION_BOUNDARY 32 409#define BIGGEST_ALIGNMENT 32 410 411/* Make strings word-aligned so strcpy from constants will be faster. */ 412#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 413 (TREE_CODE (EXP) == STRING_CST \ 414 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 415 416#define EMPTY_FIELD_BOUNDARY 32 417 418#define STRUCTURE_SIZE_BOUNDARY 32 419 420/* Used when parsing command line option -mstructure_size_boundary. */ 421extern char * structure_size_string; 422 423#define STRICT_ALIGNMENT 1 424 425#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT 426 427 428/* Layout of Source Language Data Types */ 429 430#define DEFAULT_SIGNED_CHAR 0 431 432#define TARGET_BELL 007 433#define TARGET_BS 010 434#define TARGET_TAB 011 435#define TARGET_NEWLINE 012 436#define TARGET_VT 013 437#define TARGET_FF 014 438#define TARGET_CR 015 439 440 441/* Register Usage */ 442 443/* Note there are 16 hard registers on the Thumb. We invent a 17th register 444 which is assigned to ARG_POINTER_REGNUM, but this is later removed by 445 elimination passes in the compiler. */ 446#define FIRST_PSEUDO_REGISTER 17 447 448/* ??? This is questionable. */ 449#define FIXED_REGISTERS \ 450{ \ 451 0,0,0,0, \ 452 0,0,0,0, \ 453 0,0,0,1, \ 454 0,1,1,1,1 \ 455} 456 457/* ??? This is questionable. */ 458#define CALL_USED_REGISTERS \ 459{ \ 460 1,1,1,1, \ 461 0,0,0,0, \ 462 0,0,0,1, \ 463 1,1,1,1,1 \ 464} 465 466#define HARD_REGNO_NREGS(REGNO,MODE) \ 467 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \ 468 / UNITS_PER_WORD) 469 470/* ??? Probably should only allow DImode/DFmode in even numbered registers. */ 471#define HARD_REGNO_MODE_OK(REGNO,MODE) ((GET_MODE_SIZE (MODE) > UNITS_PER_WORD) ? (REGNO < 7) : 1) 472 473#define MODES_TIEABLE_P(MODE1,MODE2) 1 474 475/* The NOARG_LO_REGS class is the set of LO_REGS that are not used for passing 476 arguments to functions. These are the registers that are available for 477 spilling during reload. The code in reload1.c:init_reload() will detect this 478 class and place it into 'reload_address_base_reg_class'. */ 479 480enum reg_class 481{ 482 NO_REGS, 483 NONARG_LO_REGS, 484 LO_REGS, 485 STACK_REG, 486 BASE_REGS, 487 HI_REGS, 488 ALL_REGS, 489 LIM_REG_CLASSES 490}; 491 492#define GENERAL_REGS ALL_REGS 493 494#define N_REG_CLASSES (int) LIM_REG_CLASSES 495 496#define REG_CLASS_NAMES \ 497{ \ 498 "NO_REGS", \ 499 "NONARG_LO_REGS", \ 500 "LO_REGS", \ 501 "STACK_REG", \ 502 "BASE_REGS", \ 503 "HI_REGS", \ 504 "ALL_REGS" \ 505} 506 507#define REG_CLASS_CONTENTS \ 508{ \ 509 0x00000, \ 510 0x000f0, \ 511 0x000ff, \ 512 0x02000, \ 513 0x020ff, \ 514 0x0ff00, \ 515 0x1ffff, \ 516} 517 518#define REGNO_REG_CLASS(REGNO) \ 519 ((REGNO) == STACK_POINTER_REGNUM ? STACK_REG \ 520 : (REGNO) < 8 ? ((REGNO) < 4 ? LO_REGS \ 521 : NONARG_LO_REGS) \ 522 : HI_REGS) 523 524#define BASE_REG_CLASS BASE_REGS 525 526#define INDEX_REG_CLASS LO_REGS 527 528/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows 529 registers explicitly used in the rtl to be used as spill registers 530 but prevents the compiler from extending the lifetime of these 531 registers. */ 532 533#define SMALL_REGISTER_CLASSES 1 534 535#define REG_CLASS_FROM_LETTER(C) \ 536 ((C) == 'l' ? LO_REGS \ 537 : (C) == 'h' ? HI_REGS \ 538 : (C) == 'b' ? BASE_REGS \ 539 : (C) == 'k' ? STACK_REG \ 540 : NO_REGS) 541 542#define REGNO_OK_FOR_BASE_P(REGNO) \ 543 ((REGNO) < 8 \ 544 || (REGNO) == STACK_POINTER_REGNUM \ 545 || (unsigned) reg_renumber[REGNO] < 8 \ 546 || (unsigned) reg_renumber[REGNO] == STACK_POINTER_REGNUM) 547 548#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 549 ((REGNO) < 8 \ 550 || (unsigned) reg_renumber[REGNO] < 8 \ 551 || (GET_MODE_SIZE (MODE) >= 4 \ 552 && ((REGNO) == STACK_POINTER_REGNUM \ 553 || (unsigned) reg_renumber[REGNO] == STACK_POINTER_REGNUM))) 554 555#define REGNO_OK_FOR_INDEX_P(REGNO) \ 556 ((REGNO) < 8 \ 557 || (unsigned) reg_renumber[REGNO] < 8) 558 559/* ??? This looks suspiciously wrong. */ 560/* We need to leave BASE_REGS reloads alone, in order to avoid caller_save 561 lossage. Caller_saves requests a BASE_REGS reload (caller_save_spill_class) 562 and then later we verify that one was allocated. If PREFERRED_RELOAD_CLASS 563 says to allocate a LO_REGS spill instead, then this mismatch gives an 564 abort. Alternatively, this could be fixed by modifying BASE_REG_CLASS 565 to be LO_REGS instead of BASE_REGS. It is not clear what affect this 566 change would have. */ 567/* ??? This looks even more suspiciously wrong. PREFERRED_RELOAD_CLASS 568 must always return a strict subset of the input class. Just blindly 569 returning LO_REGS is safe only if the input class is a superset of LO_REGS, 570 but there is no check for this. Added another exception for NONARG_LO_REGS 571 because it is not a superset of LO_REGS. */ 572/* ??? We now use NONARG_LO_REGS for caller_save_spill_class, so the 573 comments about BASE_REGS are now obsolete. */ 574#define PREFERRED_RELOAD_CLASS(X,CLASS) \ 575 ((CLASS) == BASE_REGS || (CLASS) == NONARG_LO_REGS ? (CLASS) \ 576 : LO_REGS) 577/* 578 ((CONSTANT_P ((X)) && GET_CODE ((X)) != CONST_INT \ 579 && ! CONSTANT_POOL_ADDRESS_P((X))) ? NO_REGS \ 580 : (GET_CODE ((X)) == CONST_INT \ 581 && (unsigned HOST_WIDE_INT) INTVAL ((X)) > 255) ? NO_REGS \ 582 : LO_REGS) */ 583 584/* Must leave BASE_REGS and NONARG_LO_REGS reloads alone, see comment 585 above. */ 586#define SECONDARY_RELOAD_CLASS(CLASS,MODE,X) \ 587 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS && (CLASS) != NONARG_LO_REGS \ 588 ? ((true_regnum (X) == -1 ? LO_REGS \ 589 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 590 : NO_REGS)) \ 591 : NO_REGS) 592 593#define CLASS_MAX_NREGS(CLASS,MODE) HARD_REGNO_NREGS(0,(MODE)) 594 595int thumb_shiftable_const (); 596 597#define CONST_OK_FOR_LETTER_P(VAL,C) \ 598 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 \ 599 : (C) == 'J' ? (VAL) > -256 && (VAL) <= 0 \ 600 : (C) == 'K' ? thumb_shiftable_const (VAL) \ 601 : (C) == 'L' ? (VAL) > -8 && (VAL) < 8 \ 602 : (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \ 603 && ((VAL) & 3) == 0) \ 604 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \ 605 : (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \ 606 : 0) 607 608#define CONST_DOUBLE_OK_FOR_LETTER_P(VAL,C) 0 609 610#define EXTRA_CONSTRAINT(X,C) \ 611 ((C) == 'Q' ? (GET_CODE (X) == MEM \ 612 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0) 613 614/* Stack Layout and Calling Conventions */ 615 616#define STACK_GROWS_DOWNWARD 1 617 618/* #define FRAME_GROWS_DOWNWARD 1 */ 619 620/* #define ARGS_GROW_DOWNWARD 1 */ 621 622#define STARTING_FRAME_OFFSET 0 623 624#define FIRST_PARM_OFFSET(FNDECL) 0 625 626/* Registers that address the stack frame */ 627 628#define STACK_POINTER_REGNUM 13 /* Defined by the TPCS. */ 629 630#define FRAME_POINTER_REGNUM 7 /* TPCS defines this as 11 but it does not really mean it. */ 631 632#define ARG_POINTER_REGNUM 16 /* A fake hard register that is eliminated later on. */ 633 634#define STATIC_CHAIN_REGNUM 9 635 636#define FRAME_POINTER_REQUIRED 0 637 638#define ELIMINABLE_REGS \ 639{{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 640 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ 641 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} 642 643/* On the Thumb we always want to perform the eliminations as we 644 actually only have one real register pointing to the stashed 645 variables: the stack pointer, and we never use the frame pointer. */ 646#define CAN_ELIMINATE(FROM,TO) 1 647 648/* Note: This macro must match the code in thumb_function_prologue() in thumb.c. */ 649#define INITIAL_ELIMINATION_OFFSET(FROM,TO,OFFSET) \ 650{ \ 651 (OFFSET) = 0; \ 652 if ((FROM) == ARG_POINTER_REGNUM) \ 653 { \ 654 int count_regs = 0; \ 655 int regno; \ 656 (OFFSET) += get_frame_size (); \ 657 for (regno = 8; regno < 13; regno++) \ 658 if (regs_ever_live[regno] && ! call_used_regs[regno]) \ 659 count_regs++; \ 660 if (count_regs) \ 661 (OFFSET) += 4 * count_regs; \ 662 count_regs = 0; \ 663 for (regno = 0; regno < 8; regno++) \ 664 if (regs_ever_live[regno] && ! call_used_regs[regno]) \ 665 count_regs++; \ 666 if (count_regs || ! leaf_function_p () || far_jump_used_p()) \ 667 (OFFSET) += 4 * (count_regs + 1); \ 668 if (TARGET_BACKTRACE) { \ 669 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \ 670 (OFFSET) += 20; \ 671 else \ 672 (OFFSET) += 16; } \ 673 } \ 674 if ((TO) == STACK_POINTER_REGNUM) \ 675 (OFFSET) += current_function_outgoing_args_size; \ 676} 677 678/* Passing Arguments on the stack */ 679 680#define PROMOTE_PROTOTYPES 1 681 682#define ACCUMULATE_OUTGOING_ARGS 1 683 684#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 685 686#define FUNCTION_ARG(CUM,MODE,TYPE,NAMED) \ 687 ((NAMED) ? ((CUM) >= 16 ? 0 : gen_rtx (REG, (MODE), (CUM) / 4)) \ 688 : 0) 689 690#define FUNCTION_ARG_PARTIAL_NREGS(CUM,MODE,TYPE,NAMED) \ 691 (((CUM) < 16 && (CUM) + (((MODE) == BLKmode) \ 692 ? int_size_in_bytes (TYPE) \ 693 : HARD_REGNO_NREGS (0, (MODE)) * 4) > 16) \ 694 ? 4 - (CUM) / 4 : 0) 695 696#define CUMULATIVE_ARGS int 697 698#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ 699 ((CUM) = ((FNTYPE) && aggregate_value_p (TREE_TYPE (FNTYPE))) ? 4 : 0) 700 701#define FUNCTION_ARG_ADVANCE(CUM,MODE,TYPE,NAMED) \ 702 (CUM) += ((((MODE) == BLKmode) \ 703 ? int_size_in_bytes (TYPE) \ 704 : GET_MODE_SIZE (MODE)) + 3) & ~3 705 706#define FUNCTION_ARG_REGNO_P(REGNO) \ 707 ((REGNO) >=0 && (REGNO) <= 3) 708 709#define FUNCTION_VALUE(VALTYPE,FUNC) gen_rtx (REG, TYPE_MODE (VALTYPE), 0) 710 711#define LIBCALL_VALUE(MODE) gen_rtx (REG, (MODE), 0) 712 713#define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == 0) 714 715 /* How large values are returned */ 716/* A C expression which can inhibit the returning of certain function values 717 in registers, based on the type of value. */ 718#define RETURN_IN_MEMORY(TYPE) thumb_return_in_memory (TYPE) 719 720/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 721 values must be in memory. On the ARM, they need only do so if larger 722 than a word, or if they contain elements offset from zero in the struct. */ 723#define DEFAULT_PCC_STRUCT_RETURN 0 724 725 726#define STRUCT_VALUE_REGNUM 0 727 728#define FUNCTION_PROLOGUE(FILE,SIZE) thumb_function_prologue((FILE),(SIZE)) 729 730#define FUNCTION_EPILOGUE(FILE,SIZE) thumb_function_epilogue((FILE),(SIZE)) 731 732/* Generating code for profiling */ 733#define FUNCTION_PROFILER(STREAM,LABELNO) \ 734{ \ 735 fprintf ((STREAM), "\tmov\\tip, lr\n"); \ 736 fprintf ((STREAM), "\tbl\tmcount\n"); \ 737 fprintf ((STREAM), "\t.word\tLP%d\n", (LABELNO)); \ 738} 739 740/* Implementing the Varargs Macros */ 741 742#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \ 743{ \ 744 extern int current_function_anonymous_args; \ 745 current_function_anonymous_args = 1; \ 746 if ((CUM) < 16) \ 747 (PRETEND_SIZE) = 16 - (CUM); \ 748} 749 750/* Trampolines for nested functions */ 751 752/* Output assembler code for a block containing the constant parts of 753 a trampoline, leaving space for the variable parts. 754 755 On the Thumb we always switch into ARM mode to execute the trampoline. 756 Why - because it is easier. This code will always be branched to via 757 a BX instruction and since the compiler magically generates the address 758 of the function the linker has no opportunity to ensure that the 759 bottom bit is set. Thus the processor will be in ARM mode when it 760 reaches this code. So we duplicate the ARM trampoline code and add 761 a switch into Thumb mode as well. 762 763 On the ARM, (if r8 is the static chain regnum, and remembering that 764 referencing pc adds an offset of 8) the trampoline looks like: 765 ldr r8, [pc, #0] 766 ldr pc, [pc] 767 .word static chain value 768 .word function's address 769 ??? FIXME: When the trampoline returns, r8 will be clobbered. */ 770#define TRAMPOLINE_TEMPLATE(FILE) \ 771{ \ 772 fprintf ((FILE), "\t.code 32\n"); \ 773 fprintf ((FILE), ".Ltrampoline_start:\n"); \ 774 fprintf ((FILE), "\tldr\t%s, [%spc, #8]\n", \ 775 reg_names[STATIC_CHAIN_REGNUM], REGISTER_PREFIX); \ 776 fprintf ((FILE), "\tldr\t%sip, [%spc, #8]\n", \ 777 REGISTER_PREFIX, REGISTER_PREFIX); \ 778 fprintf ((FILE), "\torr\t%sip, %sip, #1\n", \ 779 REGISTER_PREFIX, REGISTER_PREFIX); \ 780 fprintf ((FILE), "\tbx\t%sip\n", REGISTER_PREFIX); \ 781 fprintf ((FILE), "\t.word\t0\n"); \ 782 fprintf ((FILE), "\t.word\t0\n"); \ 783 fprintf ((FILE), "\t.code 16\n"); \ 784} 785 786/* Length in units of the trampoline for entering a nested function. */ 787#define TRAMPOLINE_SIZE 24 788 789/* Alignment required for a trampoline in units. */ 790#define TRAMPOLINE_ALIGN 4 791 792#define INITIALIZE_TRAMPOLINE(ADDR,FNADDR,CHAIN) \ 793{ \ 794 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((ADDR), 16)), \ 795 (CHAIN)); \ 796 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((ADDR), 20)), \ 797 (FNADDR)); \ 798} 799 800 801/* Implicit Calls to Library Routines */ 802 803#define TARGET_MEM_FUNCTIONS 1 804 805#define OVERRIDE_OPTIONS thumb_override_options () 806 807 808/* Addressing Modes */ 809 810#define HAVE_POST_INCREMENT 1 811 812#define CONSTANT_ADDRESS_P(X) \ 813 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) 814 815#define MAX_REGS_PER_ADDRESS 2 816 817#ifdef REG_OK_STRICT 818 819#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 820#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 821 822#define REG_MODE_OK_FOR_BASE_P(X,MODE) \ 823 REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 824 825#else /* REG_OK_STRICT */ 826 827#define REG_OK_FOR_BASE_P(X) \ 828 (REGNO (X) < 8 || REGNO (X) == STACK_POINTER_REGNUM \ 829 || (X) == arg_pointer_rtx \ 830 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 831 832#define REG_MODE_OK_FOR_BASE_P(X,MODE) \ 833 (REGNO (X) < 8 \ 834 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 835 || (GET_MODE_SIZE (MODE) >= 4 \ 836 && (REGNO (X) == STACK_POINTER_REGNUM \ 837 || (X) == arg_pointer_rtx))) 838 839#define REG_OK_FOR_INDEX_P(X) \ 840 (REGNO (X) < 8 \ 841 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 842 843#endif /* REG_OK_STRICT */ 844 845/* In a REG+REG address, both must be INDEX registers. */ 846#define REG_OK_FOR_INDEXED_BASE_P(X) REG_OK_FOR_INDEX_P(X) 847 848#define LEGITIMATE_OFFSET(MODE,VAL) \ 849(GET_MODE_SIZE (MODE) == 1 ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \ 850 : GET_MODE_SIZE (MODE) == 2 ? ((unsigned HOST_WIDE_INT) (VAL) < 64 \ 851 && ((VAL) & 1) == 0) \ 852 : ((VAL) >= 0 && ((VAL) + GET_MODE_SIZE (MODE)) <= 128 \ 853 && ((VAL) & 3) == 0)) 854 855/* The AP may be eliminated to either the SP or the FP, so we use the 856 least common denominator, e.g. SImode, and offsets from 0 to 64. */ 857 858/* ??? Verify whether the above is the right approach. */ 859 860/* ??? Also, the FP may be eliminated to the SP, so perhaps that 861 needs special handling also. */ 862 863/* ??? Look at how the mips16 port solves this problem. It probably uses 864 better ways to solve some of these problems. */ 865 866/* Although it is not incorrect, we don't accept QImode and HImode 867 addresses based on the frame pointer or arg pointer until the reload pass starts. 868 This is so that eliminating such addresses into stack based ones 869 won't produce impossible code. */ 870#define GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \ 871{ \ 872 /* ??? Not clear if this is right. Experiment. */ \ 873 if (GET_MODE_SIZE (MODE) < 4 \ 874 && ! (reload_in_progress || reload_completed) \ 875 && (reg_mentioned_p (frame_pointer_rtx, X) \ 876 || reg_mentioned_p (arg_pointer_rtx, X) \ 877 || reg_mentioned_p (virtual_incoming_args_rtx, X) \ 878 || reg_mentioned_p (virtual_outgoing_args_rtx, X) \ 879 || reg_mentioned_p (virtual_stack_dynamic_rtx, X) \ 880 || reg_mentioned_p (virtual_stack_vars_rtx, X))) \ 881 ; \ 882 /* Accept any base register. SP only in SImode or larger. */ \ 883 else if (GET_CODE (X) == REG && REG_MODE_OK_FOR_BASE_P(X, MODE)) \ 884 goto WIN; \ 885 /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */ \ 886 else if (GET_MODE_SIZE (MODE) >= 4 && CONSTANT_P (X) \ 887 && CONSTANT_POOL_ADDRESS_P (X)) \ 888 goto WIN; \ 889 /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */ \ 890 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \ 891 && (GET_CODE (X) == LABEL_REF \ 892 || (GET_CODE (X) == CONST \ 893 && GET_CODE (XEXP (X, 0)) == PLUS \ 894 && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF \ 895 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))) \ 896 goto WIN; \ 897 /* Post-inc indexing only supported for SImode and larger. */ \ 898 else if (GET_CODE (X) == POST_INC && GET_MODE_SIZE (MODE) >= 4 \ 899 && GET_CODE (XEXP (X, 0)) == REG \ 900 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \ 901 goto WIN; \ 902 else if (GET_CODE (X) == PLUS) \ 903 { \ 904 /* REG+REG address can be any two index registers. */ \ 905 /* ??? REG+REG addresses have been completely disabled before \ 906 reload completes, because we do not have enough available \ 907 reload registers. We only have 3 guaranteed reload registers \ 908 (NONARG_LO_REGS - the frame pointer), but we need at least 4 \ 909 to support REG+REG addresses. We have left them enabled after \ 910 reload completes, in the hope that reload_cse_regs and related \ 911 routines will be able to create them after the fact. It is \ 912 probably possible to support REG+REG addresses with additional \ 913 reload work, but I do not not have enough time to attempt such \ 914 a change at this time. */ \ 915 /* ??? Normally checking the mode here is wrong, since it isn't \ 916 impossible to use REG+REG with DFmode. However, the movdf \ 917 pattern requires offsettable addresses, and REG+REG is not \ 918 offsettable, so it must be rejected somehow. Trying to use \ 919 'o' fails, because offsettable_address_p does a QImode check. \ 920 QImode is not valid for stack addresses, and has a smaller \ 921 range for non-stack bases, and this causes valid addresses \ 922 to be rejected. So we just eliminate REG+REG here by checking \ 923 the mode. */ \ 924 /* We also disallow FRAME+REG addressing since we know that FRAME \ 925 will be replaced with STACK, and SP relative addressing only \ 926 permits SP+OFFSET. */ \ 927 if (GET_MODE_SIZE (MODE) <= 4 \ 928 /* ??? See comment above. */ \ 929 && reload_completed \ 930 && GET_CODE (XEXP (X, 0)) == REG \ 931 && GET_CODE (XEXP (X, 1)) == REG \ 932 && XEXP (X, 0) != frame_pointer_rtx \ 933 && XEXP (X, 1) != frame_pointer_rtx \ 934 && XEXP (X, 0) != virtual_stack_vars_rtx \ 935 && XEXP (X, 1) != virtual_stack_vars_rtx \ 936 && REG_OK_FOR_INDEX_P (XEXP (X, 0)) \ 937 && REG_OK_FOR_INDEX_P (XEXP (X, 1))) \ 938 goto WIN; \ 939 /* REG+const has 5-7 bit offset for non-SP registers. */ \ 940 else if (GET_CODE (XEXP (X, 0)) == REG \ 941 && (REG_OK_FOR_INDEX_P (XEXP (X, 0)) \ 942 || XEXP (X, 0) == arg_pointer_rtx) \ 943 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 944 && LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \ 945 goto WIN; \ 946 /* REG+const has 10 bit offset for SP, but only SImode and \ 947 larger is supported. */ \ 948 /* ??? Should probably check for DI/DFmode overflow here \ 949 just like GO_IF_LEGITIMATE_OFFSET does. */ \ 950 else if (GET_CODE (XEXP (X, 0)) == REG \ 951 && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \ 952 && GET_MODE_SIZE (MODE) >= 4 \ 953 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 954 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (X, 1)) < 1024 \ 955 && (INTVAL (XEXP (X, 1)) & 3) == 0) \ 956 goto WIN; \ 957 } \ 958} 959 960/* ??? If an HImode FP+large_offset address is converted to an HImode 961 SP+large_offset address, then reload won't know how to fix it. It sees 962 only that SP isn't valid for HImode, and so reloads the SP into an index 963 register, but the resulting address is still invalid because the offset 964 is too big. We fix it here instead by reloading the entire address. */ 965/* We could probably achieve better results by defining PROMOTE_MODE to help 966 cope with the variances between the Thumb's signed and unsigned byte and 967 halfword load instructions. */ 968#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 969{ \ 970 if (GET_CODE (X) == PLUS \ 971 && GET_MODE_SIZE (MODE) < 4 \ 972 && GET_CODE (XEXP (X, 0)) == REG \ 973 && XEXP (X, 0) == stack_pointer_rtx \ 974 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 975 && ! LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \ 976 { \ 977 rtx orig_X = X; \ 978 X = copy_rtx (X); \ 979 push_reload (orig_X, NULL_RTX, &X, NULL_PTR, \ 980 BASE_REG_CLASS, \ 981 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \ 982 goto WIN; \ 983 } \ 984} 985 986#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) 987 988#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) 989 990#define LEGITIMATE_CONSTANT_P(X) \ 991 (GET_CODE (X) == CONST_INT \ 992 || GET_CODE (X) == CONST_DOUBLE \ 993 || CONSTANT_ADDRESS_P (X)) 994 995 996/* Condition Code Status */ 997 998#define NOTICE_UPDATE_CC(EXP,INSN) \ 999{ \ 1000 if (get_attr_conds ((INSN)) != CONDS_UNCHANGED) \ 1001 CC_STATUS_INIT; \ 1002} 1003 1004 1005/* Describing Relative Costs of Operations */ 1006 1007#define SLOW_BYTE_ACCESS 0 1008 1009#define SLOW_UNALIGNED_ACCESS 1 1010 1011#define NO_FUNCTION_CSE 1 1012 1013#define NO_RECURSIVE_FUNCTION_CSE 1 1014 1015#define REGISTER_MOVE_COST(FROM,TO) \ 1016 (((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2) 1017 1018#define MEMORY_MOVE_COST(M,CLASS,IN) \ 1019 ((GET_MODE_SIZE(M) < 4 ? 8 : 2 * GET_MODE_SIZE(M)) * (CLASS == LO_REGS ? 1 : 2)) 1020 1021/* This will allow better space optimization when compiling with -O */ 1022#define BRANCH_COST (optimize > 1 ? 1 : 0) 1023 1024#define RTX_COSTS(X,CODE,OUTER) \ 1025 case MULT: \ 1026 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 1027 { \ 1028 int cycles = 0; \ 1029 unsigned HOST_WIDE_INT i = INTVAL (XEXP (X, 1)); \ 1030 while (i) \ 1031 { \ 1032 i >>= 2; \ 1033 cycles++; \ 1034 } \ 1035 return COSTS_N_INSNS (2) + cycles; \ 1036 } \ 1037 return COSTS_N_INSNS (1) + 16; \ 1038 case ASHIFT: case ASHIFTRT: case LSHIFTRT: case ROTATERT: \ 1039 case PLUS: case MINUS: case COMPARE: case NEG: case NOT: \ 1040 return COSTS_N_INSNS (1); \ 1041 case SET: \ 1042 return (COSTS_N_INSNS (1) \ 1043 + 4 * ((GET_CODE (SET_SRC (X)) == MEM) \ 1044 + GET_CODE (SET_DEST (X)) == MEM)) 1045 1046#define CONST_COSTS(X,CODE,OUTER) \ 1047 case CONST_INT: \ 1048 if ((OUTER) == SET) \ 1049 { \ 1050 if ((unsigned HOST_WIDE_INT) INTVAL (X) < 256) \ 1051 return 0; \ 1052 if (thumb_shiftable_const (INTVAL (X))) \ 1053 return COSTS_N_INSNS (2); \ 1054 return COSTS_N_INSNS (3); \ 1055 } \ 1056 else if (OUTER == PLUS \ 1057 && INTVAL (X) < 256 && INTVAL (X) > -256) \ 1058 return 0; \ 1059 else if (OUTER == COMPARE \ 1060 && (unsigned HOST_WIDE_INT) INTVAL (X) < 256) \ 1061 return 0; \ 1062 else if (OUTER == ASHIFT || OUTER == ASHIFTRT \ 1063 || OUTER == LSHIFTRT) \ 1064 return 0; \ 1065 return COSTS_N_INSNS (2); \ 1066 case CONST: \ 1067 case CONST_DOUBLE: \ 1068 case LABEL_REF: \ 1069 case SYMBOL_REF: \ 1070 return COSTS_N_INSNS(3); 1071 1072#define ADDRESS_COST(X) \ 1073 ((GET_CODE (X) == REG \ 1074 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \ 1075 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \ 1076 ? 1 : 2) 1077 1078 1079/* Position Independent Code */ 1080 1081#define PRINT_OPERAND(STREAM,X,CODE) \ 1082 thumb_print_operand((STREAM), (X), (CODE)) 1083 1084#define PRINT_OPERAND_ADDRESS(STREAM,X) \ 1085{ \ 1086 if (GET_CODE ((X)) == REG) \ 1087 fprintf ((STREAM), "[%s]", reg_names[REGNO ((X))]); \ 1088 else if (GET_CODE ((X)) == POST_INC) \ 1089 fprintf ((STREAM), "%s!", reg_names[REGNO (XEXP (X, 0))]); \ 1090 else if (GET_CODE ((X)) == PLUS) \ 1091 { \ 1092 if (GET_CODE (XEXP ((X), 1)) == CONST_INT) \ 1093 fprintf ((STREAM), "[%s, #%d]", \ 1094 reg_names[REGNO (XEXP ((X), 0))], \ 1095 (int) INTVAL (XEXP ((X), 1))); \ 1096 else \ 1097 fprintf ((STREAM), "[%s, %s]", \ 1098 reg_names[REGNO (XEXP ((X), 0))], \ 1099 reg_names[REGNO (XEXP ((X), 1))]); \ 1100 } \ 1101 else \ 1102 output_addr_const ((STREAM), (X)); \ 1103} 1104 1105#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '@' || ((CODE) == '_')) 1106 1107/* Emit a special directive when defining a function name. 1108 This is used by the assembler to assit with interworking. */ 1109#define ASM_DECLARE_FUNCTION_NAME(file, name, decl) \ 1110 if (! is_called_in_ARM_mode (decl)) \ 1111 fprintf (file, "\t.thumb_func\n") ; \ 1112 else \ 1113 fprintf (file, "\t.code\t32\n") ; \ 1114 ASM_OUTPUT_LABEL (file, name) 1115 1116#define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ 1117 asm_fprintf ((STREAM), "\tpush {%R%s}\n", reg_names[(REGNO)]) 1118 1119#define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ 1120 fprintf ((STREAM), "\tpop {%R%s}\n", reg_names[(REGNO)]) 1121 1122#define FINAL_PRESCAN_INSN(INSN,OPVEC,NOPERANDS) \ 1123 final_prescan_insn((INSN)) 1124 1125/* Controlling Debugging Information Format */ 1126#define DBX_REGISTER_NUMBER(REGNO) (REGNO) 1127 1128/* Specific options for DBX Output */ 1129 1130#define DBX_DEBUGGING_INFO 1 1131 1132#define DEFAULT_GDB_EXTENSIONS 1 1133 1134 1135/* Cross Compilation and Floating Point */ 1136 1137#define REAL_ARITHMETIC 1138 1139 1140/* Miscellaneous Parameters */ 1141 1142#define PREDICATE_CODES \ 1143 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, 1144 1145#define CASE_VECTOR_MODE Pmode 1146 1147#define WORD_REGISTER_OPERATIONS 1148 1149#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1150 1151#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR 1152 1153#define EASY_DIV_EXPR TRUNC_DIV_EXPR 1154 1155#define MOVE_MAX 4 1156 1157#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 1158 1159#define STORE_FLAG_VALUE 1 1160 1161#define Pmode SImode 1162 1163#define FUNCTION_MODE SImode 1164 1165#define DOLLARS_IN_IDENTIFIERS 0 1166 1167#define NO_DOLLAR_IN_LABEL 1 1168 1169#define HAVE_ATEXIT 1170 1171/* The literal pool needs to reside in the text area due to the 1172 limited PC addressing range: */ 1173#define MACHINE_DEPENDENT_REORG(INSN) thumb_reorg ((INSN)) 1174 1175 1176/* Options specific to Thumb */ 1177 1178/* True if a return instruction can be used in this function. */ 1179int thumb_trivial_epilogue (); 1180#define USE_RETURN (reload_completed && thumb_trivial_epilogue ()) 1181 1182extern char * thumb_unexpanded_epilogue (); 1183extern char * output_move_mem_multiple (); 1184extern char * thumb_load_double_from_address (); 1185extern char * output_return (); 1186extern int far_jump_used_p(); 1187extern int is_called_in_ARM_mode (); 1188 1189