1/* Output routines for GCC for ARM. 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000 3 Free Software Foundation, Inc. 4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) 5 and Martin Simmons (@harleqn.co.uk). 6 More major hacks by Richard Earnshaw (rearnsha@arm.com). 7 8This file is part of GNU CC. 9 10GNU CC is free software; you can redistribute it and/or modify 11it under the terms of the GNU General Public License as published by 12the Free Software Foundation; either version 2, or (at your option) 13any later version. 14 15GNU CC is distributed in the hope that it will be useful, 16but WITHOUT ANY WARRANTY; without even the implied warranty of 17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18GNU General Public License for more details. 19 20You should have received a copy of the GNU General Public License 21along with GNU CC; see the file COPYING. If not, write to 22the Free Software Foundation, 59 Temple Place - Suite 330, 23Boston, MA 02111-1307, USA. */ 24 25#include "config.h" 26#include "system.h" 27#include "rtl.h" 28#include "regs.h" 29#include "hard-reg-set.h" 30#include "real.h" 31#include "insn-config.h" 32#include "conditions.h" 33#include "insn-flags.h" 34#include "output.h" 35#include "insn-attr.h" 36#include "flags.h" 37#include "reload.h" 38#include "tree.h" 39#include "expr.h" 40#include "toplev.h" 41#include "recog.h" 42 43/* The maximum number of insns skipped which will be conditionalised if 44 possible. */ 45static int max_insns_skipped = 5; 46 47extern FILE * asm_out_file; 48/* Some function declarations. */ 49 50static HOST_WIDE_INT int_log2 PROTO ((HOST_WIDE_INT)); 51static char * output_multi_immediate PROTO ((rtx *, char *, char *, int, 52 HOST_WIDE_INT)); 53static int arm_gen_constant PROTO ((enum rtx_code, enum machine_mode, 54 HOST_WIDE_INT, rtx, rtx, int, int)); 55static int arm_naked_function_p PROTO ((tree)); 56static void init_fpa_table PROTO ((void)); 57static enum machine_mode select_dominance_cc_mode PROTO ((rtx, rtx, 58 HOST_WIDE_INT)); 59static HOST_WIDE_INT add_constant PROTO ((rtx, enum machine_mode, int *)); 60static void dump_table PROTO ((rtx)); 61static int fixit PROTO ((rtx, enum machine_mode, int)); 62static rtx find_barrier PROTO ((rtx, int)); 63static int broken_move PROTO ((rtx)); 64static char * fp_const_from_val PROTO ((REAL_VALUE_TYPE *)); 65static int eliminate_lr2ip PROTO ((rtx *)); 66static char * shift_op PROTO ((rtx, HOST_WIDE_INT *)); 67static int pattern_really_clobbers_lr PROTO ((rtx)); 68static int function_really_clobbers_lr PROTO ((rtx)); 69static void emit_multi_reg_push PROTO ((int)); 70static void emit_sfm PROTO ((int, int)); 71static enum arm_cond_code get_arm_condition_code PROTO ((rtx)); 72static int const_ok_for_op RTX_CODE_PROTO ((HOST_WIDE_INT, Rcode)); 73 74/* True if we are currently building a constant table. */ 75int making_const_table; 76 77/* Define the information needed to generate branch insns. This is 78 stored from the compare operation. */ 79rtx arm_compare_op0, arm_compare_op1; 80 81/* What type of floating point are we tuning for? */ 82enum floating_point_type arm_fpu; 83 84/* What type of floating point instructions are available? */ 85enum floating_point_type arm_fpu_arch; 86 87/* What program mode is the cpu running in? 26-bit mode or 32-bit mode */ 88enum prog_mode_type arm_prgmode; 89 90/* Set by the -mfp=... option */ 91const char * target_fp_name = NULL; 92 93/* Used to parse -mstructure_size_boundary command line option. */ 94const char * structure_size_string = NULL; 95int arm_structure_size_boundary = 32; /* Used to be 8 */ 96 97/* Bit values used to identify processor capabilities. */ 98#define FL_CO_PROC 0x01 /* Has external co-processor bus */ 99#define FL_FAST_MULT 0x02 /* Fast multiply */ 100#define FL_MODE26 0x04 /* 26-bit mode support */ 101#define FL_MODE32 0x08 /* 32-bit mode support */ 102#define FL_ARCH4 0x10 /* Architecture rel 4 */ 103#define FL_THUMB 0x20 /* Thumb aware */ 104#define FL_LDSCHED 0x40 /* Load scheduling necessary */ 105#define FL_STRONG 0x80 /* StrongARM */ 106 107/* The bits in this mask specify which instructions we are allowed to generate. */ 108static int insn_flags = 0; 109/* The bits in this mask specify which instruction scheduling options should 110 be used. Note - there is an overlap with the FL_FAST_MULT. For some 111 hardware we want to be able to generate the multiply instructions, but to 112 tune as if they were not present in the architecture. */ 113static int tune_flags = 0; 114 115/* The following are used in the arm.md file as equivalents to bits 116 in the above two flag variables. */ 117 118/* Nonzero if this is an "M" variant of the processor. */ 119int arm_fast_multiply = 0; 120 121/* Nonzero if this chip supports the ARM Architecture 4 extensions */ 122int arm_arch4 = 0; 123 124/* Nonzero if this chip can benefit from load scheduling. */ 125int arm_ld_sched = 0; 126 127/* Nonzero if this chip is a StrongARM. */ 128int arm_is_strong = 0; 129 130/* Nonzero if this chip is a an ARM6 or an ARM7. */ 131int arm_is_6_or_7 = 0; 132 133/* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we 134 must report the mode of the memory reference from PRINT_OPERAND to 135 PRINT_OPERAND_ADDRESS. */ 136enum machine_mode output_memory_reference_mode; 137 138/* Nonzero if the prologue must setup `fp'. */ 139int current_function_anonymous_args; 140 141/* The register number to be used for the PIC offset register. */ 142int arm_pic_register = 9; 143 144/* Location counter of .text segment. */ 145int arm_text_location = 0; 146 147/* Set to one if we think that lr is only saved because of subroutine calls, 148 but all of these can be `put after' return insns */ 149int lr_save_eliminated; 150 151/* Set to 1 when a return insn is output, this means that the epilogue 152 is not needed. */ 153static int return_used_this_function; 154 155/* Set to 1 after arm_reorg has started. Reset to start at the start of 156 the next function. */ 157static int after_arm_reorg = 0; 158 159/* The maximum number of insns to be used when loading a constant. */ 160static int arm_constant_limit = 3; 161 162/* For an explanation of these variables, see final_prescan_insn below. */ 163int arm_ccfsm_state; 164enum arm_cond_code arm_current_cc; 165rtx arm_target_insn; 166int arm_target_label; 167 168/* The condition codes of the ARM, and the inverse function. */ 169char * arm_condition_codes[] = 170{ 171 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", 172 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" 173}; 174 175static enum arm_cond_code get_arm_condition_code (); 176 177#define streq(string1, string2) (strcmp (string1, string2) == 0) 178 179/* Initialization code */ 180 181struct processors 182{ 183 char * name; 184 unsigned int flags; 185}; 186 187/* Not all of these give usefully different compilation alternatives, 188 but there is no simple way of generalizing them. */ 189static struct processors all_cores[] = 190{ 191 /* ARM Cores */ 192 193 {"arm2", FL_CO_PROC | FL_MODE26 }, 194 {"arm250", FL_CO_PROC | FL_MODE26 }, 195 {"arm3", FL_CO_PROC | FL_MODE26 }, 196 {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 197 {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 198 {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 199 {"arm610", FL_MODE26 | FL_MODE32 }, 200 {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 201 {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 202 {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, /* arm7m doesn't exist on its own, */ 203 {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, /* but only with D, (and I), */ 204 {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, /* but those don't alter the code, */ 205 {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, /* so arm7m is sometimes used. */ 206 {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, 207 {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 208 {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 209 {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 210 {"arm710", FL_MODE26 | FL_MODE32 }, 211 {"arm710c", FL_MODE26 | FL_MODE32 }, 212 {"arm7100", FL_MODE26 | FL_MODE32 }, 213 {"arm7500", FL_MODE26 | FL_MODE32 }, 214 {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, /* Doesn't really have an external co-proc, but does have embedded fpu. */ 215 {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB }, 216 {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, 217 {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, 218 {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, 219 {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, 220 {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, 221 {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, 222 {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, 223 224 {NULL, 0} 225}; 226 227static struct processors all_architectures[] = 228{ 229 /* ARM Architectures */ 230 231 {"armv2", FL_CO_PROC | FL_MODE26 }, 232 {"armv2a", FL_CO_PROC | FL_MODE26 }, 233 {"armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 234 {"armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, 235 {"armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 }, 236 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no 237 implementations that support it, so we will leave it out for now. */ 238 {"armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB }, 239 {NULL, 0} 240}; 241 242/* This is a magic stucture. The 'string' field is magically filled in 243 with a pointer to the value specified by the user on the command line 244 assuming that the user has specified such a value. */ 245 246struct arm_cpu_select arm_select[] = 247{ 248 /* string name processors */ 249 { NULL, "-mcpu=", all_cores }, 250 { NULL, "-march=", all_architectures }, 251 { NULL, "-mtune=", all_cores } 252}; 253 254/* Return the number of bits set in value' */ 255static unsigned int 256bit_count (value) 257 signed int value; 258{ 259 unsigned int count = 0; 260 261 while (value) 262 { 263 value &= ~(value & - value); 264 ++ count; 265 } 266 267 return count; 268} 269 270/* Fix up any incompatible options that the user has specified. 271 This has now turned into a maze. */ 272void 273arm_override_options () 274{ 275 unsigned i; 276 277 /* Set up the flags based on the cpu/architecture selected by the user. */ 278 for (i = sizeof (arm_select) / sizeof (arm_select[0]); i--;) 279 { 280 struct arm_cpu_select * ptr = arm_select + i; 281 282 if (ptr->string != NULL && ptr->string[0] != '\0') 283 { 284 struct processors * sel; 285 286 for (sel = ptr->processors; sel->name != NULL; sel ++) 287 if (streq (ptr->string, sel->name)) 288 { 289 if (i == 2) 290 tune_flags = sel->flags; 291 else 292 { 293 /* If we have been given an architecture and a processor 294 make sure that they are compatible. We only generate 295 a warning though, and we prefer the CPU over the 296 architecture. */ 297 if (insn_flags != 0 && (insn_flags ^ sel->flags)) 298 warning ("switch -mcpu=%s conflicts with -mtune= switch", 299 ptr->string); 300 301 insn_flags = sel->flags; 302 } 303 304 break; 305 } 306 307 if (sel->name == NULL) 308 error ("bad value (%s) for %s switch", ptr->string, ptr->name); 309 } 310 } 311 312 /* If the user did not specify a processor, choose one for them. */ 313 if (insn_flags == 0) 314 { 315 struct processors * sel; 316 unsigned int sought; 317 static struct cpu_default 318 { 319 int cpu; 320 char * name; 321 } 322 cpu_defaults[] = 323 { 324 { TARGET_CPU_arm2, "arm2" }, 325 { TARGET_CPU_arm6, "arm6" }, 326 { TARGET_CPU_arm610, "arm610" }, 327 { TARGET_CPU_arm710, "arm710" }, 328 { TARGET_CPU_arm7m, "arm7m" }, 329 { TARGET_CPU_arm7500fe, "arm7500fe" }, 330 { TARGET_CPU_arm7tdmi, "arm7tdmi" }, 331 { TARGET_CPU_arm8, "arm8" }, 332 { TARGET_CPU_arm810, "arm810" }, 333 { TARGET_CPU_arm9, "arm9" }, 334 { TARGET_CPU_strongarm, "strongarm" }, 335 { TARGET_CPU_generic, "arm" }, 336 { 0, 0 } 337 }; 338 struct cpu_default * def; 339 340 /* Find the default. */ 341 for (def = cpu_defaults; def->name; def ++) 342 if (def->cpu == TARGET_CPU_DEFAULT) 343 break; 344 345 /* Make sure we found the default CPU. */ 346 if (def->name == NULL) 347 abort (); 348 349 /* Find the default CPU's flags. */ 350 for (sel = all_cores; sel->name != NULL; sel ++) 351 if (streq (def->name, sel->name)) 352 break; 353 354 if (sel->name == NULL) 355 abort (); 356 357 insn_flags = sel->flags; 358 359 /* Now check to see if the user has specified some command line 360 switch that require certain abilities from the cpu. */ 361 sought = 0; 362 363 if (TARGET_THUMB_INTERWORK) 364 { 365 sought |= (FL_THUMB | FL_MODE32); 366 367 /* Force apcs-32 to be used for interworking. */ 368 target_flags |= ARM_FLAG_APCS_32; 369 370 /* There are no ARM processor that supports both APCS-26 and 371 interworking. Therefore we force FL_MODE26 to be removed 372 from insn_flags here (if it was set), so that the search 373 below will always be able to find a compatible processor. */ 374 insn_flags &= ~ FL_MODE26; 375 } 376 377 if (! TARGET_APCS_32) 378 sought |= FL_MODE26; 379 380 if (sought != 0 && ((sought & insn_flags) != sought)) 381 { 382 /* Try to locate a CPU type that supports all of the abilities 383 of the default CPU, plus the extra abilities requested by 384 the user. */ 385 for (sel = all_cores; sel->name != NULL; sel ++) 386 if ((sel->flags & sought) == (sought | insn_flags)) 387 break; 388 389 if (sel->name == NULL) 390 { 391 unsigned int current_bit_count = 0; 392 struct processors * best_fit = NULL; 393 394 /* Ideally we would like to issue an error message here 395 saying that it was not possible to find a CPU compatible 396 with the default CPU, but which also supports the command 397 line options specified by the programmer, and so they 398 ought to use the -mcpu=<name> command line option to 399 override the default CPU type. 400 401 Unfortunately this does not work with multilibing. We 402 need to be able to support multilibs for -mapcs-26 and for 403 -mthumb-interwork and there is no CPU that can support both 404 options. Instead if we cannot find a cpu that has both the 405 characteristics of the default cpu and the given command line 406 options we scan the array again looking for a best match. */ 407 for (sel = all_cores; sel->name != NULL; sel ++) 408 if ((sel->flags & sought) == sought) 409 { 410 unsigned int count; 411 412 count = bit_count (sel->flags & insn_flags); 413 414 if (count >= current_bit_count) 415 { 416 best_fit = sel; 417 current_bit_count = count; 418 } 419 } 420 421 if (best_fit == NULL) 422 abort (); 423 else 424 sel = best_fit; 425 } 426 427 insn_flags = sel->flags; 428 } 429 } 430 431 /* If tuning has not been specified, tune for whichever processor or 432 architecture has been selected. */ 433 if (tune_flags == 0) 434 tune_flags = insn_flags; 435 436 /* Make sure that the processor choice does not conflict with any of the 437 other command line choices. */ 438 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32)) 439 { 440 /* If APCS-32 was not the default then it must have been set by the 441 user, so issue a warning message. If the user has specified 442 "-mapcs-32 -mcpu=arm2" then we loose here. */ 443 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0) 444 warning ("target CPU does not support APCS-32" ); 445 target_flags &= ~ ARM_FLAG_APCS_32; 446 } 447 else if (! TARGET_APCS_32 && !(insn_flags & FL_MODE26)) 448 { 449 warning ("target CPU does not support APCS-26" ); 450 target_flags |= ARM_FLAG_APCS_32; 451 } 452 453 if (TARGET_THUMB_INTERWORK && !(insn_flags & FL_THUMB)) 454 { 455 warning ("target CPU does not support interworking" ); 456 target_flags &= ~ARM_FLAG_THUMB; 457 } 458 459 /* If interworking is enabled then APCS-32 must be selected as well. */ 460 if (TARGET_THUMB_INTERWORK) 461 { 462 if (! TARGET_APCS_32) 463 warning ("interworking forces APCS-32 to be used" ); 464 target_flags |= ARM_FLAG_APCS_32; 465 } 466 467 if (TARGET_APCS_STACK && ! TARGET_APCS) 468 { 469 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame"); 470 target_flags |= ARM_FLAG_APCS_FRAME; 471 } 472 473 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer) 474 warning ("-g with -fomit-frame-pointer may not give sensible debugging"); 475 476 if (TARGET_POKE_FUNCTION_NAME) 477 target_flags |= ARM_FLAG_APCS_FRAME; 478 479 if (TARGET_APCS_REENT && flag_pic) 480 fatal ("-fpic and -mapcs-reent are incompatible"); 481 482 if (TARGET_APCS_REENT) 483 warning ("APCS reentrant code not supported. Ignored"); 484 485 /* If stack checking is disabled, we can use r10 as the PIC register, 486 which keeps r9 available. */ 487 if (flag_pic && ! TARGET_APCS_STACK) 488 arm_pic_register = 10; 489 490 if (TARGET_APCS_FLOAT) 491 warning ("Passing floating point arguments in fp regs not yet supported"); 492 493 /* Initialise boolean versions of the flags, for use in the arm.md file. */ 494 arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0; 495 arm_arch4 = (insn_flags & FL_ARCH4) != 0; 496 497 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0; 498 arm_is_strong = (tune_flags & FL_STRONG) != 0; 499 arm_is_6_or_7 = ((tune_flags & (FL_MODE26 | FL_MODE32)) 500 && !(tune_flags & FL_ARCH4)); 501 502 /* Default value for floating point code... if no co-processor 503 bus, then schedule for emulated floating point. Otherwise, 504 assume the user has an FPA. 505 Note: this does not prevent use of floating point instructions, 506 -msoft-float does that. */ 507 arm_fpu = (tune_flags & FL_CO_PROC) ? FP_HARD : FP_SOFT3; 508 509 if (target_fp_name) 510 { 511 if (streq (target_fp_name, "2")) 512 arm_fpu_arch = FP_SOFT2; 513 else if (streq (target_fp_name, "3")) 514 arm_fpu_arch = FP_SOFT3; 515 else 516 fatal ("Invalid floating point emulation option: -mfpe-%s", 517 target_fp_name); 518 } 519 else 520 arm_fpu_arch = FP_DEFAULT; 521 522 if (TARGET_FPE && arm_fpu != FP_HARD) 523 arm_fpu = FP_SOFT2; 524 525 /* For arm2/3 there is no need to do any scheduling if there is only 526 a floating point emulator, or we are doing software floating-point. */ 527 if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD) && (tune_flags & FL_MODE32) == 0) 528 flag_schedule_insns = flag_schedule_insns_after_reload = 0; 529 530 arm_prog_mode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26; 531 532 if (structure_size_string != NULL) 533 { 534 int size = strtol (structure_size_string, NULL, 0); 535 536 if (size == 8 || size == 32) 537 arm_structure_size_boundary = size; 538 else 539 warning ("Structure size boundary can only be set to 8 or 32"); 540 } 541 542 /* If optimizing for space, don't synthesize constants. 543 For processors with load scheduling, it never costs more than 2 cycles 544 to load a constant, and the load scheduler may well reduce that to 1. */ 545 if (optimize_size || (tune_flags & FL_LDSCHED)) 546 arm_constant_limit = 1; 547 548 /* If optimizing for size, bump the number of instructions that we 549 are prepared to conditionally execute (even on a StrongARM). 550 Otherwise for the StrongARM, which has early execution of branches, 551 a sequence that is worth skipping is shorter. */ 552 if (optimize_size) 553 max_insns_skipped = 6; 554 else if (arm_is_strong) 555 max_insns_skipped = 3; 556} 557 558/* Return 1 if it is possible to return using a single instruction */ 559 560int 561use_return_insn (iscond) 562 int iscond; 563{ 564 int regno; 565 566 if (!reload_completed 567 || current_function_pretend_args_size 568 || current_function_anonymous_args 569 || ((get_frame_size () + current_function_outgoing_args_size != 0) 570 && !(TARGET_APCS && frame_pointer_needed))) 571 return 0; 572 573 /* Can't be done if interworking with Thumb, and any registers have been 574 stacked. Similarly, on StrongARM, conditional returns are expensive 575 if they aren't taken and registers have been stacked. */ 576 if (iscond && arm_is_strong && frame_pointer_needed) 577 return 0; 578 if ((iscond && arm_is_strong) 579 || TARGET_THUMB_INTERWORK) 580 { 581 for (regno = 0; regno < 16; regno++) 582 if (regs_ever_live[regno] && ! call_used_regs[regno]) 583 return 0; 584 585 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) 586 return 0; 587 } 588 589 /* Can't be done if any of the FPU regs are pushed, since this also 590 requires an insn */ 591 for (regno = 16; regno < 24; regno++) 592 if (regs_ever_live[regno] && ! call_used_regs[regno]) 593 return 0; 594 595 /* If a function is naked, don't use the "return" insn. */ 596 if (arm_naked_function_p (current_function_decl)) 597 return 0; 598 599 return 1; 600} 601 602/* Return TRUE if int I is a valid immediate ARM constant. */ 603 604int 605const_ok_for_arm (i) 606 HOST_WIDE_INT i; 607{ 608 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF; 609 610 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must 611 be all zero, or all one. */ 612 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0 613 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) 614 != ((~(unsigned HOST_WIDE_INT) 0) 615 & ~(unsigned HOST_WIDE_INT) 0xffffffff))) 616 return FALSE; 617 618 /* Fast return for 0 and powers of 2 */ 619 if ((i & (i - 1)) == 0) 620 return TRUE; 621 622 do 623 { 624 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0) 625 return TRUE; 626 mask = 627 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff) 628 >> (32 - 2)) | ~((unsigned HOST_WIDE_INT) 0xffffffff); 629 } while (mask != ~(unsigned HOST_WIDE_INT) 0xFF); 630 631 return FALSE; 632} 633 634/* Return true if I is a valid constant for the operation CODE. */ 635static int 636const_ok_for_op (i, code) 637 HOST_WIDE_INT i; 638 enum rtx_code code; 639{ 640 if (const_ok_for_arm (i)) 641 return 1; 642 643 switch (code) 644 { 645 case PLUS: 646 return const_ok_for_arm (ARM_SIGN_EXTEND (-i)); 647 648 case MINUS: /* Should only occur with (MINUS I reg) => rsb */ 649 case XOR: 650 case IOR: 651 return 0; 652 653 case AND: 654 return const_ok_for_arm (ARM_SIGN_EXTEND (~i)); 655 656 default: 657 abort (); 658 } 659} 660 661/* Emit a sequence of insns to handle a large constant. 662 CODE is the code of the operation required, it can be any of SET, PLUS, 663 IOR, AND, XOR, MINUS; 664 MODE is the mode in which the operation is being performed; 665 VAL is the integer to operate on; 666 SOURCE is the other operand (a register, or a null-pointer for SET); 667 SUBTARGETS means it is safe to create scratch registers if that will 668 either produce a simpler sequence, or we will want to cse the values. 669 Return value is the number of insns emitted. */ 670 671int 672arm_split_constant (code, mode, val, target, source, subtargets) 673 enum rtx_code code; 674 enum machine_mode mode; 675 HOST_WIDE_INT val; 676 rtx target; 677 rtx source; 678 int subtargets; 679{ 680 if (subtargets || code == SET 681 || (GET_CODE (target) == REG && GET_CODE (source) == REG 682 && REGNO (target) != REGNO (source))) 683 { 684 /* After arm_reorg has been called, we can't fix up expensive 685 constants by pushing them into memory so we must synthesise 686 them in-line, regardless of the cost. This is only likely to 687 be more costly on chips that have load delay slots and we are 688 compiling without running the scheduler (so no splitting 689 occurred before the final instruction emission). 690 691 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c 692 */ 693 if (! after_arm_reorg 694 && (arm_gen_constant (code, mode, val, target, source, 1, 0) 695 > arm_constant_limit + (code != SET))) 696 { 697 if (code == SET) 698 { 699 /* Currently SET is the only monadic value for CODE, all 700 the rest are diadic. */ 701 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val))); 702 return 1; 703 } 704 else 705 { 706 rtx temp = subtargets ? gen_reg_rtx (mode) : target; 707 708 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val))); 709 /* For MINUS, the value is subtracted from, since we never 710 have subtraction of a constant. */ 711 if (code == MINUS) 712 emit_insn (gen_rtx_SET (VOIDmode, target, 713 gen_rtx (code, mode, temp, source))); 714 else 715 emit_insn (gen_rtx_SET (VOIDmode, target, 716 gen_rtx (code, mode, source, temp))); 717 return 2; 718 } 719 } 720 } 721 722 return arm_gen_constant (code, mode, val, target, source, subtargets, 1); 723} 724 725/* As above, but extra parameter GENERATE which, if clear, suppresses 726 RTL generation. */ 727int 728arm_gen_constant (code, mode, val, target, source, subtargets, generate) 729 enum rtx_code code; 730 enum machine_mode mode; 731 HOST_WIDE_INT val; 732 rtx target; 733 rtx source; 734 int subtargets; 735 int generate; 736{ 737 int can_invert = 0; 738 int can_negate = 0; 739 int can_negate_initial = 0; 740 int can_shift = 0; 741 int i; 742 int num_bits_set = 0; 743 int set_sign_bit_copies = 0; 744 int clear_sign_bit_copies = 0; 745 int clear_zero_bit_copies = 0; 746 int set_zero_bit_copies = 0; 747 int insns = 0; 748 unsigned HOST_WIDE_INT temp1, temp2; 749 unsigned HOST_WIDE_INT remainder = val & 0xffffffff; 750 751 /* find out which operations are safe for a given CODE. Also do a quick 752 check for degenerate cases; these can occur when DImode operations 753 are split. */ 754 switch (code) 755 { 756 case SET: 757 can_invert = 1; 758 can_shift = 1; 759 can_negate = 1; 760 break; 761 762 case PLUS: 763 can_negate = 1; 764 can_negate_initial = 1; 765 break; 766 767 case IOR: 768 if (remainder == 0xffffffff) 769 { 770 if (generate) 771 emit_insn (gen_rtx_SET (VOIDmode, target, 772 GEN_INT (ARM_SIGN_EXTEND (val)))); 773 return 1; 774 } 775 if (remainder == 0) 776 { 777 if (reload_completed && rtx_equal_p (target, source)) 778 return 0; 779 if (generate) 780 emit_insn (gen_rtx_SET (VOIDmode, target, source)); 781 return 1; 782 } 783 break; 784 785 case AND: 786 if (remainder == 0) 787 { 788 if (generate) 789 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx)); 790 return 1; 791 } 792 if (remainder == 0xffffffff) 793 { 794 if (reload_completed && rtx_equal_p (target, source)) 795 return 0; 796 if (generate) 797 emit_insn (gen_rtx_SET (VOIDmode, target, source)); 798 return 1; 799 } 800 can_invert = 1; 801 break; 802 803 case XOR: 804 if (remainder == 0) 805 { 806 if (reload_completed && rtx_equal_p (target, source)) 807 return 0; 808 if (generate) 809 emit_insn (gen_rtx_SET (VOIDmode, target, source)); 810 return 1; 811 } 812 if (remainder == 0xffffffff) 813 { 814 if (generate) 815 emit_insn (gen_rtx_SET (VOIDmode, target, 816 gen_rtx_NOT (mode, source))); 817 return 1; 818 } 819 820 /* We don't know how to handle this yet below. */ 821 abort (); 822 823 case MINUS: 824 /* We treat MINUS as (val - source), since (source - val) is always 825 passed as (source + (-val)). */ 826 if (remainder == 0) 827 { 828 if (generate) 829 emit_insn (gen_rtx_SET (VOIDmode, target, 830 gen_rtx_NEG (mode, source))); 831 return 1; 832 } 833 if (const_ok_for_arm (val)) 834 { 835 if (generate) 836 emit_insn (gen_rtx_SET (VOIDmode, target, 837 gen_rtx_MINUS (mode, GEN_INT (val), 838 source))); 839 return 1; 840 } 841 can_negate = 1; 842 843 break; 844 845 default: 846 abort (); 847 } 848 849 /* If we can do it in one insn get out quickly */ 850 if (const_ok_for_arm (val) 851 || (can_negate_initial && const_ok_for_arm (-val)) 852 || (can_invert && const_ok_for_arm (~val))) 853 { 854 if (generate) 855 emit_insn (gen_rtx_SET (VOIDmode, target, 856 (source ? gen_rtx (code, mode, source, 857 GEN_INT (val)) 858 : GEN_INT (val)))); 859 return 1; 860 } 861 862 863 /* Calculate a few attributes that may be useful for specific 864 optimizations. */ 865 866 for (i = 31; i >= 0; i--) 867 { 868 if ((remainder & (1 << i)) == 0) 869 clear_sign_bit_copies++; 870 else 871 break; 872 } 873 874 for (i = 31; i >= 0; i--) 875 { 876 if ((remainder & (1 << i)) != 0) 877 set_sign_bit_copies++; 878 else 879 break; 880 } 881 882 for (i = 0; i <= 31; i++) 883 { 884 if ((remainder & (1 << i)) == 0) 885 clear_zero_bit_copies++; 886 else 887 break; 888 } 889 890 for (i = 0; i <= 31; i++) 891 { 892 if ((remainder & (1 << i)) != 0) 893 set_zero_bit_copies++; 894 else 895 break; 896 } 897 898 switch (code) 899 { 900 case SET: 901 /* See if we can do this by sign_extending a constant that is known 902 to be negative. This is a good, way of doing it, since the shift 903 may well merge into a subsequent insn. */ 904 if (set_sign_bit_copies > 1) 905 { 906 if (const_ok_for_arm 907 (temp1 = ARM_SIGN_EXTEND (remainder 908 << (set_sign_bit_copies - 1)))) 909 { 910 if (generate) 911 { 912 rtx new_src = subtargets ? gen_reg_rtx (mode) : target; 913 emit_insn (gen_rtx_SET (VOIDmode, new_src, 914 GEN_INT (temp1))); 915 emit_insn (gen_ashrsi3 (target, new_src, 916 GEN_INT (set_sign_bit_copies - 1))); 917 } 918 return 2; 919 } 920 /* For an inverted constant, we will need to set the low bits, 921 these will be shifted out of harm's way. */ 922 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1; 923 if (const_ok_for_arm (~temp1)) 924 { 925 if (generate) 926 { 927 rtx new_src = subtargets ? gen_reg_rtx (mode) : target; 928 emit_insn (gen_rtx_SET (VOIDmode, new_src, 929 GEN_INT (temp1))); 930 emit_insn (gen_ashrsi3 (target, new_src, 931 GEN_INT (set_sign_bit_copies - 1))); 932 } 933 return 2; 934 } 935 } 936 937 /* See if we can generate this by setting the bottom (or the top) 938 16 bits, and then shifting these into the other half of the 939 word. We only look for the simplest cases, to do more would cost 940 too much. Be careful, however, not to generate this when the 941 alternative would take fewer insns. */ 942 if (val & 0xffff0000) 943 { 944 temp1 = remainder & 0xffff0000; 945 temp2 = remainder & 0x0000ffff; 946 947 /* Overlaps outside this range are best done using other methods. */ 948 for (i = 9; i < 24; i++) 949 { 950 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder) 951 && ! const_ok_for_arm (temp2)) 952 { 953 rtx new_src = (subtargets 954 ? (generate ? gen_reg_rtx (mode) : NULL_RTX) 955 : target); 956 insns = arm_gen_constant (code, mode, temp2, new_src, 957 source, subtargets, generate); 958 source = new_src; 959 if (generate) 960 emit_insn (gen_rtx_SET 961 (VOIDmode, target, 962 gen_rtx_IOR (mode, 963 gen_rtx_ASHIFT (mode, source, 964 GEN_INT (i)), 965 source))); 966 return insns + 1; 967 } 968 } 969 970 /* Don't duplicate cases already considered. */ 971 for (i = 17; i < 24; i++) 972 { 973 if (((temp1 | (temp1 >> i)) == remainder) 974 && ! const_ok_for_arm (temp1)) 975 { 976 rtx new_src = (subtargets 977 ? (generate ? gen_reg_rtx (mode) : NULL_RTX) 978 : target); 979 insns = arm_gen_constant (code, mode, temp1, new_src, 980 source, subtargets, generate); 981 source = new_src; 982 if (generate) 983 emit_insn 984 (gen_rtx_SET (VOIDmode, target, 985 gen_rtx_IOR 986 (mode, 987 gen_rtx_LSHIFTRT (mode, source, 988 GEN_INT (i)), 989 source))); 990 return insns + 1; 991 } 992 } 993 } 994 break; 995 996 case IOR: 997 case XOR: 998 /* If we have IOR or XOR, and the constant can be loaded in a 999 single instruction, and we can find a temporary to put it in, 1000 then this can be done in two instructions instead of 3-4. */ 1001 if (subtargets 1002 /* TARGET can't be NULL if SUBTARGETS is 0 */ 1003 || (reload_completed && ! reg_mentioned_p (target, source))) 1004 { 1005 if (const_ok_for_arm (ARM_SIGN_EXTEND (~ val))) 1006 { 1007 if (generate) 1008 { 1009 rtx sub = subtargets ? gen_reg_rtx (mode) : target; 1010 1011 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val))); 1012 emit_insn (gen_rtx_SET (VOIDmode, target, 1013 gen_rtx (code, mode, source, sub))); 1014 } 1015 return 2; 1016 } 1017 } 1018 1019 if (code == XOR) 1020 break; 1021 1022 if (set_sign_bit_copies > 8 1023 && (val & (-1 << (32 - set_sign_bit_copies))) == val) 1024 { 1025 if (generate) 1026 { 1027 rtx sub = subtargets ? gen_reg_rtx (mode) : target; 1028 rtx shift = GEN_INT (set_sign_bit_copies); 1029 1030 emit_insn (gen_rtx_SET (VOIDmode, sub, 1031 gen_rtx_NOT (mode, 1032 gen_rtx_ASHIFT (mode, 1033 source, 1034 shift)))); 1035 emit_insn (gen_rtx_SET (VOIDmode, target, 1036 gen_rtx_NOT (mode, 1037 gen_rtx_LSHIFTRT (mode, sub, 1038 shift)))); 1039 } 1040 return 2; 1041 } 1042 1043 if (set_zero_bit_copies > 8 1044 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder) 1045 { 1046 if (generate) 1047 { 1048 rtx sub = subtargets ? gen_reg_rtx (mode) : target; 1049 rtx shift = GEN_INT (set_zero_bit_copies); 1050 1051 emit_insn (gen_rtx_SET (VOIDmode, sub, 1052 gen_rtx_NOT (mode, 1053 gen_rtx_LSHIFTRT (mode, 1054 source, 1055 shift)))); 1056 emit_insn (gen_rtx_SET (VOIDmode, target, 1057 gen_rtx_NOT (mode, 1058 gen_rtx_ASHIFT (mode, sub, 1059 shift)))); 1060 } 1061 return 2; 1062 } 1063 1064 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~ val))) 1065 { 1066 if (generate) 1067 { 1068 rtx sub = subtargets ? gen_reg_rtx (mode) : target; 1069 emit_insn (gen_rtx_SET (VOIDmode, sub, 1070 gen_rtx_NOT (mode, source))); 1071 source = sub; 1072 if (subtargets) 1073 sub = gen_reg_rtx (mode); 1074 emit_insn (gen_rtx_SET (VOIDmode, sub, 1075 gen_rtx_AND (mode, source, 1076 GEN_INT (temp1)))); 1077 emit_insn (gen_rtx_SET (VOIDmode, target, 1078 gen_rtx_NOT (mode, sub))); 1079 } 1080 return 3; 1081 } 1082 break; 1083 1084 case AND: 1085 /* See if two shifts will do 2 or more insn's worth of work. */ 1086 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24) 1087 { 1088 HOST_WIDE_INT shift_mask = ((0xffffffff 1089 << (32 - clear_sign_bit_copies)) 1090 & 0xffffffff); 1091 1092 if ((remainder | shift_mask) != 0xffffffff) 1093 { 1094 if (generate) 1095 { 1096 rtx new_src = subtargets ? gen_reg_rtx (mode) : target; 1097 insns = arm_gen_constant (AND, mode, remainder | shift_mask, 1098 new_src, source, subtargets, 1); 1099 source = new_src; 1100 } 1101 else 1102 { 1103 rtx targ = subtargets ? NULL_RTX : target; 1104 insns = arm_gen_constant (AND, mode, remainder | shift_mask, 1105 targ, source, subtargets, 0); 1106 } 1107 } 1108 1109 if (generate) 1110 { 1111 rtx new_src = subtargets ? gen_reg_rtx (mode) : target; 1112 rtx shift = GEN_INT (clear_sign_bit_copies); 1113 1114 emit_insn (gen_ashlsi3 (new_src, source, shift)); 1115 emit_insn (gen_lshrsi3 (target, new_src, shift)); 1116 } 1117 1118 return insns + 2; 1119 } 1120 1121 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24) 1122 { 1123 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1; 1124 1125 if ((remainder | shift_mask) != 0xffffffff) 1126 { 1127 if (generate) 1128 { 1129 rtx new_src = subtargets ? gen_reg_rtx (mode) : target; 1130 1131 insns = arm_gen_constant (AND, mode, remainder | shift_mask, 1132 new_src, source, subtargets, 1); 1133 source = new_src; 1134 } 1135 else 1136 { 1137 rtx targ = subtargets ? NULL_RTX : target; 1138 1139 insns = arm_gen_constant (AND, mode, remainder | shift_mask, 1140 targ, source, subtargets, 0); 1141 } 1142 } 1143 1144 if (generate) 1145 { 1146 rtx new_src = subtargets ? gen_reg_rtx (mode) : target; 1147 rtx shift = GEN_INT (clear_zero_bit_copies); 1148 1149 emit_insn (gen_lshrsi3 (new_src, source, shift)); 1150 emit_insn (gen_ashlsi3 (target, new_src, shift)); 1151 } 1152 1153 return insns + 2; 1154 } 1155 1156 break; 1157 1158 default: 1159 break; 1160 } 1161 1162 for (i = 0; i < 32; i++) 1163 if (remainder & (1 << i)) 1164 num_bits_set++; 1165 1166 if (code == AND || (can_invert && num_bits_set > 16)) 1167 remainder = (~remainder) & 0xffffffff; 1168 else if (code == PLUS && num_bits_set > 16) 1169 remainder = (-remainder) & 0xffffffff; 1170 else 1171 { 1172 can_invert = 0; 1173 can_negate = 0; 1174 } 1175 1176 /* Now try and find a way of doing the job in either two or three 1177 instructions. 1178 We start by looking for the largest block of zeros that are aligned on 1179 a 2-bit boundary, we then fill up the temps, wrapping around to the 1180 top of the word when we drop off the bottom. 1181 In the worst case this code should produce no more than four insns. */ 1182 { 1183 int best_start = 0; 1184 int best_consecutive_zeros = 0; 1185 1186 for (i = 0; i < 32; i += 2) 1187 { 1188 int consecutive_zeros = 0; 1189 1190 if (! (remainder & (3 << i))) 1191 { 1192 while ((i < 32) && ! (remainder & (3 << i))) 1193 { 1194 consecutive_zeros += 2; 1195 i += 2; 1196 } 1197 if (consecutive_zeros > best_consecutive_zeros) 1198 { 1199 best_consecutive_zeros = consecutive_zeros; 1200 best_start = i - consecutive_zeros; 1201 } 1202 i -= 2; 1203 } 1204 } 1205 1206 /* Now start emitting the insns, starting with the one with the highest 1207 bit set: we do this so that the smallest number will be emitted last; 1208 this is more likely to be combinable with addressing insns. */ 1209 i = best_start; 1210 do 1211 { 1212 int end; 1213 1214 if (i <= 0) 1215 i += 32; 1216 if (remainder & (3 << (i - 2))) 1217 { 1218 end = i - 8; 1219 if (end < 0) 1220 end += 32; 1221 temp1 = remainder & ((0x0ff << end) 1222 | ((i < end) ? (0xff >> (32 - end)) : 0)); 1223 remainder &= ~temp1; 1224 1225 if (generate) 1226 { 1227 rtx new_src; 1228 1229 if (code == SET) 1230 emit_insn (gen_rtx_SET (VOIDmode, 1231 new_src = (subtargets 1232 ? gen_reg_rtx (mode) 1233 : target), 1234 GEN_INT (can_invert 1235 ? ~temp1 : temp1))); 1236 else if (code == MINUS) 1237 emit_insn (gen_rtx_SET (VOIDmode, 1238 new_src = (subtargets 1239 ? gen_reg_rtx (mode) 1240 : target), 1241 gen_rtx (code, mode, GEN_INT (temp1), 1242 source))); 1243 else 1244 emit_insn (gen_rtx_SET (VOIDmode, 1245 new_src = (remainder 1246 ? (subtargets 1247 ? gen_reg_rtx (mode) 1248 : target) 1249 : target), 1250 gen_rtx (code, mode, source, 1251 GEN_INT (can_invert ? ~temp1 1252 : (can_negate 1253 ? -temp1 1254 : temp1))))); 1255 source = new_src; 1256 } 1257 1258 if (code == SET) 1259 { 1260 can_invert = 0; 1261 code = PLUS; 1262 } 1263 else if (code == MINUS) 1264 code = PLUS; 1265 1266 insns++; 1267 i -= 6; 1268 } 1269 i -= 2; 1270 } while (remainder); 1271 } 1272 return insns; 1273} 1274 1275/* Canonicalize a comparison so that we are more likely to recognize it. 1276 This can be done for a few constant compares, where we can make the 1277 immediate value easier to load. */ 1278enum rtx_code 1279arm_canonicalize_comparison (code, op1) 1280 enum rtx_code code; 1281 rtx *op1; 1282{ 1283 unsigned HOST_WIDE_INT i = INTVAL (*op1); 1284 1285 switch (code) 1286 { 1287 case EQ: 1288 case NE: 1289 return code; 1290 1291 case GT: 1292 case LE: 1293 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) 1294 - 1) 1295 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1)))) 1296 { 1297 *op1 = GEN_INT (i+1); 1298 return code == GT ? GE : LT; 1299 } 1300 break; 1301 1302 case GE: 1303 case LT: 1304 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) 1305 && (const_ok_for_arm (i-1) || const_ok_for_arm (- (i-1)))) 1306 { 1307 *op1 = GEN_INT (i-1); 1308 return code == GE ? GT : LE; 1309 } 1310 break; 1311 1312 case GTU: 1313 case LEU: 1314 if (i != ~((unsigned HOST_WIDE_INT) 0) 1315 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1)))) 1316 { 1317 *op1 = GEN_INT (i + 1); 1318 return code == GTU ? GEU : LTU; 1319 } 1320 break; 1321 1322 case GEU: 1323 case LTU: 1324 if (i != 0 1325 && (const_ok_for_arm (i - 1) || const_ok_for_arm (- (i - 1)))) 1326 { 1327 *op1 = GEN_INT (i - 1); 1328 return code == GEU ? GTU : LEU; 1329 } 1330 break; 1331 1332 default: 1333 abort (); 1334 } 1335 1336 return code; 1337} 1338 1339/* Decide whether a type should be returned in memory (true) 1340 or in a register (false). This is called by the macro 1341 RETURN_IN_MEMORY. */ 1342int 1343arm_return_in_memory (type) 1344 tree type; 1345{ 1346 if (! AGGREGATE_TYPE_P (type)) 1347 { 1348 /* All simple types are returned in registers. */ 1349 return 0; 1350 } 1351 else if (int_size_in_bytes (type) > 4) 1352 { 1353 /* All structures/unions bigger than one word are returned in memory. */ 1354 return 1; 1355 } 1356 else if (TREE_CODE (type) == RECORD_TYPE) 1357 { 1358 tree field; 1359 1360 /* For a struct the APCS says that we must return in a register if 1361 every addressable element has an offset of zero. For practical 1362 purposes this means that the structure can have at most one non 1363 bit-field element and that this element must be the first one in 1364 the structure. */ 1365 1366 /* Find the first field, ignoring non FIELD_DECL things which will 1367 have been created by C++. */ 1368 for (field = TYPE_FIELDS (type); 1369 field && TREE_CODE (field) != FIELD_DECL; 1370 field = TREE_CHAIN (field)) 1371 continue; 1372 1373 if (field == NULL) 1374 return 0; /* An empty structure. Allowed by an extension to ANSI C. */ 1375 1376 /* Now check the remaining fields, if any. */ 1377 for (field = TREE_CHAIN (field); 1378 field; 1379 field = TREE_CHAIN (field)) 1380 { 1381 if (TREE_CODE (field) != FIELD_DECL) 1382 continue; 1383 1384 if (! DECL_BIT_FIELD_TYPE (field)) 1385 return 1; 1386 } 1387 1388 return 0; 1389 } 1390 else if (TREE_CODE (type) == UNION_TYPE) 1391 { 1392 tree field; 1393 1394 /* Unions can be returned in registers if every element is 1395 integral, or can be returned in an integer register. */ 1396 for (field = TYPE_FIELDS (type); 1397 field; 1398 field = TREE_CHAIN (field)) 1399 { 1400 if (TREE_CODE (field) != FIELD_DECL) 1401 continue; 1402 1403 if (FLOAT_TYPE_P (TREE_TYPE (field))) 1404 return 1; 1405 1406 if (RETURN_IN_MEMORY (TREE_TYPE (field))) 1407 return 1; 1408 } 1409 1410 return 0; 1411 } 1412 1413 /* XXX Not sure what should be done for other aggregates, so put them in 1414 memory. */ 1415 return 1; 1416} 1417 1418int 1419legitimate_pic_operand_p (x) 1420 rtx x; 1421{ 1422 if (CONSTANT_P (x) && flag_pic 1423 && (GET_CODE (x) == SYMBOL_REF 1424 || (GET_CODE (x) == CONST 1425 && GET_CODE (XEXP (x, 0)) == PLUS 1426 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))) 1427 return 0; 1428 1429 return 1; 1430} 1431 1432rtx 1433legitimize_pic_address (orig, mode, reg) 1434 rtx orig; 1435 enum machine_mode mode; 1436 rtx reg; 1437{ 1438 if (GET_CODE (orig) == SYMBOL_REF) 1439 { 1440 rtx pic_ref, address; 1441 rtx insn; 1442 int subregs = 0; 1443 1444 if (reg == 0) 1445 { 1446 if (reload_in_progress || reload_completed) 1447 abort (); 1448 else 1449 reg = gen_reg_rtx (Pmode); 1450 1451 subregs = 1; 1452 } 1453 1454#ifdef AOF_ASSEMBLER 1455 /* The AOF assembler can generate relocations for these directly, and 1456 understands that the PIC register has to be added into the offset. 1457 */ 1458 insn = emit_insn (gen_pic_load_addr_based (reg, orig)); 1459#else 1460 if (subregs) 1461 address = gen_reg_rtx (Pmode); 1462 else 1463 address = reg; 1464 1465 emit_insn (gen_pic_load_addr (address, orig)); 1466 1467 pic_ref = gen_rtx_MEM (Pmode, 1468 gen_rtx_PLUS (Pmode, pic_offset_table_rtx, 1469 address)); 1470 RTX_UNCHANGING_P (pic_ref) = 1; 1471 insn = emit_move_insn (reg, pic_ref); 1472#endif 1473 current_function_uses_pic_offset_table = 1; 1474 /* Put a REG_EQUAL note on this insn, so that it can be optimized 1475 by loop. */ 1476 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, 1477 REG_NOTES (insn)); 1478 return reg; 1479 } 1480 else if (GET_CODE (orig) == CONST) 1481 { 1482 rtx base, offset; 1483 1484 if (GET_CODE (XEXP (orig, 0)) == PLUS 1485 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) 1486 return orig; 1487 1488 if (reg == 0) 1489 { 1490 if (reload_in_progress || reload_completed) 1491 abort (); 1492 else 1493 reg = gen_reg_rtx (Pmode); 1494 } 1495 1496 if (GET_CODE (XEXP (orig, 0)) == PLUS) 1497 { 1498 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); 1499 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, 1500 base == reg ? 0 : reg); 1501 } 1502 else 1503 abort (); 1504 1505 if (GET_CODE (offset) == CONST_INT) 1506 { 1507 /* The base register doesn't really matter, we only want to 1508 test the index for the appropriate mode. */ 1509 GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win); 1510 1511 if (! reload_in_progress && ! reload_completed) 1512 offset = force_reg (Pmode, offset); 1513 else 1514 abort (); 1515 1516 win: 1517 if (GET_CODE (offset) == CONST_INT) 1518 return plus_constant_for_output (base, INTVAL (offset)); 1519 } 1520 1521 if (GET_MODE_SIZE (mode) > 4 1522 && (GET_MODE_CLASS (mode) == MODE_INT 1523 || TARGET_SOFT_FLOAT)) 1524 { 1525 emit_insn (gen_addsi3 (reg, base, offset)); 1526 return reg; 1527 } 1528 1529 return gen_rtx_PLUS (Pmode, base, offset); 1530 } 1531 else if (GET_CODE (orig) == LABEL_REF) 1532 current_function_uses_pic_offset_table = 1; 1533 1534 return orig; 1535} 1536 1537static rtx pic_rtx; 1538 1539int 1540is_pic(x) 1541 rtx x; 1542{ 1543 if (x == pic_rtx) 1544 return 1; 1545 return 0; 1546} 1547 1548void 1549arm_finalize_pic () 1550{ 1551#ifndef AOF_ASSEMBLER 1552 rtx l1, pic_tmp, pic_tmp2, seq; 1553 rtx global_offset_table; 1554 1555 if (current_function_uses_pic_offset_table == 0) 1556 return; 1557 1558 if (! flag_pic) 1559 abort (); 1560 1561 start_sequence (); 1562 l1 = gen_label_rtx (); 1563 1564 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); 1565 /* On the ARM the PC register contains 'dot + 8' at the time of the 1566 addition. */ 1567 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), 8); 1568 if (GOT_PCREL) 1569 pic_tmp2 = gen_rtx_CONST (VOIDmode, 1570 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx)); 1571 else 1572 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table); 1573 1574 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp)); 1575 1576 emit_insn (gen_pic_load_addr (pic_offset_table_rtx, pic_rtx)); 1577 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1)); 1578 1579 seq = gen_sequence (); 1580 end_sequence (); 1581 emit_insn_after (seq, get_insns ()); 1582 1583 /* Need to emit this whether or not we obey regdecls, 1584 since setjmp/longjmp can cause life info to screw up. */ 1585 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); 1586#endif /* AOF_ASSEMBLER */ 1587} 1588 1589#define REG_OR_SUBREG_REG(X) \ 1590 (GET_CODE (X) == REG \ 1591 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG)) 1592 1593#define REG_OR_SUBREG_RTX(X) \ 1594 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X)) 1595 1596#define ARM_FRAME_RTX(X) \ 1597 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 1598 || (X) == arg_pointer_rtx) 1599 1600int 1601arm_rtx_costs (x, code) 1602 rtx x; 1603 enum rtx_code code; 1604{ 1605 enum machine_mode mode = GET_MODE (x); 1606 enum rtx_code subcode; 1607 int extra_cost; 1608 1609 switch (code) 1610 { 1611 case MEM: 1612 /* Memory costs quite a lot for the first word, but subsequent words 1613 load at the equivalent of a single insn each. */ 1614 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) 1615 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0)); 1616 1617 case DIV: 1618 case MOD: 1619 return 100; 1620 1621 case ROTATE: 1622 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG) 1623 return 4; 1624 /* Fall through */ 1625 case ROTATERT: 1626 if (mode != SImode) 1627 return 8; 1628 /* Fall through */ 1629 case ASHIFT: case LSHIFTRT: case ASHIFTRT: 1630 if (mode == DImode) 1631 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8) 1632 + ((GET_CODE (XEXP (x, 0)) == REG 1633 || (GET_CODE (XEXP (x, 0)) == SUBREG 1634 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)) 1635 ? 0 : 8)); 1636 return (1 + ((GET_CODE (XEXP (x, 0)) == REG 1637 || (GET_CODE (XEXP (x, 0)) == SUBREG 1638 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)) 1639 ? 0 : 4) 1640 + ((GET_CODE (XEXP (x, 1)) == REG 1641 || (GET_CODE (XEXP (x, 1)) == SUBREG 1642 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG) 1643 || (GET_CODE (XEXP (x, 1)) == CONST_INT)) 1644 ? 0 : 4)); 1645 1646 case MINUS: 1647 if (mode == DImode) 1648 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8) 1649 + ((REG_OR_SUBREG_REG (XEXP (x, 0)) 1650 || (GET_CODE (XEXP (x, 0)) == CONST_INT 1651 && const_ok_for_arm (INTVAL (XEXP (x, 0))))) 1652 ? 0 : 8)); 1653 1654 if (GET_MODE_CLASS (mode) == MODE_FLOAT) 1655 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1)) 1656 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE 1657 && const_double_rtx_ok_for_fpu (XEXP (x, 1)))) 1658 ? 0 : 8) 1659 + ((REG_OR_SUBREG_REG (XEXP (x, 0)) 1660 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE 1661 && const_double_rtx_ok_for_fpu (XEXP (x, 0)))) 1662 ? 0 : 8)); 1663 1664 if (((GET_CODE (XEXP (x, 0)) == CONST_INT 1665 && const_ok_for_arm (INTVAL (XEXP (x, 0))) 1666 && REG_OR_SUBREG_REG (XEXP (x, 1)))) 1667 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT 1668 || subcode == ASHIFTRT || subcode == LSHIFTRT 1669 || subcode == ROTATE || subcode == ROTATERT 1670 || (subcode == MULT 1671 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT 1672 && ((INTVAL (XEXP (XEXP (x, 1), 1)) & 1673 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0))) 1674 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0)) 1675 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1)) 1676 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT) 1677 && REG_OR_SUBREG_REG (XEXP (x, 0)))) 1678 return 1; 1679 /* Fall through */ 1680 1681 case PLUS: 1682 if (GET_MODE_CLASS (mode) == MODE_FLOAT) 1683 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8) 1684 + ((REG_OR_SUBREG_REG (XEXP (x, 1)) 1685 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE 1686 && const_double_rtx_ok_for_fpu (XEXP (x, 1)))) 1687 ? 0 : 8)); 1688 1689 /* Fall through */ 1690 case AND: case XOR: case IOR: 1691 extra_cost = 0; 1692 1693 /* Normally the frame registers will be spilt into reg+const during 1694 reload, so it is a bad idea to combine them with other instructions, 1695 since then they might not be moved outside of loops. As a compromise 1696 we allow integration with ops that have a constant as their second 1697 operand. */ 1698 if ((REG_OR_SUBREG_REG (XEXP (x, 0)) 1699 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))) 1700 && GET_CODE (XEXP (x, 1)) != CONST_INT) 1701 || (REG_OR_SUBREG_REG (XEXP (x, 0)) 1702 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))))) 1703 extra_cost = 4; 1704 1705 if (mode == DImode) 1706 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8) 1707 + ((REG_OR_SUBREG_REG (XEXP (x, 1)) 1708 || (GET_CODE (XEXP (x, 1)) == CONST_INT 1709 && const_ok_for_op (INTVAL (XEXP (x, 1)), code))) 1710 ? 0 : 8)); 1711 1712 if (REG_OR_SUBREG_REG (XEXP (x, 0))) 1713 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost) 1714 + ((REG_OR_SUBREG_REG (XEXP (x, 1)) 1715 || (GET_CODE (XEXP (x, 1)) == CONST_INT 1716 && const_ok_for_op (INTVAL (XEXP (x, 1)), code))) 1717 ? 0 : 4)); 1718 1719 else if (REG_OR_SUBREG_REG (XEXP (x, 1))) 1720 return (1 + extra_cost 1721 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT 1722 || subcode == LSHIFTRT || subcode == ASHIFTRT 1723 || subcode == ROTATE || subcode == ROTATERT 1724 || (subcode == MULT 1725 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 1726 && ((INTVAL (XEXP (XEXP (x, 0), 1)) & 1727 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0))) 1728 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0))) 1729 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1))) 1730 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)) 1731 ? 0 : 4)); 1732 1733 return 8; 1734 1735 case MULT: 1736 /* There is no point basing this on the tuning, since it is always the 1737 fast variant if it exists at all */ 1738 if (arm_fast_multiply && mode == DImode 1739 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) 1740 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND 1741 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) 1742 return 8; 1743 1744 if (GET_MODE_CLASS (mode) == MODE_FLOAT 1745 || mode == DImode) 1746 return 30; 1747 1748 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 1749 { 1750 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) 1751 & (unsigned HOST_WIDE_INT) 0xffffffff); 1752 int add_cost = const_ok_for_arm (i) ? 4 : 8; 1753 int j; 1754 /* Tune as appropriate */ 1755 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2); 1756 1757 for (j = 0; i && j < 32; j += booth_unit_size) 1758 { 1759 i >>= booth_unit_size; 1760 add_cost += 2; 1761 } 1762 1763 return add_cost; 1764 } 1765 1766 return (((tune_flags & FL_FAST_MULT) ? 8 : 30) 1767 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4) 1768 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4)); 1769 1770 case TRUNCATE: 1771 if (arm_fast_multiply && mode == SImode 1772 && GET_CODE (XEXP (x, 0)) == LSHIFTRT 1773 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT 1774 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) 1775 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1))) 1776 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND 1777 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND)) 1778 return 8; 1779 return 99; 1780 1781 case NEG: 1782 if (GET_MODE_CLASS (mode) == MODE_FLOAT) 1783 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6); 1784 /* Fall through */ 1785 case NOT: 1786 if (mode == DImode) 1787 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4); 1788 1789 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4); 1790 1791 case IF_THEN_ELSE: 1792 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) 1793 return 14; 1794 return 2; 1795 1796 case COMPARE: 1797 return 1; 1798 1799 case ABS: 1800 return 4 + (mode == DImode ? 4 : 0); 1801 1802 case SIGN_EXTEND: 1803 if (GET_MODE (XEXP (x, 0)) == QImode) 1804 return (4 + (mode == DImode ? 4 : 0) 1805 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); 1806 /* Fall through */ 1807 case ZERO_EXTEND: 1808 switch (GET_MODE (XEXP (x, 0))) 1809 { 1810 case QImode: 1811 return (1 + (mode == DImode ? 4 : 0) 1812 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); 1813 1814 case HImode: 1815 return (4 + (mode == DImode ? 4 : 0) 1816 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); 1817 1818 case SImode: 1819 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); 1820 1821 default: 1822 break; 1823 } 1824 abort (); 1825 1826 default: 1827 return 99; 1828 } 1829} 1830 1831int 1832arm_adjust_cost (insn, link, dep, cost) 1833 rtx insn; 1834 rtx link; 1835 rtx dep; 1836 int cost; 1837{ 1838 rtx i_pat, d_pat; 1839 1840 /* XXX This is not strictly true for the FPA. */ 1841 if (REG_NOTE_KIND(link) == REG_DEP_ANTI 1842 || REG_NOTE_KIND(link) == REG_DEP_OUTPUT) 1843 return 0; 1844 1845 if ((i_pat = single_set (insn)) != NULL 1846 && GET_CODE (SET_SRC (i_pat)) == MEM 1847 && (d_pat = single_set (dep)) != NULL 1848 && GET_CODE (SET_DEST (d_pat)) == MEM) 1849 { 1850 /* This is a load after a store, there is no conflict if the load reads 1851 from a cached area. Assume that loads from the stack, and from the 1852 constant pool are cached, and that others will miss. This is a 1853 hack. */ 1854 1855/* debug_rtx (insn); 1856 debug_rtx (dep); 1857 debug_rtx (link); 1858 fprintf (stderr, "costs %d\n", cost); */ 1859 1860 if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat), 0)) 1861 || reg_mentioned_p (stack_pointer_rtx, XEXP (SET_SRC (i_pat), 0)) 1862 || reg_mentioned_p (frame_pointer_rtx, XEXP (SET_SRC (i_pat), 0)) 1863 || reg_mentioned_p (hard_frame_pointer_rtx, 1864 XEXP (SET_SRC (i_pat), 0))) 1865 { 1866/* fprintf (stderr, "***** Now 1\n"); */ 1867 return 1; 1868 } 1869 } 1870 1871 return cost; 1872} 1873 1874/* This code has been fixed for cross compilation. */ 1875 1876static int fpa_consts_inited = 0; 1877 1878char *strings_fpa[8] = { 1879 "0", "1", "2", "3", 1880 "4", "5", "0.5", "10" 1881}; 1882 1883static REAL_VALUE_TYPE values_fpa[8]; 1884 1885static void 1886init_fpa_table () 1887{ 1888 int i; 1889 REAL_VALUE_TYPE r; 1890 1891 for (i = 0; i < 8; i++) 1892 { 1893 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode); 1894 values_fpa[i] = r; 1895 } 1896 1897 fpa_consts_inited = 1; 1898} 1899 1900/* Return TRUE if rtx X is a valid immediate FPU constant. */ 1901 1902int 1903const_double_rtx_ok_for_fpu (x) 1904 rtx x; 1905{ 1906 REAL_VALUE_TYPE r; 1907 int i; 1908 1909 if (!fpa_consts_inited) 1910 init_fpa_table (); 1911 1912 REAL_VALUE_FROM_CONST_DOUBLE (r, x); 1913 if (REAL_VALUE_MINUS_ZERO (r)) 1914 return 0; 1915 1916 for (i = 0; i < 8; i++) 1917 if (REAL_VALUES_EQUAL (r, values_fpa[i])) 1918 return 1; 1919 1920 return 0; 1921} 1922 1923/* Return TRUE if rtx X is a valid immediate FPU constant. */ 1924 1925int 1926neg_const_double_rtx_ok_for_fpu (x) 1927 rtx x; 1928{ 1929 REAL_VALUE_TYPE r; 1930 int i; 1931 1932 if (!fpa_consts_inited) 1933 init_fpa_table (); 1934 1935 REAL_VALUE_FROM_CONST_DOUBLE (r, x); 1936 r = REAL_VALUE_NEGATE (r); 1937 if (REAL_VALUE_MINUS_ZERO (r)) 1938 return 0; 1939 1940 for (i = 0; i < 8; i++) 1941 if (REAL_VALUES_EQUAL (r, values_fpa[i])) 1942 return 1; 1943 1944 return 0; 1945} 1946 1947/* Predicates for `match_operand' and `match_operator'. */ 1948 1949/* s_register_operand is the same as register_operand, but it doesn't accept 1950 (SUBREG (MEM)...). 1951 1952 This function exists because at the time it was put in it led to better 1953 code. SUBREG(MEM) always needs a reload in the places where 1954 s_register_operand is used, and this seemed to lead to excessive 1955 reloading. */ 1956 1957int 1958s_register_operand (op, mode) 1959 register rtx op; 1960 enum machine_mode mode; 1961{ 1962 if (GET_MODE (op) != mode && mode != VOIDmode) 1963 return 0; 1964 1965 if (GET_CODE (op) == SUBREG) 1966 op = SUBREG_REG (op); 1967 1968 /* We don't consider registers whose class is NO_REGS 1969 to be a register operand. */ 1970 return (GET_CODE (op) == REG 1971 && (REGNO (op) >= FIRST_PSEUDO_REGISTER 1972 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); 1973} 1974 1975/* Only accept reg, subreg(reg), const_int. */ 1976 1977int 1978reg_or_int_operand (op, mode) 1979 register rtx op; 1980 enum machine_mode mode; 1981{ 1982 if (GET_CODE (op) == CONST_INT) 1983 return 1; 1984 1985 if (GET_MODE (op) != mode && mode != VOIDmode) 1986 return 0; 1987 1988 if (GET_CODE (op) == SUBREG) 1989 op = SUBREG_REG (op); 1990 1991 /* We don't consider registers whose class is NO_REGS 1992 to be a register operand. */ 1993 return (GET_CODE (op) == REG 1994 && (REGNO (op) >= FIRST_PSEUDO_REGISTER 1995 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); 1996} 1997 1998/* Return 1 if OP is an item in memory, given that we are in reload. */ 1999 2000int 2001reload_memory_operand (op, mode) 2002 rtx op; 2003 enum machine_mode mode ATTRIBUTE_UNUSED; 2004{ 2005 int regno = true_regnum (op); 2006 2007 return (! CONSTANT_P (op) 2008 && (regno == -1 2009 || (GET_CODE (op) == REG 2010 && REGNO (op) >= FIRST_PSEUDO_REGISTER))); 2011} 2012 2013/* Return 1 if OP is a valid memory address, but not valid for a signed byte 2014 memory access (architecture V4) */ 2015int 2016bad_signed_byte_operand (op, mode) 2017 rtx op; 2018 enum machine_mode mode; 2019{ 2020 if (! memory_operand (op, mode) || GET_CODE (op) != MEM) 2021 return 0; 2022 2023 op = XEXP (op, 0); 2024 2025 /* A sum of anything more complex than reg + reg or reg + const is bad */ 2026 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS) 2027 && (! s_register_operand (XEXP (op, 0), VOIDmode) 2028 || (! s_register_operand (XEXP (op, 1), VOIDmode) 2029 && GET_CODE (XEXP (op, 1)) != CONST_INT))) 2030 return 1; 2031 2032 /* Big constants are also bad */ 2033 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT 2034 && (INTVAL (XEXP (op, 1)) > 0xff 2035 || -INTVAL (XEXP (op, 1)) > 0xff)) 2036 return 1; 2037 2038 /* Everything else is good, or can will automatically be made so. */ 2039 return 0; 2040} 2041 2042/* Return TRUE for valid operands for the rhs of an ARM instruction. */ 2043 2044int 2045arm_rhs_operand (op, mode) 2046 rtx op; 2047 enum machine_mode mode; 2048{ 2049 return (s_register_operand (op, mode) 2050 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))); 2051} 2052 2053/* Return TRUE for valid operands for the rhs of an ARM instruction, or a load. 2054 */ 2055 2056int 2057arm_rhsm_operand (op, mode) 2058 rtx op; 2059 enum machine_mode mode; 2060{ 2061 return (s_register_operand (op, mode) 2062 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))) 2063 || memory_operand (op, mode)); 2064} 2065 2066/* Return TRUE for valid operands for the rhs of an ARM instruction, or if a 2067 constant that is valid when negated. */ 2068 2069int 2070arm_add_operand (op, mode) 2071 rtx op; 2072 enum machine_mode mode; 2073{ 2074 return (s_register_operand (op, mode) 2075 || (GET_CODE (op) == CONST_INT 2076 && (const_ok_for_arm (INTVAL (op)) 2077 || const_ok_for_arm (-INTVAL (op))))); 2078} 2079 2080int 2081arm_not_operand (op, mode) 2082 rtx op; 2083 enum machine_mode mode; 2084{ 2085 return (s_register_operand (op, mode) 2086 || (GET_CODE (op) == CONST_INT 2087 && (const_ok_for_arm (INTVAL (op)) 2088 || const_ok_for_arm (~INTVAL (op))))); 2089} 2090 2091/* Return TRUE if the operand is a memory reference which contains an 2092 offsettable address. */ 2093int 2094offsettable_memory_operand (op, mode) 2095 register rtx op; 2096 enum machine_mode mode; 2097{ 2098 if (mode == VOIDmode) 2099 mode = GET_MODE (op); 2100 2101 return (mode == GET_MODE (op) 2102 && GET_CODE (op) == MEM 2103 && offsettable_address_p (reload_completed | reload_in_progress, 2104 mode, XEXP (op, 0))); 2105} 2106 2107/* Return TRUE if the operand is a memory reference which is, or can be 2108 made word aligned by adjusting the offset. */ 2109int 2110alignable_memory_operand (op, mode) 2111 register rtx op; 2112 enum machine_mode mode; 2113{ 2114 rtx reg; 2115 2116 if (mode == VOIDmode) 2117 mode = GET_MODE (op); 2118 2119 if (mode != GET_MODE (op) || GET_CODE (op) != MEM) 2120 return 0; 2121 2122 op = XEXP (op, 0); 2123 2124 return ((GET_CODE (reg = op) == REG 2125 || (GET_CODE (op) == SUBREG 2126 && GET_CODE (reg = SUBREG_REG (op)) == REG) 2127 || (GET_CODE (op) == PLUS 2128 && GET_CODE (XEXP (op, 1)) == CONST_INT 2129 && (GET_CODE (reg = XEXP (op, 0)) == REG 2130 || (GET_CODE (XEXP (op, 0)) == SUBREG 2131 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG)))) 2132 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 4); 2133} 2134 2135/* Similar to s_register_operand, but does not allow hard integer 2136 registers. */ 2137int 2138f_register_operand (op, mode) 2139 register rtx op; 2140 enum machine_mode mode; 2141{ 2142 if (GET_MODE (op) != mode && mode != VOIDmode) 2143 return 0; 2144 2145 if (GET_CODE (op) == SUBREG) 2146 op = SUBREG_REG (op); 2147 2148 /* We don't consider registers whose class is NO_REGS 2149 to be a register operand. */ 2150 return (GET_CODE (op) == REG 2151 && (REGNO (op) >= FIRST_PSEUDO_REGISTER 2152 || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS)); 2153} 2154 2155/* Return TRUE for valid operands for the rhs of an FPU instruction. */ 2156 2157int 2158fpu_rhs_operand (op, mode) 2159 rtx op; 2160 enum machine_mode mode; 2161{ 2162 if (s_register_operand (op, mode)) 2163 return TRUE; 2164 else if (GET_CODE (op) == CONST_DOUBLE) 2165 return (const_double_rtx_ok_for_fpu (op)); 2166 2167 return FALSE; 2168} 2169 2170int 2171fpu_add_operand (op, mode) 2172 rtx op; 2173 enum machine_mode mode; 2174{ 2175 if (s_register_operand (op, mode)) 2176 return TRUE; 2177 else if (GET_CODE (op) == CONST_DOUBLE) 2178 return (const_double_rtx_ok_for_fpu (op) 2179 || neg_const_double_rtx_ok_for_fpu (op)); 2180 2181 return FALSE; 2182} 2183 2184/* Return nonzero if OP is a constant power of two. */ 2185 2186int 2187power_of_two_operand (op, mode) 2188 rtx op; 2189 enum machine_mode mode ATTRIBUTE_UNUSED; 2190{ 2191 if (GET_CODE (op) == CONST_INT) 2192 { 2193 HOST_WIDE_INT value = INTVAL(op); 2194 return value != 0 && (value & (value - 1)) == 0; 2195 } 2196 return FALSE; 2197} 2198 2199/* Return TRUE for a valid operand of a DImode operation. 2200 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address). 2201 Note that this disallows MEM(REG+REG), but allows 2202 MEM(PRE/POST_INC/DEC(REG)). */ 2203 2204int 2205di_operand (op, mode) 2206 rtx op; 2207 enum machine_mode mode; 2208{ 2209 if (s_register_operand (op, mode)) 2210 return TRUE; 2211 2212 if (GET_CODE (op) == SUBREG) 2213 op = SUBREG_REG (op); 2214 2215 switch (GET_CODE (op)) 2216 { 2217 case CONST_DOUBLE: 2218 case CONST_INT: 2219 return TRUE; 2220 2221 case MEM: 2222 return memory_address_p (DImode, XEXP (op, 0)); 2223 2224 default: 2225 return FALSE; 2226 } 2227} 2228 2229/* Return TRUE for a valid operand of a DFmode operation when -msoft-float. 2230 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address). 2231 Note that this disallows MEM(REG+REG), but allows 2232 MEM(PRE/POST_INC/DEC(REG)). */ 2233 2234int 2235soft_df_operand (op, mode) 2236 rtx op; 2237 enum machine_mode mode; 2238{ 2239 if (s_register_operand (op, mode)) 2240 return TRUE; 2241 2242 if (GET_CODE (op) == SUBREG) 2243 op = SUBREG_REG (op); 2244 2245 switch (GET_CODE (op)) 2246 { 2247 case CONST_DOUBLE: 2248 return TRUE; 2249 2250 case MEM: 2251 return memory_address_p (DFmode, XEXP (op, 0)); 2252 2253 default: 2254 return FALSE; 2255 } 2256} 2257 2258/* Return TRUE for valid index operands. */ 2259 2260int 2261index_operand (op, mode) 2262 rtx op; 2263 enum machine_mode mode; 2264{ 2265 return (s_register_operand(op, mode) 2266 || (immediate_operand (op, mode) 2267 && INTVAL (op) < 4096 && INTVAL (op) > -4096)); 2268} 2269 2270/* Return TRUE for valid shifts by a constant. This also accepts any 2271 power of two on the (somewhat overly relaxed) assumption that the 2272 shift operator in this case was a mult. */ 2273 2274int 2275const_shift_operand (op, mode) 2276 rtx op; 2277 enum machine_mode mode; 2278{ 2279 return (power_of_two_operand (op, mode) 2280 || (immediate_operand (op, mode) 2281 && (INTVAL (op) < 32 && INTVAL (op) > 0))); 2282} 2283 2284/* Return TRUE for arithmetic operators which can be combined with a multiply 2285 (shift). */ 2286 2287int 2288shiftable_operator (x, mode) 2289 rtx x; 2290 enum machine_mode mode; 2291{ 2292 if (GET_MODE (x) != mode) 2293 return FALSE; 2294 else 2295 { 2296 enum rtx_code code = GET_CODE (x); 2297 2298 return (code == PLUS || code == MINUS 2299 || code == IOR || code == XOR || code == AND); 2300 } 2301} 2302 2303/* Return TRUE for shift operators. */ 2304 2305int 2306shift_operator (x, mode) 2307 rtx x; 2308 enum machine_mode mode; 2309{ 2310 if (GET_MODE (x) != mode) 2311 return FALSE; 2312 else 2313 { 2314 enum rtx_code code = GET_CODE (x); 2315 2316 if (code == MULT) 2317 return power_of_two_operand (XEXP (x, 1), mode); 2318 2319 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT 2320 || code == ROTATERT); 2321 } 2322} 2323 2324int equality_operator (x, mode) 2325 rtx x; 2326 enum machine_mode mode ATTRIBUTE_UNUSED; 2327{ 2328 return GET_CODE (x) == EQ || GET_CODE (x) == NE; 2329} 2330 2331/* Return TRUE for SMIN SMAX UMIN UMAX operators. */ 2332 2333int 2334minmax_operator (x, mode) 2335 rtx x; 2336 enum machine_mode mode; 2337{ 2338 enum rtx_code code = GET_CODE (x); 2339 2340 if (GET_MODE (x) != mode) 2341 return FALSE; 2342 2343 return code == SMIN || code == SMAX || code == UMIN || code == UMAX; 2344} 2345 2346/* return TRUE if x is EQ or NE */ 2347 2348/* Return TRUE if this is the condition code register, if we aren't given 2349 a mode, accept any class CCmode register */ 2350 2351int 2352cc_register (x, mode) 2353 rtx x; 2354 enum machine_mode mode; 2355{ 2356 if (mode == VOIDmode) 2357 { 2358 mode = GET_MODE (x); 2359 if (GET_MODE_CLASS (mode) != MODE_CC) 2360 return FALSE; 2361 } 2362 2363 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24) 2364 return TRUE; 2365 2366 return FALSE; 2367} 2368 2369/* Return TRUE if this is the condition code register, if we aren't given 2370 a mode, accept any class CCmode register which indicates a dominance 2371 expression. */ 2372 2373int 2374dominant_cc_register (x, mode) 2375 rtx x; 2376 enum machine_mode mode; 2377{ 2378 if (mode == VOIDmode) 2379 { 2380 mode = GET_MODE (x); 2381 if (GET_MODE_CLASS (mode) != MODE_CC) 2382 return FALSE; 2383 } 2384 2385 if (mode != CC_DNEmode && mode != CC_DEQmode 2386 && mode != CC_DLEmode && mode != CC_DLTmode 2387 && mode != CC_DGEmode && mode != CC_DGTmode 2388 && mode != CC_DLEUmode && mode != CC_DLTUmode 2389 && mode != CC_DGEUmode && mode != CC_DGTUmode) 2390 return FALSE; 2391 2392 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24) 2393 return TRUE; 2394 2395 return FALSE; 2396} 2397 2398/* Return TRUE if X references a SYMBOL_REF. */ 2399int 2400symbol_mentioned_p (x) 2401 rtx x; 2402{ 2403 register char *fmt; 2404 register int i; 2405 2406 if (GET_CODE (x) == SYMBOL_REF) 2407 return 1; 2408 2409 fmt = GET_RTX_FORMAT (GET_CODE (x)); 2410 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) 2411 { 2412 if (fmt[i] == 'E') 2413 { 2414 register int j; 2415 2416 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 2417 if (symbol_mentioned_p (XVECEXP (x, i, j))) 2418 return 1; 2419 } 2420 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i))) 2421 return 1; 2422 } 2423 2424 return 0; 2425} 2426 2427/* Return TRUE if X references a LABEL_REF. */ 2428int 2429label_mentioned_p (x) 2430 rtx x; 2431{ 2432 register char *fmt; 2433 register int i; 2434 2435 if (GET_CODE (x) == LABEL_REF) 2436 return 1; 2437 2438 fmt = GET_RTX_FORMAT (GET_CODE (x)); 2439 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) 2440 { 2441 if (fmt[i] == 'E') 2442 { 2443 register int j; 2444 2445 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 2446 if (label_mentioned_p (XVECEXP (x, i, j))) 2447 return 1; 2448 } 2449 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i))) 2450 return 1; 2451 } 2452 2453 return 0; 2454} 2455 2456enum rtx_code 2457minmax_code (x) 2458 rtx x; 2459{ 2460 enum rtx_code code = GET_CODE (x); 2461 2462 if (code == SMAX) 2463 return GE; 2464 else if (code == SMIN) 2465 return LE; 2466 else if (code == UMIN) 2467 return LEU; 2468 else if (code == UMAX) 2469 return GEU; 2470 2471 abort (); 2472} 2473 2474/* Return 1 if memory locations are adjacent */ 2475 2476int 2477adjacent_mem_locations (a, b) 2478 rtx a, b; 2479{ 2480 int val0 = 0, val1 = 0; 2481 int reg0, reg1; 2482 2483 if ((GET_CODE (XEXP (a, 0)) == REG 2484 || (GET_CODE (XEXP (a, 0)) == PLUS 2485 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT)) 2486 && (GET_CODE (XEXP (b, 0)) == REG 2487 || (GET_CODE (XEXP (b, 0)) == PLUS 2488 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT))) 2489 { 2490 if (GET_CODE (XEXP (a, 0)) == PLUS) 2491 { 2492 reg0 = REGNO (XEXP (XEXP (a, 0), 0)); 2493 val0 = INTVAL (XEXP (XEXP (a, 0), 1)); 2494 } 2495 else 2496 reg0 = REGNO (XEXP (a, 0)); 2497 if (GET_CODE (XEXP (b, 0)) == PLUS) 2498 { 2499 reg1 = REGNO (XEXP (XEXP (b, 0), 0)); 2500 val1 = INTVAL (XEXP (XEXP (b, 0), 1)); 2501 } 2502 else 2503 reg1 = REGNO (XEXP (b, 0)); 2504 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4); 2505 } 2506 return 0; 2507} 2508 2509/* Return 1 if OP is a load multiple operation. It is known to be 2510 parallel and the first section will be tested. */ 2511 2512int 2513load_multiple_operation (op, mode) 2514 rtx op; 2515 enum machine_mode mode ATTRIBUTE_UNUSED; 2516{ 2517 HOST_WIDE_INT count = XVECLEN (op, 0); 2518 int dest_regno; 2519 rtx src_addr; 2520 HOST_WIDE_INT i = 1, base = 0; 2521 rtx elt; 2522 2523 if (count <= 1 2524 || GET_CODE (XVECEXP (op, 0, 0)) != SET) 2525 return 0; 2526 2527 /* Check to see if this might be a write-back */ 2528 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS) 2529 { 2530 i++; 2531 base = 1; 2532 2533 /* Now check it more carefully */ 2534 if (GET_CODE (SET_DEST (elt)) != REG 2535 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG 2536 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt)) 2537 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT 2538 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4 2539 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER 2540 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG 2541 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0)) 2542 != REGNO (SET_DEST (elt))) 2543 return 0; 2544 2545 count--; 2546 } 2547 2548 /* Perform a quick check so we don't blow up below. */ 2549 if (count <= i 2550 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET 2551 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG 2552 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM) 2553 return 0; 2554 2555 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1))); 2556 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0); 2557 2558 for (; i < count; i++) 2559 { 2560 elt = XVECEXP (op, 0, i); 2561 2562 if (GET_CODE (elt) != SET 2563 || GET_CODE (SET_DEST (elt)) != REG 2564 || GET_MODE (SET_DEST (elt)) != SImode 2565 || REGNO (SET_DEST (elt)) != dest_regno + i - base 2566 || GET_CODE (SET_SRC (elt)) != MEM 2567 || GET_MODE (SET_SRC (elt)) != SImode 2568 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS 2569 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) 2570 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT 2571 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4) 2572 return 0; 2573 } 2574 2575 return 1; 2576} 2577 2578/* Return 1 if OP is a store multiple operation. It is known to be 2579 parallel and the first section will be tested. */ 2580 2581int 2582store_multiple_operation (op, mode) 2583 rtx op; 2584 enum machine_mode mode ATTRIBUTE_UNUSED; 2585{ 2586 HOST_WIDE_INT count = XVECLEN (op, 0); 2587 int src_regno; 2588 rtx dest_addr; 2589 HOST_WIDE_INT i = 1, base = 0; 2590 rtx elt; 2591 2592 if (count <= 1 2593 || GET_CODE (XVECEXP (op, 0, 0)) != SET) 2594 return 0; 2595 2596 /* Check to see if this might be a write-back */ 2597 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS) 2598 { 2599 i++; 2600 base = 1; 2601 2602 /* Now check it more carefully */ 2603 if (GET_CODE (SET_DEST (elt)) != REG 2604 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG 2605 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt)) 2606 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT 2607 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4 2608 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER 2609 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG 2610 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0)) 2611 != REGNO (SET_DEST (elt))) 2612 return 0; 2613 2614 count--; 2615 } 2616 2617 /* Perform a quick check so we don't blow up below. */ 2618 if (count <= i 2619 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET 2620 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM 2621 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG) 2622 return 0; 2623 2624 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1))); 2625 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0); 2626 2627 for (; i < count; i++) 2628 { 2629 elt = XVECEXP (op, 0, i); 2630 2631 if (GET_CODE (elt) != SET 2632 || GET_CODE (SET_SRC (elt)) != REG 2633 || GET_MODE (SET_SRC (elt)) != SImode 2634 || REGNO (SET_SRC (elt)) != src_regno + i - base 2635 || GET_CODE (SET_DEST (elt)) != MEM 2636 || GET_MODE (SET_DEST (elt)) != SImode 2637 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS 2638 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) 2639 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT 2640 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4) 2641 return 0; 2642 } 2643 2644 return 1; 2645} 2646 2647int 2648load_multiple_sequence (operands, nops, regs, base, load_offset) 2649 rtx *operands; 2650 int nops; 2651 int *regs; 2652 int *base; 2653 HOST_WIDE_INT *load_offset; 2654{ 2655 int unsorted_regs[4]; 2656 HOST_WIDE_INT unsorted_offsets[4]; 2657 int order[4]; 2658 int base_reg = -1; 2659 int i; 2660 2661 /* Can only handle 2, 3, or 4 insns at present, though could be easily 2662 extended if required. */ 2663 if (nops < 2 || nops > 4) 2664 abort (); 2665 2666 /* Loop over the operands and check that the memory references are 2667 suitable (ie immediate offsets from the same base register). At 2668 the same time, extract the target register, and the memory 2669 offsets. */ 2670 for (i = 0; i < nops; i++) 2671 { 2672 rtx reg; 2673 rtx offset; 2674 2675 /* Convert a subreg of a mem into the mem itself. */ 2676 if (GET_CODE (operands[nops + i]) == SUBREG) 2677 operands[nops + i] = alter_subreg(operands[nops + i]); 2678 2679 if (GET_CODE (operands[nops + i]) != MEM) 2680 abort (); 2681 2682 /* Don't reorder volatile memory references; it doesn't seem worth 2683 looking for the case where the order is ok anyway. */ 2684 if (MEM_VOLATILE_P (operands[nops + i])) 2685 return 0; 2686 2687 offset = const0_rtx; 2688 2689 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG 2690 || (GET_CODE (reg) == SUBREG 2691 && GET_CODE (reg = SUBREG_REG (reg)) == REG)) 2692 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS 2693 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) 2694 == REG) 2695 || (GET_CODE (reg) == SUBREG 2696 && GET_CODE (reg = SUBREG_REG (reg)) == REG)) 2697 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) 2698 == CONST_INT))) 2699 { 2700 if (i == 0) 2701 { 2702 base_reg = REGNO(reg); 2703 unsorted_regs[0] = (GET_CODE (operands[i]) == REG 2704 ? REGNO (operands[i]) 2705 : REGNO (SUBREG_REG (operands[i]))); 2706 order[0] = 0; 2707 } 2708 else 2709 { 2710 if (base_reg != REGNO (reg)) 2711 /* Not addressed from the same base register. */ 2712 return 0; 2713 2714 unsorted_regs[i] = (GET_CODE (operands[i]) == REG 2715 ? REGNO (operands[i]) 2716 : REGNO (SUBREG_REG (operands[i]))); 2717 if (unsorted_regs[i] < unsorted_regs[order[0]]) 2718 order[0] = i; 2719 } 2720 2721 /* If it isn't an integer register, or if it overwrites the 2722 base register but isn't the last insn in the list, then 2723 we can't do this. */ 2724 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14 2725 || (i != nops - 1 && unsorted_regs[i] == base_reg)) 2726 return 0; 2727 2728 unsorted_offsets[i] = INTVAL (offset); 2729 } 2730 else 2731 /* Not a suitable memory address. */ 2732 return 0; 2733 } 2734 2735 /* All the useful information has now been extracted from the 2736 operands into unsorted_regs and unsorted_offsets; additionally, 2737 order[0] has been set to the lowest numbered register in the 2738 list. Sort the registers into order, and check that the memory 2739 offsets are ascending and adjacent. */ 2740 2741 for (i = 1; i < nops; i++) 2742 { 2743 int j; 2744 2745 order[i] = order[i - 1]; 2746 for (j = 0; j < nops; j++) 2747 if (unsorted_regs[j] > unsorted_regs[order[i - 1]] 2748 && (order[i] == order[i - 1] 2749 || unsorted_regs[j] < unsorted_regs[order[i]])) 2750 order[i] = j; 2751 2752 /* Have we found a suitable register? if not, one must be used more 2753 than once. */ 2754 if (order[i] == order[i - 1]) 2755 return 0; 2756 2757 /* Is the memory address adjacent and ascending? */ 2758 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) 2759 return 0; 2760 } 2761 2762 if (base) 2763 { 2764 *base = base_reg; 2765 2766 for (i = 0; i < nops; i++) 2767 regs[i] = unsorted_regs[order[i]]; 2768 2769 *load_offset = unsorted_offsets[order[0]]; 2770 } 2771 2772 if (unsorted_offsets[order[0]] == 0) 2773 return 1; /* ldmia */ 2774 2775 if (unsorted_offsets[order[0]] == 4) 2776 return 2; /* ldmib */ 2777 2778 if (unsorted_offsets[order[nops - 1]] == 0) 2779 return 3; /* ldmda */ 2780 2781 if (unsorted_offsets[order[nops - 1]] == -4) 2782 return 4; /* ldmdb */ 2783 2784 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm if 2785 the offset isn't small enough. The reason 2 ldrs are faster is because 2786 these ARMs are able to do more than one cache access in a single cycle. 2787 The ARM9 and StrongARM have Harvard caches, whilst the ARM8 has a double 2788 bandwidth cache. This means that these cores can do both an instruction 2789 fetch and a data fetch in a single cycle, so the trick of calculating the 2790 address into a scratch register (one of the result regs) and then doing a 2791 load multiple actually becomes slower (and no smaller in code size). That 2792 is the transformation 2793 2794 ldr rd1, [rbase + offset] 2795 ldr rd2, [rbase + offset + 4] 2796 2797 to 2798 2799 add rd1, rbase, offset 2800 ldmia rd1, {rd1, rd2} 2801 2802 produces worse code -- '3 cycles + any stalls on rd2' instead of '2 cycles 2803 + any stalls on rd2'. On ARMs with only one cache access per cycle, the 2804 first sequence could never complete in less than 6 cycles, whereas the ldm 2805 sequence would only take 5 and would make better use of sequential accesses 2806 if not hitting the cache. 2807 2808 We cheat here and test 'arm_ld_sched' which we currently know to only be 2809 true for the ARM8, ARM9 and StrongARM. If this ever changes, then the test 2810 below needs to be reworked. */ 2811 if (nops == 2 && arm_ld_sched) 2812 return 0; 2813 2814 /* Can't do it without setting up the offset, only do this if it takes 2815 no more than one insn. */ 2816 return (const_ok_for_arm (unsorted_offsets[order[0]]) 2817 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0; 2818} 2819 2820char * 2821emit_ldm_seq (operands, nops) 2822 rtx *operands; 2823 int nops; 2824{ 2825 int regs[4]; 2826 int base_reg; 2827 HOST_WIDE_INT offset; 2828 char buf[100]; 2829 int i; 2830 2831 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset)) 2832 { 2833 case 1: 2834 strcpy (buf, "ldm%?ia\t"); 2835 break; 2836 2837 case 2: 2838 strcpy (buf, "ldm%?ib\t"); 2839 break; 2840 2841 case 3: 2842 strcpy (buf, "ldm%?da\t"); 2843 break; 2844 2845 case 4: 2846 strcpy (buf, "ldm%?db\t"); 2847 break; 2848 2849 case 5: 2850 if (offset >= 0) 2851 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, 2852 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], 2853 (long) offset); 2854 else 2855 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, 2856 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], 2857 (long) -offset); 2858 output_asm_insn (buf, operands); 2859 base_reg = regs[0]; 2860 strcpy (buf, "ldm%?ia\t"); 2861 break; 2862 2863 default: 2864 abort (); 2865 } 2866 2867 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, 2868 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); 2869 2870 for (i = 1; i < nops; i++) 2871 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, 2872 reg_names[regs[i]]); 2873 2874 strcat (buf, "}\t%@ phole ldm"); 2875 2876 output_asm_insn (buf, operands); 2877 return ""; 2878} 2879 2880int 2881store_multiple_sequence (operands, nops, regs, base, load_offset) 2882 rtx *operands; 2883 int nops; 2884 int *regs; 2885 int *base; 2886 HOST_WIDE_INT *load_offset; 2887{ 2888 int unsorted_regs[4]; 2889 HOST_WIDE_INT unsorted_offsets[4]; 2890 int order[4]; 2891 int base_reg = -1; 2892 int i; 2893 2894 /* Can only handle 2, 3, or 4 insns at present, though could be easily 2895 extended if required. */ 2896 if (nops < 2 || nops > 4) 2897 abort (); 2898 2899 /* Loop over the operands and check that the memory references are 2900 suitable (ie immediate offsets from the same base register). At 2901 the same time, extract the target register, and the memory 2902 offsets. */ 2903 for (i = 0; i < nops; i++) 2904 { 2905 rtx reg; 2906 rtx offset; 2907 2908 /* Convert a subreg of a mem into the mem itself. */ 2909 if (GET_CODE (operands[nops + i]) == SUBREG) 2910 operands[nops + i] = alter_subreg(operands[nops + i]); 2911 2912 if (GET_CODE (operands[nops + i]) != MEM) 2913 abort (); 2914 2915 /* Don't reorder volatile memory references; it doesn't seem worth 2916 looking for the case where the order is ok anyway. */ 2917 if (MEM_VOLATILE_P (operands[nops + i])) 2918 return 0; 2919 2920 offset = const0_rtx; 2921 2922 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG 2923 || (GET_CODE (reg) == SUBREG 2924 && GET_CODE (reg = SUBREG_REG (reg)) == REG)) 2925 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS 2926 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) 2927 == REG) 2928 || (GET_CODE (reg) == SUBREG 2929 && GET_CODE (reg = SUBREG_REG (reg)) == REG)) 2930 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) 2931 == CONST_INT))) 2932 { 2933 if (i == 0) 2934 { 2935 base_reg = REGNO(reg); 2936 unsorted_regs[0] = (GET_CODE (operands[i]) == REG 2937 ? REGNO (operands[i]) 2938 : REGNO (SUBREG_REG (operands[i]))); 2939 order[0] = 0; 2940 } 2941 else 2942 { 2943 if (base_reg != REGNO (reg)) 2944 /* Not addressed from the same base register. */ 2945 return 0; 2946 2947 unsorted_regs[i] = (GET_CODE (operands[i]) == REG 2948 ? REGNO (operands[i]) 2949 : REGNO (SUBREG_REG (operands[i]))); 2950 if (unsorted_regs[i] < unsorted_regs[order[0]]) 2951 order[0] = i; 2952 } 2953 2954 /* If it isn't an integer register, then we can't do this. */ 2955 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14) 2956 return 0; 2957 2958 unsorted_offsets[i] = INTVAL (offset); 2959 } 2960 else 2961 /* Not a suitable memory address. */ 2962 return 0; 2963 } 2964 2965 /* All the useful information has now been extracted from the 2966 operands into unsorted_regs and unsorted_offsets; additionally, 2967 order[0] has been set to the lowest numbered register in the 2968 list. Sort the registers into order, and check that the memory 2969 offsets are ascending and adjacent. */ 2970 2971 for (i = 1; i < nops; i++) 2972 { 2973 int j; 2974 2975 order[i] = order[i - 1]; 2976 for (j = 0; j < nops; j++) 2977 if (unsorted_regs[j] > unsorted_regs[order[i - 1]] 2978 && (order[i] == order[i - 1] 2979 || unsorted_regs[j] < unsorted_regs[order[i]])) 2980 order[i] = j; 2981 2982 /* Have we found a suitable register? if not, one must be used more 2983 than once. */ 2984 if (order[i] == order[i - 1]) 2985 return 0; 2986 2987 /* Is the memory address adjacent and ascending? */ 2988 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) 2989 return 0; 2990 } 2991 2992 if (base) 2993 { 2994 *base = base_reg; 2995 2996 for (i = 0; i < nops; i++) 2997 regs[i] = unsorted_regs[order[i]]; 2998 2999 *load_offset = unsorted_offsets[order[0]]; 3000 } 3001 3002 if (unsorted_offsets[order[0]] == 0) 3003 return 1; /* stmia */ 3004 3005 if (unsorted_offsets[order[0]] == 4) 3006 return 2; /* stmib */ 3007 3008 if (unsorted_offsets[order[nops - 1]] == 0) 3009 return 3; /* stmda */ 3010 3011 if (unsorted_offsets[order[nops - 1]] == -4) 3012 return 4; /* stmdb */ 3013 3014 return 0; 3015} 3016 3017char * 3018emit_stm_seq (operands, nops) 3019 rtx *operands; 3020 int nops; 3021{ 3022 int regs[4]; 3023 int base_reg; 3024 HOST_WIDE_INT offset; 3025 char buf[100]; 3026 int i; 3027 3028 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset)) 3029 { 3030 case 1: 3031 strcpy (buf, "stm%?ia\t"); 3032 break; 3033 3034 case 2: 3035 strcpy (buf, "stm%?ib\t"); 3036 break; 3037 3038 case 3: 3039 strcpy (buf, "stm%?da\t"); 3040 break; 3041 3042 case 4: 3043 strcpy (buf, "stm%?db\t"); 3044 break; 3045 3046 default: 3047 abort (); 3048 } 3049 3050 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, 3051 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); 3052 3053 for (i = 1; i < nops; i++) 3054 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, 3055 reg_names[regs[i]]); 3056 3057 strcat (buf, "}\t%@ phole stm"); 3058 3059 output_asm_insn (buf, operands); 3060 return ""; 3061} 3062 3063int 3064multi_register_push (op, mode) 3065 rtx op; 3066 enum machine_mode mode ATTRIBUTE_UNUSED; 3067{ 3068 if (GET_CODE (op) != PARALLEL 3069 || (GET_CODE (XVECEXP (op, 0, 0)) != SET) 3070 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC) 3071 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != 2)) 3072 return 0; 3073 3074 return 1; 3075} 3076 3077 3078/* Routines for use with attributes */ 3079 3080/* Return nonzero if ATTR is a valid attribute for DECL. 3081 ATTRIBUTES are any existing attributes and ARGS are the arguments 3082 supplied with ATTR. 3083 3084 Supported attributes: 3085 3086 naked: don't output any prologue or epilogue code, the user is assumed 3087 to do the right thing. */ 3088 3089int 3090arm_valid_machine_decl_attribute (decl, attr, args) 3091 tree decl; 3092 tree attr; 3093 tree args; 3094{ 3095 if (args != NULL_TREE) 3096 return 0; 3097 3098 if (is_attribute_p ("naked", attr)) 3099 return TREE_CODE (decl) == FUNCTION_DECL; 3100 return 0; 3101} 3102 3103/* Return non-zero if FUNC is a naked function. */ 3104 3105static int 3106arm_naked_function_p (func) 3107 tree func; 3108{ 3109 tree a; 3110 3111 if (TREE_CODE (func) != FUNCTION_DECL) 3112 abort (); 3113 3114 a = lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (func)); 3115 return a != NULL_TREE; 3116} 3117 3118/* Routines for use in generating RTL */ 3119 3120rtx 3121arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p, 3122 in_struct_p, scalar_p) 3123 int base_regno; 3124 int count; 3125 rtx from; 3126 int up; 3127 int write_back; 3128 int unchanging_p; 3129 int in_struct_p; 3130 int scalar_p; 3131{ 3132 int i = 0, j; 3133 rtx result; 3134 int sign = up ? 1 : -1; 3135 rtx mem; 3136 3137 result = gen_rtx_PARALLEL (VOIDmode, 3138 rtvec_alloc (count + (write_back ? 2 : 0))); 3139 if (write_back) 3140 { 3141 XVECEXP (result, 0, 0) 3142 = gen_rtx_SET (GET_MODE (from), from, 3143 plus_constant (from, count * 4 * sign)); 3144 i = 1; 3145 count++; 3146 } 3147 3148 for (j = 0; i < count; i++, j++) 3149 { 3150 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign)); 3151 RTX_UNCHANGING_P (mem) = unchanging_p; 3152 MEM_IN_STRUCT_P (mem) = in_struct_p; 3153 MEM_SCALAR_P (mem) = scalar_p; 3154 XVECEXP (result, 0, i) 3155 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem); 3156 } 3157 3158 if (write_back) 3159 XVECEXP (result, 0, i) = gen_rtx_CLOBBER (SImode, from); 3160 3161 return result; 3162} 3163 3164rtx 3165arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p, 3166 in_struct_p, scalar_p) 3167 int base_regno; 3168 int count; 3169 rtx to; 3170 int up; 3171 int write_back; 3172 int unchanging_p; 3173 int in_struct_p; 3174 int scalar_p; 3175{ 3176 int i = 0, j; 3177 rtx result; 3178 int sign = up ? 1 : -1; 3179 rtx mem; 3180 3181 result = gen_rtx_PARALLEL (VOIDmode, 3182 rtvec_alloc (count + (write_back ? 2 : 0))); 3183 if (write_back) 3184 { 3185 XVECEXP (result, 0, 0) 3186 = gen_rtx_SET (GET_MODE (to), to, 3187 plus_constant (to, count * 4 * sign)); 3188 i = 1; 3189 count++; 3190 } 3191 3192 for (j = 0; i < count; i++, j++) 3193 { 3194 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign)); 3195 RTX_UNCHANGING_P (mem) = unchanging_p; 3196 MEM_IN_STRUCT_P (mem) = in_struct_p; 3197 MEM_SCALAR_P (mem) = scalar_p; 3198 3199 XVECEXP (result, 0, i) 3200 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j)); 3201 } 3202 3203 if (write_back) 3204 XVECEXP (result, 0, i) = gen_rtx_CLOBBER (SImode, to); 3205 3206 return result; 3207} 3208 3209int 3210arm_gen_movstrqi (operands) 3211 rtx *operands; 3212{ 3213 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes; 3214 int i; 3215 rtx src, dst; 3216 rtx st_src, st_dst, fin_src, fin_dst; 3217 rtx part_bytes_reg = NULL; 3218 rtx mem; 3219 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p; 3220 int dst_scalar_p, src_scalar_p; 3221 3222 if (GET_CODE (operands[2]) != CONST_INT 3223 || GET_CODE (operands[3]) != CONST_INT 3224 || INTVAL (operands[2]) > 64 3225 || INTVAL (operands[3]) & 3) 3226 return 0; 3227 3228 st_dst = XEXP (operands[0], 0); 3229 st_src = XEXP (operands[1], 0); 3230 3231 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]); 3232 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]); 3233 dst_scalar_p = MEM_SCALAR_P (operands[0]); 3234 src_unchanging_p = RTX_UNCHANGING_P (operands[1]); 3235 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]); 3236 src_scalar_p = MEM_SCALAR_P (operands[1]); 3237 3238 fin_dst = dst = copy_to_mode_reg (SImode, st_dst); 3239 fin_src = src = copy_to_mode_reg (SImode, st_src); 3240 3241 in_words_to_go = (INTVAL (operands[2]) + 3) / 4; 3242 out_words_to_go = INTVAL (operands[2]) / 4; 3243 last_bytes = INTVAL (operands[2]) & 3; 3244 3245 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0) 3246 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3); 3247 3248 for (i = 0; in_words_to_go >= 2; i+=4) 3249 { 3250 if (in_words_to_go > 4) 3251 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE, 3252 src_unchanging_p, 3253 src_in_struct_p, 3254 src_scalar_p)); 3255 else 3256 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE, 3257 FALSE, src_unchanging_p, 3258 src_in_struct_p, src_scalar_p)); 3259 3260 if (out_words_to_go) 3261 { 3262 if (out_words_to_go > 4) 3263 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE, 3264 dst_unchanging_p, 3265 dst_in_struct_p, 3266 dst_scalar_p)); 3267 else if (out_words_to_go != 1) 3268 emit_insn (arm_gen_store_multiple (0, out_words_to_go, 3269 dst, TRUE, 3270 (last_bytes == 0 3271 ? FALSE : TRUE), 3272 dst_unchanging_p, 3273 dst_in_struct_p, 3274 dst_scalar_p)); 3275 else 3276 { 3277 mem = gen_rtx_MEM (SImode, dst); 3278 RTX_UNCHANGING_P (mem) = dst_unchanging_p; 3279 MEM_IN_STRUCT_P (mem) = dst_in_struct_p; 3280 MEM_SCALAR_P (mem) = dst_scalar_p; 3281 emit_move_insn (mem, gen_rtx_REG (SImode, 0)); 3282 if (last_bytes != 0) 3283 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4))); 3284 } 3285 } 3286 3287 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4; 3288 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4; 3289 } 3290 3291 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */ 3292 if (out_words_to_go) 3293 { 3294 rtx sreg; 3295 3296 mem = gen_rtx_MEM (SImode, src); 3297 RTX_UNCHANGING_P (mem) = src_unchanging_p; 3298 MEM_IN_STRUCT_P (mem) = src_in_struct_p; 3299 MEM_SCALAR_P (mem) = src_scalar_p; 3300 emit_move_insn (sreg = gen_reg_rtx (SImode), mem); 3301 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4)); 3302 3303 mem = gen_rtx_MEM (SImode, dst); 3304 RTX_UNCHANGING_P (mem) = dst_unchanging_p; 3305 MEM_IN_STRUCT_P (mem) = dst_in_struct_p; 3306 MEM_SCALAR_P (mem) = dst_scalar_p; 3307 emit_move_insn (mem, sreg); 3308 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4)); 3309 in_words_to_go--; 3310 3311 if (in_words_to_go) /* Sanity check */ 3312 abort (); 3313 } 3314 3315 if (in_words_to_go) 3316 { 3317 if (in_words_to_go < 0) 3318 abort (); 3319 3320 mem = gen_rtx_MEM (SImode, src); 3321 RTX_UNCHANGING_P (mem) = src_unchanging_p; 3322 MEM_IN_STRUCT_P (mem) = src_in_struct_p; 3323 MEM_SCALAR_P (mem) = src_scalar_p; 3324 part_bytes_reg = copy_to_mode_reg (SImode, mem); 3325 } 3326 3327 if (BYTES_BIG_ENDIAN && last_bytes) 3328 { 3329 rtx tmp = gen_reg_rtx (SImode); 3330 3331 if (part_bytes_reg == NULL) 3332 abort (); 3333 3334 /* The bytes we want are in the top end of the word */ 3335 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, 3336 GEN_INT (8 * (4 - last_bytes)))); 3337 part_bytes_reg = tmp; 3338 3339 while (last_bytes) 3340 { 3341 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1)); 3342 RTX_UNCHANGING_P (mem) = dst_unchanging_p; 3343 MEM_IN_STRUCT_P (mem) = dst_in_struct_p; 3344 MEM_SCALAR_P (mem) = dst_scalar_p; 3345 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0)); 3346 if (--last_bytes) 3347 { 3348 tmp = gen_reg_rtx (SImode); 3349 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8))); 3350 part_bytes_reg = tmp; 3351 } 3352 } 3353 3354 } 3355 else 3356 { 3357 while (last_bytes) 3358 { 3359 if (part_bytes_reg == NULL) 3360 abort (); 3361 3362 mem = gen_rtx_MEM (QImode, dst); 3363 RTX_UNCHANGING_P (mem) = dst_unchanging_p; 3364 MEM_IN_STRUCT_P (mem) = dst_in_struct_p; 3365 MEM_SCALAR_P (mem) = dst_scalar_p; 3366 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0)); 3367 if (--last_bytes) 3368 { 3369 rtx tmp = gen_reg_rtx (SImode); 3370 3371 emit_insn (gen_addsi3 (dst, dst, const1_rtx)); 3372 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8))); 3373 part_bytes_reg = tmp; 3374 } 3375 } 3376 } 3377 3378 return 1; 3379} 3380 3381/* Generate a memory reference for a half word, such that it will be loaded 3382 into the top 16 bits of the word. We can assume that the address is 3383 known to be alignable and of the form reg, or plus (reg, const). */ 3384rtx 3385gen_rotated_half_load (memref) 3386 rtx memref; 3387{ 3388 HOST_WIDE_INT offset = 0; 3389 rtx base = XEXP (memref, 0); 3390 3391 if (GET_CODE (base) == PLUS) 3392 { 3393 offset = INTVAL (XEXP (base, 1)); 3394 base = XEXP (base, 0); 3395 } 3396 3397 /* If we aren't allowed to generate unaligned addresses, then fail. */ 3398 if (TARGET_SHORT_BY_BYTES 3399 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0))) 3400 return NULL; 3401 3402 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2)); 3403 3404 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2)) 3405 return base; 3406 3407 return gen_rtx_ROTATE (SImode, base, GEN_INT (16)); 3408} 3409 3410static enum machine_mode 3411select_dominance_cc_mode (x, y, cond_or) 3412 rtx x; 3413 rtx y; 3414 HOST_WIDE_INT cond_or; 3415{ 3416 enum rtx_code cond1, cond2; 3417 int swapped = 0; 3418 3419 /* Currently we will probably get the wrong result if the individual 3420 comparisons are not simple. This also ensures that it is safe to 3421 reverse a comparison if necessary. */ 3422 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1)) 3423 != CCmode) 3424 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1)) 3425 != CCmode)) 3426 return CCmode; 3427 3428 if (cond_or) 3429 cond1 = reverse_condition (cond1); 3430 3431 /* If the comparisons are not equal, and one doesn't dominate the other, 3432 then we can't do this. */ 3433 if (cond1 != cond2 3434 && ! comparison_dominates_p (cond1, cond2) 3435 && (swapped = 1, ! comparison_dominates_p (cond2, cond1))) 3436 return CCmode; 3437 3438 if (swapped) 3439 { 3440 enum rtx_code temp = cond1; 3441 cond1 = cond2; 3442 cond2 = temp; 3443 } 3444 3445 switch (cond1) 3446 { 3447 case EQ: 3448 if (cond2 == EQ || ! cond_or) 3449 return CC_DEQmode; 3450 3451 switch (cond2) 3452 { 3453 case LE: return CC_DLEmode; 3454 case LEU: return CC_DLEUmode; 3455 case GE: return CC_DGEmode; 3456 case GEU: return CC_DGEUmode; 3457 default: break; 3458 } 3459 3460 break; 3461 3462 case LT: 3463 if (cond2 == LT || ! cond_or) 3464 return CC_DLTmode; 3465 if (cond2 == LE) 3466 return CC_DLEmode; 3467 if (cond2 == NE) 3468 return CC_DNEmode; 3469 break; 3470 3471 case GT: 3472 if (cond2 == GT || ! cond_or) 3473 return CC_DGTmode; 3474 if (cond2 == GE) 3475 return CC_DGEmode; 3476 if (cond2 == NE) 3477 return CC_DNEmode; 3478 break; 3479 3480 case LTU: 3481 if (cond2 == LTU || ! cond_or) 3482 return CC_DLTUmode; 3483 if (cond2 == LEU) 3484 return CC_DLEUmode; 3485 if (cond2 == NE) 3486 return CC_DNEmode; 3487 break; 3488 3489 case GTU: 3490 if (cond2 == GTU || ! cond_or) 3491 return CC_DGTUmode; 3492 if (cond2 == GEU) 3493 return CC_DGEUmode; 3494 if (cond2 == NE) 3495 return CC_DNEmode; 3496 break; 3497 3498 /* The remaining cases only occur when both comparisons are the 3499 same. */ 3500 case NE: 3501 return CC_DNEmode; 3502 3503 case LE: 3504 return CC_DLEmode; 3505 3506 case GE: 3507 return CC_DGEmode; 3508 3509 case LEU: 3510 return CC_DLEUmode; 3511 3512 case GEU: 3513 return CC_DGEUmode; 3514 3515 default: 3516 break; 3517 } 3518 3519 abort (); 3520} 3521 3522enum machine_mode 3523arm_select_cc_mode (op, x, y) 3524 enum rtx_code op; 3525 rtx x; 3526 rtx y; 3527{ 3528 /* All floating point compares return CCFP if it is an equality 3529 comparison, and CCFPE otherwise. */ 3530 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 3531 return (op == EQ || op == NE) ? CCFPmode : CCFPEmode; 3532 3533 /* A compare with a shifted operand. Because of canonicalization, the 3534 comparison will have to be swapped when we emit the assembler. */ 3535 if (GET_MODE (y) == SImode && GET_CODE (y) == REG 3536 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT 3537 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE 3538 || GET_CODE (x) == ROTATERT)) 3539 return CC_SWPmode; 3540 3541 /* This is a special case that is used by combine to allow a 3542 comparison of a shifted byte load to be split into a zero-extend 3543 followed by a comparison of the shifted integer (only valid for 3544 equalities and unsigned inequalities). */ 3545 if (GET_MODE (x) == SImode 3546 && GET_CODE (x) == ASHIFT 3547 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24 3548 && GET_CODE (XEXP (x, 0)) == SUBREG 3549 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM 3550 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode 3551 && (op == EQ || op == NE 3552 || op == GEU || op == GTU || op == LTU || op == LEU) 3553 && GET_CODE (y) == CONST_INT) 3554 return CC_Zmode; 3555 3556 /* An operation that sets the condition codes as a side-effect, the 3557 V flag is not set correctly, so we can only use comparisons where 3558 this doesn't matter. (For LT and GE we can use "mi" and "pl" 3559 instead. */ 3560 if (GET_MODE (x) == SImode 3561 && y == const0_rtx 3562 && (op == EQ || op == NE || op == LT || op == GE) 3563 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS 3564 || GET_CODE (x) == AND || GET_CODE (x) == IOR 3565 || GET_CODE (x) == XOR || GET_CODE (x) == MULT 3566 || GET_CODE (x) == NOT || GET_CODE (x) == NEG 3567 || GET_CODE (x) == LSHIFTRT 3568 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT 3569 || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT)) 3570 return CC_NOOVmode; 3571 3572 /* A construct for a conditional compare, if the false arm contains 3573 0, then both conditions must be true, otherwise either condition 3574 must be true. Not all conditions are possible, so CCmode is 3575 returned if it can't be done. */ 3576 if (GET_CODE (x) == IF_THEN_ELSE 3577 && (XEXP (x, 2) == const0_rtx 3578 || XEXP (x, 2) == const1_rtx) 3579 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' 3580 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<') 3581 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 3582 INTVAL (XEXP (x, 2))); 3583 3584 if (GET_MODE (x) == QImode && (op == EQ || op == NE)) 3585 return CC_Zmode; 3586 3587 if (GET_MODE (x) == SImode && (op == LTU || op == GEU) 3588 && GET_CODE (x) == PLUS 3589 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y))) 3590 return CC_Cmode; 3591 3592 return CCmode; 3593} 3594 3595/* X and Y are two things to compare using CODE. Emit the compare insn and 3596 return the rtx for register 0 in the proper mode. FP means this is a 3597 floating point compare: I don't think that it is needed on the arm. */ 3598 3599rtx 3600gen_compare_reg (code, x, y) 3601 enum rtx_code code; 3602 rtx x, y; 3603{ 3604 enum machine_mode mode = SELECT_CC_MODE (code, x, y); 3605 rtx cc_reg = gen_rtx_REG (mode, 24); 3606 3607 emit_insn (gen_rtx_SET (VOIDmode, cc_reg, 3608 gen_rtx_COMPARE (mode, x, y))); 3609 3610 return cc_reg; 3611} 3612 3613void 3614arm_reload_in_hi (operands) 3615 rtx *operands; 3616{ 3617 rtx ref = operands[1]; 3618 rtx base, scratch; 3619 HOST_WIDE_INT offset = 0; 3620 3621 if (GET_CODE (ref) == SUBREG) 3622 { 3623 offset = SUBREG_WORD (ref) * UNITS_PER_WORD; 3624 if (BYTES_BIG_ENDIAN) 3625 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref))) 3626 - MIN (UNITS_PER_WORD, 3627 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref))))); 3628 ref = SUBREG_REG (ref); 3629 } 3630 3631 if (GET_CODE (ref) == REG) 3632 { 3633 /* We have a pseudo which has been spilt onto the stack; there 3634 are two cases here: the first where there is a simple 3635 stack-slot replacement and a second where the stack-slot is 3636 out of range, or is used as a subreg. */ 3637 if (reg_equiv_mem[REGNO (ref)]) 3638 { 3639 ref = reg_equiv_mem[REGNO (ref)]; 3640 base = find_replacement (&XEXP (ref, 0)); 3641 } 3642 else 3643 /* The slot is out of range, or was dressed up in a SUBREG */ 3644 base = reg_equiv_address[REGNO (ref)]; 3645 } 3646 else 3647 base = find_replacement (&XEXP (ref, 0)); 3648 3649 /* Handle the case where the address is too complex to be offset by 1. */ 3650 if (GET_CODE (base) == MINUS 3651 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) 3652 { 3653 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); 3654 3655 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base)); 3656 base = base_plus; 3657 } 3658 else if (GET_CODE (base) == PLUS) 3659 { 3660 /* The addend must be CONST_INT, or we would have dealt with it above */ 3661 HOST_WIDE_INT hi, lo; 3662 3663 offset += INTVAL (XEXP (base, 1)); 3664 base = XEXP (base, 0); 3665 3666 /* Rework the address into a legal sequence of insns */ 3667 /* Valid range for lo is -4095 -> 4095 */ 3668 lo = (offset >= 0 3669 ? (offset & 0xfff) 3670 : -((-offset) & 0xfff)); 3671 3672 /* Corner case, if lo is the max offset then we would be out of range 3673 once we have added the additional 1 below, so bump the msb into the 3674 pre-loading insn(s). */ 3675 if (lo == 4095) 3676 lo &= 0x7ff; 3677 3678 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFF) 3679 ^ (HOST_WIDE_INT) 0x80000000) 3680 - (HOST_WIDE_INT) 0x80000000); 3681 3682 if (hi + lo != offset) 3683 abort (); 3684 3685 if (hi != 0) 3686 { 3687 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); 3688 3689 /* Get the base address; addsi3 knows how to handle constants 3690 that require more than one insn */ 3691 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); 3692 base = base_plus; 3693 offset = lo; 3694 } 3695 } 3696 3697 scratch = gen_rtx_REG (SImode, REGNO (operands[2])); 3698 emit_insn (gen_zero_extendqisi2 (scratch, 3699 gen_rtx_MEM (QImode, 3700 plus_constant (base, 3701 offset)))); 3702 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0), 3703 gen_rtx_MEM (QImode, 3704 plus_constant (base, 3705 offset + 1)))); 3706 if (! BYTES_BIG_ENDIAN) 3707 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0), 3708 gen_rtx_IOR (SImode, 3709 gen_rtx_ASHIFT 3710 (SImode, 3711 gen_rtx_SUBREG (SImode, operands[0], 0), 3712 GEN_INT (8)), 3713 scratch))); 3714 else 3715 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0), 3716 gen_rtx_IOR (SImode, 3717 gen_rtx_ASHIFT (SImode, scratch, 3718 GEN_INT (8)), 3719 gen_rtx_SUBREG (SImode, operands[0], 3720 0)))); 3721} 3722 3723/* Handle storing a half-word to memory during reload by synthesising as two 3724 byte stores. Take care not to clobber the input values until after we 3725 have moved them somewhere safe. This code assumes that if the DImode 3726 scratch in operands[2] overlaps either the input value or output address 3727 in some way, then that value must die in this insn (we absolutely need 3728 two scratch registers for some corner cases). */ 3729void 3730arm_reload_out_hi (operands) 3731 rtx *operands; 3732{ 3733 rtx ref = operands[0]; 3734 rtx outval = operands[1]; 3735 rtx base, scratch; 3736 HOST_WIDE_INT offset = 0; 3737 3738 if (GET_CODE (ref) == SUBREG) 3739 { 3740 offset = SUBREG_WORD (ref) * UNITS_PER_WORD; 3741 if (BYTES_BIG_ENDIAN) 3742 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref))) 3743 - MIN (UNITS_PER_WORD, 3744 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref))))); 3745 ref = SUBREG_REG (ref); 3746 } 3747 3748 3749 if (GET_CODE (ref) == REG) 3750 { 3751 /* We have a pseudo which has been spilt onto the stack; there 3752 are two cases here: the first where there is a simple 3753 stack-slot replacement and a second where the stack-slot is 3754 out of range, or is used as a subreg. */ 3755 if (reg_equiv_mem[REGNO (ref)]) 3756 { 3757 ref = reg_equiv_mem[REGNO (ref)]; 3758 base = find_replacement (&XEXP (ref, 0)); 3759 } 3760 else 3761 /* The slot is out of range, or was dressed up in a SUBREG */ 3762 base = reg_equiv_address[REGNO (ref)]; 3763 } 3764 else 3765 base = find_replacement (&XEXP (ref, 0)); 3766 3767 scratch = gen_rtx_REG (SImode, REGNO (operands[2])); 3768 3769 /* Handle the case where the address is too complex to be offset by 1. */ 3770 if (GET_CODE (base) == MINUS 3771 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) 3772 { 3773 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); 3774 3775 /* Be careful not to destroy OUTVAL. */ 3776 if (reg_overlap_mentioned_p (base_plus, outval)) 3777 { 3778 /* Updating base_plus might destroy outval, see if we can 3779 swap the scratch and base_plus. */ 3780 if (! reg_overlap_mentioned_p (scratch, outval)) 3781 { 3782 rtx tmp = scratch; 3783 scratch = base_plus; 3784 base_plus = tmp; 3785 } 3786 else 3787 { 3788 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); 3789 3790 /* Be conservative and copy OUTVAL into the scratch now, 3791 this should only be necessary if outval is a subreg 3792 of something larger than a word. */ 3793 /* XXX Might this clobber base? I can't see how it can, 3794 since scratch is known to overlap with OUTVAL, and 3795 must be wider than a word. */ 3796 emit_insn (gen_movhi (scratch_hi, outval)); 3797 outval = scratch_hi; 3798 } 3799 } 3800 3801 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base)); 3802 base = base_plus; 3803 } 3804 else if (GET_CODE (base) == PLUS) 3805 { 3806 /* The addend must be CONST_INT, or we would have dealt with it above */ 3807 HOST_WIDE_INT hi, lo; 3808 3809 offset += INTVAL (XEXP (base, 1)); 3810 base = XEXP (base, 0); 3811 3812 /* Rework the address into a legal sequence of insns */ 3813 /* Valid range for lo is -4095 -> 4095 */ 3814 lo = (offset >= 0 3815 ? (offset & 0xfff) 3816 : -((-offset) & 0xfff)); 3817 3818 /* Corner case, if lo is the max offset then we would be out of range 3819 once we have added the additional 1 below, so bump the msb into the 3820 pre-loading insn(s). */ 3821 if (lo == 4095) 3822 lo &= 0x7ff; 3823 3824 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFF) 3825 ^ (HOST_WIDE_INT) 0x80000000) 3826 - (HOST_WIDE_INT) 0x80000000); 3827 3828 if (hi + lo != offset) 3829 abort (); 3830 3831 if (hi != 0) 3832 { 3833 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); 3834 3835 /* Be careful not to destroy OUTVAL. */ 3836 if (reg_overlap_mentioned_p (base_plus, outval)) 3837 { 3838 /* Updating base_plus might destroy outval, see if we 3839 can swap the scratch and base_plus. */ 3840 if (! reg_overlap_mentioned_p (scratch, outval)) 3841 { 3842 rtx tmp = scratch; 3843 scratch = base_plus; 3844 base_plus = tmp; 3845 } 3846 else 3847 { 3848 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); 3849 3850 /* Be conservative and copy outval into scratch now, 3851 this should only be necessary if outval is a 3852 subreg of something larger than a word. */ 3853 /* XXX Might this clobber base? I can't see how it 3854 can, since scratch is known to overlap with 3855 outval. */ 3856 emit_insn (gen_movhi (scratch_hi, outval)); 3857 outval = scratch_hi; 3858 } 3859 } 3860 3861 /* Get the base address; addsi3 knows how to handle constants 3862 that require more than one insn */ 3863 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); 3864 base = base_plus; 3865 offset = lo; 3866 } 3867 } 3868 3869 if (BYTES_BIG_ENDIAN) 3870 { 3871 emit_insn (gen_movqi (gen_rtx_MEM (QImode, 3872 plus_constant (base, offset + 1)), 3873 gen_rtx_SUBREG (QImode, outval, 0))); 3874 emit_insn (gen_lshrsi3 (scratch, 3875 gen_rtx_SUBREG (SImode, outval, 0), 3876 GEN_INT (8))); 3877 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), 3878 gen_rtx_SUBREG (QImode, scratch, 0))); 3879 } 3880 else 3881 { 3882 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), 3883 gen_rtx_SUBREG (QImode, outval, 0))); 3884 emit_insn (gen_lshrsi3 (scratch, 3885 gen_rtx_SUBREG (SImode, outval, 0), 3886 GEN_INT (8))); 3887 emit_insn (gen_movqi (gen_rtx_MEM (QImode, 3888 plus_constant (base, offset + 1)), 3889 gen_rtx_SUBREG (QImode, scratch, 0))); 3890 } 3891} 3892 3893/* Routines for manipulation of the constant pool. */ 3894/* This is unashamedly hacked from the version in sh.c, since the problem is 3895 extremely similar. */ 3896 3897/* Arm instructions cannot load a large constant into a register, 3898 constants have to come from a pc relative load. The reference of a pc 3899 relative load instruction must be less than 1k infront of the instruction. 3900 This means that we often have to dump a constant inside a function, and 3901 generate code to branch around it. 3902 3903 It is important to minimize this, since the branches will slow things 3904 down and make things bigger. 3905 3906 Worst case code looks like: 3907 3908 ldr rn, L1 3909 b L2 3910 align 3911 L1: .long value 3912 L2: 3913 .. 3914 3915 ldr rn, L3 3916 b L4 3917 align 3918 L3: .long value 3919 L4: 3920 .. 3921 3922 We fix this by performing a scan before scheduling, which notices which 3923 instructions need to have their operands fetched from the constant table 3924 and builds the table. 3925 3926 3927 The algorithm is: 3928 3929 scan, find an instruction which needs a pcrel move. Look forward, find th 3930 last barrier which is within MAX_COUNT bytes of the requirement. 3931 If there isn't one, make one. Process all the instructions between 3932 the find and the barrier. 3933 3934 In the above example, we can tell that L3 is within 1k of L1, so 3935 the first move can be shrunk from the 2 insn+constant sequence into 3936 just 1 insn, and the constant moved to L3 to make: 3937 3938 ldr rn, L1 3939 .. 3940 ldr rn, L3 3941 b L4 3942 align 3943 L1: .long value 3944 L3: .long value 3945 L4: 3946 3947 Then the second move becomes the target for the shortening process. 3948 3949 */ 3950 3951typedef struct 3952{ 3953 rtx value; /* Value in table */ 3954 HOST_WIDE_INT next_offset; 3955 enum machine_mode mode; /* Mode of value */ 3956} pool_node; 3957 3958/* The maximum number of constants that can fit into one pool, since 3959 the pc relative range is 0...1020 bytes and constants are at least 4 3960 bytes long */ 3961 3962#define MAX_POOL_SIZE (1020/4) 3963static pool_node pool_vector[MAX_POOL_SIZE]; 3964static int pool_size; 3965static rtx pool_vector_label; 3966 3967/* Add a constant to the pool and return its offset within the current 3968 pool. 3969 3970 X is the rtx we want to replace. MODE is its mode. On return, 3971 ADDRESS_ONLY will be non-zero if we really want the address of such 3972 a constant, not the constant itself. */ 3973static HOST_WIDE_INT 3974add_constant (x, mode, address_only) 3975 rtx x; 3976 enum machine_mode mode; 3977 int * address_only; 3978{ 3979 int i; 3980 HOST_WIDE_INT offset; 3981 3982 * address_only = 0; 3983 3984 if (mode == SImode && GET_CODE (x) == MEM && CONSTANT_P (XEXP (x, 0)) 3985 && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0))) 3986 x = get_pool_constant (XEXP (x, 0)); 3987 else if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P(x)) 3988 { 3989 *address_only = 1; 3990 mode = get_pool_mode (x); 3991 x = get_pool_constant (x); 3992 } 3993#ifndef AOF_ASSEMBLER 3994 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == 3) 3995 x = XVECEXP (x, 0, 0); 3996#endif 3997 3998#ifdef AOF_ASSEMBLER 3999 /* PIC Symbol references need to be converted into offsets into the 4000 based area. */ 4001 if (flag_pic && GET_CODE (x) == SYMBOL_REF) 4002 x = aof_pic_entry (x); 4003#endif /* AOF_ASSEMBLER */ 4004 4005 /* First see if we've already got it */ 4006 for (i = 0; i < pool_size; i++) 4007 { 4008 if (GET_CODE (x) == pool_vector[i].value->code 4009 && mode == pool_vector[i].mode) 4010 { 4011 if (GET_CODE (x) == CODE_LABEL) 4012 { 4013 if (XINT (x, 3) != XINT (pool_vector[i].value, 3)) 4014 continue; 4015 } 4016 if (rtx_equal_p (x, pool_vector[i].value)) 4017 return pool_vector[i].next_offset - GET_MODE_SIZE (mode); 4018 } 4019 } 4020 4021 /* Need a new one */ 4022 pool_vector[pool_size].next_offset = GET_MODE_SIZE (mode); 4023 offset = 0; 4024 if (pool_size == 0) 4025 pool_vector_label = gen_label_rtx (); 4026 else 4027 pool_vector[pool_size].next_offset 4028 += (offset = pool_vector[pool_size - 1].next_offset); 4029 4030 pool_vector[pool_size].value = x; 4031 pool_vector[pool_size].mode = mode; 4032 pool_size++; 4033 return offset; 4034} 4035 4036/* Output the literal table */ 4037static void 4038dump_table (scan) 4039 rtx scan; 4040{ 4041 int i; 4042 4043 scan = emit_label_after (gen_label_rtx (), scan); 4044 scan = emit_insn_after (gen_align_4 (), scan); 4045 scan = emit_label_after (pool_vector_label, scan); 4046 4047 for (i = 0; i < pool_size; i++) 4048 { 4049 pool_node *p = pool_vector + i; 4050 4051 switch (GET_MODE_SIZE (p->mode)) 4052 { 4053 case 4: 4054 scan = emit_insn_after (gen_consttable_4 (p->value), scan); 4055 break; 4056 4057 case 8: 4058 scan = emit_insn_after (gen_consttable_8 (p->value), scan); 4059 break; 4060 4061 default: 4062 abort (); 4063 break; 4064 } 4065 } 4066 4067 scan = emit_insn_after (gen_consttable_end (), scan); 4068 scan = emit_barrier_after (scan); 4069 pool_size = 0; 4070} 4071 4072/* Non zero if the src operand needs to be fixed up */ 4073static int 4074fixit (src, mode, destreg) 4075 rtx src; 4076 enum machine_mode mode; 4077 int destreg; 4078{ 4079 if (CONSTANT_P (src)) 4080 { 4081 if (GET_CODE (src) == CONST_INT) 4082 return (! const_ok_for_arm (INTVAL (src)) 4083 && ! const_ok_for_arm (~INTVAL (src))); 4084 if (GET_CODE (src) == CONST_DOUBLE) 4085 return (GET_MODE (src) == VOIDmode 4086 || destreg < 16 4087 || (! const_double_rtx_ok_for_fpu (src) 4088 && ! neg_const_double_rtx_ok_for_fpu (src))); 4089 return symbol_mentioned_p (src); 4090 } 4091#ifndef AOF_ASSEMBLER 4092 else if (GET_CODE (src) == UNSPEC && XINT (src, 1) == 3) 4093 return 1; 4094#endif 4095 else 4096 return (mode == SImode && GET_CODE (src) == MEM 4097 && GET_CODE (XEXP (src, 0)) == SYMBOL_REF 4098 && CONSTANT_POOL_ADDRESS_P (XEXP (src, 0))); 4099} 4100 4101/* Find the last barrier less than MAX_COUNT bytes from FROM, or create one. */ 4102static rtx 4103find_barrier (from, max_count) 4104 rtx from; 4105 int max_count; 4106{ 4107 int count = 0; 4108 rtx found_barrier = 0; 4109 rtx last = from; 4110 4111 while (from && count < max_count) 4112 { 4113 rtx tmp; 4114 4115 if (GET_CODE (from) == BARRIER) 4116 found_barrier = from; 4117 4118 /* Count the length of this insn */ 4119 if (GET_CODE (from) == INSN 4120 && GET_CODE (PATTERN (from)) == SET 4121 && CONSTANT_P (SET_SRC (PATTERN (from))) 4122 && CONSTANT_POOL_ADDRESS_P (SET_SRC (PATTERN (from)))) 4123 count += 8; 4124 /* Handle table jumps as a single entity. */ 4125 else if (GET_CODE (from) == JUMP_INSN 4126 && JUMP_LABEL (from) != 0 4127 && ((tmp = next_real_insn (JUMP_LABEL (from))) 4128 == next_real_insn (from)) 4129 && tmp != NULL 4130 && GET_CODE (tmp) == JUMP_INSN 4131 && (GET_CODE (PATTERN (tmp)) == ADDR_VEC 4132 || GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC)) 4133 { 4134 int elt = GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC ? 1 : 0; 4135 count += (get_attr_length (from) 4136 + GET_MODE_SIZE (SImode) * XVECLEN (PATTERN (tmp), elt)); 4137 /* Continue after the dispatch table. */ 4138 last = from; 4139 from = NEXT_INSN (tmp); 4140 continue; 4141 } 4142 else 4143 count += get_attr_length (from); 4144 4145 last = from; 4146 from = NEXT_INSN (from); 4147 } 4148 4149 if (! found_barrier) 4150 { 4151 /* We didn't find a barrier in time to 4152 dump our stuff, so we'll make one. */ 4153 rtx label = gen_label_rtx (); 4154 4155 if (from) 4156 from = PREV_INSN (last); 4157 else 4158 from = get_last_insn (); 4159 4160 /* Walk back to be just before any jump. */ 4161 while (GET_CODE (from) == JUMP_INSN 4162 || GET_CODE (from) == NOTE 4163 || GET_CODE (from) == CODE_LABEL) 4164 from = PREV_INSN (from); 4165 4166 from = emit_jump_insn_after (gen_jump (label), from); 4167 JUMP_LABEL (from) = label; 4168 found_barrier = emit_barrier_after (from); 4169 emit_label_after (label, found_barrier); 4170 } 4171 4172 return found_barrier; 4173} 4174 4175/* Non zero if the insn is a move instruction which needs to be fixed. */ 4176static int 4177broken_move (insn) 4178 rtx insn; 4179{ 4180 if (!INSN_DELETED_P (insn) 4181 && GET_CODE (insn) == INSN 4182 && GET_CODE (PATTERN (insn)) == SET) 4183 { 4184 rtx pat = PATTERN (insn); 4185 rtx src = SET_SRC (pat); 4186 rtx dst = SET_DEST (pat); 4187 int destreg; 4188 enum machine_mode mode = GET_MODE (dst); 4189 4190 if (dst == pc_rtx) 4191 return 0; 4192 4193 if (GET_CODE (dst) == REG) 4194 destreg = REGNO (dst); 4195 else if (GET_CODE (dst) == SUBREG && GET_CODE (SUBREG_REG (dst)) == REG) 4196 destreg = REGNO (SUBREG_REG (dst)); 4197 else 4198 return 0; 4199 4200 return fixit (src, mode, destreg); 4201 } 4202 return 0; 4203} 4204 4205void 4206arm_reorg (first) 4207 rtx first; 4208{ 4209 rtx insn; 4210 int count_size; 4211 4212#if 0 4213 /* The ldr instruction can work with up to a 4k offset, and most constants 4214 will be loaded with one of these instructions; however, the adr 4215 instruction and the ldf instructions only work with a 1k offset. This 4216 code needs to be rewritten to use the 4k offset when possible, and to 4217 adjust when a 1k offset is needed. For now we just use a 1k offset 4218 from the start. */ 4219 count_size = 4000; 4220 4221 /* Floating point operands can't work further than 1024 bytes from the 4222 PC, so to make things simple we restrict all loads for such functions. 4223 */ 4224 if (TARGET_HARD_FLOAT) 4225 { 4226 int regno; 4227 4228 for (regno = 16; regno < 24; regno++) 4229 if (regs_ever_live[regno]) 4230 { 4231 count_size = 1000; 4232 break; 4233 } 4234 } 4235#else 4236 count_size = 1000; 4237#endif /* 0 */ 4238 4239 for (insn = first; insn; insn = NEXT_INSN (insn)) 4240 { 4241 if (broken_move (insn)) 4242 { 4243 /* This is a broken move instruction, scan ahead looking for 4244 a barrier to stick the constant table behind */ 4245 rtx scan; 4246 rtx barrier = find_barrier (insn, count_size); 4247 4248 /* Now find all the moves between the points and modify them */ 4249 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan)) 4250 { 4251 if (broken_move (scan)) 4252 { 4253 /* This is a broken move instruction, add it to the pool */ 4254 rtx pat = PATTERN (scan); 4255 rtx src = SET_SRC (pat); 4256 rtx dst = SET_DEST (pat); 4257 enum machine_mode mode = GET_MODE (dst); 4258 HOST_WIDE_INT offset; 4259 rtx newinsn = scan; 4260 rtx newsrc; 4261 rtx addr; 4262 int scratch; 4263 int address_only; 4264 4265 /* If this is an HImode constant load, convert it into 4266 an SImode constant load. Since the register is always 4267 32 bits this is safe. We have to do this, since the 4268 load pc-relative instruction only does a 32-bit load. */ 4269 if (mode == HImode) 4270 { 4271 mode = SImode; 4272 if (GET_CODE (dst) != REG) 4273 abort (); 4274 PUT_MODE (dst, SImode); 4275 } 4276 4277 offset = add_constant (src, mode, &address_only); 4278 addr = plus_constant (gen_rtx_LABEL_REF (VOIDmode, 4279 pool_vector_label), 4280 offset); 4281 4282 /* If we only want the address of the pool entry, or 4283 for wide moves to integer regs we need to split 4284 the address calculation off into a separate insn. 4285 If necessary, the load can then be done with a 4286 load-multiple. This is safe, since we have 4287 already noted the length of such insns to be 8, 4288 and we are immediately over-writing the scratch 4289 we have grabbed with the final result. */ 4290 if ((address_only || GET_MODE_SIZE (mode) > 4) 4291 && (scratch = REGNO (dst)) < 16) 4292 { 4293 rtx reg; 4294 4295 if (mode == SImode) 4296 reg = dst; 4297 else 4298 reg = gen_rtx_REG (SImode, scratch); 4299 4300 newinsn = emit_insn_after (gen_movaddr (reg, addr), 4301 newinsn); 4302 addr = reg; 4303 } 4304 4305 if (! address_only) 4306 { 4307 newsrc = gen_rtx_MEM (mode, addr); 4308 4309 /* XXX Fixme -- I think the following is bogus. */ 4310 /* Build a jump insn wrapper around the move instead 4311 of an ordinary insn, because we want to have room for 4312 the target label rtx in fld[7], which an ordinary 4313 insn doesn't have. */ 4314 newinsn 4315 = emit_jump_insn_after (gen_rtx_SET (VOIDmode, dst, 4316 newsrc), 4317 newinsn); 4318 JUMP_LABEL (newinsn) = pool_vector_label; 4319 4320 /* But it's still an ordinary insn */ 4321 PUT_CODE (newinsn, INSN); 4322 } 4323 4324 /* Kill old insn */ 4325 delete_insn (scan); 4326 scan = newinsn; 4327 } 4328 } 4329 dump_table (barrier); 4330 insn = scan; 4331 } 4332 } 4333 4334 after_arm_reorg = 1; 4335} 4336 4337 4338/* Routines to output assembly language. */ 4339 4340/* If the rtx is the correct value then return the string of the number. 4341 In this way we can ensure that valid double constants are generated even 4342 when cross compiling. */ 4343char * 4344fp_immediate_constant (x) 4345 rtx x; 4346{ 4347 REAL_VALUE_TYPE r; 4348 int i; 4349 4350 if (!fpa_consts_inited) 4351 init_fpa_table (); 4352 4353 REAL_VALUE_FROM_CONST_DOUBLE (r, x); 4354 for (i = 0; i < 8; i++) 4355 if (REAL_VALUES_EQUAL (r, values_fpa[i])) 4356 return strings_fpa[i]; 4357 4358 abort (); 4359} 4360 4361/* As for fp_immediate_constant, but value is passed directly, not in rtx. */ 4362static char * 4363fp_const_from_val (r) 4364 REAL_VALUE_TYPE *r; 4365{ 4366 int i; 4367 4368 if (! fpa_consts_inited) 4369 init_fpa_table (); 4370 4371 for (i = 0; i < 8; i++) 4372 if (REAL_VALUES_EQUAL (*r, values_fpa[i])) 4373 return strings_fpa[i]; 4374 4375 abort (); 4376} 4377 4378/* Output the operands of a LDM/STM instruction to STREAM. 4379 MASK is the ARM register set mask of which only bits 0-15 are important. 4380 INSTR is the possibly suffixed base register. HAT unequals zero if a hat 4381 must follow the register list. */ 4382 4383void 4384print_multi_reg (stream, instr, mask, hat) 4385 FILE *stream; 4386 char *instr; 4387 int mask, hat; 4388{ 4389 int i; 4390 int not_first = FALSE; 4391 4392 fputc ('\t', stream); 4393 fprintf (stream, instr, REGISTER_PREFIX); 4394 fputs (", {", stream); 4395 for (i = 0; i < 16; i++) 4396 if (mask & (1 << i)) 4397 { 4398 if (not_first) 4399 fprintf (stream, ", "); 4400 fprintf (stream, "%s%s", REGISTER_PREFIX, reg_names[i]); 4401 not_first = TRUE; 4402 } 4403 4404 fprintf (stream, "}%s\n", hat ? "^" : ""); 4405} 4406 4407/* Output a 'call' insn. */ 4408 4409char * 4410output_call (operands) 4411 rtx *operands; 4412{ 4413 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */ 4414 4415 if (REGNO (operands[0]) == 14) 4416 { 4417 operands[0] = gen_rtx_REG (SImode, 12); 4418 output_asm_insn ("mov%?\t%0, %|lr", operands); 4419 } 4420 output_asm_insn ("mov%?\t%|lr, %|pc", operands); 4421 4422 if (TARGET_THUMB_INTERWORK) 4423 output_asm_insn ("bx%?\t%0", operands); 4424 else 4425 output_asm_insn ("mov%?\t%|pc, %0", operands); 4426 4427 return ""; 4428} 4429 4430static int 4431eliminate_lr2ip (x) 4432 rtx *x; 4433{ 4434 int something_changed = 0; 4435 rtx x0 = *x; 4436 int code = GET_CODE (x0); 4437 register int i, j; 4438 register char *fmt; 4439 4440 switch (code) 4441 { 4442 case REG: 4443 if (REGNO (x0) == 14) 4444 { 4445 *x = gen_rtx_REG (SImode, 12); 4446 return 1; 4447 } 4448 return 0; 4449 default: 4450 /* Scan through the sub-elements and change any references there */ 4451 fmt = GET_RTX_FORMAT (code); 4452 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 4453 if (fmt[i] == 'e') 4454 something_changed |= eliminate_lr2ip (&XEXP (x0, i)); 4455 else if (fmt[i] == 'E') 4456 for (j = 0; j < XVECLEN (x0, i); j++) 4457 something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j)); 4458 return something_changed; 4459 } 4460} 4461 4462/* Output a 'call' insn that is a reference in memory. */ 4463 4464char * 4465output_call_mem (operands) 4466 rtx *operands; 4467{ 4468 operands[0] = copy_rtx (operands[0]); /* Be ultra careful */ 4469 /* Handle calls using lr by using ip (which may be clobbered in subr anyway). 4470 */ 4471 if (eliminate_lr2ip (&operands[0])) 4472 output_asm_insn ("mov%?\t%|ip, %|lr", operands); 4473 4474 if (TARGET_THUMB_INTERWORK) 4475 { 4476 output_asm_insn ("ldr%?\t%|ip, %0", operands); 4477 output_asm_insn ("mov%?\t%|lr, %|pc", operands); 4478 output_asm_insn ("bx%?\t%|ip", operands); 4479 } 4480 else 4481 { 4482 output_asm_insn ("mov%?\t%|lr, %|pc", operands); 4483 output_asm_insn ("ldr%?\t%|pc, %0", operands); 4484 } 4485 4486 return ""; 4487} 4488 4489 4490/* Output a move from arm registers to an fpu registers. 4491 OPERANDS[0] is an fpu register. 4492 OPERANDS[1] is the first registers of an arm register pair. */ 4493 4494char * 4495output_mov_long_double_fpu_from_arm (operands) 4496 rtx *operands; 4497{ 4498 int arm_reg0 = REGNO (operands[1]); 4499 rtx ops[3]; 4500 4501 if (arm_reg0 == 12) 4502 abort(); 4503 4504 ops[0] = gen_rtx_REG (SImode, arm_reg0); 4505 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); 4506 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); 4507 4508 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops); 4509 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands); 4510 return ""; 4511} 4512 4513/* Output a move from an fpu register to arm registers. 4514 OPERANDS[0] is the first registers of an arm register pair. 4515 OPERANDS[1] is an fpu register. */ 4516 4517char * 4518output_mov_long_double_arm_from_fpu (operands) 4519 rtx *operands; 4520{ 4521 int arm_reg0 = REGNO (operands[0]); 4522 rtx ops[3]; 4523 4524 if (arm_reg0 == 12) 4525 abort(); 4526 4527 ops[0] = gen_rtx_REG (SImode, arm_reg0); 4528 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); 4529 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); 4530 4531 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands); 4532 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops); 4533 return ""; 4534} 4535 4536/* Output a move from arm registers to arm registers of a long double 4537 OPERANDS[0] is the destination. 4538 OPERANDS[1] is the source. */ 4539char * 4540output_mov_long_double_arm_from_arm (operands) 4541 rtx *operands; 4542{ 4543 /* We have to be careful here because the two might overlap */ 4544 int dest_start = REGNO (operands[0]); 4545 int src_start = REGNO (operands[1]); 4546 rtx ops[2]; 4547 int i; 4548 4549 if (dest_start < src_start) 4550 { 4551 for (i = 0; i < 3; i++) 4552 { 4553 ops[0] = gen_rtx_REG (SImode, dest_start + i); 4554 ops[1] = gen_rtx_REG (SImode, src_start + i); 4555 output_asm_insn ("mov%?\t%0, %1", ops); 4556 } 4557 } 4558 else 4559 { 4560 for (i = 2; i >= 0; i--) 4561 { 4562 ops[0] = gen_rtx_REG (SImode, dest_start + i); 4563 ops[1] = gen_rtx_REG (SImode, src_start + i); 4564 output_asm_insn ("mov%?\t%0, %1", ops); 4565 } 4566 } 4567 4568 return ""; 4569} 4570 4571 4572/* Output a move from arm registers to an fpu registers. 4573 OPERANDS[0] is an fpu register. 4574 OPERANDS[1] is the first registers of an arm register pair. */ 4575 4576char * 4577output_mov_double_fpu_from_arm (operands) 4578 rtx *operands; 4579{ 4580 int arm_reg0 = REGNO (operands[1]); 4581 rtx ops[2]; 4582 4583 if (arm_reg0 == 12) 4584 abort(); 4585 ops[0] = gen_rtx_REG (SImode, arm_reg0); 4586 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); 4587 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops); 4588 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands); 4589 return ""; 4590} 4591 4592/* Output a move from an fpu register to arm registers. 4593 OPERANDS[0] is the first registers of an arm register pair. 4594 OPERANDS[1] is an fpu register. */ 4595 4596char * 4597output_mov_double_arm_from_fpu (operands) 4598 rtx *operands; 4599{ 4600 int arm_reg0 = REGNO (operands[0]); 4601 rtx ops[2]; 4602 4603 if (arm_reg0 == 12) 4604 abort(); 4605 4606 ops[0] = gen_rtx_REG (SImode, arm_reg0); 4607 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); 4608 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands); 4609 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops); 4610 return ""; 4611} 4612 4613/* Output a move between double words. 4614 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM 4615 or MEM<-REG and all MEMs must be offsettable addresses. */ 4616 4617char * 4618output_move_double (operands) 4619 rtx * operands; 4620{ 4621 enum rtx_code code0 = GET_CODE (operands[0]); 4622 enum rtx_code code1 = GET_CODE (operands[1]); 4623 rtx otherops[3]; 4624 4625 if (code0 == REG) 4626 { 4627 int reg0 = REGNO (operands[0]); 4628 4629 otherops[0] = gen_rtx_REG (SImode, 1 + reg0); 4630 4631 if (code1 == REG) 4632 { 4633 int reg1 = REGNO (operands[1]); 4634 if (reg1 == 12) 4635 abort(); 4636 4637 /* Ensure the second source is not overwritten */ 4638 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1)) 4639 output_asm_insn("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands); 4640 else 4641 output_asm_insn("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands); 4642 } 4643 else if (code1 == CONST_DOUBLE) 4644 { 4645 if (GET_MODE (operands[1]) == DFmode) 4646 { 4647 long l[2]; 4648 union real_extract u; 4649 4650 bcopy ((char *) &CONST_DOUBLE_LOW (operands[1]), (char *) &u, 4651 sizeof (u)); 4652 REAL_VALUE_TO_TARGET_DOUBLE (u.d, l); 4653 otherops[1] = GEN_INT(l[1]); 4654 operands[1] = GEN_INT(l[0]); 4655 } 4656 else if (GET_MODE (operands[1]) != VOIDmode) 4657 abort (); 4658 else if (WORDS_BIG_ENDIAN) 4659 { 4660 4661 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); 4662 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); 4663 } 4664 else 4665 { 4666 4667 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); 4668 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); 4669 } 4670 output_mov_immediate (operands); 4671 output_mov_immediate (otherops); 4672 } 4673 else if (code1 == CONST_INT) 4674 { 4675#if HOST_BITS_PER_WIDE_INT > 32 4676 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us 4677 what the upper word is. */ 4678 if (WORDS_BIG_ENDIAN) 4679 { 4680 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1]))); 4681 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32); 4682 } 4683 else 4684 { 4685 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32); 4686 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1]))); 4687 } 4688#else 4689 /* Sign extend the intval into the high-order word */ 4690 if (WORDS_BIG_ENDIAN) 4691 { 4692 otherops[1] = operands[1]; 4693 operands[1] = (INTVAL (operands[1]) < 0 4694 ? constm1_rtx : const0_rtx); 4695 } 4696 else 4697 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx; 4698#endif 4699 output_mov_immediate (otherops); 4700 output_mov_immediate (operands); 4701 } 4702 else if (code1 == MEM) 4703 { 4704 switch (GET_CODE (XEXP (operands[1], 0))) 4705 { 4706 case REG: 4707 output_asm_insn ("ldm%?ia\t%m1, %M0", operands); 4708 break; 4709 4710 case PRE_INC: 4711 abort (); /* Should never happen now */ 4712 break; 4713 4714 case PRE_DEC: 4715 output_asm_insn ("ldm%?db\t%m1!, %M0", operands); 4716 break; 4717 4718 case POST_INC: 4719 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands); 4720 break; 4721 4722 case POST_DEC: 4723 abort (); /* Should never happen now */ 4724 break; 4725 4726 case LABEL_REF: 4727 case CONST: 4728 output_asm_insn ("adr%?\t%0, %1", operands); 4729 output_asm_insn ("ldm%?ia\t%0, %M0", operands); 4730 break; 4731 4732 default: 4733 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1), 4734 GET_MODE (XEXP (XEXP (operands[1], 0), 1)))) 4735 { 4736 otherops[0] = operands[0]; 4737 otherops[1] = XEXP (XEXP (operands[1], 0), 0); 4738 otherops[2] = XEXP (XEXP (operands[1], 0), 1); 4739 if (GET_CODE (XEXP (operands[1], 0)) == PLUS) 4740 { 4741 if (GET_CODE (otherops[2]) == CONST_INT) 4742 { 4743 switch (INTVAL (otherops[2])) 4744 { 4745 case -8: 4746 output_asm_insn ("ldm%?db\t%1, %M0", otherops); 4747 return ""; 4748 case -4: 4749 output_asm_insn ("ldm%?da\t%1, %M0", otherops); 4750 return ""; 4751 case 4: 4752 output_asm_insn ("ldm%?ib\t%1, %M0", otherops); 4753 return ""; 4754 } 4755 if (!(const_ok_for_arm (INTVAL (otherops[2])))) 4756 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops); 4757 else 4758 output_asm_insn ("add%?\t%0, %1, %2", otherops); 4759 } 4760 else 4761 output_asm_insn ("add%?\t%0, %1, %2", otherops); 4762 } 4763 else 4764 output_asm_insn ("sub%?\t%0, %1, %2", otherops); 4765 return "ldm%?ia\t%0, %M0"; 4766 } 4767 else 4768 { 4769 otherops[1] = adj_offsettable_operand (operands[1], 4); 4770 /* Take care of overlapping base/data reg. */ 4771 if (reg_mentioned_p (operands[0], operands[1])) 4772 { 4773 output_asm_insn ("ldr%?\t%0, %1", otherops); 4774 output_asm_insn ("ldr%?\t%0, %1", operands); 4775 } 4776 else 4777 { 4778 output_asm_insn ("ldr%?\t%0, %1", operands); 4779 output_asm_insn ("ldr%?\t%0, %1", otherops); 4780 } 4781 } 4782 } 4783 } 4784 else 4785 abort(); /* Constraints should prevent this */ 4786 } 4787 else if (code0 == MEM && code1 == REG) 4788 { 4789 if (REGNO (operands[1]) == 12) 4790 abort(); 4791 4792 switch (GET_CODE (XEXP (operands[0], 0))) 4793 { 4794 case REG: 4795 output_asm_insn ("stm%?ia\t%m0, %M1", operands); 4796 break; 4797 4798 case PRE_INC: 4799 abort (); /* Should never happen now */ 4800 break; 4801 4802 case PRE_DEC: 4803 output_asm_insn ("stm%?db\t%m0!, %M1", operands); 4804 break; 4805 4806 case POST_INC: 4807 output_asm_insn ("stm%?ia\t%m0!, %M1", operands); 4808 break; 4809 4810 case POST_DEC: 4811 abort (); /* Should never happen now */ 4812 break; 4813 4814 case PLUS: 4815 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) 4816 { 4817 switch (INTVAL (XEXP (XEXP (operands[0], 0), 1))) 4818 { 4819 case -8: 4820 output_asm_insn ("stm%?db\t%m0, %M1", operands); 4821 return ""; 4822 4823 case -4: 4824 output_asm_insn ("stm%?da\t%m0, %M1", operands); 4825 return ""; 4826 4827 case 4: 4828 output_asm_insn ("stm%?ib\t%m0, %M1", operands); 4829 return ""; 4830 } 4831 } 4832 /* Fall through */ 4833 4834 default: 4835 otherops[0] = adj_offsettable_operand (operands[0], 4); 4836 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1])); 4837 output_asm_insn ("str%?\t%1, %0", operands); 4838 output_asm_insn ("str%?\t%1, %0", otherops); 4839 } 4840 } 4841 else 4842 abort(); /* Constraints should prevent this */ 4843 4844 return ""; 4845} 4846 4847 4848/* Output an arbitrary MOV reg, #n. 4849 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */ 4850 4851char * 4852output_mov_immediate (operands) 4853 rtx *operands; 4854{ 4855 HOST_WIDE_INT n = INTVAL (operands[1]); 4856 int n_ones = 0; 4857 int i; 4858 4859 /* Try to use one MOV */ 4860 if (const_ok_for_arm (n)) 4861 { 4862 output_asm_insn ("mov%?\t%0, %1", operands); 4863 return ""; 4864 } 4865 4866 /* Try to use one MVN */ 4867 if (const_ok_for_arm (~n)) 4868 { 4869 operands[1] = GEN_INT (~n); 4870 output_asm_insn ("mvn%?\t%0, %1", operands); 4871 return ""; 4872 } 4873 4874 /* If all else fails, make it out of ORRs or BICs as appropriate. */ 4875 4876 for (i=0; i < 32; i++) 4877 if (n & 1 << i) 4878 n_ones++; 4879 4880 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */ 4881 output_multi_immediate(operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, 4882 ~n); 4883 else 4884 output_multi_immediate(operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, 4885 n); 4886 4887 return ""; 4888} 4889 4890 4891/* Output an ADD r, s, #n where n may be too big for one instruction. If 4892 adding zero to one register, output nothing. */ 4893 4894char * 4895output_add_immediate (operands) 4896 rtx *operands; 4897{ 4898 HOST_WIDE_INT n = INTVAL (operands[2]); 4899 4900 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1])) 4901 { 4902 if (n < 0) 4903 output_multi_immediate (operands, 4904 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2, 4905 -n); 4906 else 4907 output_multi_immediate (operands, 4908 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2, 4909 n); 4910 } 4911 4912 return ""; 4913} 4914 4915/* Output a multiple immediate operation. 4916 OPERANDS is the vector of operands referred to in the output patterns. 4917 INSTR1 is the output pattern to use for the first constant. 4918 INSTR2 is the output pattern to use for subsequent constants. 4919 IMMED_OP is the index of the constant slot in OPERANDS. 4920 N is the constant value. */ 4921 4922static char * 4923output_multi_immediate (operands, instr1, instr2, immed_op, n) 4924 rtx *operands; 4925 char *instr1, *instr2; 4926 int immed_op; 4927 HOST_WIDE_INT n; 4928{ 4929#if HOST_BITS_PER_WIDE_INT > 32 4930 n &= 0xffffffff; 4931#endif 4932 4933 if (n == 0) 4934 { 4935 operands[immed_op] = const0_rtx; 4936 output_asm_insn (instr1, operands); /* Quick and easy output */ 4937 } 4938 else 4939 { 4940 int i; 4941 char *instr = instr1; 4942 4943 /* Note that n is never zero here (which would give no output) */ 4944 for (i = 0; i < 32; i += 2) 4945 { 4946 if (n & (3 << i)) 4947 { 4948 operands[immed_op] = GEN_INT (n & (255 << i)); 4949 output_asm_insn (instr, operands); 4950 instr = instr2; 4951 i += 6; 4952 } 4953 } 4954 } 4955 return ""; 4956} 4957 4958 4959/* Return the appropriate ARM instruction for the operation code. 4960 The returned result should not be overwritten. OP is the rtx of the 4961 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator 4962 was shifted. */ 4963 4964char * 4965arithmetic_instr (op, shift_first_arg) 4966 rtx op; 4967 int shift_first_arg; 4968{ 4969 switch (GET_CODE (op)) 4970 { 4971 case PLUS: 4972 return "add"; 4973 4974 case MINUS: 4975 return shift_first_arg ? "rsb" : "sub"; 4976 4977 case IOR: 4978 return "orr"; 4979 4980 case XOR: 4981 return "eor"; 4982 4983 case AND: 4984 return "and"; 4985 4986 default: 4987 abort (); 4988 } 4989} 4990 4991 4992/* Ensure valid constant shifts and return the appropriate shift mnemonic 4993 for the operation code. The returned result should not be overwritten. 4994 OP is the rtx code of the shift. 4995 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant 4996 shift. */ 4997 4998static char * 4999shift_op (op, amountp) 5000 rtx op; 5001 HOST_WIDE_INT *amountp; 5002{ 5003 char *mnem; 5004 enum rtx_code code = GET_CODE (op); 5005 5006 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG) 5007 *amountp = -1; 5008 else if (GET_CODE (XEXP (op, 1)) == CONST_INT) 5009 *amountp = INTVAL (XEXP (op, 1)); 5010 else 5011 abort (); 5012 5013 switch (code) 5014 { 5015 case ASHIFT: 5016 mnem = "asl"; 5017 break; 5018 5019 case ASHIFTRT: 5020 mnem = "asr"; 5021 break; 5022 5023 case LSHIFTRT: 5024 mnem = "lsr"; 5025 break; 5026 5027 case ROTATERT: 5028 mnem = "ror"; 5029 break; 5030 5031 case MULT: 5032 /* We never have to worry about the amount being other than a 5033 power of 2, since this case can never be reloaded from a reg. */ 5034 if (*amountp != -1) 5035 *amountp = int_log2 (*amountp); 5036 else 5037 abort (); 5038 return "asl"; 5039 5040 default: 5041 abort (); 5042 } 5043 5044 if (*amountp != -1) 5045 { 5046 /* This is not 100% correct, but follows from the desire to merge 5047 multiplication by a power of 2 with the recognizer for a 5048 shift. >=32 is not a valid shift for "asl", so we must try and 5049 output a shift that produces the correct arithmetical result. 5050 Using lsr #32 is identical except for the fact that the carry bit 5051 is not set correctly if we set the flags; but we never use the 5052 carry bit from such an operation, so we can ignore that. */ 5053 if (code == ROTATERT) 5054 *amountp &= 31; /* Rotate is just modulo 32 */ 5055 else if (*amountp != (*amountp & 31)) 5056 { 5057 if (code == ASHIFT) 5058 mnem = "lsr"; 5059 *amountp = 32; 5060 } 5061 5062 /* Shifts of 0 are no-ops. */ 5063 if (*amountp == 0) 5064 return NULL; 5065 } 5066 5067 return mnem; 5068} 5069 5070 5071/* Obtain the shift from the POWER of two. */ 5072 5073static HOST_WIDE_INT 5074int_log2 (power) 5075 HOST_WIDE_INT power; 5076{ 5077 HOST_WIDE_INT shift = 0; 5078 5079 while (((((HOST_WIDE_INT) 1) << shift) & power) == 0) 5080 { 5081 if (shift > 31) 5082 abort (); 5083 shift++; 5084 } 5085 5086 return shift; 5087} 5088 5089/* Output a .ascii pseudo-op, keeping track of lengths. This is because 5090 /bin/as is horribly restrictive. */ 5091 5092void 5093output_ascii_pseudo_op (stream, p, len) 5094 FILE *stream; 5095 unsigned char *p; 5096 int len; 5097{ 5098 int i; 5099 int len_so_far = 1000; 5100 int chars_so_far = 0; 5101 5102 for (i = 0; i < len; i++) 5103 { 5104 register int c = p[i]; 5105 5106 if (len_so_far > 50) 5107 { 5108 if (chars_so_far) 5109 fputs ("\"\n", stream); 5110 fputs ("\t.ascii\t\"", stream); 5111 len_so_far = 0; 5112 chars_so_far = 0; 5113 } 5114 5115 if (c == '\"' || c == '\\') 5116 { 5117 putc('\\', stream); 5118 len_so_far++; 5119 } 5120 5121 if (c >= ' ' && c < 0177) 5122 { 5123 putc (c, stream); 5124 len_so_far++; 5125 } 5126 else 5127 { 5128 fprintf (stream, "\\%03o", c); 5129 len_so_far +=4; 5130 } 5131 5132 chars_so_far++; 5133 } 5134 5135 fputs ("\"\n", stream); 5136} 5137 5138 5139/* Try to determine whether a pattern really clobbers the link register. 5140 This information is useful when peepholing, so that lr need not be pushed 5141 if we combine a call followed by a return. 5142 NOTE: This code does not check for side-effect expressions in a SET_SRC: 5143 such a check should not be needed because these only update an existing 5144 value within a register; the register must still be set elsewhere within 5145 the function. */ 5146 5147static int 5148pattern_really_clobbers_lr (x) 5149 rtx x; 5150{ 5151 int i; 5152 5153 switch (GET_CODE (x)) 5154 { 5155 case SET: 5156 switch (GET_CODE (SET_DEST (x))) 5157 { 5158 case REG: 5159 return REGNO (SET_DEST (x)) == 14; 5160 5161 case SUBREG: 5162 if (GET_CODE (XEXP (SET_DEST (x), 0)) == REG) 5163 return REGNO (XEXP (SET_DEST (x), 0)) == 14; 5164 5165 if (GET_CODE (XEXP (SET_DEST (x), 0)) == MEM) 5166 return 0; 5167 abort (); 5168 5169 default: 5170 return 0; 5171 } 5172 5173 case PARALLEL: 5174 for (i = 0; i < XVECLEN (x, 0); i++) 5175 if (pattern_really_clobbers_lr (XVECEXP (x, 0, i))) 5176 return 1; 5177 return 0; 5178 5179 case CLOBBER: 5180 switch (GET_CODE (XEXP (x, 0))) 5181 { 5182 case REG: 5183 return REGNO (XEXP (x, 0)) == 14; 5184 5185 case SUBREG: 5186 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG) 5187 return REGNO (XEXP (XEXP (x, 0), 0)) == 14; 5188 abort (); 5189 5190 default: 5191 return 0; 5192 } 5193 5194 case UNSPEC: 5195 return 1; 5196 5197 default: 5198 return 0; 5199 } 5200} 5201 5202static int 5203function_really_clobbers_lr (first) 5204 rtx first; 5205{ 5206 rtx insn, next; 5207 5208 for (insn = first; insn; insn = next_nonnote_insn (insn)) 5209 { 5210 switch (GET_CODE (insn)) 5211 { 5212 case BARRIER: 5213 case NOTE: 5214 case CODE_LABEL: 5215 case JUMP_INSN: /* Jump insns only change the PC (and conds) */ 5216 case INLINE_HEADER: 5217 break; 5218 5219 case INSN: 5220 if (pattern_really_clobbers_lr (PATTERN (insn))) 5221 return 1; 5222 break; 5223 5224 case CALL_INSN: 5225 /* Don't yet know how to handle those calls that are not to a 5226 SYMBOL_REF */ 5227 if (GET_CODE (PATTERN (insn)) != PARALLEL) 5228 abort (); 5229 5230 switch (GET_CODE (XVECEXP (PATTERN (insn), 0, 0))) 5231 { 5232 case CALL: 5233 if (GET_CODE (XEXP (XEXP (XVECEXP (PATTERN (insn), 0, 0), 0), 0)) 5234 != SYMBOL_REF) 5235 return 1; 5236 break; 5237 5238 case SET: 5239 if (GET_CODE (XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn), 5240 0, 0)), 0), 0)) 5241 != SYMBOL_REF) 5242 return 1; 5243 break; 5244 5245 default: /* Don't recognize it, be safe */ 5246 return 1; 5247 } 5248 5249 /* A call can be made (by peepholing) not to clobber lr iff it is 5250 followed by a return. There may, however, be a use insn iff 5251 we are returning the result of the call. 5252 If we run off the end of the insn chain, then that means the 5253 call was at the end of the function. Unfortunately we don't 5254 have a return insn for the peephole to recognize, so we 5255 must reject this. (Can this be fixed by adding our own insn?) */ 5256 if ((next = next_nonnote_insn (insn)) == NULL) 5257 return 1; 5258 5259 /* No need to worry about lr if the call never returns */ 5260 if (GET_CODE (next) == BARRIER) 5261 break; 5262 5263 if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == USE 5264 && (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) 5265 && (REGNO (SET_DEST (XVECEXP (PATTERN (insn), 0, 0))) 5266 == REGNO (XEXP (PATTERN (next), 0)))) 5267 if ((next = next_nonnote_insn (next)) == NULL) 5268 return 1; 5269 5270 if (GET_CODE (next) == JUMP_INSN 5271 && GET_CODE (PATTERN (next)) == RETURN) 5272 break; 5273 return 1; 5274 5275 default: 5276 abort (); 5277 } 5278 } 5279 5280 /* We have reached the end of the chain so lr was _not_ clobbered */ 5281 return 0; 5282} 5283 5284char * 5285output_return_instruction (operand, really_return, reverse) 5286 rtx operand; 5287 int really_return; 5288 int reverse; 5289{ 5290 char instr[100]; 5291 int reg, live_regs = 0; 5292 int volatile_func = (optimize > 0 5293 && TREE_THIS_VOLATILE (current_function_decl)); 5294 5295 return_used_this_function = 1; 5296 5297 if (volatile_func) 5298 { 5299 rtx ops[2]; 5300 /* If this function was declared non-returning, and we have found a tail 5301 call, then we have to trust that the called function won't return. */ 5302 if (! really_return) 5303 return ""; 5304 5305 /* Otherwise, trap an attempted return by aborting. */ 5306 ops[0] = operand; 5307 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_GOT ? "abort(PLT)" 5308 : "abort"); 5309 assemble_external_libcall (ops[1]); 5310 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops); 5311 return ""; 5312 } 5313 5314 if (current_function_calls_alloca && ! really_return) 5315 abort(); 5316 5317 for (reg = 0; reg <= 10; reg++) 5318 if (regs_ever_live[reg] && ! call_used_regs[reg]) 5319 live_regs++; 5320 5321 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) 5322 live_regs++; 5323 5324 if (live_regs || (regs_ever_live[14] && ! lr_save_eliminated)) 5325 live_regs++; 5326 5327 if (frame_pointer_needed) 5328 live_regs += 4; 5329 5330 if (live_regs) 5331 { 5332 if (lr_save_eliminated || ! regs_ever_live[14]) 5333 live_regs++; 5334 5335 if (frame_pointer_needed) 5336 strcpy (instr, 5337 reverse ? "ldm%?%D0ea\t%|fp, {" : "ldm%?%d0ea\t%|fp, {"); 5338 else 5339 strcpy (instr, 5340 reverse ? "ldm%?%D0fd\t%|sp!, {" : "ldm%?%d0fd\t%|sp!, {"); 5341 5342 for (reg = 0; reg <= 10; reg++) 5343 if (regs_ever_live[reg] 5344 && (! call_used_regs[reg] 5345 || (flag_pic && reg == PIC_OFFSET_TABLE_REGNUM))) 5346 { 5347 strcat (instr, "%|"); 5348 strcat (instr, reg_names[reg]); 5349 if (--live_regs) 5350 strcat (instr, ", "); 5351 } 5352 5353 if (frame_pointer_needed) 5354 { 5355 strcat (instr, "%|"); 5356 strcat (instr, reg_names[11]); 5357 strcat (instr, ", "); 5358 strcat (instr, "%|"); 5359 strcat (instr, reg_names[13]); 5360 strcat (instr, ", "); 5361 strcat (instr, "%|"); 5362 strcat (instr, TARGET_THUMB_INTERWORK || (! really_return) 5363 ? reg_names[14] : reg_names[15] ); 5364 } 5365 else 5366 { 5367 strcat (instr, "%|"); 5368 if (TARGET_THUMB_INTERWORK && really_return) 5369 strcat (instr, reg_names[12]); 5370 else 5371 strcat (instr, really_return ? reg_names[15] : reg_names[14]); 5372 } 5373 strcat (instr, (TARGET_APCS_32 || !really_return) ? "}" : "}^"); 5374 output_asm_insn (instr, &operand); 5375 5376 if (TARGET_THUMB_INTERWORK && really_return) 5377 { 5378 strcpy (instr, "bx%?"); 5379 strcat (instr, reverse ? "%D0" : "%d0"); 5380 strcat (instr, "\t%|"); 5381 strcat (instr, frame_pointer_needed ? "lr" : "ip"); 5382 5383 output_asm_insn (instr, & operand); 5384 } 5385 } 5386 else if (really_return) 5387 { 5388 if (TARGET_THUMB_INTERWORK) 5389 sprintf (instr, "bx%%?%%%s0\t%%|lr", reverse ? "D" : "d"); 5390 else 5391 sprintf (instr, "mov%%?%%%s0%s\t%%|pc, %%|lr", 5392 reverse ? "D" : "d", TARGET_APCS_32 ? "" : "s"); 5393 5394 output_asm_insn (instr, & operand); 5395 } 5396 5397 return ""; 5398} 5399 5400/* Return nonzero if optimizing and the current function is volatile. 5401 Such functions never return, and many memory cycles can be saved 5402 by not storing register values that will never be needed again. 5403 This optimization was added to speed up context switching in a 5404 kernel application. */ 5405 5406int 5407arm_volatile_func () 5408{ 5409 return (optimize > 0 && TREE_THIS_VOLATILE (current_function_decl)); 5410} 5411 5412/* Write the function name into the code section, directly preceding 5413 the function prologue. 5414 5415 Code will be output similar to this: 5416 t0 5417 .ascii "arm_poke_function_name", 0 5418 .align 5419 t1 5420 .word 0xff000000 + (t1 - t0) 5421 arm_poke_function_name 5422 mov ip, sp 5423 stmfd sp!, {fp, ip, lr, pc} 5424 sub fp, ip, #4 5425 5426 When performing a stack backtrace, code can inspect the value 5427 of 'pc' stored at 'fp' + 0. If the trace function then looks 5428 at location pc - 12 and the top 8 bits are set, then we know 5429 that there is a function name embedded immediately preceding this 5430 location and has length ((pc[-3]) & 0xff000000). 5431 5432 We assume that pc is declared as a pointer to an unsigned long. 5433 5434 It is of no benefit to output the function name if we are assembling 5435 a leaf function. These function types will not contain a stack 5436 backtrace structure, therefore it is not possible to determine the 5437 function name. */ 5438 5439void 5440arm_poke_function_name (stream, name) 5441 FILE * stream; 5442 char * name; 5443{ 5444 unsigned long alignlength; 5445 unsigned long length; 5446 rtx x; 5447 5448 length = strlen (name); 5449 alignlength = (length + 1) + 3 & ~3; 5450 5451 ASM_OUTPUT_ASCII (stream, name, length + 1); 5452 ASM_OUTPUT_ALIGN (stream, 2); 5453 x = GEN_INT (0xff000000UL + alignlength); 5454 ASM_OUTPUT_INT (stream, x); 5455} 5456 5457/* The amount of stack adjustment that happens here, in output_return and in 5458 output_epilogue must be exactly the same as was calculated during reload, 5459 or things will point to the wrong place. The only time we can safely 5460 ignore this constraint is when a function has no arguments on the stack, 5461 no stack frame requirement and no live registers execpt for `lr'. If we 5462 can guarantee that by making all function calls into tail calls and that 5463 lr is not clobbered in any other way, then there is no need to push lr 5464 onto the stack. */ 5465 5466void 5467output_func_prologue (f, frame_size) 5468 FILE *f; 5469 int frame_size; 5470{ 5471 int reg, live_regs_mask = 0; 5472 int volatile_func = (optimize > 0 5473 && TREE_THIS_VOLATILE (current_function_decl)); 5474 5475 /* Nonzero if we must stuff some register arguments onto the stack as if 5476 they were passed there. */ 5477 int store_arg_regs = 0; 5478 5479 if (arm_ccfsm_state || arm_target_insn) 5480 abort (); /* Sanity check */ 5481 5482 if (arm_naked_function_p (current_function_decl)) 5483 return; 5484 5485 return_used_this_function = 0; 5486 lr_save_eliminated = 0; 5487 5488 fprintf (f, "\t%s args = %d, pretend = %d, frame = %d\n", 5489 ASM_COMMENT_START, current_function_args_size, 5490 current_function_pretend_args_size, frame_size); 5491 fprintf (f, "\t%s frame_needed = %d, current_function_anonymous_args = %d\n", 5492 ASM_COMMENT_START, frame_pointer_needed, 5493 current_function_anonymous_args); 5494 5495 if (volatile_func) 5496 fprintf (f, "\t%s Volatile function.\n", ASM_COMMENT_START); 5497 5498 if (current_function_anonymous_args && current_function_pretend_args_size) 5499 store_arg_regs = 1; 5500 5501 for (reg = 0; reg <= 10; reg++) 5502 if (regs_ever_live[reg] && ! call_used_regs[reg]) 5503 live_regs_mask |= (1 << reg); 5504 5505 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) 5506 live_regs_mask |= (1 << PIC_OFFSET_TABLE_REGNUM); 5507 5508 if (frame_pointer_needed) 5509 live_regs_mask |= 0xD800; 5510 else if (regs_ever_live[14]) 5511 { 5512 if (! current_function_args_size 5513 && ! function_really_clobbers_lr (get_insns ())) 5514 lr_save_eliminated = 1; 5515 else 5516 live_regs_mask |= 0x4000; 5517 } 5518 5519 if (live_regs_mask) 5520 { 5521 /* if a di mode load/store multiple is used, and the base register 5522 is r3, then r4 can become an ever live register without lr 5523 doing so, in this case we need to push lr as well, or we 5524 will fail to get a proper return. */ 5525 5526 live_regs_mask |= 0x4000; 5527 lr_save_eliminated = 0; 5528 5529 } 5530 5531 if (lr_save_eliminated) 5532 fprintf (f,"\t%s I don't think this function clobbers lr\n", 5533 ASM_COMMENT_START); 5534 5535#ifdef AOF_ASSEMBLER 5536 if (flag_pic) 5537 fprintf (f, "\tmov\t%sip, %s%s\n", REGISTER_PREFIX, REGISTER_PREFIX, 5538 reg_names[PIC_OFFSET_TABLE_REGNUM]); 5539#endif 5540} 5541 5542 5543void 5544output_func_epilogue (f, frame_size) 5545 FILE *f; 5546 int frame_size; 5547{ 5548 int reg, live_regs_mask = 0; 5549 /* If we need this then it will always be at least this much */ 5550 int floats_offset = 12; 5551 rtx operands[3]; 5552 int volatile_func = (optimize > 0 5553 && TREE_THIS_VOLATILE (current_function_decl)); 5554 5555 if (use_return_insn (FALSE) && return_used_this_function) 5556 { 5557 if ((frame_size + current_function_outgoing_args_size) != 0 5558 && !(frame_pointer_needed && TARGET_APCS)) 5559 abort (); 5560 goto epilogue_done; 5561 } 5562 5563 /* Naked functions don't have epilogues. */ 5564 if (arm_naked_function_p (current_function_decl)) 5565 goto epilogue_done; 5566 5567 /* A volatile function should never return. Call abort. */ 5568 if (TARGET_ABORT_NORETURN && volatile_func) 5569 { 5570 rtx op; 5571 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_GOT ? "abort(PLT)" : "abort"); 5572 assemble_external_libcall (op); 5573 output_asm_insn ("bl\t%a0", &op); 5574 goto epilogue_done; 5575 } 5576 5577 for (reg = 0; reg <= 10; reg++) 5578 if (regs_ever_live[reg] && ! call_used_regs[reg]) 5579 { 5580 live_regs_mask |= (1 << reg); 5581 floats_offset += 4; 5582 } 5583 5584 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) 5585 { 5586 live_regs_mask |= (1 << PIC_OFFSET_TABLE_REGNUM); 5587 floats_offset += 4; 5588 } 5589 5590 if (frame_pointer_needed) 5591 { 5592 if (arm_fpu_arch == FP_SOFT2) 5593 { 5594 for (reg = 23; reg > 15; reg--) 5595 if (regs_ever_live[reg] && ! call_used_regs[reg]) 5596 { 5597 floats_offset += 12; 5598 fprintf (f, "\tldfe\t%s%s, [%sfp, #-%d]\n", REGISTER_PREFIX, 5599 reg_names[reg], REGISTER_PREFIX, floats_offset); 5600 } 5601 } 5602 else 5603 { 5604 int start_reg = 23; 5605 5606 for (reg = 23; reg > 15; reg--) 5607 { 5608 if (regs_ever_live[reg] && ! call_used_regs[reg]) 5609 { 5610 floats_offset += 12; 5611 /* We can't unstack more than four registers at once */ 5612 if (start_reg - reg == 3) 5613 { 5614 fprintf (f, "\tlfm\t%s%s, 4, [%sfp, #-%d]\n", 5615 REGISTER_PREFIX, reg_names[reg], 5616 REGISTER_PREFIX, floats_offset); 5617 start_reg = reg - 1; 5618 } 5619 } 5620 else 5621 { 5622 if (reg != start_reg) 5623 fprintf (f, "\tlfm\t%s%s, %d, [%sfp, #-%d]\n", 5624 REGISTER_PREFIX, reg_names[reg + 1], 5625 start_reg - reg, REGISTER_PREFIX, floats_offset); 5626 5627 start_reg = reg - 1; 5628 } 5629 } 5630 5631 /* Just in case the last register checked also needs unstacking. */ 5632 if (reg != start_reg) 5633 fprintf (f, "\tlfm\t%s%s, %d, [%sfp, #-%d]\n", 5634 REGISTER_PREFIX, reg_names[reg + 1], 5635 start_reg - reg, REGISTER_PREFIX, floats_offset); 5636 } 5637 5638 if (TARGET_THUMB_INTERWORK) 5639 { 5640 live_regs_mask |= 0x6800; 5641 print_multi_reg (f, "ldmea\t%sfp", live_regs_mask, FALSE); 5642 fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX); 5643 } 5644 else 5645 { 5646 live_regs_mask |= 0xA800; 5647 print_multi_reg (f, "ldmea\t%sfp", live_regs_mask, 5648 TARGET_APCS_32 ? FALSE : TRUE); 5649 } 5650 } 5651 else 5652 { 5653 /* Restore stack pointer if necessary. */ 5654 if (frame_size + current_function_outgoing_args_size != 0) 5655 { 5656 operands[0] = operands[1] = stack_pointer_rtx; 5657 operands[2] = GEN_INT (frame_size 5658 + current_function_outgoing_args_size); 5659 output_add_immediate (operands); 5660 } 5661 5662 if (arm_fpu_arch == FP_SOFT2) 5663 { 5664 for (reg = 16; reg < 24; reg++) 5665 if (regs_ever_live[reg] && ! call_used_regs[reg]) 5666 fprintf (f, "\tldfe\t%s%s, [%ssp], #12\n", REGISTER_PREFIX, 5667 reg_names[reg], REGISTER_PREFIX); 5668 } 5669 else 5670 { 5671 int start_reg = 16; 5672 5673 for (reg = 16; reg < 24; reg++) 5674 { 5675 if (regs_ever_live[reg] && ! call_used_regs[reg]) 5676 { 5677 if (reg - start_reg == 3) 5678 { 5679 fprintf (f, "\tlfmfd\t%s%s, 4, [%ssp]!\n", 5680 REGISTER_PREFIX, reg_names[start_reg], 5681 REGISTER_PREFIX); 5682 start_reg = reg + 1; 5683 } 5684 } 5685 else 5686 { 5687 if (reg != start_reg) 5688 fprintf (f, "\tlfmfd\t%s%s, %d, [%ssp]!\n", 5689 REGISTER_PREFIX, reg_names[start_reg], 5690 reg - start_reg, REGISTER_PREFIX); 5691 5692 start_reg = reg + 1; 5693 } 5694 } 5695 5696 /* Just in case the last register checked also needs unstacking. */ 5697 if (reg != start_reg) 5698 fprintf (f, "\tlfmfd\t%s%s, %d, [%ssp]!\n", 5699 REGISTER_PREFIX, reg_names[start_reg], 5700 reg - start_reg, REGISTER_PREFIX); 5701 } 5702 5703 if (current_function_pretend_args_size == 0 && regs_ever_live[14]) 5704 { 5705 if (TARGET_THUMB_INTERWORK) 5706 { 5707 if (! lr_save_eliminated) 5708 live_regs_mask |= 0x4000; 5709 5710 if (live_regs_mask != 0) 5711 print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask, FALSE); 5712 5713 fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX); 5714 } 5715 else if (lr_save_eliminated) 5716 fprintf (f, (TARGET_APCS_32 ? "\tmov\t%spc, %slr\n" 5717 : "\tmovs\t%spc, %slr\n"), 5718 REGISTER_PREFIX, REGISTER_PREFIX, f); 5719 else 5720 print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask | 0x8000, 5721 TARGET_APCS_32 ? FALSE : TRUE); 5722 } 5723 else 5724 { 5725 if (live_regs_mask || regs_ever_live[14]) 5726 { 5727 /* Restore the integer regs, and the return address into lr */ 5728 if (! lr_save_eliminated) 5729 live_regs_mask |= 0x4000; 5730 5731 if (live_regs_mask != 0) 5732 print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask, FALSE); 5733 } 5734 5735 if (current_function_pretend_args_size) 5736 { 5737 /* Unwind the pre-pushed regs */ 5738 operands[0] = operands[1] = stack_pointer_rtx; 5739 operands[2] = GEN_INT (current_function_pretend_args_size); 5740 output_add_immediate (operands); 5741 } 5742 /* And finally, go home */ 5743 if (TARGET_THUMB_INTERWORK) 5744 fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX); 5745 else if (TARGET_APCS_32) 5746 fprintf (f, "\tmov\t%spc, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX ); 5747 else 5748 fprintf (f, "\tmovs\t%spc, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX ); 5749 } 5750 } 5751 5752epilogue_done: 5753 5754 /* Reset the ARM-specific per-function variables. */ 5755 current_function_anonymous_args = 0; 5756 after_arm_reorg = 0; 5757} 5758 5759static void 5760emit_multi_reg_push (mask) 5761 int mask; 5762{ 5763 int num_regs = 0; 5764 int i, j; 5765 rtx par; 5766 5767 for (i = 0; i < 16; i++) 5768 if (mask & (1 << i)) 5769 num_regs++; 5770 5771 if (num_regs == 0 || num_regs > 16) 5772 abort (); 5773 5774 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs)); 5775 5776 for (i = 0; i < 16; i++) 5777 { 5778 if (mask & (1 << i)) 5779 { 5780 XVECEXP (par, 0, 0) 5781 = gen_rtx_SET (VOIDmode, 5782 gen_rtx_MEM (BLKmode, 5783 gen_rtx_PRE_DEC (BLKmode, 5784 stack_pointer_rtx)), 5785 gen_rtx_UNSPEC (BLKmode, 5786 gen_rtvec (1, 5787 gen_rtx_REG (SImode, i)), 5788 2)); 5789 break; 5790 } 5791 } 5792 5793 for (j = 1, i++; j < num_regs; i++) 5794 { 5795 if (mask & (1 << i)) 5796 { 5797 XVECEXP (par, 0, j) 5798 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, i)); 5799 j++; 5800 } 5801 } 5802 5803 emit_insn (par); 5804} 5805 5806static void 5807emit_sfm (base_reg, count) 5808 int base_reg; 5809 int count; 5810{ 5811 rtx par; 5812 int i; 5813 5814 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 5815 5816 XVECEXP (par, 0, 0) 5817 = gen_rtx_SET (VOIDmode, 5818 gen_rtx_MEM (BLKmode, 5819 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)), 5820 gen_rtx_UNSPEC (BLKmode, 5821 gen_rtvec (1, gen_rtx_REG (XFmode, 5822 base_reg++)), 5823 2)); 5824 for (i = 1; i < count; i++) 5825 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, 5826 gen_rtx_REG (XFmode, base_reg++)); 5827 5828 emit_insn (par); 5829} 5830 5831void 5832arm_expand_prologue () 5833{ 5834 int reg; 5835 rtx amount = GEN_INT (-(get_frame_size () 5836 + current_function_outgoing_args_size)); 5837 int live_regs_mask = 0; 5838 int store_arg_regs = 0; 5839 int volatile_func = (optimize > 0 5840 && TREE_THIS_VOLATILE (current_function_decl)); 5841 5842 /* Naked functions don't have prologues. */ 5843 if (arm_naked_function_p (current_function_decl)) 5844 return; 5845 5846 if (current_function_anonymous_args && current_function_pretend_args_size) 5847 store_arg_regs = 1; 5848 5849 if (! volatile_func) 5850 { 5851 for (reg = 0; reg <= 10; reg++) 5852 if (regs_ever_live[reg] && ! call_used_regs[reg]) 5853 live_regs_mask |= 1 << reg; 5854 5855 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) 5856 live_regs_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; 5857 5858 if (regs_ever_live[14]) 5859 live_regs_mask |= 0x4000; 5860 } 5861 5862 if (frame_pointer_needed) 5863 { 5864 live_regs_mask |= 0xD800; 5865 emit_insn (gen_movsi (gen_rtx_REG (SImode, 12), 5866 stack_pointer_rtx)); 5867 } 5868 5869 if (current_function_pretend_args_size) 5870 { 5871 if (store_arg_regs) 5872 emit_multi_reg_push ((0xf0 >> (current_function_pretend_args_size / 4)) 5873 & 0xf); 5874 else 5875 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, 5876 GEN_INT (-current_function_pretend_args_size))); 5877 } 5878 5879 if (live_regs_mask) 5880 { 5881 /* If we have to push any regs, then we must push lr as well, or 5882 we won't get a proper return. */ 5883 live_regs_mask |= 0x4000; 5884 emit_multi_reg_push (live_regs_mask); 5885 } 5886 5887 /* For now the integer regs are still pushed in output_func_epilogue (). */ 5888 5889 if (! volatile_func) 5890 { 5891 if (arm_fpu_arch == FP_SOFT2) 5892 { 5893 for (reg = 23; reg > 15; reg--) 5894 if (regs_ever_live[reg] && ! call_used_regs[reg]) 5895 emit_insn (gen_rtx_SET 5896 (VOIDmode, 5897 gen_rtx_MEM (XFmode, 5898 gen_rtx_PRE_DEC (XFmode, 5899 stack_pointer_rtx)), 5900 gen_rtx_REG (XFmode, reg))); 5901 } 5902 else 5903 { 5904 int start_reg = 23; 5905 5906 for (reg = 23; reg > 15; reg--) 5907 { 5908 if (regs_ever_live[reg] && ! call_used_regs[reg]) 5909 { 5910 if (start_reg - reg == 3) 5911 { 5912 emit_sfm (reg, 4); 5913 start_reg = reg - 1; 5914 } 5915 } 5916 else 5917 { 5918 if (start_reg != reg) 5919 emit_sfm (reg + 1, start_reg - reg); 5920 start_reg = reg - 1; 5921 } 5922 } 5923 5924 if (start_reg != reg) 5925 emit_sfm (reg + 1, start_reg - reg); 5926 } 5927 } 5928 5929 if (frame_pointer_needed) 5930 emit_insn (gen_addsi3 (hard_frame_pointer_rtx, gen_rtx_REG (SImode, 12), 5931 (GEN_INT 5932 (-(4 + current_function_pretend_args_size))))); 5933 5934 if (amount != const0_rtx) 5935 { 5936 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, amount)); 5937 emit_insn (gen_rtx_CLOBBER (VOIDmode, 5938 gen_rtx_MEM (BLKmode, stack_pointer_rtx))); 5939 } 5940 5941 /* If we are profiling, make sure no instructions are scheduled before 5942 the call to mcount. Similarly if the user has requested no 5943 scheduling in the prolog. */ 5944 if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO) 5945 emit_insn (gen_blockage ()); 5946} 5947 5948 5949/* If CODE is 'd', then the X is a condition operand and the instruction 5950 should only be executed if the condition is true. 5951 if CODE is 'D', then the X is a condition operand and the instruction 5952 should only be executed if the condition is false: however, if the mode 5953 of the comparison is CCFPEmode, then always execute the instruction -- we 5954 do this because in these circumstances !GE does not necessarily imply LT; 5955 in these cases the instruction pattern will take care to make sure that 5956 an instruction containing %d will follow, thereby undoing the effects of 5957 doing this instruction unconditionally. 5958 If CODE is 'N' then X is a floating point operand that must be negated 5959 before output. 5960 If CODE is 'B' then output a bitwise inverted value of X (a const int). 5961 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */ 5962 5963void 5964arm_print_operand (stream, x, code) 5965 FILE *stream; 5966 rtx x; 5967 int code; 5968{ 5969 switch (code) 5970 { 5971 case '@': 5972 fputs (ASM_COMMENT_START, stream); 5973 return; 5974 5975 case '|': 5976 fputs (REGISTER_PREFIX, stream); 5977 return; 5978 5979 case '?': 5980 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4) 5981 fputs (arm_condition_codes[arm_current_cc], stream); 5982 return; 5983 5984 case 'N': 5985 { 5986 REAL_VALUE_TYPE r; 5987 REAL_VALUE_FROM_CONST_DOUBLE (r, x); 5988 r = REAL_VALUE_NEGATE (r); 5989 fprintf (stream, "%s", fp_const_from_val (&r)); 5990 } 5991 return; 5992 5993 case 'B': 5994 if (GET_CODE (x) == CONST_INT) 5995 { 5996 HOST_WIDE_INT val; 5997 val = ARM_SIGN_EXTEND (~ INTVAL (x)); 5998 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val); 5999 } 6000 else 6001 { 6002 putc ('~', stream); 6003 output_addr_const (stream, x); 6004 } 6005 return; 6006 6007 case 'i': 6008 fprintf (stream, "%s", arithmetic_instr (x, 1)); 6009 return; 6010 6011 case 'I': 6012 fprintf (stream, "%s", arithmetic_instr (x, 0)); 6013 return; 6014 6015 case 'S': 6016 { 6017 HOST_WIDE_INT val; 6018 char * shift = shift_op (x, & val); 6019 6020 if (shift) 6021 { 6022 fprintf (stream, ", %s ", shift_op (x, & val)); 6023 if (val == -1) 6024 arm_print_operand (stream, XEXP (x, 1), 0); 6025 else 6026 { 6027 fputc ('#', stream); 6028 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val); 6029 } 6030 } 6031 } 6032 return; 6033 6034 case 'Q': 6035 if (REGNO (x) > 15) 6036 abort (); 6037 fputs (REGISTER_PREFIX, stream); 6038 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)], stream); 6039 return; 6040 6041 case 'R': 6042 if (REGNO (x) > 15) 6043 abort (); 6044 fputs (REGISTER_PREFIX, stream); 6045 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)], stream); 6046 return; 6047 6048 case 'm': 6049 fputs (REGISTER_PREFIX, stream); 6050 if (GET_CODE (XEXP (x, 0)) == REG) 6051 fputs (reg_names[REGNO (XEXP (x, 0))], stream); 6052 else 6053 fputs (reg_names[REGNO (XEXP (XEXP (x, 0), 0))], stream); 6054 return; 6055 6056 case 'M': 6057 fprintf (stream, "{%s%s-%s%s}", REGISTER_PREFIX, reg_names[REGNO (x)], 6058 REGISTER_PREFIX, reg_names[REGNO (x) - 1 6059 + ((GET_MODE_SIZE (GET_MODE (x)) 6060 + GET_MODE_SIZE (SImode) - 1) 6061 / GET_MODE_SIZE (SImode))]); 6062 return; 6063 6064 case 'd': 6065 if (x) 6066 fputs (arm_condition_codes[get_arm_condition_code (x)], 6067 stream); 6068 return; 6069 6070 case 'D': 6071 if (x) 6072 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE 6073 (get_arm_condition_code (x))], 6074 stream); 6075 return; 6076 6077 default: 6078 if (x == 0) 6079 abort (); 6080 6081 if (GET_CODE (x) == REG) 6082 { 6083 fputs (REGISTER_PREFIX, stream); 6084 fputs (reg_names[REGNO (x)], stream); 6085 } 6086 else if (GET_CODE (x) == MEM) 6087 { 6088 output_memory_reference_mode = GET_MODE (x); 6089 output_address (XEXP (x, 0)); 6090 } 6091 else if (GET_CODE (x) == CONST_DOUBLE) 6092 fprintf (stream, "#%s", fp_immediate_constant (x)); 6093 else if (GET_CODE (x) == NEG) 6094 abort (); /* This should never happen now. */ 6095 else 6096 { 6097 fputc ('#', stream); 6098 output_addr_const (stream, x); 6099 } 6100 } 6101} 6102 6103 6104/* A finite state machine takes care of noticing whether or not instructions 6105 can be conditionally executed, and thus decrease execution time and code 6106 size by deleting branch instructions. The fsm is controlled by 6107 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */ 6108 6109/* The state of the fsm controlling condition codes are: 6110 0: normal, do nothing special 6111 1: make ASM_OUTPUT_OPCODE not output this instruction 6112 2: make ASM_OUTPUT_OPCODE not output this instruction 6113 3: make instructions conditional 6114 4: make instructions conditional 6115 6116 State transitions (state->state by whom under condition): 6117 0 -> 1 final_prescan_insn if the `target' is a label 6118 0 -> 2 final_prescan_insn if the `target' is an unconditional branch 6119 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch 6120 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch 6121 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached 6122 (the target label has CODE_LABEL_NUMBER equal to arm_target_label). 6123 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached 6124 (the target insn is arm_target_insn). 6125 6126 If the jump clobbers the conditions then we use states 2 and 4. 6127 6128 A similar thing can be done with conditional return insns. 6129 6130 XXX In case the `target' is an unconditional branch, this conditionalising 6131 of the instructions always reduces code size, but not always execution 6132 time. But then, I want to reduce the code size to somewhere near what 6133 /bin/cc produces. */ 6134 6135/* Returns the index of the ARM condition code string in 6136 `arm_condition_codes'. COMPARISON should be an rtx like 6137 `(eq (...) (...))'. */ 6138 6139static enum arm_cond_code 6140get_arm_condition_code (comparison) 6141 rtx comparison; 6142{ 6143 enum machine_mode mode = GET_MODE (XEXP (comparison, 0)); 6144 register int code; 6145 register enum rtx_code comp_code = GET_CODE (comparison); 6146 6147 if (GET_MODE_CLASS (mode) != MODE_CC) 6148 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0), 6149 XEXP (comparison, 1)); 6150 6151 switch (mode) 6152 { 6153 case CC_DNEmode: code = ARM_NE; goto dominance; 6154 case CC_DEQmode: code = ARM_EQ; goto dominance; 6155 case CC_DGEmode: code = ARM_GE; goto dominance; 6156 case CC_DGTmode: code = ARM_GT; goto dominance; 6157 case CC_DLEmode: code = ARM_LE; goto dominance; 6158 case CC_DLTmode: code = ARM_LT; goto dominance; 6159 case CC_DGEUmode: code = ARM_CS; goto dominance; 6160 case CC_DGTUmode: code = ARM_HI; goto dominance; 6161 case CC_DLEUmode: code = ARM_LS; goto dominance; 6162 case CC_DLTUmode: code = ARM_CC; 6163 6164 dominance: 6165 if (comp_code != EQ && comp_code != NE) 6166 abort (); 6167 6168 if (comp_code == EQ) 6169 return ARM_INVERSE_CONDITION_CODE (code); 6170 return code; 6171 6172 case CC_NOOVmode: 6173 switch (comp_code) 6174 { 6175 case NE: return ARM_NE; 6176 case EQ: return ARM_EQ; 6177 case GE: return ARM_PL; 6178 case LT: return ARM_MI; 6179 default: abort (); 6180 } 6181 6182 case CC_Zmode: 6183 case CCFPmode: 6184 switch (comp_code) 6185 { 6186 case NE: return ARM_NE; 6187 case EQ: return ARM_EQ; 6188 default: abort (); 6189 } 6190 6191 case CCFPEmode: 6192 switch (comp_code) 6193 { 6194 case GE: return ARM_GE; 6195 case GT: return ARM_GT; 6196 case LE: return ARM_LS; 6197 case LT: return ARM_MI; 6198 default: abort (); 6199 } 6200 6201 case CC_SWPmode: 6202 switch (comp_code) 6203 { 6204 case NE: return ARM_NE; 6205 case EQ: return ARM_EQ; 6206 case GE: return ARM_LE; 6207 case GT: return ARM_LT; 6208 case LE: return ARM_GE; 6209 case LT: return ARM_GT; 6210 case GEU: return ARM_LS; 6211 case GTU: return ARM_CC; 6212 case LEU: return ARM_CS; 6213 case LTU: return ARM_HI; 6214 default: abort (); 6215 } 6216 6217 case CC_Cmode: 6218 switch (comp_code) 6219 { 6220 case LTU: return ARM_CS; 6221 case GEU: return ARM_CC; 6222 default: abort (); 6223 } 6224 6225 case CCmode: 6226 switch (comp_code) 6227 { 6228 case NE: return ARM_NE; 6229 case EQ: return ARM_EQ; 6230 case GE: return ARM_GE; 6231 case GT: return ARM_GT; 6232 case LE: return ARM_LE; 6233 case LT: return ARM_LT; 6234 case GEU: return ARM_CS; 6235 case GTU: return ARM_HI; 6236 case LEU: return ARM_LS; 6237 case LTU: return ARM_CC; 6238 default: abort (); 6239 } 6240 6241 default: abort (); 6242 } 6243 6244 abort (); 6245} 6246 6247 6248void 6249arm_final_prescan_insn (insn) 6250 rtx insn; 6251{ 6252 /* BODY will hold the body of INSN. */ 6253 register rtx body = PATTERN (insn); 6254 6255 /* This will be 1 if trying to repeat the trick, and things need to be 6256 reversed if it appears to fail. */ 6257 int reverse = 0; 6258 6259 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is 6260 taken are clobbered, even if the rtl suggests otherwise. It also 6261 means that we have to grub around within the jump expression to find 6262 out what the conditions are when the jump isn't taken. */ 6263 int jump_clobbers = 0; 6264 6265 /* If we start with a return insn, we only succeed if we find another one. */ 6266 int seeking_return = 0; 6267 6268 /* START_INSN will hold the insn from where we start looking. This is the 6269 first insn after the following code_label if REVERSE is true. */ 6270 rtx start_insn = insn; 6271 6272 /* If in state 4, check if the target branch is reached, in order to 6273 change back to state 0. */ 6274 if (arm_ccfsm_state == 4) 6275 { 6276 if (insn == arm_target_insn) 6277 { 6278 arm_target_insn = NULL; 6279 arm_ccfsm_state = 0; 6280 } 6281 return; 6282 } 6283 6284 /* If in state 3, it is possible to repeat the trick, if this insn is an 6285 unconditional branch to a label, and immediately following this branch 6286 is the previous target label which is only used once, and the label this 6287 branch jumps to is not too far off. */ 6288 if (arm_ccfsm_state == 3) 6289 { 6290 if (simplejump_p (insn)) 6291 { 6292 start_insn = next_nonnote_insn (start_insn); 6293 if (GET_CODE (start_insn) == BARRIER) 6294 { 6295 /* XXX Isn't this always a barrier? */ 6296 start_insn = next_nonnote_insn (start_insn); 6297 } 6298 if (GET_CODE (start_insn) == CODE_LABEL 6299 && CODE_LABEL_NUMBER (start_insn) == arm_target_label 6300 && LABEL_NUSES (start_insn) == 1) 6301 reverse = TRUE; 6302 else 6303 return; 6304 } 6305 else if (GET_CODE (body) == RETURN) 6306 { 6307 start_insn = next_nonnote_insn (start_insn); 6308 if (GET_CODE (start_insn) == BARRIER) 6309 start_insn = next_nonnote_insn (start_insn); 6310 if (GET_CODE (start_insn) == CODE_LABEL 6311 && CODE_LABEL_NUMBER (start_insn) == arm_target_label 6312 && LABEL_NUSES (start_insn) == 1) 6313 { 6314 reverse = TRUE; 6315 seeking_return = 1; 6316 } 6317 else 6318 return; 6319 } 6320 else 6321 return; 6322 } 6323 6324 if (arm_ccfsm_state != 0 && !reverse) 6325 abort (); 6326 if (GET_CODE (insn) != JUMP_INSN) 6327 return; 6328 6329 /* This jump might be paralleled with a clobber of the condition codes 6330 the jump should always come first */ 6331 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) 6332 body = XVECEXP (body, 0, 0); 6333 6334#if 0 6335 /* If this is a conditional return then we don't want to know */ 6336 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC 6337 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE 6338 && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN 6339 || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)) 6340 return; 6341#endif 6342 6343 if (reverse 6344 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC 6345 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE)) 6346 { 6347 int insns_skipped; 6348 int fail = FALSE, succeed = FALSE; 6349 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */ 6350 int then_not_else = TRUE; 6351 rtx this_insn = start_insn, label = 0; 6352 6353 if (get_attr_conds (insn) == CONDS_JUMP_CLOB) 6354 { 6355 /* The code below is wrong for these, and I haven't time to 6356 fix it now. So we just do the safe thing and return. This 6357 whole function needs re-writing anyway. */ 6358 jump_clobbers = 1; 6359 return; 6360 } 6361 6362 /* Register the insn jumped to. */ 6363 if (reverse) 6364 { 6365 if (!seeking_return) 6366 label = XEXP (SET_SRC (body), 0); 6367 } 6368 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF) 6369 label = XEXP (XEXP (SET_SRC (body), 1), 0); 6370 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF) 6371 { 6372 label = XEXP (XEXP (SET_SRC (body), 2), 0); 6373 then_not_else = FALSE; 6374 } 6375 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN) 6376 seeking_return = 1; 6377 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN) 6378 { 6379 seeking_return = 1; 6380 then_not_else = FALSE; 6381 } 6382 else 6383 abort (); 6384 6385 /* See how many insns this branch skips, and what kind of insns. If all 6386 insns are okay, and the label or unconditional branch to the same 6387 label is not too far away, succeed. */ 6388 for (insns_skipped = 0; 6389 !fail && !succeed && insns_skipped++ < max_insns_skipped;) 6390 { 6391 rtx scanbody; 6392 6393 this_insn = next_nonnote_insn (this_insn); 6394 if (!this_insn) 6395 break; 6396 6397 switch (GET_CODE (this_insn)) 6398 { 6399 case CODE_LABEL: 6400 /* Succeed if it is the target label, otherwise fail since 6401 control falls in from somewhere else. */ 6402 if (this_insn == label) 6403 { 6404 if (jump_clobbers) 6405 { 6406 arm_ccfsm_state = 2; 6407 this_insn = next_nonnote_insn (this_insn); 6408 } 6409 else 6410 arm_ccfsm_state = 1; 6411 succeed = TRUE; 6412 } 6413 else 6414 fail = TRUE; 6415 break; 6416 6417 case BARRIER: 6418 /* Succeed if the following insn is the target label. 6419 Otherwise fail. 6420 If return insns are used then the last insn in a function 6421 will be a barrier. */ 6422 this_insn = next_nonnote_insn (this_insn); 6423 if (this_insn && this_insn == label) 6424 { 6425 if (jump_clobbers) 6426 { 6427 arm_ccfsm_state = 2; 6428 this_insn = next_nonnote_insn (this_insn); 6429 } 6430 else 6431 arm_ccfsm_state = 1; 6432 succeed = TRUE; 6433 } 6434 else 6435 fail = TRUE; 6436 break; 6437 6438 case CALL_INSN: 6439 /* If using 32-bit addresses the cc is not preserved over 6440 calls */ 6441 if (TARGET_APCS_32) 6442 { 6443 /* Succeed if the following insn is the target label, 6444 or if the following two insns are a barrier and 6445 the target label. */ 6446 this_insn = next_nonnote_insn (this_insn); 6447 if (this_insn && GET_CODE (this_insn) == BARRIER) 6448 this_insn = next_nonnote_insn (this_insn); 6449 6450 if (this_insn && this_insn == label 6451 && insns_skipped < max_insns_skipped) 6452 { 6453 if (jump_clobbers) 6454 { 6455 arm_ccfsm_state = 2; 6456 this_insn = next_nonnote_insn (this_insn); 6457 } 6458 else 6459 arm_ccfsm_state = 1; 6460 succeed = TRUE; 6461 } 6462 else 6463 fail = TRUE; 6464 } 6465 break; 6466 6467 case JUMP_INSN: 6468 /* If this is an unconditional branch to the same label, succeed. 6469 If it is to another label, do nothing. If it is conditional, 6470 fail. */ 6471 /* XXX Probably, the tests for SET and the PC are unnecessary. */ 6472 6473 scanbody = PATTERN (this_insn); 6474 if (GET_CODE (scanbody) == SET 6475 && GET_CODE (SET_DEST (scanbody)) == PC) 6476 { 6477 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF 6478 && XEXP (SET_SRC (scanbody), 0) == label && !reverse) 6479 { 6480 arm_ccfsm_state = 2; 6481 succeed = TRUE; 6482 } 6483 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE) 6484 fail = TRUE; 6485 } 6486 /* Fail if a conditional return is undesirable (eg on a 6487 StrongARM), but still allow this if optimizing for size. */ 6488 else if (GET_CODE (scanbody) == RETURN 6489 && ! use_return_insn (TRUE) 6490 && ! optimize_size) 6491 fail = TRUE; 6492 else if (GET_CODE (scanbody) == RETURN 6493 && seeking_return) 6494 { 6495 arm_ccfsm_state = 2; 6496 succeed = TRUE; 6497 } 6498 else if (GET_CODE (scanbody) == PARALLEL) 6499 { 6500 switch (get_attr_conds (this_insn)) 6501 { 6502 case CONDS_NOCOND: 6503 break; 6504 default: 6505 fail = TRUE; 6506 break; 6507 } 6508 } 6509 break; 6510 6511 case INSN: 6512 /* Instructions using or affecting the condition codes make it 6513 fail. */ 6514 scanbody = PATTERN (this_insn); 6515 if (! (GET_CODE (scanbody) == SET 6516 || GET_CODE (scanbody) == PARALLEL) 6517 || get_attr_conds (this_insn) != CONDS_NOCOND) 6518 fail = TRUE; 6519 break; 6520 6521 default: 6522 break; 6523 } 6524 } 6525 if (succeed) 6526 { 6527 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse)) 6528 arm_target_label = CODE_LABEL_NUMBER (label); 6529 else if (seeking_return || arm_ccfsm_state == 2) 6530 { 6531 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE) 6532 { 6533 this_insn = next_nonnote_insn (this_insn); 6534 if (this_insn && (GET_CODE (this_insn) == BARRIER 6535 || GET_CODE (this_insn) == CODE_LABEL)) 6536 abort (); 6537 } 6538 if (!this_insn) 6539 { 6540 /* Oh, dear! we ran off the end.. give up */ 6541 recog (PATTERN (insn), insn, NULL_PTR); 6542 arm_ccfsm_state = 0; 6543 arm_target_insn = NULL; 6544 return; 6545 } 6546 arm_target_insn = this_insn; 6547 } 6548 else 6549 abort (); 6550 if (jump_clobbers) 6551 { 6552 if (reverse) 6553 abort (); 6554 arm_current_cc = 6555 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body), 6556 0), 0), 1)); 6557 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND) 6558 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); 6559 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE) 6560 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); 6561 } 6562 else 6563 { 6564 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from 6565 what it was. */ 6566 if (!reverse) 6567 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body), 6568 0)); 6569 } 6570 6571 if (reverse || then_not_else) 6572 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); 6573 } 6574 /* restore recog_operand (getting the attributes of other insns can 6575 destroy this array, but final.c assumes that it remains intact 6576 across this call; since the insn has been recognized already we 6577 call recog direct). */ 6578 recog (PATTERN (insn), insn, NULL_PTR); 6579 } 6580} 6581 6582#ifdef AOF_ASSEMBLER 6583/* Special functions only needed when producing AOF syntax assembler. */ 6584 6585rtx aof_pic_label = NULL_RTX; 6586struct pic_chain 6587{ 6588 struct pic_chain *next; 6589 char *symname; 6590}; 6591 6592static struct pic_chain *aof_pic_chain = NULL; 6593 6594rtx 6595aof_pic_entry (x) 6596 rtx x; 6597{ 6598 struct pic_chain **chainp; 6599 int offset; 6600 6601 if (aof_pic_label == NULL_RTX) 6602 { 6603 /* This needs to persist throughout the compilation. */ 6604 end_temporary_allocation (); 6605 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons"); 6606 resume_temporary_allocation (); 6607 } 6608 6609 for (offset = 0, chainp = &aof_pic_chain; *chainp; 6610 offset += 4, chainp = &(*chainp)->next) 6611 if ((*chainp)->symname == XSTR (x, 0)) 6612 return plus_constant (aof_pic_label, offset); 6613 6614 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain)); 6615 (*chainp)->next = NULL; 6616 (*chainp)->symname = XSTR (x, 0); 6617 return plus_constant (aof_pic_label, offset); 6618} 6619 6620void 6621aof_dump_pic_table (f) 6622 FILE *f; 6623{ 6624 struct pic_chain *chain; 6625 6626 if (aof_pic_chain == NULL) 6627 return; 6628 6629 fprintf (f, "\tAREA |%s$$adcons|, BASED %s%s\n", 6630 reg_names[PIC_OFFSET_TABLE_REGNUM], REGISTER_PREFIX, 6631 reg_names[PIC_OFFSET_TABLE_REGNUM]); 6632 fputs ("|x$adcons|\n", f); 6633 6634 for (chain = aof_pic_chain; chain; chain = chain->next) 6635 { 6636 fputs ("\tDCD\t", f); 6637 assemble_name (f, chain->symname); 6638 fputs ("\n", f); 6639 } 6640} 6641 6642int arm_text_section_count = 1; 6643 6644char * 6645aof_text_section () 6646{ 6647 static char buf[100]; 6648 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY", 6649 arm_text_section_count++); 6650 if (flag_pic) 6651 strcat (buf, ", PIC, REENTRANT"); 6652 return buf; 6653} 6654 6655static int arm_data_section_count = 1; 6656 6657char * 6658aof_data_section () 6659{ 6660 static char buf[100]; 6661 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++); 6662 return buf; 6663} 6664 6665/* The AOF assembler is religiously strict about declarations of 6666 imported and exported symbols, so that it is impossible to declare 6667 a function as imported near the beginning of the file, and then to 6668 export it later on. It is, however, possible to delay the decision 6669 until all the functions in the file have been compiled. To get 6670 around this, we maintain a list of the imports and exports, and 6671 delete from it any that are subsequently defined. At the end of 6672 compilation we spit the remainder of the list out before the END 6673 directive. */ 6674 6675struct import 6676{ 6677 struct import *next; 6678 char *name; 6679}; 6680 6681static struct import *imports_list = NULL; 6682 6683void 6684aof_add_import (name) 6685 char *name; 6686{ 6687 struct import *new; 6688 6689 for (new = imports_list; new; new = new->next) 6690 if (new->name == name) 6691 return; 6692 6693 new = (struct import *) xmalloc (sizeof (struct import)); 6694 new->next = imports_list; 6695 imports_list = new; 6696 new->name = name; 6697} 6698 6699void 6700aof_delete_import (name) 6701 char *name; 6702{ 6703 struct import **old; 6704 6705 for (old = &imports_list; *old; old = & (*old)->next) 6706 { 6707 if ((*old)->name == name) 6708 { 6709 *old = (*old)->next; 6710 return; 6711 } 6712 } 6713} 6714 6715int arm_main_function = 0; 6716 6717void 6718aof_dump_imports (f) 6719 FILE *f; 6720{ 6721 /* The AOF assembler needs this to cause the startup code to be extracted 6722 from the library. Brining in __main causes the whole thing to work 6723 automagically. */ 6724 if (arm_main_function) 6725 { 6726 text_section (); 6727 fputs ("\tIMPORT __main\n", f); 6728 fputs ("\tDCD __main\n", f); 6729 } 6730 6731 /* Now dump the remaining imports. */ 6732 while (imports_list) 6733 { 6734 fprintf (f, "\tIMPORT\t"); 6735 assemble_name (f, imports_list->name); 6736 fputc ('\n', f); 6737 imports_list = imports_list->next; 6738 } 6739} 6740#endif /* AOF_ASSEMBLER */ 6741