1@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001, 2@c 2002, 2003, 2004 3@c Free Software Foundation, Inc. 4@c This is part of the GAS manual. 5@c For copying conditions, see the file as.texinfo. 6@ifset GENERIC 7@page 8@node MIPS-Dependent 9@chapter MIPS Dependent Features 10@end ifset 11@ifclear GENERIC 12@node Machine Dependencies 13@chapter MIPS Dependent Features 14@end ifclear 15 16@cindex MIPS processor 17@sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several 18different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32, 19and MIPS64. For information about the @sc{mips} instruction set, see 20@cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall). 21For an overview of @sc{mips} assembly conventions, see ``Appendix D: 22Assembly Language Programming'' in the same work. 23 24@menu 25* MIPS Opts:: Assembler options 26* MIPS Object:: ECOFF object code 27* MIPS Stabs:: Directives for debugging information 28* MIPS ISA:: Directives to override the ISA level 29* MIPS symbol sizes:: Directives to override the size of symbols 30* MIPS autoextend:: Directives for extending MIPS 16 bit instructions 31* MIPS insn:: Directive to mark data as an instruction 32* MIPS option stack:: Directives to save and restore options 33* MIPS ASE instruction generation overrides:: Directives to control 34 generation of MIPS ASE instructions 35@end menu 36 37@node MIPS Opts 38@section Assembler options 39 40The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these 41special options: 42 43@table @code 44@cindex @code{-G} option (MIPS) 45@item -G @var{num} 46This option sets the largest size of an object that can be referenced 47implicitly with the @code{gp} register. It is only accepted for targets 48that use @sc{ecoff} format. The default value is 8. 49 50@cindex @code{-EB} option (MIPS) 51@cindex @code{-EL} option (MIPS) 52@cindex MIPS big-endian output 53@cindex MIPS little-endian output 54@cindex big-endian output, MIPS 55@cindex little-endian output, MIPS 56@item -EB 57@itemx -EL 58Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or 59little-endian output at run time (unlike the other @sc{gnu} development 60tools, which must be configured for one or the other). Use @samp{-EB} 61to select big-endian output, and @samp{-EL} for little-endian. 62 63@cindex MIPS architecture options 64@item -mips1 65@itemx -mips2 66@itemx -mips3 67@itemx -mips4 68@itemx -mips5 69@itemx -mips32 70@itemx -mips32r2 71@itemx -mips64 72@itemx -mips64r2 73Generate code for a particular MIPS Instruction Set Architecture level. 74@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors, 75@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the 76@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and 77@sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, 78@samp{-mips64}, and @samp{-mips64r2} 79correspond to generic 80@sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64}, 81and @sc{MIPS64 Release 2} 82ISA processors, respectively. You can also switch 83instruction sets during the assembly; see @ref{MIPS ISA, Directives to 84override the ISA level}. 85 86@item -mgp32 87@itemx -mfp32 88Some macros have different expansions for 32-bit and 64-bit registers. 89The register sizes are normally inferred from the ISA and ABI, but these 90flags force a certain group of registers to be treated as 32 bits wide at 91all times. @samp{-mgp32} controls the size of general-purpose registers 92and @samp{-mfp32} controls the size of floating-point registers. 93 94On some MIPS variants there is a 32-bit mode flag; when this flag is 95set, 64-bit instructions generate a trap. Also, some 32-bit OSes only 96save the 32-bit registers on a context switch, so it is essential never 97to use the 64-bit registers. 98 99@item -mgp64 100Assume that 64-bit general purpose registers are available. This is 101provided in the interests of symmetry with -gp32. 102 103@item -mips16 104@itemx -no-mips16 105Generate code for the MIPS 16 processor. This is equivalent to putting 106@samp{.set mips16} at the start of the assembly file. @samp{-no-mips16} 107turns off this option. 108 109@item -mips3d 110@itemx -no-mips3d 111Generate code for the MIPS-3D Application Specific Extension. 112This tells the assembler to accept MIPS-3D instructions. 113@samp{-no-mips3d} turns off this option. 114 115@item -mdmx 116@itemx -no-mdmx 117Generate code for the MDMX Application Specific Extension. 118This tells the assembler to accept MDMX instructions. 119@samp{-no-mdmx} turns off this option. 120 121@item -mdsp 122@itemx -mno-dsp 123Generate code for the DSP Application Specific Extension. 124This tells the assembler to accept DSP instructions. 125@samp{-mno-dsp} turns off this option. 126 127@item -mmt 128@itemx -mno-mt 129Generate code for the MT Application Specific Extension. 130This tells the assembler to accept MT instructions. 131@samp{-mno-mt} turns off this option. 132 133@item -mfix7000 134@itemx -mno-fix7000 135Cause nops to be inserted if the read of the destination register 136of an mfhi or mflo instruction occurs in the following two instructions. 137 138@item -mfix-vr4120 139@itemx -no-mfix-vr4120 140Insert nops to work around certain VR4120 errata. This option is 141intended to be used on GCC-generated code: it is not designed to catch 142all problems in hand-written assembler code. 143 144@item -mfix-vr4130 145@itemx -no-mfix-vr4130 146Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata. 147 148@item -m4010 149@itemx -no-m4010 150Generate code for the LSI @sc{r4010} chip. This tells the assembler to 151accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc}, 152etc.), and to not schedule @samp{nop} instructions around accesses to 153the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this 154option. 155 156@item -m4650 157@itemx -no-m4650 158Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept 159the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} 160instructions around accesses to the @samp{HI} and @samp{LO} registers. 161@samp{-no-m4650} turns off this option. 162 163@itemx -m3900 164@itemx -no-m3900 165@itemx -m4100 166@itemx -no-m4100 167For each option @samp{-m@var{nnnn}}, generate code for the MIPS 168@sc{r@var{nnnn}} chip. This tells the assembler to accept instructions 169specific to that chip, and to schedule for that chip's hazards. 170 171@item -march=@var{cpu} 172Generate code for a particular MIPS cpu. It is exactly equivalent to 173@samp{-m@var{cpu}}, except that there are more value of @var{cpu} 174understood. Valid @var{cpu} value are: 175 176@quotation 1772000, 1783000, 1793900, 1804000, 1814010, 1824100, 1834111, 184vr4120, 185vr4130, 186vr4181, 1874300, 1884400, 1894600, 1904650, 1915000, 192rm5200, 193rm5230, 194rm5231, 195rm5261, 196rm5721, 197vr5400, 198vr5500, 1996000, 200rm7000, 2018000, 202rm9000, 20310000, 20412000, 205mips32-4k, 206sb1 207@end quotation 208 209@item -mtune=@var{cpu} 210Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are 211identical to @samp{-march=@var{cpu}}. 212 213@item -mabi=@var{abi} 214Record which ABI the source code uses. The recognized arguments 215are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}. 216 217@item -msym32 218@itemx -mno-sym32 219@cindex -msym32 220@cindex -mno-sym32 221Equivalent to adding @code{.set sym32} or @code{.set nosym32} to 222the beginning of the assembler input. @xref{MIPS symbol sizes}. 223 224@cindex @code{-nocpp} ignored (MIPS) 225@item -nocpp 226This option is ignored. It is accepted for command-line compatibility with 227other assemblers, which use it to turn off C style preprocessing. With 228@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the 229@sc{gnu} assembler itself never runs the C preprocessor. 230 231@item --construct-floats 232@itemx --no-construct-floats 233@cindex --construct-floats 234@cindex --no-construct-floats 235The @code{--no-construct-floats} option disables the construction of 236double width floating point constants by loading the two halves of the 237value into the two single width floating point registers that make up 238the double width register. This feature is useful if the processor 239support the FR bit in its status register, and this bit is known (by 240the programmer) to be set. This bit prevents the aliasing of the double 241width register by the single width registers. 242 243By default @code{--construct-floats} is selected, allowing construction 244of these floating point constants. 245 246@item --trap 247@itemx --no-break 248@c FIXME! (1) reflect these options (next item too) in option summaries; 249@c (2) stop teasing, say _which_ instructions expanded _how_. 250@code{@value{AS}} automatically macro expands certain division and 251multiplication instructions to check for overflow and division by zero. This 252option causes @code{@value{AS}} to generate code to take a trap exception 253rather than a break exception when an error is detected. The trap instructions 254are only supported at Instruction Set Architecture level 2 and higher. 255 256@item --break 257@itemx --no-trap 258Generate code to take a break exception rather than a trap exception when an 259error is detected. This is the default. 260 261@item -mpdr 262@itemx -mno-pdr 263Control generation of @code{.pdr} sections. Off by default on IRIX, on 264elsewhere. 265 266@item -mshared 267@itemx -mno-shared 268When generating code using the Unix calling conventions (selected by 269@samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code 270which can go into a shared library. The @samp{-mno-shared} option 271tells gas to generate code which uses the calling convention, but can 272not go into a shared library. The resulting code is slightly more 273efficient. This option only affects the handling of the 274@samp{.cpload} and @samp{.cpsetup} pseudo-ops. 275@end table 276 277@node MIPS Object 278@section MIPS ECOFF object code 279 280@cindex ECOFF sections 281@cindex MIPS ECOFF sections 282Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections 283besides the usual @code{.text}, @code{.data} and @code{.bss}. The 284additional sections are @code{.rdata}, used for read-only data, 285@code{.sdata}, used for small data, and @code{.sbss}, used for small 286common objects. 287 288@cindex small objects, MIPS ECOFF 289@cindex @code{gp} register, MIPS 290When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28}) 291register to form the address of a ``small object''. Any object in the 292@code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense. 293For external objects, or for objects in the @code{.bss} section, you can use 294the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via 295@code{$gp}; the default value is 8, meaning that a reference to any object 296eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to 297@code{@value{AS}} prevents it from using the @code{$gp} register on the basis 298of object size (but the assembler uses @code{$gp} for objects in @code{.sdata} 299or @code{sbss} in any case). The size of an object in the @code{.bss} section 300is set by the @code{.comm} or @code{.lcomm} directive that defines it. The 301size of an external object may be set with the @code{.extern} directive. For 302example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes 303in length, whie leaving @code{sym} otherwise undefined. 304 305Using small @sc{ecoff} objects requires linker support, and assumes that the 306@code{$gp} register is correctly initialized (normally done automatically by 307the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the 308@code{$gp} register. 309 310@node MIPS Stabs 311@section Directives for debugging information 312 313@cindex MIPS debugging directives 314@sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for 315generating debugging information which are not support by traditional @sc{mips} 316assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file}, 317@code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val}, 318@code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information 319generated by the three @code{.stab} directives can only be read by @sc{gdb}, 320not by traditional @sc{mips} debuggers (this enhancement is required to fully 321support C++ debugging). These directives are primarily used by compilers, not 322assembly language programmers! 323 324@node MIPS symbol sizes 325@section Directives to override the size of symbols 326 327@cindex @code{.set sym32} 328@cindex @code{.set nosym32} 329The n64 ABI allows symbols to have any 64-bit value. Although this 330provides a great deal of flexibility, it means that some macros have 331much longer expansions than their 32-bit counterparts. For example, 332the non-PIC expansion of @samp{dla $4,sym} is usually: 333 334@smallexample 335lui $4,%highest(sym) 336lui $1,%hi(sym) 337daddiu $4,$4,%higher(sym) 338daddiu $1,$1,%lo(sym) 339dsll32 $4,$4,0 340daddu $4,$4,$1 341@end smallexample 342 343whereas the 32-bit expansion is simply: 344 345@smallexample 346lui $4,%hi(sym) 347daddiu $4,$4,%lo(sym) 348@end smallexample 349 350n64 code is sometimes constructed in such a way that all symbolic 351constants are known to have 32-bit values, and in such cases, it's 352preferable to use the 32-bit expansion instead of the 64-bit 353expansion. 354 355You can use the @code{.set sym32} directive to tell the assembler 356that, from this point on, all expressions of the form 357@samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}} 358have 32-bit values. For example: 359 360@smallexample 361.set sym32 362dla $4,sym 363lw $4,sym+16 364sw $4,sym+0x8000($4) 365@end smallexample 366 367will cause the assembler to treat @samp{sym}, @code{sym+16} and 368@code{sym+0x8000} as 32-bit values. The handling of non-symbolic 369addresses is not affected. 370 371The directive @code{.set nosym32} ends a @code{.set sym32} block and 372reverts to the normal behavior. It is also possible to change the 373symbol size using the command-line options @option{-msym32} and 374@option{-mno-sym32}. 375 376These options and directives are always accepted, but at present, 377they have no effect for anything other than n64. 378 379@node MIPS ISA 380@section Directives to override the ISA level 381 382@cindex MIPS ISA override 383@kindex @code{.set mips@var{n}} 384@sc{gnu} @code{@value{AS}} supports an additional directive to change 385the @sc{mips} Instruction Set Architecture level on the fly: @code{.set 386mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64 387or 64r2. 388The values other than 0 make the assembler accept instructions 389for the corresponding @sc{isa} level, from that point on in the 390assembly. @code{.set mips@var{n}} affects not only which instructions 391are permitted, but also how certain macros are expanded. @code{.set 392mips0} restores the @sc{isa} level to its original level: either the 393level you selected with command line options, or the default for your 394configuration. You can use this feature to permit specific @sc{r4000} 395instructions while assembling in 32 bit mode. Use this directive with 396care! 397 398The directive @samp{.set mips16} puts the assembler into MIPS 16 mode, 399in which it will assemble instructions for the MIPS 16 processor. Use 400@samp{.set nomips16} to return to normal 32 bit mode. 401 402Traditional @sc{mips} assemblers do not support this directive. 403 404@node MIPS autoextend 405@section Directives for extending MIPS 16 bit instructions 406 407@kindex @code{.set autoextend} 408@kindex @code{.set noautoextend} 409By default, MIPS 16 instructions are automatically extended to 32 bits 410when necessary. The directive @samp{.set noautoextend} will turn this 411off. When @samp{.set noautoextend} is in effect, any 32 bit instruction 412must be explicitly extended with the @samp{.e} modifier (e.g., 413@samp{li.e $4,1000}). The directive @samp{.set autoextend} may be used 414to once again automatically extend instructions when necessary. 415 416This directive is only meaningful when in MIPS 16 mode. Traditional 417@sc{mips} assemblers do not support this directive. 418 419@node MIPS insn 420@section Directive to mark data as an instruction 421 422@kindex @code{.insn} 423The @code{.insn} directive tells @code{@value{AS}} that the following 424data is actually instructions. This makes a difference in MIPS 16 mode: 425when loading the address of a label which precedes instructions, 426@code{@value{AS}} automatically adds 1 to the value, so that jumping to 427the loaded address will do the right thing. 428 429@node MIPS option stack 430@section Directives to save and restore options 431 432@cindex MIPS option stack 433@kindex @code{.set push} 434@kindex @code{.set pop} 435The directives @code{.set push} and @code{.set pop} may be used to save 436and restore the current settings for all the options which are 437controlled by @code{.set}. The @code{.set push} directive saves the 438current settings on a stack. The @code{.set pop} directive pops the 439stack and restores the settings. 440 441These directives can be useful inside an macro which must change an 442option such as the ISA level or instruction reordering but does not want 443to change the state of the code which invoked the macro. 444 445Traditional @sc{mips} assemblers do not support these directives. 446 447@node MIPS ASE instruction generation overrides 448@section Directives to control generation of MIPS ASE instructions 449 450@cindex MIPS MIPS-3D instruction generation override 451@kindex @code{.set mips3d} 452@kindex @code{.set nomips3d} 453The directive @code{.set mips3d} makes the assembler accept instructions 454from the MIPS-3D Application Specific Extension from that point on 455in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D 456instructions from being accepted. 457 458@cindex MIPS MDMX instruction generation override 459@kindex @code{.set mdmx} 460@kindex @code{.set nomdmx} 461The directive @code{.set mdmx} makes the assembler accept instructions 462from the MDMX Application Specific Extension from that point on 463in the assembly. The @code{.set nomdmx} directive prevents MDMX 464instructions from being accepted. 465 466@cindex MIPS DSP instruction generation override 467@kindex @code{.set dsp} 468@kindex @code{.set nodsp} 469The directive @code{.set dsp} makes the assembler accept instructions 470from the DSP Application Specific Extension from that point on 471in the assembly. The @code{.set nodsp} directive prevents DSP 472instructions from being accepted. 473 474@cindex MIPS MT instruction generation override 475@kindex @code{.set mt} 476@kindex @code{.set nomt} 477The directive @code{.set mt} makes the assembler accept instructions 478from the MT Application Specific Extension from that point on 479in the assembly. The @code{.set nomt} directive prevents MT 480instructions from being accepted. 481 482Traditional @sc{mips} assemblers do not support these directives. 483