1# _ashrsi3.S for Lattice Mico32 2# Contributed by Jon Beniston <jon@beniston.com> and Richard Henderson. 3# 4# Copyright (C) 2009-2015 Free Software Foundation, Inc. 5# 6# This file is free software; you can redistribute it and/or modify it 7# under the terms of the GNU General Public License as published by the 8# Free Software Foundation; either version 3, or (at your option) any 9# later version. 10# 11# This file is distributed in the hope that it will be useful, but 12# WITHOUT ANY WARRANTY; without even the implied warranty of 13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14# General Public License for more details. 15# 16# Under Section 7 of GPL version 3, you are granted additional 17# permissions described in the GCC Runtime Library Exception, version 18# 3.1, as published by the Free Software Foundation. 19# 20# You should have received a copy of the GNU General Public License and 21# a copy of the GCC Runtime Library Exception along with this program; 22# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 23# <http://www.gnu.org/licenses/>. 24# 25 26/* Arithmetic right shift. */ 27 28 .global __ashrsi3 29 .type __ashrsi3,@function 30 31__ashrsi3: 32 /* Only use 5 LSBs, as that's all the h/w shifter uses. */ 33 andi r2, r2, 0x1f 34 /* Get address of offset into unrolled shift loop to jump to. */ 35#ifdef __PIC__ 36 lw r3, (gp+got(__ashrsi3_0)) 37#else 38 mvhi r3, hi(__ashrsi3_0) 39 ori r3, r3, lo(__ashrsi3_0) 40#endif 41 add r2, r2, r2 42 add r2, r2, r2 43 sub r3, r3, r2 44 b r3 45 46__ashrsi3_31: 47 sri r1, r1, 1 48__ashrsi3_30: 49 sri r1, r1, 1 50__ashrsi3_29: 51 sri r1, r1, 1 52__ashrsi3_28: 53 sri r1, r1, 1 54__ashrsi3_27: 55 sri r1, r1, 1 56__ashrsi3_26: 57 sri r1, r1, 1 58__ashrsi3_25: 59 sri r1, r1, 1 60__ashrsi3_24: 61 sri r1, r1, 1 62__ashrsi3_23: 63 sri r1, r1, 1 64__ashrsi3_22: 65 sri r1, r1, 1 66__ashrsi3_21: 67 sri r1, r1, 1 68__ashrsi3_20: 69 sri r1, r1, 1 70__ashrsi3_19: 71 sri r1, r1, 1 72__ashrsi3_18: 73 sri r1, r1, 1 74__ashrsi3_17: 75 sri r1, r1, 1 76__ashrsi3_16: 77 sri r1, r1, 1 78__ashrsi3_15: 79 sri r1, r1, 1 80__ashrsi3_14: 81 sri r1, r1, 1 82__ashrsi3_13: 83 sri r1, r1, 1 84__ashrsi3_12: 85 sri r1, r1, 1 86__ashrsi3_11: 87 sri r1, r1, 1 88__ashrsi3_10: 89 sri r1, r1, 1 90__ashrsi3_9: 91 sri r1, r1, 1 92__ashrsi3_8: 93 sri r1, r1, 1 94__ashrsi3_7: 95 sri r1, r1, 1 96__ashrsi3_6: 97 sri r1, r1, 1 98__ashrsi3_5: 99 sri r1, r1, 1 100__ashrsi3_4: 101 sri r1, r1, 1 102__ashrsi3_3: 103 sri r1, r1, 1 104__ashrsi3_2: 105 sri r1, r1, 1 106__ashrsi3_1: 107 sri r1, r1, 1 108__ashrsi3_0: 109 ret 110