1/* Based on execute/simd-1.c, modified by joern.rennecke@st.com to 2 trigger a reload bug. Verified for gcc mainline from 20050722 13:00 UTC 3 for sh-elf -m4 -O2. */ 4/* { dg-options "-Wno-psabi" } */ 5 6#ifndef STACK_SIZE 7#define STACK_SIZE (256*1024) 8#endif 9 10extern void abort (void); 11extern void exit (int); 12 13typedef struct { char c[STACK_SIZE/2]; } big_t; 14 15typedef int __attribute__((mode(SI))) __attribute__((vector_size (8))) vecint; 16typedef int __attribute__((mode(SI))) siint; 17 18vecint i = { 150, 100 }; 19vecint j = { 10, 13 }; 20vecint k; 21 22union { 23 vecint v; 24 siint i[2]; 25} res; 26 27void 28verify (siint a1, siint a2, siint b1, siint b2, big_t big) 29{ 30 if (a1 != b1 31 || a2 != b2) 32 abort (); 33} 34 35int 36main () 37{ 38 big_t big; 39 vecint k0, k1, k2, k3, k4, k5, k6, k7; 40 41 k0 = i + j; 42 res.v = k0; 43 44 verify (res.i[0], res.i[1], 160, 113, big); 45 46 k1 = i * j; 47 res.v = k1; 48 49 verify (res.i[0], res.i[1], 1500, 1300, big); 50 51 k2 = i / j; 52/* This is the observed failure - reload 0 has the wrong type and thus the 53 conflict with reload 1 is missed: 54 55(insn:HI 94 92 96 1 pr23135.c:46 (parallel [ 56 (set (subreg:SI (reg:DI 253) 0) 57 (div:SI (reg:SI 4 r4) 58 (reg:SI 5 r5))) 59 (clobber (reg:SI 146 pr)) 60 (clobber (reg:DF 64 fr0)) 61 (clobber (reg:DF 66 fr2)) 62 (use (reg:PSI 151 )) 63 (use (reg/f:SI 256)) 64 ]) 60 {divsi3_i4} (insn_list:REG_DEP_TRUE 90 (insn_list:REG_DEP_TRUE 89 65(insn_list:REG_DEP_TRUE 42 (insn_list:REG_DEP_TRUE 83 (insn_list:REG_DEP_TRUE 92 66 (insn_list:REG_DEP_TRUE 91 (nil))))))) 67 (expr_list:REG_DEAD (reg:SI 4 r4) 68 (expr_list:REG_DEAD (reg:SI 5 r5) 69 (expr_list:REG_UNUSED (reg:DF 66 fr2) 70 (expr_list:REG_UNUSED (reg:DF 64 fr0) 71 (expr_list:REG_UNUSED (reg:SI 146 pr) 72 (insn_list:REG_RETVAL 91 (nil)))))))) 73 74Reloads for insn # 94 75Reload 0: reload_in (SI) = (plus:SI (reg/f:SI 14 r14) 76 (const_int 64 [0x40])) 77 GENERAL_REGS, RELOAD_FOR_OUTADDR_ADDRESS (opnum = 0) 78 reload_in_reg: (plus:SI (reg/f:SI 14 r14) 79 (const_int 64 [0x40])) 80 reload_reg_rtx: (reg:SI 3 r3) 81Reload 1: GENERAL_REGS, RELOAD_FOR_OUTPUT_ADDRESS (opnum = 0), can't combine, se 82condary_reload_p 83 reload_reg_rtx: (reg:SI 3 r3) 84Reload 2: reload_out (SI) = (mem:SI (plus:SI (plus:SI (reg/f:SI 14 r14) 85 (const_int 64 [0x40])) 86 (const_int 28 [0x1c])) [ 16 S8 A32]) 87 FPUL_REGS, RELOAD_FOR_OUTPUT (opnum = 0) 88 reload_out_reg: (subreg:SI (reg:DI 253) 0) 89 reload_reg_rtx: (reg:SI 150 fpul) 90 secondary_out_reload = 1 91 92Reload 3: reload_in (SI) = (symbol_ref:SI ("__sdivsi3_i4") [flags 0x1]) 93 GENERAL_REGS, RELOAD_FOR_INPUT (opnum = 1), can't combine 94 reload_in_reg: (reg/f:SI 256) 95 reload_reg_rtx: (reg:SI 3 r3) 96 */ 97 98 99 res.v = k2; 100 101 verify (res.i[0], res.i[1], 15, 7, big); 102 103 k3 = i & j; 104 res.v = k3; 105 106 verify (res.i[0], res.i[1], 2, 4, big); 107 108 k4 = i | j; 109 res.v = k4; 110 111 verify (res.i[0], res.i[1], 158, 109, big); 112 113 k5 = i ^ j; 114 res.v = k5; 115 116 verify (res.i[0], res.i[1], 156, 105, big); 117 118 k6 = -i; 119 res.v = k6; 120 verify (res.i[0], res.i[1], -150, -100, big); 121 122 k7 = ~i; 123 res.v = k7; 124 verify (res.i[0], res.i[1], -151, -101, big); 125 126 k = k0 + k1 + k3 + k4 + k5 + k6 + k7; 127 res.v = k; 128 verify (res.i[0], res.i[1], 1675, 1430, big); 129 130 k = k0 * k1 * k3 * k4 * k5 * k6 * k7; 131 res.v = k; 132 verify (res.i[0], res.i[1], 1456467968, -1579586240, big); 133 134 k = k0 / k1 / k2 / k3 / k4 / k5 / k6 / k7; 135 res.v = k; 136 verify (res.i[0], res.i[1], 0, 0, big); 137 138 exit (0); 139} 140