1;; Constraint definitions for SPARC.
2;; Copyright (C) 2008-2015 Free Software Foundation, Inc.
3;;
4;; This file is part of GCC.
5;;
6;; GCC is free software; you can redistribute it and/or modify
7;; it under the terms of the GNU General Public License as published by
8;; the Free Software Foundation; either version 3, or (at your option)
9;; any later version.
10;;
11;; GCC is distributed in the hope that it will be useful,
12;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14;; GNU General Public License for more details.
15;;
16;; You should have received a copy of the GNU General Public License
17;; along with GCC; see the file COPYING3.  If not see
18;; <http://www.gnu.org/licenses/>.
19
20;;; Unused letters:
21;;;     B
22;;;    a        jkl    q  tuv xyz
23
24
25;; Register constraints
26
27(define_register_constraint "b" "(TARGET_V9 && TARGET_VIS ? EXTRA_FP_REGS : NO_REGS)"
28 "Any floating-point register in VIS mode")
29
30(define_register_constraint "c" "FPCC_REGS"
31 "Floating-point condition code register")
32
33(define_register_constraint "d" "(TARGET_V9 && TARGET_VIS ? FP_REGS : NO_REGS)"
34 "Lower floating-point register in VIS mode")
35
36;; In the non-V9 case, coerce V9 'e' class to 'f', so we can use 'e' in the
37;; MD file for V8 and V9.
38(define_register_constraint "e" "(TARGET_FPU ? (TARGET_V9 ? EXTRA_FP_REGS : FP_REGS) : NO_REGS)"
39 "Any floating-point register")
40
41(define_register_constraint "f" "(TARGET_FPU ? FP_REGS : NO_REGS)"
42 "Lower floating-point register")
43 
44(define_register_constraint "h" "(TARGET_V9 && TARGET_V8PLUS ? I64_REGS : NO_REGS)"
45 "64-bit global or out register in V8+ mode")
46
47;; Floating-point constant constraints
48
49(define_constraint "G"
50 "The floating-point zero constant"
51 (and (match_code "const_double")
52      (match_test "const_zero_operand (op, mode)")))
53
54(define_constraint "C"
55 "The floating-point all-ones constant"
56 (and (match_code "const_double")
57      (match_test "const_all_ones_operand (op, mode)")))
58
59;; Integer constant constraints
60
61(define_constraint "A"
62 "Signed 5-bit integer constant"
63 (and (match_code "const_int")
64      (match_test "SPARC_SIMM5_P (ival)")))
65
66(define_constraint "H"
67 "Valid operand of double arithmetic operation"
68 (and (match_code "const_double")
69      (match_test "arith_double_operand (op, DImode)")))
70
71(define_constraint "I"
72 "Signed 13-bit integer constant"
73 (and (match_code "const_int")
74      (match_test "SPARC_SIMM13_P (ival)")))
75
76(define_constraint "J"
77 "The integer zero constant"
78 (and (match_code "const_int")
79      (match_test "ival == 0")))
80
81(define_constraint "K"
82 "Signed 32-bit constant that can be loaded with a sethi instruction"
83 (and (match_code "const_int")
84      (match_test "SPARC_SETHI32_P (ival)")))
85
86(define_constraint "L"
87 "Signed 11-bit integer constant"
88 (and (match_code "const_int")
89      (match_test "SPARC_SIMM11_P (ival)")))
90
91(define_constraint "M"
92 "Signed 10-bit integer constant"
93 (and (match_code "const_int")
94      (match_test "SPARC_SIMM10_P (ival)")))
95
96(define_constraint "N"
97 "Signed constant that can be loaded with a sethi instruction"
98 (and (match_code "const_int")
99      (match_test "SPARC_SETHI_P (ival)")))
100
101(define_constraint "O"
102 "The 4096 constant"
103 (and (match_code "const_int")
104      (match_test "ival == 4096")))
105
106(define_constraint "P"
107 "The integer constant -1"
108 (and (match_code "const_int")
109      (match_test "ival == -1")))
110
111(define_constraint "D"
112 "const_vector"
113  (and (match_code "const_vector")
114       (match_test "GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT")))
115
116(define_constraint "Q"
117 "Floating-point constant that can be loaded with a sethi instruction"
118 (and (match_code "const_double")
119      (match_test "fp_sethi_p (op)")))
120
121(define_constraint "R"
122 "Floating-point constant that can be loaded with a move instruction"
123 (and (match_code "const_double")
124      (match_test "fp_mov_p (op)")))
125
126(define_constraint "S"
127 "Floating-point constant that can be loaded with a high/lo_sum sequence"
128 (and (match_code "const_double")
129      (match_test "fp_high_losum_p (op)")))
130
131;; Not needed in 64-bit mode
132(define_memory_constraint "T"
133 "Memory reference whose address is aligned to 8-byte boundary"
134 (and (match_test "TARGET_ARCH32")
135      (match_code "mem")
136      (match_test "memory_ok_for_ldd (op)")))
137
138;; This awkward register constraint is necessary because it is not
139;; possible to express the "must be even numbered register" condition
140;; using register classes.  The problem is that membership in a
141;; register class requires that all registers of a multi-regno
142;; register be included in the set.  It is add_to_hard_reg_set
143;; and in_hard_reg_set_p which populate and test regsets with these
144;; semantics.
145;;
146;; So this means that we would have to put both the even and odd
147;; register into the register class, which would not restrict things
148;; at all.
149;;
150;; Using a combination of GENERAL_REGS and HARD_REGNO_MODE_OK is not a
151;; full solution either.  In fact, even though IRA uses the macro
152;; HARD_REGNO_MODE_OK to calculate which registers are prohibited from
153;; use in certain modes, it still can allocate an odd hard register
154;; for DImode values.  This is due to how IRA populates the table
155;; ira_useful_class_mode_regs[][].  It suffers from the same problem
156;; as using a register class to describe this restriction.  Namely, it
157;; sets both the odd and even part of an even register pair in the
158;; regset.  Therefore IRA can and will allocate odd registers for
159;; DImode values on 32-bit.
160;;
161;; There are legitimate cases where DImode values can end up in odd
162;; hard registers, the most notable example is argument passing.
163;;
164;; What saves us is reload and the DImode splitters.  Both are
165;; necessary.  The odd register splitters cannot match if, for
166;; example, we have a non-offsetable MEM.  Reload will notice this
167;; case and reload the address into a single hard register.
168;;
169;; The real downfall of this awkward register constraint is that it does
170;; not evaluate to a true register class like a bonafide use of
171;; define_register_constraint would.  This currently means that we cannot
172;; use LRA on Sparc, since the constraint processing of LRA really depends
173;; upon whether an extra constraint is for registers or not.  It uses
174;; reg_class_for_constraint, and checks it against NO_REGS.
175(define_constraint "U"
176 "Pseudo-register or hard even-numbered integer register"
177 (and (match_test "TARGET_ARCH32")
178      (match_code "reg")
179      (ior (match_test "REGNO (op) < FIRST_PSEUDO_REGISTER")
180	   (not (match_test "reload_in_progress && reg_renumber [REGNO (op)] < 0")))
181      (match_test "register_ok_for_ldd (op)")))
182
183;; Equivalent to 'T' but available in 64-bit mode
184(define_memory_constraint "W"
185 "Memory reference for 'e' constraint floating-point register"
186 (and (match_code "mem")
187      (match_test "memory_ok_for_ldd (op)")))
188
189(define_memory_constraint "w"
190  "A memory with only a base register"
191  (match_operand 0 "mem_noofs_operand"))
192
193(define_constraint "Y"
194 "The vector zero constant"
195 (and (match_code "const_vector")
196      (match_test "const_zero_operand (op, mode)")))
197
198(define_constraint "Z"
199 "The vector all ones constant"
200 (and (match_code "const_vector")
201      (match_test "const_all_ones_operand (op, mode)")))
202