1;; DFA-based pipeline description for the XLR.
2;;   Copyright (C) 2008-2015 Free Software Foundation, Inc.
3;;
4;; xlr.md   Machine Description for the RMI XLR Microprocessor
5;; This file is part of GCC.
6
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
9;; by the Free Software Foundation; either version 3, or (at your
10;; option) any later version.
11
12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15;; License for more details.
16
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3.  If not see
19;; <http://www.gnu.org/licenses/>.
20
21(define_automaton "xlr_main,xlr_muldiv")
22
23;; Definitions for xlr_main automaton.
24(define_cpu_unit "xlr_main_pipe" "xlr_main")
25
26(define_insn_reservation "ir_xlr_alu_slt" 2
27  (and (eq_attr "cpu" "xlr") 
28       (eq_attr "type" "slt"))
29  "xlr_main_pipe")
30
31(define_insn_reservation "ir_xlr_alu_clz" 2
32  (and (eq_attr "cpu" "xlr") 
33       (eq_attr "type" "clz"))
34  "xlr_main_pipe")
35
36;; Integer arithmetic instructions.
37(define_insn_reservation "ir_xlr_alu" 1
38  (and (eq_attr "cpu" "xlr") 
39       (eq_attr "type" "move,arith,shift,logical,signext,const,unknown,multi,nop,trap,atomic,syncloop"))
40  "xlr_main_pipe")
41
42;; Integer arithmetic instructions.
43(define_insn_reservation "ir_xlr_condmove" 2
44  (and (eq_attr "cpu" "xlr") 
45       (eq_attr "type" "condmove"))
46  "xlr_main_pipe")
47
48;; Load/store instructions.
49(define_insn_reservation "ir_xlr_load" 4
50  (and (eq_attr "cpu" "xlr") 
51       (eq_attr "type" "load"))
52  "xlr_main_pipe")
53
54(define_insn_reservation "ir_xlr_store" 1
55  (and  (eq_attr "cpu" "xlr") 
56        (eq_attr "type" "store"))
57  "xlr_main_pipe")
58
59(define_insn_reservation "ir_xlr_prefetch_x" 1
60  (and (eq_attr "cpu" "xlr")
61       (eq_attr "type" "prefetch,prefetchx"))
62  "xlr_main_pipe")
63
64;; Branch instructions - use branch misprediction latency.
65(define_insn_reservation "ir_xlr_branch" 1
66  (and (eq_attr "cpu" "xlr") 
67       (eq_attr "type" "branch,jump,call"))
68  "xlr_main_pipe")
69
70;; Coprocessor move instructions.
71(define_insn_reservation "ir_xlr_xfer" 2
72  (and (eq_attr "cpu" "xlr") 
73       (eq_attr "type" "mtc,mfc"))
74  "xlr_main_pipe")
75
76(define_bypass 5 "ir_xlr_xfer" "ir_xlr_xfer")
77
78;; Definitions for the xlr_muldiv automaton.
79(define_cpu_unit "xlr_imuldiv_nopipe" "xlr_muldiv")
80
81(define_insn_reservation "ir_xlr_imul" 8
82  (and (eq_attr "cpu" "xlr") 
83       (eq_attr "type" "imul,imul3,imadd"))
84  "xlr_main_pipe,xlr_imuldiv_nopipe*6")
85
86(define_insn_reservation "ir_xlr_div" 68
87  (and (eq_attr "cpu" "xlr") 
88       (eq_attr "type" "idiv"))
89  "xlr_main_pipe,xlr_imuldiv_nopipe*67")
90
91(define_insn_reservation "xlr_hilo" 2
92  (and (eq_attr "cpu" "xlr") 
93       (eq_attr "type" "mfhi,mflo,mthi,mtlo"))
94  "xlr_imuldiv_nopipe")
95