1;; DFA-based pipeline description for the XLP.
2;; Copyright (C) 2012-2015 Free Software Foundation, Inc.
3;;
4;; xlp.md   Machine Description for the Broadcom XLP Microprocessor
5;; This file is part of GCC.
6
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
9;; by the Free Software Foundation; either version 3, or (at your
10;; option) any later version.
11
12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15;; License for more details.
16
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3.  If not see
19;; <http://www.gnu.org/licenses/>.
20
21(define_automaton "xlp_cpu")
22
23;; CPU function units.
24(define_cpu_unit "xlp_ex0" "xlp_cpu")
25(define_cpu_unit "xlp_ex1" "xlp_cpu")
26(define_cpu_unit "xlp_ex2" "xlp_cpu")
27(define_cpu_unit "xlp_ex3" "xlp_cpu")
28
29;; Integer Multiply Unit
30(define_cpu_unit "xlp_div" "xlp_cpu")
31
32;; ALU2 completion port.
33(define_cpu_unit "xlp_ex2_wrb" "xlp_cpu")
34
35(define_automaton "xlp_fpu")
36
37;; Floating-point units.
38(define_cpu_unit "xlp_fp" "xlp_fpu")
39
40;; Floating Point Sqrt/Divide
41(define_cpu_unit "xlp_divsq" "xlp_fpu")
42
43;; FPU completion port.
44(define_cpu_unit "xlp_fp_wrb" "xlp_fpu")
45
46;; Define reservations for common combinations.
47
48;;
49;; The ordering of the instruction-execution-path/resource-usage
50;; descriptions (also known as reservation RTL) is roughly ordered
51;; based on the define attribute RTL for the "type" classification.
52;; When modifying, remember that the first test that matches is the
53;; reservation used!
54;;
55(define_insn_reservation "ir_xlp_unknown" 1
56  (and (eq_attr "cpu" "xlp")
57       (eq_attr "type" "unknown,multi"))
58  "xlp_ex0+xlp_ex1+xlp_ex2+xlp_ex3")
59
60(define_insn_reservation "ir_xlp_branch" 1
61  (and (eq_attr "cpu" "xlp")
62       (eq_attr "type" "branch,jump,call"))
63  "xlp_ex3")
64
65(define_insn_reservation "ir_xlp_prefetch" 1
66  (and (eq_attr "cpu" "xlp")
67       (eq_attr "type" "prefetch,prefetchx"))
68  "xlp_ex0|xlp_ex1")
69
70(define_insn_reservation "ir_xlp_load" 4
71  (and (eq_attr "cpu" "xlp")
72       (eq_attr "type" "load"))
73  "xlp_ex0|xlp_ex1")
74
75(define_insn_reservation "ir_xlp_fpload" 5
76  (and (eq_attr "cpu" "xlp")
77       (eq_attr "type" "fpload,fpidxload"))
78  "xlp_ex0|xlp_ex1")
79
80(define_insn_reservation "ir_xlp_alu" 1
81  (and (eq_attr "cpu" "xlp")
82       (eq_attr "type" "const,arith,shift,slt,clz,signext,logical,move,trap,nop"))
83  "xlp_ex0|xlp_ex1|(xlp_ex2,xlp_ex2_wrb)|xlp_ex3")
84
85(define_insn_reservation "ir_xlp_condmov" 1
86  (and (eq_attr "cpu" "xlp")
87       (eq_attr "type" "condmove")
88       (eq_attr "mode" "SI,DI"))
89  "xlp_ex2,xlp_ex2_wrb")
90
91(define_insn_reservation "ir_xlp_mul" 5
92  (and (eq_attr "cpu" "xlp")
93       (eq_attr "type" "imul,imadd"))
94  "xlp_ex2,nothing*4,xlp_ex2_wrb")
95
96(define_insn_reservation "ir_xlp_mul3" 3
97  (and (eq_attr "cpu" "xlp")
98       (eq_attr "type" "imul3"))
99  "xlp_ex2,nothing*2,xlp_ex2_wrb")
100
101(define_insn_reservation "ir_xlp_div" 24
102  (and (eq_attr "cpu" "xlp")
103       (eq_attr "mode" "SI")
104       (eq_attr "type" "idiv"))
105  "xlp_ex2+xlp_div,xlp_div*23,xlp_ex2_wrb")
106
107(define_insn_reservation "ir_xlp_ddiv" 48
108  (and (eq_attr "cpu" "xlp")
109       (eq_attr "mode" "DI")
110       (eq_attr "type" "idiv"))
111  "xlp_ex2+xlp_div,xlp_div*47,xlp_ex2_wrb")
112
113(define_insn_reservation "ir_xlp_store" 1
114  (and (eq_attr "cpu" "xlp")
115       (eq_attr "type" "store,fpstore,fpidxstore"))
116  "xlp_ex0|xlp_ex1")
117
118(define_insn_reservation "ir_xlp_fpmove" 2
119  (and (eq_attr "cpu" "xlp")
120       (eq_attr "type" "mfc"))
121 "xlp_ex3,xlp_fp,xlp_fp_wrb")
122
123(define_insn_reservation "ir_xlp_mfhi" 1
124  (and (eq_attr "cpu" "xlp")
125       (eq_attr "type" "mfhi"))
126  "xlp_ex2,xlp_ex2_wrb")
127
128(define_insn_reservation "ir_xlp_mflo" 1
129  (and (eq_attr "cpu" "xlp")
130       (eq_attr "type" "mflo"))
131  "xlp_ex2,xlp_ex2_wrb")
132
133(define_insn_reservation "ir_xlp_mthi" 1
134  (and (eq_attr "cpu" "xlp")
135       (eq_attr "type" "mthi"))
136  "xlp_ex2,xlp_ex2_wrb")
137
138(define_insn_reservation "ir_xlp_mtlo" 3
139  (and (eq_attr "cpu" "xlp")
140       (eq_attr "type" "mtlo"))
141  "xlp_ex2,nothing*2,xlp_ex2_wrb")
142
143(define_insn_reservation "ir_xlp_fp2" 2
144  (and (eq_attr "cpu" "xlp")
145       (eq_attr "type" "fmove,fneg,fabs,condmove"))
146  "xlp_fp,nothing,xlp_fp_wrb")
147
148(define_insn_reservation "ir_xlp_fp3" 3
149  (and (eq_attr "cpu" "xlp")
150       (eq_attr "type" "fcmp"))
151  "xlp_fp,nothing*2,xlp_fp_wrb")
152
153(define_insn_reservation "ir_xlp_fp4" 4
154  (and (eq_attr "cpu" "xlp")
155       (eq_attr "type" "fcvt"))
156  "xlp_fp,nothing*3,xlp_fp_wrb")
157
158(define_insn_reservation "ir_xlp_fp5" 5
159  (and (eq_attr "cpu" "xlp")
160       (eq_attr "mode" "SF")
161       (eq_attr "type" "fadd,fmul"))
162  "xlp_fp,nothing*4,xlp_fp_wrb")
163
164(define_insn_reservation "ir_xlp_fp6" 6
165  (and (eq_attr "cpu" "xlp")
166       (eq_attr "mode" "DF")
167       (eq_attr "type" "fadd,fmul"))
168  "xlp_fp,nothing*5,xlp_fp_wrb")
169
170(define_insn_reservation "ir_xlp_fp9" 9
171  (and (eq_attr "cpu" "xlp")
172       (eq_attr "mode" "SF")
173       (eq_attr "type" "fmadd"))
174  "xlp_fp,nothing*3,xlp_fp,nothing*3,xlp_fp_wrb")
175
176(define_insn_reservation "ir_xlp_fp11" 11
177  (and (eq_attr "cpu" "xlp")
178       (eq_attr "mode" "DF")
179       (eq_attr "type" "fmadd"))
180  "xlp_fp,nothing*4,xlp_fp,nothing*4,xlp_fp_wrb")
181
182(define_insn_reservation "ir_xlp_fpcomplex_s" 23
183  (and (eq_attr "cpu" "xlp")
184       (eq_attr "mode" "SF")
185       (eq_attr "type" "fdiv,frdiv,frdiv1,frdiv2,fsqrt,frsqrt,frsqrt1,frsqrt2"))
186  "xlp_fp+xlp_divsq,xlp_divsq*22,xlp_fp_wrb")
187
188(define_insn_reservation "ir_xlp_fpcomplex_d" 38
189  (and (eq_attr "cpu" "xlp")
190       (eq_attr "mode" "DF")
191       (eq_attr "type" "fdiv,frdiv,frdiv1,frdiv2,fsqrt,frsqrt,frsqrt1,frsqrt2"))
192  "xlp_fp+xlp_divsq,xlp_divsq*37,xlp_fp_wrb")
193
194(define_bypass 3 "ir_xlp_mul" "ir_xlp_mfhi")
195
196(define_insn_reservation "ir_xlp_atomic" 15
197  (and (eq_attr "cpu" "xlp")
198       (eq_attr "type" "atomic"))
199  "xlp_ex0|xlp_ex1")
200
201;; Sync loop consists of (in order)
202;; (1) optional sync,
203;; (2) LL instruction,
204;; (3) branch and 1-2 ALU instructions,
205;; (4) SC instruction,
206;; (5) optional sync,
207;; (6) branch and ALU instruction.
208;; The net result of this reservation is a big delay with flush of
209;; ALU pipeline and outgoing reservations discouraging use of EX3.
210(define_insn_reservation "ir_xlp_sync_loop" 40
211  (and (eq_attr "cpu" "xlp")
212       (eq_attr "type" "syncloop"))
213  "(xlp_ex0+xlp_ex1+xlp_ex2+xlp_ex3)*39,xlp_ex3+(xlp_ex0|xlp_ex1|(xlp_ex2,xlp_ex2_wrb))")
214